authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-09-18 16:38:57+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-09-19 04:01:08+02:00
log47c932f8960e361282269202dc8ad7e63e3a06eb
tree59370577ae6c4b8687f9906659b5fed5f20a2d7d
parent19943f0f2169d5dd1d9499512dd94cb6d03dd94f

std.simd: suggest more sensible vector sizes across the board

1 files changed, 18 insertions(+), 14 deletions(-)

lib/std/simd.zig+18-14
...@@ -23,20 +23,24 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)...@@ -23,20 +23,24 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
23 } else if (cpu.arch.isArm()) {23 } else if (cpu.arch.isArm()) {
24 if (cpu.has(.arm, .neon)) break :blk 128;24 if (cpu.has(.arm, .neon)) break :blk 128;
25 } else if (cpu.arch.isAARCH64()) {25 } else if (cpu.arch.isAARCH64()) {
26 // SVE allows up to 2048 bits in the specification, as of 2022 the most powerful machine has implemented 512-bit26 // NVIDIA Grace supports 128-bit SVE
27 // I think is safer to just be on 128 until is more common27 // AWS Graviton3 supports 256-bit SVE
28 // TODO: Check on this return when bigger values are more common28 // Fujitsu A64FX supports 512-bit SVE
29 if (cpu.has(.aarch64, .sve)) break :blk 128;29 // -> 256-bit seems like a good default for now.
30 if (cpu.has(.aarch64, .sve)) break :blk 256;
30 if (cpu.has(.aarch64, .neon)) break :blk 128;31 if (cpu.has(.aarch64, .neon)) break :blk 128;
31 } else if (cpu.arch.isPowerPC()) {32 } else if (cpu.arch == .hexagon) {
32 if (cpu.has(.powerpc, .altivec)) break :blk 128;33 if (cpu.has(.hexagon, .hvx_length64b)) break :blk 512;
34 if (cpu.has(.hexagon, .hvx)) break :blk 1024;
35 } else if (cpu.arch.isLoongArch()) {
36 if (cpu.has(.loongarch, .lasx)) break :blk 256;
37 if (cpu.has(.loongarch, .lsx)) break :blk 128;
33 } else if (cpu.arch.isMIPS()) {38 } else if (cpu.arch.isMIPS()) {
34 if (cpu.has(.mips, .msa)) break :blk 128;39 if (cpu.has(.mips, .msa)) break :blk 128;
35 // TODO: Test MIPS capability to handle bigger vectors
36 // In theory MDMX and by extension mips3d have 32 registers of 64 bits which can use in parallel
37 // for multiple processing, but I don't know what's optimal here, if using
38 // the 2048 bits or using just 64 per vector or something in between
39 if (cpu.has(.mips, .mips3d)) break :blk 64;40 if (cpu.has(.mips, .mips3d)) break :blk 64;
41 } else if (cpu.arch.isPowerPC()) {
42 if (cpu.has(.powerpc, .vsx)) break :blk 128;
43 if (cpu.has(.powerpc, .altivec)) break :blk 128;
40 } else if (cpu.arch.isRISCV()) {44 } else if (cpu.arch.isRISCV()) {
41 // In RISC-V Vector Registers are length agnostic so there's no good way to determine the best size.45 // In RISC-V Vector Registers are length agnostic so there's no good way to determine the best size.
42 // The usual vector length in most RISC-V cpus is 256 bits, however it can get to multiple kB.46 // The usual vector length in most RISC-V cpus is 256 bits, however it can get to multiple kB.
...@@ -60,12 +64,12 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)...@@ -60,12 +64,12 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
6064
61 break :blk 256;65 break :blk 256;
62 }66 }
67 } else if (cpu.arch == .s390x) {
68 if (cpu.has(.s390x, .vector)) break :blk 128;
63 } else if (cpu.arch.isSPARC()) {69 } else if (cpu.arch.isSPARC()) {
64 // TODO: Test Sparc capability to handle bigger vectors
65 // In theory Sparc have 32 registers of 64 bits which can use in parallel
66 // for multiple processing, but I don't know what's optimal here, if using
67 // the 2048 bits or using just 64 per vector or something in between
68 if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;70 if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;
71 } else if (cpu.arch == .ve) {
72 if (cpu.has(.ve, .vpu)) break :blk 2048;
69 } else if (cpu.arch.isWasm()) {73 } else if (cpu.arch.isWasm()) {
70 if (cpu.has(.wasm, .simd128)) break :blk 128;74 if (cpu.has(.wasm, .simd128)) break :blk 128;
71 }75 }