| ... | ... | @@ -32,67 +32,75 @@ pub const Result = union(enum) { |
| 32 | 32 | fail: *Module.ErrorMsg, |
| 33 | 33 | }; |
| 34 | 34 | |
| 35 | pub const GenerateSymbolError = error{ |
| 36 | OutOfMemory, |
| 37 | /// A Decl that this symbol depends on had a semantic analysis failure. |
| 38 | AnalysisFail, |
| 39 | }; |
| 40 | |
| 35 | 41 | pub fn generateSymbol( |
| 36 | 42 | bin_file: *link.File.Elf, |
| 37 | 43 | src: usize, |
| 38 | 44 | typed_value: TypedValue, |
| 39 | 45 | code: *std.ArrayList(u8), |
| 40 | | ) error{ |
| 41 | | OutOfMemory, |
| 42 | | /// A Decl that this symbol depends on had a semantic analysis failure. |
| 43 | | AnalysisFail, |
| 44 | | }!Result { |
| 46 | ) GenerateSymbolError!Result { |
| 45 | 47 | const tracy = trace(@src()); |
| 46 | 48 | defer tracy.end(); |
| 47 | 49 | |
| 48 | 50 | switch (typed_value.ty.zigTypeTag()) { |
| 49 | 51 | .Fn => { |
| 50 | | const module_fn = typed_value.val.cast(Value.Payload.Function).?.func; |
| 51 | | |
| 52 | | const fn_type = module_fn.owner_decl.typed_value.most_recent.typed_value.ty; |
| 53 | | const param_types = try bin_file.allocator.alloc(Type, fn_type.fnParamLen()); |
| 54 | | defer bin_file.allocator.free(param_types); |
| 55 | | fn_type.fnParamTypes(param_types); |
| 56 | | var mc_args = try bin_file.allocator.alloc(MCValue, param_types.len); |
| 57 | | defer bin_file.allocator.free(mc_args); |
| 58 | | |
| 59 | | var branch_stack = std.ArrayList(Function.Branch).init(bin_file.allocator); |
| 60 | | defer { |
| 61 | | assert(branch_stack.items.len == 1); |
| 62 | | branch_stack.items[0].deinit(bin_file.allocator); |
| 63 | | branch_stack.deinit(); |
| 64 | | } |
| 65 | | const branch = try branch_stack.addOne(); |
| 66 | | branch.* = .{}; |
| 67 | | |
| 68 | | var function = Function{ |
| 69 | | .gpa = bin_file.allocator, |
| 70 | | .target = &bin_file.options.target, |
| 71 | | .bin_file = bin_file, |
| 72 | | .mod_fn = module_fn, |
| 73 | | .code = code, |
| 74 | | .err_msg = null, |
| 75 | | .args = mc_args, |
| 76 | | .arg_index = 0, |
| 77 | | .branch_stack = &branch_stack, |
| 78 | | .src = src, |
| 79 | | }; |
| 80 | | |
| 81 | | const cc = fn_type.fnCallingConvention(); |
| 82 | | branch.max_end_stack = function.resolveParameters(src, cc, param_types, mc_args) catch |err| switch (err) { |
| 83 | | error.CodegenFail => return Result{ .fail = function.err_msg.? }, |
| 84 | | else => |e| return e, |
| 85 | | }; |
| 86 | | |
| 87 | | function.gen() catch |err| switch (err) { |
| 88 | | error.CodegenFail => return Result{ .fail = function.err_msg.? }, |
| 89 | | else => |e| return e, |
| 90 | | }; |
| 91 | | |
| 92 | | if (function.err_msg) |em| { |
| 93 | | return Result{ .fail = em }; |
| 94 | | } else { |
| 95 | | return Result{ .appended = {} }; |
| 52 | switch (bin_file.options.target.cpu.arch) { |
| 53 | .arm => return Function(.arm).generateSymbol(bin_file, src, typed_value, code), |
| 54 | .armeb => return Function(.armeb).generateSymbol(bin_file, src, typed_value, code), |
| 55 | .aarch64 => return Function(.aarch64).generateSymbol(bin_file, src, typed_value, code), |
| 56 | .aarch64_be => return Function(.aarch64_be).generateSymbol(bin_file, src, typed_value, code), |
| 57 | .aarch64_32 => return Function(.aarch64_32).generateSymbol(bin_file, src, typed_value, code), |
| 58 | .arc => return Function(.arc).generateSymbol(bin_file, src, typed_value, code), |
| 59 | .avr => return Function(.avr).generateSymbol(bin_file, src, typed_value, code), |
| 60 | .bpfel => return Function(.bpfel).generateSymbol(bin_file, src, typed_value, code), |
| 61 | .bpfeb => return Function(.bpfeb).generateSymbol(bin_file, src, typed_value, code), |
| 62 | .hexagon => return Function(.hexagon).generateSymbol(bin_file, src, typed_value, code), |
| 63 | .mips => return Function(.mips).generateSymbol(bin_file, src, typed_value, code), |
| 64 | .mipsel => return Function(.mipsel).generateSymbol(bin_file, src, typed_value, code), |
| 65 | .mips64 => return Function(.mips64).generateSymbol(bin_file, src, typed_value, code), |
| 66 | .mips64el => return Function(.mips64el).generateSymbol(bin_file, src, typed_value, code), |
| 67 | .msp430 => return Function(.msp430).generateSymbol(bin_file, src, typed_value, code), |
| 68 | .powerpc => return Function(.powerpc).generateSymbol(bin_file, src, typed_value, code), |
| 69 | .powerpc64 => return Function(.powerpc64).generateSymbol(bin_file, src, typed_value, code), |
| 70 | .powerpc64le => return Function(.powerpc64le).generateSymbol(bin_file, src, typed_value, code), |
| 71 | .r600 => return Function(.r600).generateSymbol(bin_file, src, typed_value, code), |
| 72 | .amdgcn => return Function(.amdgcn).generateSymbol(bin_file, src, typed_value, code), |
| 73 | .riscv32 => return Function(.riscv32).generateSymbol(bin_file, src, typed_value, code), |
| 74 | .riscv64 => return Function(.riscv64).generateSymbol(bin_file, src, typed_value, code), |
| 75 | .sparc => return Function(.sparc).generateSymbol(bin_file, src, typed_value, code), |
| 76 | .sparcv9 => return Function(.sparcv9).generateSymbol(bin_file, src, typed_value, code), |
| 77 | .sparcel => return Function(.sparcel).generateSymbol(bin_file, src, typed_value, code), |
| 78 | .s390x => return Function(.s390x).generateSymbol(bin_file, src, typed_value, code), |
| 79 | .tce => return Function(.tce).generateSymbol(bin_file, src, typed_value, code), |
| 80 | .tcele => return Function(.tcele).generateSymbol(bin_file, src, typed_value, code), |
| 81 | .thumb => return Function(.thumb).generateSymbol(bin_file, src, typed_value, code), |
| 82 | .thumbeb => return Function(.thumbeb).generateSymbol(bin_file, src, typed_value, code), |
| 83 | .i386 => return Function(.i386).generateSymbol(bin_file, src, typed_value, code), |
| 84 | .x86_64 => return Function(.x86_64).generateSymbol(bin_file, src, typed_value, code), |
| 85 | .xcore => return Function(.xcore).generateSymbol(bin_file, src, typed_value, code), |
| 86 | .nvptx => return Function(.nvptx).generateSymbol(bin_file, src, typed_value, code), |
| 87 | .nvptx64 => return Function(.nvptx64).generateSymbol(bin_file, src, typed_value, code), |
| 88 | .le32 => return Function(.le32).generateSymbol(bin_file, src, typed_value, code), |
| 89 | .le64 => return Function(.le64).generateSymbol(bin_file, src, typed_value, code), |
| 90 | .amdil => return Function(.amdil).generateSymbol(bin_file, src, typed_value, code), |
| 91 | .amdil64 => return Function(.amdil64).generateSymbol(bin_file, src, typed_value, code), |
| 92 | .hsail => return Function(.hsail).generateSymbol(bin_file, src, typed_value, code), |
| 93 | .hsail64 => return Function(.hsail64).generateSymbol(bin_file, src, typed_value, code), |
| 94 | .spir => return Function(.spir).generateSymbol(bin_file, src, typed_value, code), |
| 95 | .spir64 => return Function(.spir64).generateSymbol(bin_file, src, typed_value, code), |
| 96 | .kalimba => return Function(.kalimba).generateSymbol(bin_file, src, typed_value, code), |
| 97 | .shave => return Function(.shave).generateSymbol(bin_file, src, typed_value, code), |
| 98 | .lanai => return Function(.lanai).generateSymbol(bin_file, src, typed_value, code), |
| 99 | .wasm32 => return Function(.wasm32).generateSymbol(bin_file, src, typed_value, code), |
| 100 | .wasm64 => return Function(.wasm64).generateSymbol(bin_file, src, typed_value, code), |
| 101 | .renderscript32 => return Function(.renderscript32).generateSymbol(bin_file, src, typed_value, code), |
| 102 | .renderscript64 => return Function(.renderscript64).generateSymbol(bin_file, src, typed_value, code), |
| 103 | .ve => return Function(.ve).generateSymbol(bin_file, src, typed_value, code), |
| 96 | 104 | } |
| 97 | 105 | }, |
| 98 | 106 | .Array => { |
| ... | ... | @@ -189,1101 +197,1177 @@ const InnerError = error{ |
| 189 | 197 | CodegenFail, |
| 190 | 198 | }; |
| 191 | 199 | |
| 192 | | const MCValue = union(enum) { |
| 193 | | /// No runtime bits. `void` types, empty structs, u0, enums with 1 tag, etc. |
| 194 | | none, |
| 195 | | /// Control flow will not allow this value to be observed. |
| 196 | | unreach, |
| 197 | | /// No more references to this value remain. |
| 198 | | dead, |
| 199 | | /// A pointer-sized integer that fits in a register. |
| 200 | | immediate: u64, |
| 201 | | /// The constant was emitted into the code, at this offset. |
| 202 | | embedded_in_code: usize, |
| 203 | | /// The value is in a target-specific register. The value can |
| 204 | | /// be @intToEnum casted to the respective Reg enum. |
| 205 | | register: usize, |
| 206 | | /// The value is in memory at a hard-coded address. |
| 207 | | memory: u64, |
| 208 | | /// The value is one of the stack variables. |
| 209 | | stack_offset: u64, |
| 210 | | /// The value is in the compare flags assuming an unsigned operation, |
| 211 | | /// with this operator applied on top of it. |
| 212 | | compare_flags_unsigned: std.math.CompareOperator, |
| 213 | | /// The value is in the compare flags assuming a signed operation, |
| 214 | | /// with this operator applied on top of it. |
| 215 | | compare_flags_signed: std.math.CompareOperator, |
| 216 | | |
| 217 | | fn isMemory(mcv: MCValue) bool { |
| 218 | | return switch (mcv) { |
| 219 | | .embedded_in_code, .memory, .stack_offset => true, |
| 220 | | else => false, |
| 200 | fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 201 | return struct { |
| 202 | gpa: *Allocator, |
| 203 | bin_file: *link.File.Elf, |
| 204 | target: *const std.Target, |
| 205 | mod_fn: *const Module.Fn, |
| 206 | code: *std.ArrayList(u8), |
| 207 | err_msg: ?*ErrorMsg, |
| 208 | args: []MCValue, |
| 209 | arg_index: usize, |
| 210 | src: usize, |
| 211 | |
| 212 | /// Whenever there is a runtime branch, we push a Branch onto this stack, |
| 213 | /// and pop it off when the runtime branch joins. This provides an "overlay" |
| 214 | /// of the table of mappings from instructions to `MCValue` from within the branch. |
| 215 | /// This way we can modify the `MCValue` for an instruction in different ways |
| 216 | /// within different branches. Special consideration is needed when a branch |
| 217 | /// joins with its parent, to make sure all instructions have the same MCValue |
| 218 | /// across each runtime branch upon joining. |
| 219 | branch_stack: *std.ArrayList(Branch), |
| 220 | |
| 221 | const MCValue = union(enum) { |
| 222 | /// No runtime bits. `void` types, empty structs, u0, enums with 1 tag, etc. |
| 223 | none, |
| 224 | /// Control flow will not allow this value to be observed. |
| 225 | unreach, |
| 226 | /// No more references to this value remain. |
| 227 | dead, |
| 228 | /// A pointer-sized integer that fits in a register. |
| 229 | immediate: u64, |
| 230 | /// The constant was emitted into the code, at this offset. |
| 231 | embedded_in_code: usize, |
| 232 | /// The value is in a target-specific register. |
| 233 | register: Register, |
| 234 | /// The value is in memory at a hard-coded address. |
| 235 | memory: u64, |
| 236 | /// The value is one of the stack variables. |
| 237 | stack_offset: u64, |
| 238 | /// The value is in the compare flags assuming an unsigned operation, |
| 239 | /// with this operator applied on top of it. |
| 240 | compare_flags_unsigned: std.math.CompareOperator, |
| 241 | /// The value is in the compare flags assuming a signed operation, |
| 242 | /// with this operator applied on top of it. |
| 243 | compare_flags_signed: std.math.CompareOperator, |
| 244 | |
| 245 | fn isMemory(mcv: MCValue) bool { |
| 246 | return switch (mcv) { |
| 247 | .embedded_in_code, .memory, .stack_offset => true, |
| 248 | else => false, |
| 249 | }; |
| 250 | } |
| 251 | |
| 252 | fn isImmediate(mcv: MCValue) bool { |
| 253 | return switch (mcv) { |
| 254 | .immediate => true, |
| 255 | else => false, |
| 256 | }; |
| 257 | } |
| 258 | |
| 259 | fn isMutable(mcv: MCValue) bool { |
| 260 | return switch (mcv) { |
| 261 | .none => unreachable, |
| 262 | .unreach => unreachable, |
| 263 | .dead => unreachable, |
| 264 | |
| 265 | .immediate, |
| 266 | .embedded_in_code, |
| 267 | .memory, |
| 268 | .compare_flags_unsigned, |
| 269 | .compare_flags_signed, |
| 270 | => false, |
| 271 | |
| 272 | .register, |
| 273 | .stack_offset, |
| 274 | => true, |
| 275 | }; |
| 276 | } |
| 221 | 277 | }; |
| 222 | | } |
| 223 | 278 | |
| 224 | | fn isImmediate(mcv: MCValue) bool { |
| 225 | | return switch (mcv) { |
| 226 | | .immediate => true, |
| 227 | | else => false, |
| 279 | const Branch = struct { |
| 280 | inst_table: std.AutoHashMapUnmanaged(*ir.Inst, MCValue) = .{}, |
| 281 | registers: std.AutoHashMapUnmanaged(Register, RegisterAllocation) = .{}, |
| 282 | free_registers: FreeRegInt = std.math.maxInt(FreeRegInt), |
| 283 | |
| 284 | /// Maps offset to what is stored there. |
| 285 | stack: std.AutoHashMapUnmanaged(usize, StackAllocation) = .{}, |
| 286 | /// Offset from the stack base, representing the end of the stack frame. |
| 287 | max_end_stack: u32 = 0, |
| 288 | /// Represents the current end stack offset. If there is no existing slot |
| 289 | /// to place a new stack allocation, it goes here, and then bumps `max_end_stack`. |
| 290 | next_stack_offset: u32 = 0, |
| 291 | |
| 292 | fn markRegUsed(self: *Branch, reg: Register) void { |
| 293 | if (FreeRegInt == u0) return; |
| 294 | const index = reg.allocIndex() orelse return; |
| 295 | const ShiftInt = std.math.Log2Int(FreeRegInt); |
| 296 | const shift = @intCast(ShiftInt, index); |
| 297 | self.free_registers &= ~(@as(FreeRegInt, 1) << shift); |
| 298 | } |
| 299 | |
| 300 | fn markRegFree(self: *Branch, reg: Register) void { |
| 301 | if (FreeRegInt == u0) return; |
| 302 | const index = reg.allocIndex() orelse return; |
| 303 | const ShiftInt = std.math.Log2Int(FreeRegInt); |
| 304 | const shift = @intCast(ShiftInt, index); |
| 305 | self.free_registers |= @as(FreeRegInt, 1) << shift; |
| 306 | } |
| 307 | |
| 308 | fn deinit(self: *Branch, gpa: *Allocator) void { |
| 309 | self.inst_table.deinit(gpa); |
| 310 | self.registers.deinit(gpa); |
| 311 | self.stack.deinit(gpa); |
| 312 | self.* = undefined; |
| 313 | } |
| 228 | 314 | }; |
| 229 | | } |
| 230 | 315 | |
| 231 | | fn isMutable(mcv: MCValue) bool { |
| 232 | | return switch (mcv) { |
| 233 | | .none => unreachable, |
| 234 | | .unreach => unreachable, |
| 235 | | .dead => unreachable, |
| 236 | | |
| 237 | | .immediate, |
| 238 | | .embedded_in_code, |
| 239 | | .memory, |
| 240 | | .compare_flags_unsigned, |
| 241 | | .compare_flags_signed, |
| 242 | | => false, |
| 243 | | |
| 244 | | .register, |
| 245 | | .stack_offset, |
| 246 | | => true, |
| 316 | const RegisterAllocation = struct { |
| 317 | inst: *ir.Inst, |
| 247 | 318 | }; |
| 248 | | } |
| 249 | | }; |
| 250 | 319 | |
| 251 | | const Function = struct { |
| 252 | | gpa: *Allocator, |
| 253 | | bin_file: *link.File.Elf, |
| 254 | | target: *const std.Target, |
| 255 | | mod_fn: *const Module.Fn, |
| 256 | | code: *std.ArrayList(u8), |
| 257 | | err_msg: ?*ErrorMsg, |
| 258 | | args: []MCValue, |
| 259 | | arg_index: usize, |
| 260 | | src: usize, |
| 320 | const StackAllocation = struct { |
| 321 | inst: *ir.Inst, |
| 322 | size: u32, |
| 323 | }; |
| 261 | 324 | |
| 262 | | /// Whenever there is a runtime branch, we push a Branch onto this stack, |
| 263 | | /// and pop it off when the runtime branch joins. This provides an "overlay" |
| 264 | | /// of the table of mappings from instructions to `MCValue` from within the branch. |
| 265 | | /// This way we can modify the `MCValue` for an instruction in different ways |
| 266 | | /// within different branches. Special consideration is needed when a branch |
| 267 | | /// joins with its parent, to make sure all instructions have the same MCValue |
| 268 | | /// across each runtime branch upon joining. |
| 269 | | branch_stack: *std.ArrayList(Branch), |
| 270 | | |
| 271 | | const Branch = struct { |
| 272 | | inst_table: std.AutoHashMapUnmanaged(*ir.Inst, MCValue) = .{}, |
| 273 | | |
| 274 | | /// The key is an enum value of an arch-specific register. |
| 275 | | registers: std.AutoHashMapUnmanaged(usize, RegisterAllocation) = .{}, |
| 276 | | |
| 277 | | /// Maps offset to what is stored there. |
| 278 | | stack: std.AutoHashMapUnmanaged(usize, StackAllocation) = .{}, |
| 279 | | /// Offset from the stack base, representing the end of the stack frame. |
| 280 | | max_end_stack: u32 = 0, |
| 281 | | /// Represents the current end stack offset. If there is no existing slot |
| 282 | | /// to place a new stack allocation, it goes here, and then bumps `max_end_stack`. |
| 283 | | next_stack_offset: u32 = 0, |
| 284 | | |
| 285 | | fn deinit(self: *Branch, gpa: *Allocator) void { |
| 286 | | self.inst_table.deinit(gpa); |
| 287 | | self.registers.deinit(gpa); |
| 288 | | self.stack.deinit(gpa); |
| 289 | | self.* = undefined; |
| 290 | | } |
| 291 | | }; |
| 325 | const Self = @This(); |
| 292 | 326 | |
| 293 | | const RegisterAllocation = struct { |
| 294 | | inst: *ir.Inst, |
| 295 | | }; |
| 327 | fn generateSymbol( |
| 328 | bin_file: *link.File.Elf, |
| 329 | src: usize, |
| 330 | typed_value: TypedValue, |
| 331 | code: *std.ArrayList(u8), |
| 332 | ) GenerateSymbolError!Result { |
| 333 | const module_fn = typed_value.val.cast(Value.Payload.Function).?.func; |
| 296 | 334 | |
| 297 | | const StackAllocation = struct { |
| 298 | | inst: *ir.Inst, |
| 299 | | size: u32, |
| 300 | | }; |
| 335 | const fn_type = module_fn.owner_decl.typed_value.most_recent.typed_value.ty; |
| 336 | const param_types = try bin_file.allocator.alloc(Type, fn_type.fnParamLen()); |
| 337 | defer bin_file.allocator.free(param_types); |
| 338 | fn_type.fnParamTypes(param_types); |
| 339 | var mc_args = try bin_file.allocator.alloc(MCValue, param_types.len); |
| 340 | defer bin_file.allocator.free(mc_args); |
| 301 | 341 | |
| 302 | | fn gen(self: *Function) !void { |
| 303 | | switch (self.target.cpu.arch) { |
| 304 | | .arm => return self.genArch(.arm), |
| 305 | | .armeb => return self.genArch(.armeb), |
| 306 | | .aarch64 => return self.genArch(.aarch64), |
| 307 | | .aarch64_be => return self.genArch(.aarch64_be), |
| 308 | | .aarch64_32 => return self.genArch(.aarch64_32), |
| 309 | | .arc => return self.genArch(.arc), |
| 310 | | .avr => return self.genArch(.avr), |
| 311 | | .bpfel => return self.genArch(.bpfel), |
| 312 | | .bpfeb => return self.genArch(.bpfeb), |
| 313 | | .hexagon => return self.genArch(.hexagon), |
| 314 | | .mips => return self.genArch(.mips), |
| 315 | | .mipsel => return self.genArch(.mipsel), |
| 316 | | .mips64 => return self.genArch(.mips64), |
| 317 | | .mips64el => return self.genArch(.mips64el), |
| 318 | | .msp430 => return self.genArch(.msp430), |
| 319 | | .powerpc => return self.genArch(.powerpc), |
| 320 | | .powerpc64 => return self.genArch(.powerpc64), |
| 321 | | .powerpc64le => return self.genArch(.powerpc64le), |
| 322 | | .r600 => return self.genArch(.r600), |
| 323 | | .amdgcn => return self.genArch(.amdgcn), |
| 324 | | .riscv32 => return self.genArch(.riscv32), |
| 325 | | .riscv64 => return self.genArch(.riscv64), |
| 326 | | .sparc => return self.genArch(.sparc), |
| 327 | | .sparcv9 => return self.genArch(.sparcv9), |
| 328 | | .sparcel => return self.genArch(.sparcel), |
| 329 | | .s390x => return self.genArch(.s390x), |
| 330 | | .tce => return self.genArch(.tce), |
| 331 | | .tcele => return self.genArch(.tcele), |
| 332 | | .thumb => return self.genArch(.thumb), |
| 333 | | .thumbeb => return self.genArch(.thumbeb), |
| 334 | | .i386 => return self.genArch(.i386), |
| 335 | | .x86_64 => return self.genArch(.x86_64), |
| 336 | | .xcore => return self.genArch(.xcore), |
| 337 | | .nvptx => return self.genArch(.nvptx), |
| 338 | | .nvptx64 => return self.genArch(.nvptx64), |
| 339 | | .le32 => return self.genArch(.le32), |
| 340 | | .le64 => return self.genArch(.le64), |
| 341 | | .amdil => return self.genArch(.amdil), |
| 342 | | .amdil64 => return self.genArch(.amdil64), |
| 343 | | .hsail => return self.genArch(.hsail), |
| 344 | | .hsail64 => return self.genArch(.hsail64), |
| 345 | | .spir => return self.genArch(.spir), |
| 346 | | .spir64 => return self.genArch(.spir64), |
| 347 | | .kalimba => return self.genArch(.kalimba), |
| 348 | | .shave => return self.genArch(.shave), |
| 349 | | .lanai => return self.genArch(.lanai), |
| 350 | | .wasm32 => return self.genArch(.wasm32), |
| 351 | | .wasm64 => return self.genArch(.wasm64), |
| 352 | | .renderscript32 => return self.genArch(.renderscript32), |
| 353 | | .renderscript64 => return self.genArch(.renderscript64), |
| 354 | | .ve => return self.genArch(.ve), |
| 355 | | } |
| 356 | | } |
| 342 | var branch_stack = std.ArrayList(Branch).init(bin_file.allocator); |
| 343 | defer { |
| 344 | assert(branch_stack.items.len == 1); |
| 345 | branch_stack.items[0].deinit(bin_file.allocator); |
| 346 | branch_stack.deinit(); |
| 347 | } |
| 348 | const branch = try branch_stack.addOne(); |
| 349 | branch.* = .{}; |
| 350 | |
| 351 | var function = Self{ |
| 352 | .gpa = bin_file.allocator, |
| 353 | .target = &bin_file.options.target, |
| 354 | .bin_file = bin_file, |
| 355 | .mod_fn = module_fn, |
| 356 | .code = code, |
| 357 | .err_msg = null, |
| 358 | .args = mc_args, |
| 359 | .arg_index = 0, |
| 360 | .branch_stack = &branch_stack, |
| 361 | .src = src, |
| 362 | }; |
| 363 | |
| 364 | const cc = fn_type.fnCallingConvention(); |
| 365 | branch.max_end_stack = function.resolveParameters(src, cc, param_types, mc_args) catch |err| switch (err) { |
| 366 | error.CodegenFail => return Result{ .fail = function.err_msg.? }, |
| 367 | else => |e| return e, |
| 368 | }; |
| 357 | 369 | |
| 358 | | fn genArch(self: *Function, comptime arch: std.Target.Cpu.Arch) !void { |
| 359 | | try self.code.ensureCapacity(self.code.items.len + 11); |
| 360 | | |
| 361 | | // push rbp |
| 362 | | // mov rbp, rsp |
| 363 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x55, 0x48, 0x89, 0xe5 }); |
| 364 | | |
| 365 | | // sub rsp, x |
| 366 | | const stack_end = self.branch_stack.items[0].max_end_stack; |
| 367 | | if (stack_end > std.math.maxInt(i32)) { |
| 368 | | return self.fail(self.src, "too much stack used in call parameters", .{}); |
| 369 | | } else if (stack_end > std.math.maxInt(i8)) { |
| 370 | | // 48 83 ec xx sub rsp,0x10 |
| 371 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x48, 0x81, 0xec }); |
| 372 | | const x = @intCast(u32, stack_end); |
| 373 | | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), x); |
| 374 | | } else if (stack_end != 0) { |
| 375 | | // 48 81 ec xx xx xx xx sub rsp,0x80 |
| 376 | | const x = @intCast(u8, stack_end); |
| 377 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x48, 0x83, 0xec, x }); |
| 370 | function.gen() catch |err| switch (err) { |
| 371 | error.CodegenFail => return Result{ .fail = function.err_msg.? }, |
| 372 | else => |e| return e, |
| 373 | }; |
| 374 | |
| 375 | if (function.err_msg) |em| { |
| 376 | return Result{ .fail = em }; |
| 377 | } else { |
| 378 | return Result{ .appended = {} }; |
| 379 | } |
| 378 | 380 | } |
| 379 | 381 | |
| 380 | | try self.genBody(self.mod_fn.analysis.success, arch); |
| 381 | | } |
| 382 | fn gen(self: *Self) !void { |
| 383 | try self.code.ensureCapacity(self.code.items.len + 11); |
| 384 | |
| 385 | // push rbp |
| 386 | // mov rbp, rsp |
| 387 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x55, 0x48, 0x89, 0xe5 }); |
| 388 | |
| 389 | // sub rsp, x |
| 390 | const stack_end = self.branch_stack.items[0].max_end_stack; |
| 391 | if (stack_end > std.math.maxInt(i32)) { |
| 392 | return self.fail(self.src, "too much stack used in call parameters", .{}); |
| 393 | } else if (stack_end > std.math.maxInt(i8)) { |
| 394 | // 48 83 ec xx sub rsp,0x10 |
| 395 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x48, 0x81, 0xec }); |
| 396 | const x = @intCast(u32, stack_end); |
| 397 | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), x); |
| 398 | } else if (stack_end != 0) { |
| 399 | // 48 81 ec xx xx xx xx sub rsp,0x80 |
| 400 | const x = @intCast(u8, stack_end); |
| 401 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x48, 0x83, 0xec, x }); |
| 402 | } |
| 382 | 403 | |
| 383 | | fn genBody(self: *Function, body: ir.Body, comptime arch: std.Target.Cpu.Arch) InnerError!void { |
| 384 | | const inst_table = &self.branch_stack.items[0].inst_table; |
| 385 | | for (body.instructions) |inst| { |
| 386 | | const new_inst = try self.genFuncInst(inst, arch); |
| 387 | | try inst_table.putNoClobber(self.gpa, inst, new_inst); |
| 404 | try self.genBody(self.mod_fn.analysis.success); |
| 388 | 405 | } |
| 389 | | } |
| 390 | 406 | |
| 391 | | fn genFuncInst(self: *Function, inst: *ir.Inst, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 392 | | switch (inst.tag) { |
| 393 | | .add => return self.genAdd(inst.cast(ir.Inst.Add).?, arch), |
| 394 | | .arg => return self.genArg(inst.cast(ir.Inst.Arg).?), |
| 395 | | .assembly => return self.genAsm(inst.cast(ir.Inst.Assembly).?, arch), |
| 396 | | .bitcast => return self.genBitCast(inst.cast(ir.Inst.BitCast).?), |
| 397 | | .block => return self.genBlock(inst.cast(ir.Inst.Block).?, arch), |
| 398 | | .br => return self.genBr(inst.cast(ir.Inst.Br).?, arch), |
| 399 | | .breakpoint => return self.genBreakpoint(inst.src, arch), |
| 400 | | .brvoid => return self.genBrVoid(inst.cast(ir.Inst.BrVoid).?, arch), |
| 401 | | .call => return self.genCall(inst.cast(ir.Inst.Call).?, arch), |
| 402 | | .cmp => return self.genCmp(inst.cast(ir.Inst.Cmp).?, arch), |
| 403 | | .condbr => return self.genCondBr(inst.cast(ir.Inst.CondBr).?, arch), |
| 404 | | .constant => unreachable, // excluded from function bodies |
| 405 | | .isnonnull => return self.genIsNonNull(inst.cast(ir.Inst.IsNonNull).?, arch), |
| 406 | | .isnull => return self.genIsNull(inst.cast(ir.Inst.IsNull).?, arch), |
| 407 | | .ptrtoint => return self.genPtrToInt(inst.cast(ir.Inst.PtrToInt).?), |
| 408 | | .ret => return self.genRet(inst.cast(ir.Inst.Ret).?, arch), |
| 409 | | .retvoid => return self.genRetVoid(inst.cast(ir.Inst.RetVoid).?, arch), |
| 410 | | .sub => return self.genSub(inst.cast(ir.Inst.Sub).?, arch), |
| 411 | | .unreach => return MCValue{ .unreach = {} }, |
| 412 | | .not => return self.genNot(inst.cast(ir.Inst.Not).?, arch), |
| 407 | fn genBody(self: *Self, body: ir.Body) InnerError!void { |
| 408 | const inst_table = &self.branch_stack.items[0].inst_table; |
| 409 | for (body.instructions) |inst| { |
| 410 | const new_inst = try self.genFuncInst(inst); |
| 411 | try inst_table.putNoClobber(self.gpa, inst, new_inst); |
| 412 | |
| 413 | var i: ir.Inst.DeathsBitIndex = 0; |
| 414 | while (inst.getOperand(i)) |operand| : (i += 1) { |
| 415 | if (inst.operandDies(i)) |
| 416 | self.processDeath(operand); |
| 417 | } |
| 418 | } |
| 413 | 419 | } |
| 414 | | } |
| 415 | 420 | |
| 416 | | fn genNot(self: *Function, inst: *ir.Inst.Not, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 417 | | // No side effects, so if it's unreferenced, do nothing. |
| 418 | | if (inst.base.isUnused()) |
| 419 | | return MCValue.dead; |
| 420 | | const operand = try self.resolveInst(inst.args.operand); |
| 421 | | switch (operand) { |
| 422 | | .dead => unreachable, |
| 423 | | .unreach => unreachable, |
| 424 | | .compare_flags_unsigned => |op| return MCValue{ |
| 425 | | .compare_flags_unsigned = switch (op) { |
| 426 | | .gte => .lt, |
| 427 | | .gt => .lte, |
| 428 | | .neq => .eq, |
| 429 | | .lt => .gte, |
| 430 | | .lte => .gt, |
| 431 | | .eq => .neq, |
| 421 | fn processDeath(self: *Self, inst: *ir.Inst) void { |
| 422 | const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; |
| 423 | const entry = branch.inst_table.getEntry(inst) orelse return; |
| 424 | const prev_value = entry.value; |
| 425 | entry.value = .dead; |
| 426 | switch (prev_value) { |
| 427 | .register => |reg| { |
| 428 | _ = branch.registers.remove(reg); |
| 429 | branch.markRegFree(reg); |
| 432 | 430 | }, |
| 433 | | }, |
| 434 | | .compare_flags_signed => |op| return MCValue{ |
| 435 | | .compare_flags_signed = switch (op) { |
| 436 | | .gte => .lt, |
| 437 | | .gt => .lte, |
| 438 | | .neq => .eq, |
| 439 | | .lt => .gte, |
| 440 | | .lte => .gt, |
| 441 | | .eq => .neq, |
| 442 | | }, |
| 443 | | }, |
| 444 | | else => {}, |
| 431 | else => {}, // TODO process stack allocation death |
| 432 | } |
| 445 | 433 | } |
| 446 | 434 | |
| 447 | | switch (arch) { |
| 448 | | .x86_64 => { |
| 449 | | var imm = ir.Inst.Constant{ |
| 450 | | .base = .{ |
| 451 | | .tag = .constant, |
| 452 | | .deaths = 0, |
| 453 | | .ty = inst.args.operand.ty, |
| 454 | | .src = inst.args.operand.src, |
| 455 | | }, |
| 456 | | .val = Value.initTag(.bool_true), |
| 457 | | }; |
| 458 | | return try self.genX8664BinMath(&inst.base, inst.args.operand, &imm.base, 6, 0x30); |
| 459 | | }, |
| 460 | | else => return self.fail(inst.base.src, "TODO implement NOT for {}", .{self.target.cpu.arch}), |
| 435 | fn genFuncInst(self: *Self, inst: *ir.Inst) !MCValue { |
| 436 | switch (inst.tag) { |
| 437 | .add => return self.genAdd(inst.castTag(.add).?), |
| 438 | .arg => return self.genArg(inst.castTag(.arg).?), |
| 439 | .assembly => return self.genAsm(inst.castTag(.assembly).?), |
| 440 | .bitcast => return self.genBitCast(inst.castTag(.bitcast).?), |
| 441 | .block => return self.genBlock(inst.castTag(.block).?), |
| 442 | .br => return self.genBr(inst.castTag(.br).?), |
| 443 | .breakpoint => return self.genBreakpoint(inst.src), |
| 444 | .brvoid => return self.genBrVoid(inst.castTag(.brvoid).?), |
| 445 | .call => return self.genCall(inst.castTag(.call).?), |
| 446 | .cmp_lt => return self.genCmp(inst.castTag(.cmp_lt).?, .lt), |
| 447 | .cmp_lte => return self.genCmp(inst.castTag(.cmp_lte).?, .lte), |
| 448 | .cmp_eq => return self.genCmp(inst.castTag(.cmp_eq).?, .eq), |
| 449 | .cmp_gte => return self.genCmp(inst.castTag(.cmp_gte).?, .gte), |
| 450 | .cmp_gt => return self.genCmp(inst.castTag(.cmp_gt).?, .gt), |
| 451 | .cmp_neq => return self.genCmp(inst.castTag(.cmp_neq).?, .neq), |
| 452 | .condbr => return self.genCondBr(inst.castTag(.condbr).?), |
| 453 | .constant => unreachable, // excluded from function bodies |
| 454 | .isnonnull => return self.genIsNonNull(inst.castTag(.isnonnull).?), |
| 455 | .isnull => return self.genIsNull(inst.castTag(.isnull).?), |
| 456 | .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?), |
| 457 | .ret => return self.genRet(inst.castTag(.ret).?), |
| 458 | .retvoid => return self.genRetVoid(inst.castTag(.retvoid).?), |
| 459 | .sub => return self.genSub(inst.castTag(.sub).?), |
| 460 | .unreach => return MCValue{ .unreach = {} }, |
| 461 | .not => return self.genNot(inst.castTag(.not).?), |
| 462 | } |
| 461 | 463 | } |
| 462 | | } |
| 463 | 464 | |
| 464 | | fn genAdd(self: *Function, inst: *ir.Inst.Add, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 465 | | // No side effects, so if it's unreferenced, do nothing. |
| 466 | | if (inst.base.isUnused()) |
| 467 | | return MCValue.dead; |
| 468 | | switch (arch) { |
| 469 | | .x86_64 => { |
| 470 | | return try self.genX8664BinMath(&inst.base, inst.args.lhs, inst.args.rhs, 0, 0x00); |
| 471 | | }, |
| 472 | | else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}), |
| 473 | | } |
| 474 | | } |
| 465 | fn genNot(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 466 | // No side effects, so if it's unreferenced, do nothing. |
| 467 | if (inst.base.isUnused()) |
| 468 | return MCValue.dead; |
| 469 | const operand = try self.resolveInst(inst.operand); |
| 470 | switch (operand) { |
| 471 | .dead => unreachable, |
| 472 | .unreach => unreachable, |
| 473 | .compare_flags_unsigned => |op| return MCValue{ |
| 474 | .compare_flags_unsigned = switch (op) { |
| 475 | .gte => .lt, |
| 476 | .gt => .lte, |
| 477 | .neq => .eq, |
| 478 | .lt => .gte, |
| 479 | .lte => .gt, |
| 480 | .eq => .neq, |
| 481 | }, |
| 482 | }, |
| 483 | .compare_flags_signed => |op| return MCValue{ |
| 484 | .compare_flags_signed = switch (op) { |
| 485 | .gte => .lt, |
| 486 | .gt => .lte, |
| 487 | .neq => .eq, |
| 488 | .lt => .gte, |
| 489 | .lte => .gt, |
| 490 | .eq => .neq, |
| 491 | }, |
| 492 | }, |
| 493 | else => {}, |
| 494 | } |
| 475 | 495 | |
| 476 | | fn genSub(self: *Function, inst: *ir.Inst.Sub, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 477 | | // No side effects, so if it's unreferenced, do nothing. |
| 478 | | if (inst.base.isUnused()) |
| 479 | | return MCValue.dead; |
| 480 | | switch (arch) { |
| 481 | | .x86_64 => { |
| 482 | | return try self.genX8664BinMath(&inst.base, inst.args.lhs, inst.args.rhs, 5, 0x28); |
| 483 | | }, |
| 484 | | else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), |
| 496 | switch (arch) { |
| 497 | .x86_64 => { |
| 498 | var imm = ir.Inst.Constant{ |
| 499 | .base = .{ |
| 500 | .tag = .constant, |
| 501 | .deaths = 0, |
| 502 | .ty = inst.operand.ty, |
| 503 | .src = inst.operand.src, |
| 504 | }, |
| 505 | .val = Value.initTag(.bool_true), |
| 506 | }; |
| 507 | return try self.genX8664BinMath(&inst.base, inst.operand, &imm.base, 6, 0x30); |
| 508 | }, |
| 509 | else => return self.fail(inst.base.src, "TODO implement NOT for {}", .{self.target.cpu.arch}), |
| 510 | } |
| 485 | 511 | } |
| 486 | | } |
| 487 | 512 | |
| 488 | | /// ADD, SUB, XOR, OR, AND |
| 489 | | fn genX8664BinMath(self: *Function, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue { |
| 490 | | try self.code.ensureCapacity(self.code.items.len + 8); |
| 491 | | |
| 492 | | const lhs = try self.resolveInst(op_lhs); |
| 493 | | const rhs = try self.resolveInst(op_rhs); |
| 494 | | |
| 495 | | // There are 2 operands, destination and source. |
| 496 | | // Either one, but not both, can be a memory operand. |
| 497 | | // Source operand can be an immediate, 8 bits or 32 bits. |
| 498 | | // So, if either one of the operands dies with this instruction, we can use it |
| 499 | | // as the result MCValue. |
| 500 | | var dst_mcv: MCValue = undefined; |
| 501 | | var src_mcv: MCValue = undefined; |
| 502 | | var src_inst: *ir.Inst = undefined; |
| 503 | | if (inst.operandDies(0) and lhs.isMutable()) { |
| 504 | | // LHS dies; use it as the destination. |
| 505 | | // Both operands cannot be memory. |
| 506 | | src_inst = op_rhs; |
| 507 | | if (lhs.isMemory() and rhs.isMemory()) { |
| 508 | | dst_mcv = try self.copyToNewRegister(op_lhs); |
| 509 | | src_mcv = rhs; |
| 510 | | } else { |
| 511 | | dst_mcv = lhs; |
| 512 | | src_mcv = rhs; |
| 513 | fn genAdd(self: *Self, inst: *ir.Inst.BinOp) !MCValue { |
| 514 | // No side effects, so if it's unreferenced, do nothing. |
| 515 | if (inst.base.isUnused()) |
| 516 | return MCValue.dead; |
| 517 | switch (arch) { |
| 518 | .x86_64 => { |
| 519 | return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 0, 0x00); |
| 520 | }, |
| 521 | else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}), |
| 513 | 522 | } |
| 514 | | } else if (inst.operandDies(1) and rhs.isMutable()) { |
| 515 | | // RHS dies; use it as the destination. |
| 516 | | // Both operands cannot be memory. |
| 517 | | src_inst = op_lhs; |
| 518 | | if (lhs.isMemory() and rhs.isMemory()) { |
| 519 | | dst_mcv = try self.copyToNewRegister(op_rhs); |
| 520 | | src_mcv = lhs; |
| 521 | | } else { |
| 522 | | dst_mcv = rhs; |
| 523 | | src_mcv = lhs; |
| 523 | } |
| 524 | |
| 525 | fn genSub(self: *Self, inst: *ir.Inst.BinOp) !MCValue { |
| 526 | // No side effects, so if it's unreferenced, do nothing. |
| 527 | if (inst.base.isUnused()) |
| 528 | return MCValue.dead; |
| 529 | switch (arch) { |
| 530 | .x86_64 => { |
| 531 | return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 5, 0x28); |
| 532 | }, |
| 533 | else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), |
| 524 | 534 | } |
| 525 | | } else { |
| 526 | | if (lhs.isMemory()) { |
| 527 | | dst_mcv = try self.copyToNewRegister(op_lhs); |
| 528 | | src_mcv = rhs; |
| 535 | } |
| 536 | |
| 537 | /// ADD, SUB, XOR, OR, AND |
| 538 | fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue { |
| 539 | try self.code.ensureCapacity(self.code.items.len + 8); |
| 540 | |
| 541 | const lhs = try self.resolveInst(op_lhs); |
| 542 | const rhs = try self.resolveInst(op_rhs); |
| 543 | |
| 544 | // There are 2 operands, destination and source. |
| 545 | // Either one, but not both, can be a memory operand. |
| 546 | // Source operand can be an immediate, 8 bits or 32 bits. |
| 547 | // So, if either one of the operands dies with this instruction, we can use it |
| 548 | // as the result MCValue. |
| 549 | var dst_mcv: MCValue = undefined; |
| 550 | var src_mcv: MCValue = undefined; |
| 551 | var src_inst: *ir.Inst = undefined; |
| 552 | if (inst.operandDies(0) and lhs.isMutable()) { |
| 553 | // LHS dies; use it as the destination. |
| 554 | // Both operands cannot be memory. |
| 529 | 555 | src_inst = op_rhs; |
| 530 | | } else { |
| 531 | | dst_mcv = try self.copyToNewRegister(op_rhs); |
| 532 | | src_mcv = lhs; |
| 556 | if (lhs.isMemory() and rhs.isMemory()) { |
| 557 | dst_mcv = try self.copyToNewRegister(op_lhs); |
| 558 | src_mcv = rhs; |
| 559 | } else { |
| 560 | dst_mcv = lhs; |
| 561 | src_mcv = rhs; |
| 562 | } |
| 563 | } else if (inst.operandDies(1) and rhs.isMutable()) { |
| 564 | // RHS dies; use it as the destination. |
| 565 | // Both operands cannot be memory. |
| 533 | 566 | src_inst = op_lhs; |
| 567 | if (lhs.isMemory() and rhs.isMemory()) { |
| 568 | dst_mcv = try self.copyToNewRegister(op_rhs); |
| 569 | src_mcv = lhs; |
| 570 | } else { |
| 571 | dst_mcv = rhs; |
| 572 | src_mcv = lhs; |
| 573 | } |
| 574 | } else { |
| 575 | if (lhs.isMemory()) { |
| 576 | dst_mcv = try self.copyToNewRegister(op_lhs); |
| 577 | src_mcv = rhs; |
| 578 | src_inst = op_rhs; |
| 579 | } else { |
| 580 | dst_mcv = try self.copyToNewRegister(op_rhs); |
| 581 | src_mcv = lhs; |
| 582 | src_inst = op_lhs; |
| 583 | } |
| 584 | } |
| 585 | // This instruction supports only signed 32-bit immediates at most. If the immediate |
| 586 | // value is larger than this, we put it in a register. |
| 587 | // A potential opportunity for future optimization here would be keeping track |
| 588 | // of the fact that the instruction is available both as an immediate |
| 589 | // and as a register. |
| 590 | switch (src_mcv) { |
| 591 | .immediate => |imm| { |
| 592 | if (imm > std.math.maxInt(u31)) { |
| 593 | src_mcv = try self.copyToNewRegister(src_inst); |
| 594 | } |
| 595 | }, |
| 596 | else => {}, |
| 534 | 597 | } |
| 598 | |
| 599 | try self.genX8664BinMathCode(inst.src, dst_mcv, src_mcv, opx, mr); |
| 600 | |
| 601 | return dst_mcv; |
| 535 | 602 | } |
| 536 | | // This instruction supports only signed 32-bit immediates at most. If the immediate |
| 537 | | // value is larger than this, we put it in a register. |
| 538 | | // A potential opportunity for future optimization here would be keeping track |
| 539 | | // of the fact that the instruction is available both as an immediate |
| 540 | | // and as a register. |
| 541 | | switch (src_mcv) { |
| 542 | | .immediate => |imm| { |
| 543 | | if (imm > std.math.maxInt(u31)) { |
| 544 | | src_mcv = try self.copyToNewRegister(src_inst); |
| 545 | | } |
| 546 | | }, |
| 547 | | else => {}, |
| 603 | |
| 604 | fn genX8664BinMathCode(self: *Self, src: usize, dst_mcv: MCValue, src_mcv: MCValue, opx: u8, mr: u8) !void { |
| 605 | switch (dst_mcv) { |
| 606 | .none => unreachable, |
| 607 | .dead, .unreach, .immediate => unreachable, |
| 608 | .compare_flags_unsigned => unreachable, |
| 609 | .compare_flags_signed => unreachable, |
| 610 | .register => |dst_reg| { |
| 611 | switch (src_mcv) { |
| 612 | .none => unreachable, |
| 613 | .dead, .unreach => unreachable, |
| 614 | .register => |src_reg| { |
| 615 | self.rex(.{ .b = dst_reg.isExtended(), .r = src_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 616 | self.code.appendSliceAssumeCapacity(&[_]u8{ mr + 0x1, 0xC0 | (@as(u8, src_reg.id() & 0b111) << 3) | @as(u8, dst_reg.id() & 0b111) }); |
| 617 | }, |
| 618 | .immediate => |imm| { |
| 619 | const imm32 = @intCast(u31, imm); // This case must be handled before calling genX8664BinMathCode. |
| 620 | // 81 /opx id |
| 621 | if (imm32 <= std.math.maxInt(u7)) { |
| 622 | self.rex(.{ .b = dst_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 623 | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 624 | 0x83, |
| 625 | 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()), |
| 626 | @intCast(u8, imm32), |
| 627 | }); |
| 628 | } else { |
| 629 | self.rex(.{ .r = dst_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 630 | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 631 | 0x81, |
| 632 | 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()), |
| 633 | }); |
| 634 | std.mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), imm32); |
| 635 | } |
| 636 | }, |
| 637 | .embedded_in_code, .memory, .stack_offset => { |
| 638 | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source memory", .{}); |
| 639 | }, |
| 640 | .compare_flags_unsigned => { |
| 641 | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (unsigned)", .{}); |
| 642 | }, |
| 643 | .compare_flags_signed => { |
| 644 | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (signed)", .{}); |
| 645 | }, |
| 646 | } |
| 647 | }, |
| 648 | .embedded_in_code, .memory, .stack_offset => { |
| 649 | return self.fail(src, "TODO implement x86 ADD/SUB/CMP destination memory", .{}); |
| 650 | }, |
| 651 | } |
| 548 | 652 | } |
| 549 | 653 | |
| 550 | | try self.genX8664BinMathCode(inst.src, dst_mcv, src_mcv, opx, mr); |
| 654 | fn genArg(self: *Self, inst: *ir.Inst.NoOp) !MCValue { |
| 655 | if (FreeRegInt == u0) { |
| 656 | return self.fail(inst.base.src, "TODO implement Register enum for {}", .{self.target.cpu.arch}); |
| 657 | } |
| 658 | if (inst.base.isUnused()) |
| 659 | return MCValue.dead; |
| 551 | 660 | |
| 552 | | return dst_mcv; |
| 553 | | } |
| 661 | const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; |
| 662 | try branch.registers.ensureCapacity(self.gpa, branch.registers.items().len + 1); |
| 554 | 663 | |
| 555 | | fn genX8664BinMathCode(self: *Function, src: usize, dst_mcv: MCValue, src_mcv: MCValue, opx: u8, mr: u8) !void { |
| 556 | | switch (dst_mcv) { |
| 557 | | .none => unreachable, |
| 558 | | .dead, .unreach, .immediate => unreachable, |
| 559 | | .compare_flags_unsigned => unreachable, |
| 560 | | .compare_flags_signed => unreachable, |
| 561 | | .register => |dst_reg_usize| { |
| 562 | | const dst_reg = @intToEnum(Reg(.x86_64), @intCast(u8, dst_reg_usize)); |
| 563 | | switch (src_mcv) { |
| 564 | | .none => unreachable, |
| 565 | | .dead, .unreach => unreachable, |
| 566 | | .register => |src_reg_usize| { |
| 567 | | const src_reg = @intToEnum(Reg(.x86_64), @intCast(u8, src_reg_usize)); |
| 568 | | self.rex(.{ .b = dst_reg.isExtended(), .r = src_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 569 | | self.code.appendSliceAssumeCapacity(&[_]u8{ mr + 0x1, 0xC0 | (@as(u8, src_reg.id() & 0b111) << 3) | @as(u8, dst_reg.id() & 0b111) }); |
| 570 | | }, |
| 571 | | .immediate => |imm| { |
| 572 | | const imm32 = @intCast(u31, imm); // This case must be handled before calling genX8664BinMathCode. |
| 573 | | // 81 /opx id |
| 574 | | if (imm32 <= std.math.maxInt(u7)) { |
| 575 | | self.rex(.{ .b = dst_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 576 | | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 577 | | 0x83, |
| 578 | | 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()), |
| 579 | | @intCast(u8, imm32), |
| 580 | | }); |
| 581 | | } else { |
| 582 | | self.rex(.{ .r = dst_reg.isExtended(), .w = dst_reg.size() == 64 }); |
| 583 | | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 584 | | 0x81, |
| 585 | | 0xC0 | (opx << 3) | @truncate(u3, dst_reg.id()), |
| 586 | | }); |
| 587 | | std.mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), imm32); |
| 588 | | } |
| 589 | | }, |
| 590 | | .embedded_in_code, .memory, .stack_offset => { |
| 591 | | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source memory", .{}); |
| 592 | | }, |
| 593 | | .compare_flags_unsigned => { |
| 594 | | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (unsigned)", .{}); |
| 595 | | }, |
| 596 | | .compare_flags_signed => { |
| 597 | | return self.fail(src, "TODO implement x86 ADD/SUB/CMP source compare flag (signed)", .{}); |
| 598 | | }, |
| 599 | | } |
| 600 | | }, |
| 601 | | .embedded_in_code, .memory, .stack_offset => { |
| 602 | | return self.fail(src, "TODO implement x86 ADD/SUB/CMP destination memory", .{}); |
| 603 | | }, |
| 604 | | } |
| 605 | | } |
| 664 | const result = self.args[self.arg_index]; |
| 665 | self.arg_index += 1; |
| 606 | 666 | |
| 607 | | fn genArg(self: *Function, inst: *ir.Inst.Arg) !MCValue { |
| 608 | | const i = self.arg_index; |
| 609 | | self.arg_index += 1; |
| 610 | | return self.args[i]; |
| 611 | | } |
| 667 | switch (result) { |
| 668 | .register => |reg| { |
| 669 | branch.registers.putAssumeCapacityNoClobber(reg, .{ .inst = &inst.base }); |
| 670 | branch.markRegUsed(reg); |
| 671 | }, |
| 672 | else => {}, |
| 673 | } |
| 674 | return result; |
| 675 | } |
| 612 | 676 | |
| 613 | | fn genBreakpoint(self: *Function, src: usize, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 614 | | switch (arch) { |
| 615 | | .i386, .x86_64 => { |
| 616 | | try self.code.append(0xcc); // int3 |
| 617 | | }, |
| 618 | | else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.target.cpu.arch}), |
| 677 | fn genBreakpoint(self: *Self, src: usize) !MCValue { |
| 678 | switch (arch) { |
| 679 | .i386, .x86_64 => { |
| 680 | try self.code.append(0xcc); // int3 |
| 681 | }, |
| 682 | else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.target.cpu.arch}), |
| 683 | } |
| 684 | return .none; |
| 619 | 685 | } |
| 620 | | return .none; |
| 621 | | } |
| 622 | 686 | |
| 623 | | fn genCall(self: *Function, inst: *ir.Inst.Call, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 624 | | const fn_ty = inst.args.func.ty; |
| 625 | | const cc = fn_ty.fnCallingConvention(); |
| 626 | | const param_types = try self.gpa.alloc(Type, fn_ty.fnParamLen()); |
| 627 | | defer self.gpa.free(param_types); |
| 628 | | fn_ty.fnParamTypes(param_types); |
| 629 | | var mc_args = try self.gpa.alloc(MCValue, param_types.len); |
| 630 | | defer self.gpa.free(mc_args); |
| 631 | | const stack_byte_count = try self.resolveParameters(inst.base.src, cc, param_types, mc_args); |
| 632 | | |
| 633 | | switch (arch) { |
| 634 | | .x86_64 => { |
| 635 | | for (mc_args) |mc_arg, arg_i| { |
| 636 | | const arg = inst.args.args[arg_i]; |
| 637 | | const arg_mcv = try self.resolveInst(inst.args.args[arg_i]); |
| 638 | | switch (mc_arg) { |
| 639 | | .none => continue, |
| 640 | | .register => |reg| { |
| 641 | | try self.genSetReg(arg.src, arch, @intToEnum(Reg(arch), @intCast(u8, reg)), arg_mcv); |
| 642 | | // TODO interact with the register allocator to mark the instruction as moved. |
| 643 | | }, |
| 644 | | .stack_offset => { |
| 645 | | // Here we need to emit instructions like this: |
| 646 | | // mov qword ptr [rsp + stack_offset], x |
| 647 | | return self.fail(inst.base.src, "TODO implement calling with parameters in memory", .{}); |
| 648 | | }, |
| 649 | | .immediate => unreachable, |
| 650 | | .unreach => unreachable, |
| 651 | | .dead => unreachable, |
| 652 | | .embedded_in_code => unreachable, |
| 653 | | .memory => unreachable, |
| 654 | | .compare_flags_signed => unreachable, |
| 655 | | .compare_flags_unsigned => unreachable, |
| 687 | fn genCall(self: *Self, inst: *ir.Inst.Call) !MCValue { |
| 688 | const fn_ty = inst.func.ty; |
| 689 | const cc = fn_ty.fnCallingConvention(); |
| 690 | const param_types = try self.gpa.alloc(Type, fn_ty.fnParamLen()); |
| 691 | defer self.gpa.free(param_types); |
| 692 | fn_ty.fnParamTypes(param_types); |
| 693 | var mc_args = try self.gpa.alloc(MCValue, param_types.len); |
| 694 | defer self.gpa.free(mc_args); |
| 695 | const stack_byte_count = try self.resolveParameters(inst.base.src, cc, param_types, mc_args); |
| 696 | |
| 697 | switch (arch) { |
| 698 | .x86_64 => { |
| 699 | for (mc_args) |mc_arg, arg_i| { |
| 700 | const arg = inst.args[arg_i]; |
| 701 | const arg_mcv = try self.resolveInst(inst.args[arg_i]); |
| 702 | switch (mc_arg) { |
| 703 | .none => continue, |
| 704 | .register => |reg| { |
| 705 | try self.genSetReg(arg.src, reg, arg_mcv); |
| 706 | // TODO interact with the register allocator to mark the instruction as moved. |
| 707 | }, |
| 708 | .stack_offset => { |
| 709 | // Here we need to emit instructions like this: |
| 710 | // mov qword ptr [rsp + stack_offset], x |
| 711 | return self.fail(inst.base.src, "TODO implement calling with parameters in memory", .{}); |
| 712 | }, |
| 713 | .immediate => unreachable, |
| 714 | .unreach => unreachable, |
| 715 | .dead => unreachable, |
| 716 | .embedded_in_code => unreachable, |
| 717 | .memory => unreachable, |
| 718 | .compare_flags_signed => unreachable, |
| 719 | .compare_flags_unsigned => unreachable, |
| 720 | } |
| 656 | 721 | } |
| 657 | | } |
| 658 | 722 | |
| 659 | | if (inst.args.func.cast(ir.Inst.Constant)) |func_inst| { |
| 660 | | if (func_inst.val.cast(Value.Payload.Function)) |func_val| { |
| 661 | | const func = func_val.func; |
| 662 | | const got = &self.bin_file.program_headers.items[self.bin_file.phdr_got_index.?]; |
| 663 | | const ptr_bits = self.target.cpu.arch.ptrBitWidth(); |
| 664 | | const ptr_bytes: u64 = @divExact(ptr_bits, 8); |
| 665 | | const got_addr = @intCast(u32, got.p_vaddr + func.owner_decl.link.offset_table_index * ptr_bytes); |
| 666 | | // ff 14 25 xx xx xx xx call [addr] |
| 667 | | try self.code.ensureCapacity(self.code.items.len + 7); |
| 668 | | self.code.appendSliceAssumeCapacity(&[3]u8{ 0xff, 0x14, 0x25 }); |
| 669 | | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), got_addr); |
| 723 | if (inst.func.cast(ir.Inst.Constant)) |func_inst| { |
| 724 | if (func_inst.val.cast(Value.Payload.Function)) |func_val| { |
| 725 | const func = func_val.func; |
| 726 | const got = &self.bin_file.program_headers.items[self.bin_file.phdr_got_index.?]; |
| 727 | const ptr_bits = self.target.cpu.arch.ptrBitWidth(); |
| 728 | const ptr_bytes: u64 = @divExact(ptr_bits, 8); |
| 729 | const got_addr = @intCast(u32, got.p_vaddr + func.owner_decl.link.offset_table_index * ptr_bytes); |
| 730 | // ff 14 25 xx xx xx xx call [addr] |
| 731 | try self.code.ensureCapacity(self.code.items.len + 7); |
| 732 | self.code.appendSliceAssumeCapacity(&[3]u8{ 0xff, 0x14, 0x25 }); |
| 733 | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), got_addr); |
| 734 | } else { |
| 735 | return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{}); |
| 736 | } |
| 670 | 737 | } else { |
| 671 | | return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{}); |
| 738 | return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{}); |
| 672 | 739 | } |
| 673 | | } else { |
| 674 | | return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{}); |
| 675 | | } |
| 676 | | }, |
| 677 | | else => return self.fail(inst.base.src, "TODO implement call for {}", .{self.target.cpu.arch}), |
| 678 | | } |
| 740 | }, |
| 741 | else => return self.fail(inst.base.src, "TODO implement call for {}", .{self.target.cpu.arch}), |
| 742 | } |
| 679 | 743 | |
| 680 | | const return_type = fn_ty.fnReturnType(); |
| 681 | | switch (return_type.zigTypeTag()) { |
| 682 | | .Void => return MCValue{ .none = {} }, |
| 683 | | .NoReturn => return MCValue{ .unreach = {} }, |
| 684 | | else => return self.fail(inst.base.src, "TODO implement fn call with non-void return value", .{}), |
| 744 | const return_type = fn_ty.fnReturnType(); |
| 745 | switch (return_type.zigTypeTag()) { |
| 746 | .Void => return MCValue{ .none = {} }, |
| 747 | .NoReturn => return MCValue{ .unreach = {} }, |
| 748 | else => return self.fail(inst.base.src, "TODO implement fn call with non-void return value", .{}), |
| 749 | } |
| 685 | 750 | } |
| 686 | | } |
| 687 | 751 | |
| 688 | | fn ret(self: *Function, src: usize, comptime arch: std.Target.Cpu.Arch, mcv: MCValue) !MCValue { |
| 689 | | if (mcv != .none) { |
| 690 | | return self.fail(src, "TODO implement return with non-void operand", .{}); |
| 691 | | } |
| 692 | | switch (arch) { |
| 693 | | .i386 => { |
| 694 | | try self.code.append(0xc3); // ret |
| 695 | | }, |
| 696 | | .x86_64 => { |
| 697 | | try self.code.appendSlice(&[_]u8{ |
| 698 | | 0x5d, // pop rbp |
| 699 | | 0xc3, // ret |
| 700 | | }); |
| 701 | | }, |
| 702 | | else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}), |
| 752 | fn ret(self: *Self, src: usize, mcv: MCValue) !MCValue { |
| 753 | if (mcv != .none) { |
| 754 | return self.fail(src, "TODO implement return with non-void operand", .{}); |
| 755 | } |
| 756 | switch (arch) { |
| 757 | .i386 => { |
| 758 | try self.code.append(0xc3); // ret |
| 759 | }, |
| 760 | .x86_64 => { |
| 761 | try self.code.appendSlice(&[_]u8{ |
| 762 | 0x5d, // pop rbp |
| 763 | 0xc3, // ret |
| 764 | }); |
| 765 | }, |
| 766 | else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}), |
| 767 | } |
| 768 | return .unreach; |
| 703 | 769 | } |
| 704 | | return .unreach; |
| 705 | | } |
| 706 | | |
| 707 | | fn genRet(self: *Function, inst: *ir.Inst.Ret, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 708 | | const operand = try self.resolveInst(inst.args.operand); |
| 709 | | return self.ret(inst.base.src, arch, operand); |
| 710 | | } |
| 711 | 770 | |
| 712 | | fn genRetVoid(self: *Function, inst: *ir.Inst.RetVoid, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 713 | | return self.ret(inst.base.src, arch, .none); |
| 714 | | } |
| 771 | fn genRet(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 772 | const operand = try self.resolveInst(inst.operand); |
| 773 | return self.ret(inst.base.src, operand); |
| 774 | } |
| 715 | 775 | |
| 716 | | fn genCmp(self: *Function, inst: *ir.Inst.Cmp, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 717 | | // No side effects, so if it's unreferenced, do nothing. |
| 718 | | if (inst.base.isUnused()) |
| 719 | | return MCValue.dead; |
| 720 | | switch (arch) { |
| 721 | | .x86_64 => { |
| 722 | | try self.code.ensureCapacity(self.code.items.len + 8); |
| 723 | | |
| 724 | | const lhs = try self.resolveInst(inst.args.lhs); |
| 725 | | const rhs = try self.resolveInst(inst.args.rhs); |
| 726 | | |
| 727 | | // There are 2 operands, destination and source. |
| 728 | | // Either one, but not both, can be a memory operand. |
| 729 | | // Source operand can be an immediate, 8 bits or 32 bits. |
| 730 | | const dst_mcv = if (lhs.isImmediate() or (lhs.isMemory() and rhs.isMemory())) |
| 731 | | try self.copyToNewRegister(inst.args.lhs) |
| 732 | | else |
| 733 | | lhs; |
| 734 | | // This instruction supports only signed 32-bit immediates at most. |
| 735 | | const src_mcv = try self.limitImmediateType(inst.args.rhs, i32); |
| 736 | | |
| 737 | | try self.genX8664BinMathCode(inst.base.src, dst_mcv, src_mcv, 7, 0x38); |
| 738 | | const info = inst.args.lhs.ty.intInfo(self.target.*); |
| 739 | | if (info.signed) { |
| 740 | | return MCValue{ .compare_flags_signed = inst.args.op }; |
| 741 | | } else { |
| 742 | | return MCValue{ .compare_flags_unsigned = inst.args.op }; |
| 743 | | } |
| 744 | | }, |
| 745 | | else => return self.fail(inst.base.src, "TODO implement cmp for {}", .{self.target.cpu.arch}), |
| 776 | fn genRetVoid(self: *Self, inst: *ir.Inst.NoOp) !MCValue { |
| 777 | return self.ret(inst.base.src, .none); |
| 746 | 778 | } |
| 747 | | } |
| 748 | 779 | |
| 749 | | fn genCondBr(self: *Function, inst: *ir.Inst.CondBr, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 750 | | switch (arch) { |
| 751 | | .x86_64 => { |
| 752 | | try self.code.ensureCapacity(self.code.items.len + 6); |
| 753 | | |
| 754 | | const cond = try self.resolveInst(inst.args.condition); |
| 755 | | switch (cond) { |
| 756 | | .compare_flags_signed => |cmp_op| { |
| 757 | | // Here we map to the opposite opcode because the jump is to the false branch. |
| 758 | | const opcode: u8 = switch (cmp_op) { |
| 759 | | .gte => 0x8c, |
| 760 | | .gt => 0x8e, |
| 761 | | .neq => 0x84, |
| 762 | | .lt => 0x8d, |
| 763 | | .lte => 0x8f, |
| 764 | | .eq => 0x85, |
| 765 | | }; |
| 766 | | return self.genX86CondBr(inst, opcode, arch); |
| 767 | | }, |
| 768 | | .compare_flags_unsigned => |cmp_op| { |
| 769 | | // Here we map to the opposite opcode because the jump is to the false branch. |
| 770 | | const opcode: u8 = switch (cmp_op) { |
| 771 | | .gte => 0x82, |
| 772 | | .gt => 0x86, |
| 773 | | .neq => 0x84, |
| 774 | | .lt => 0x83, |
| 775 | | .lte => 0x87, |
| 776 | | .eq => 0x85, |
| 777 | | }; |
| 778 | | return self.genX86CondBr(inst, opcode, arch); |
| 779 | | }, |
| 780 | | .register => |reg_usize| { |
| 781 | | const reg = @intToEnum(Reg(arch), @intCast(u8, reg_usize)); |
| 782 | | // test reg, 1 |
| 783 | | // TODO detect al, ax, eax |
| 784 | | try self.code.ensureCapacity(self.code.items.len + 4); |
| 785 | | self.rex(.{ .b = reg.isExtended(), .w = reg.size() == 64 }); |
| 786 | | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 787 | | 0xf6, |
| 788 | | @as(u8, 0xC0) | (0 << 3) | @truncate(u3, reg.id()), |
| 789 | | 0x01, |
| 790 | | }); |
| 791 | | return self.genX86CondBr(inst, 0x84, arch); |
| 792 | | }, |
| 793 | | else => return self.fail(inst.base.src, "TODO implement condbr {} when condition is {}", .{ self.target.cpu.arch, @tagName(cond) }), |
| 794 | | } |
| 795 | | }, |
| 796 | | else => return self.fail(inst.base.src, "TODO implement condbr for {}", .{self.target.cpu.arch}), |
| 780 | fn genCmp(self: *Self, inst: *ir.Inst.BinOp, op: std.math.CompareOperator) !MCValue { |
| 781 | // No side effects, so if it's unreferenced, do nothing. |
| 782 | if (inst.base.isUnused()) |
| 783 | return MCValue.dead; |
| 784 | switch (arch) { |
| 785 | .x86_64 => { |
| 786 | try self.code.ensureCapacity(self.code.items.len + 8); |
| 787 | |
| 788 | const lhs = try self.resolveInst(inst.lhs); |
| 789 | const rhs = try self.resolveInst(inst.rhs); |
| 790 | |
| 791 | // There are 2 operands, destination and source. |
| 792 | // Either one, but not both, can be a memory operand. |
| 793 | // Source operand can be an immediate, 8 bits or 32 bits. |
| 794 | const dst_mcv = if (lhs.isImmediate() or (lhs.isMemory() and rhs.isMemory())) |
| 795 | try self.copyToNewRegister(inst.lhs) |
| 796 | else |
| 797 | lhs; |
| 798 | // This instruction supports only signed 32-bit immediates at most. |
| 799 | const src_mcv = try self.limitImmediateType(inst.rhs, i32); |
| 800 | |
| 801 | try self.genX8664BinMathCode(inst.base.src, dst_mcv, src_mcv, 7, 0x38); |
| 802 | const info = inst.lhs.ty.intInfo(self.target.*); |
| 803 | if (info.signed) { |
| 804 | return MCValue{ .compare_flags_signed = op }; |
| 805 | } else { |
| 806 | return MCValue{ .compare_flags_unsigned = op }; |
| 807 | } |
| 808 | }, |
| 809 | else => return self.fail(inst.base.src, "TODO implement cmp for {}", .{self.target.cpu.arch}), |
| 810 | } |
| 797 | 811 | } |
| 798 | | } |
| 799 | 812 | |
| 800 | | fn genX86CondBr(self: *Function, inst: *ir.Inst.CondBr, opcode: u8, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 801 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x0f, opcode }); |
| 802 | | const reloc = Reloc{ .rel32 = self.code.items.len }; |
| 803 | | self.code.items.len += 4; |
| 804 | | try self.genBody(inst.args.true_body, arch); |
| 805 | | try self.performReloc(inst.base.src, reloc); |
| 806 | | try self.genBody(inst.args.false_body, arch); |
| 807 | | return MCValue.unreach; |
| 808 | | } |
| 813 | fn genCondBr(self: *Self, inst: *ir.Inst.CondBr) !MCValue { |
| 814 | switch (arch) { |
| 815 | .x86_64 => { |
| 816 | try self.code.ensureCapacity(self.code.items.len + 6); |
| 817 | |
| 818 | const cond = try self.resolveInst(inst.condition); |
| 819 | switch (cond) { |
| 820 | .compare_flags_signed => |cmp_op| { |
| 821 | // Here we map to the opposite opcode because the jump is to the false branch. |
| 822 | const opcode: u8 = switch (cmp_op) { |
| 823 | .gte => 0x8c, |
| 824 | .gt => 0x8e, |
| 825 | .neq => 0x84, |
| 826 | .lt => 0x8d, |
| 827 | .lte => 0x8f, |
| 828 | .eq => 0x85, |
| 829 | }; |
| 830 | return self.genX86CondBr(inst, opcode); |
| 831 | }, |
| 832 | .compare_flags_unsigned => |cmp_op| { |
| 833 | // Here we map to the opposite opcode because the jump is to the false branch. |
| 834 | const opcode: u8 = switch (cmp_op) { |
| 835 | .gte => 0x82, |
| 836 | .gt => 0x86, |
| 837 | .neq => 0x84, |
| 838 | .lt => 0x83, |
| 839 | .lte => 0x87, |
| 840 | .eq => 0x85, |
| 841 | }; |
| 842 | return self.genX86CondBr(inst, opcode); |
| 843 | }, |
| 844 | .register => |reg| { |
| 845 | // test reg, 1 |
| 846 | // TODO detect al, ax, eax |
| 847 | try self.code.ensureCapacity(self.code.items.len + 4); |
| 848 | self.rex(.{ .b = reg.isExtended(), .w = reg.size() == 64 }); |
| 849 | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 850 | 0xf6, |
| 851 | @as(u8, 0xC0) | (0 << 3) | @truncate(u3, reg.id()), |
| 852 | 0x01, |
| 853 | }); |
| 854 | return self.genX86CondBr(inst, 0x84); |
| 855 | }, |
| 856 | else => return self.fail(inst.base.src, "TODO implement condbr {} when condition is {}", .{ self.target.cpu.arch, @tagName(cond) }), |
| 857 | } |
| 858 | }, |
| 859 | else => return self.fail(inst.base.src, "TODO implement condbr for {}", .{self.target.cpu.arch}), |
| 860 | } |
| 861 | } |
| 809 | 862 | |
| 810 | | fn genIsNull(self: *Function, inst: *ir.Inst.IsNull, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 811 | | switch (arch) { |
| 812 | | else => return self.fail(inst.base.src, "TODO implement isnull for {}", .{self.target.cpu.arch}), |
| 863 | fn genX86CondBr(self: *Self, inst: *ir.Inst.CondBr, opcode: u8) !MCValue { |
| 864 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x0f, opcode }); |
| 865 | const reloc = Reloc{ .rel32 = self.code.items.len }; |
| 866 | self.code.items.len += 4; |
| 867 | try self.genBody(inst.then_body); |
| 868 | try self.performReloc(inst.base.src, reloc); |
| 869 | try self.genBody(inst.else_body); |
| 870 | return MCValue.unreach; |
| 813 | 871 | } |
| 814 | | } |
| 815 | 872 | |
| 816 | | fn genIsNonNull(self: *Function, inst: *ir.Inst.IsNonNull, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 817 | | // Here you can specialize this instruction if it makes sense to, otherwise the default |
| 818 | | // will call genIsNull and invert the result. |
| 819 | | switch (arch) { |
| 820 | | else => return self.fail(inst.base.src, "TODO call genIsNull and invert the result ", .{}), |
| 873 | fn genIsNull(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 874 | switch (arch) { |
| 875 | else => return self.fail(inst.base.src, "TODO implement isnull for {}", .{self.target.cpu.arch}), |
| 876 | } |
| 821 | 877 | } |
| 822 | | } |
| 823 | 878 | |
| 824 | | fn genBlock(self: *Function, inst: *ir.Inst.Block, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 825 | | if (inst.base.ty.hasCodeGenBits()) { |
| 826 | | return self.fail(inst.base.src, "TODO codegen Block with non-void type", .{}); |
| 879 | fn genIsNonNull(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 880 | // Here you can specialize this instruction if it makes sense to, otherwise the default |
| 881 | // will call genIsNull and invert the result. |
| 882 | switch (arch) { |
| 883 | else => return self.fail(inst.base.src, "TODO call genIsNull and invert the result ", .{}), |
| 884 | } |
| 827 | 885 | } |
| 828 | | // A block is nothing but a setup to be able to jump to the end. |
| 829 | | defer inst.codegen.relocs.deinit(self.gpa); |
| 830 | | try self.genBody(inst.args.body, arch); |
| 831 | 886 | |
| 832 | | for (inst.codegen.relocs.items) |reloc| try self.performReloc(inst.base.src, reloc); |
| 887 | fn genBlock(self: *Self, inst: *ir.Inst.Block) !MCValue { |
| 888 | if (inst.base.ty.hasCodeGenBits()) { |
| 889 | return self.fail(inst.base.src, "TODO codegen Block with non-void type", .{}); |
| 890 | } |
| 891 | // A block is nothing but a setup to be able to jump to the end. |
| 892 | defer inst.codegen.relocs.deinit(self.gpa); |
| 893 | try self.genBody(inst.body); |
| 833 | 894 | |
| 834 | | return MCValue.none; |
| 835 | | } |
| 895 | for (inst.codegen.relocs.items) |reloc| try self.performReloc(inst.base.src, reloc); |
| 836 | 896 | |
| 837 | | fn performReloc(self: *Function, src: usize, reloc: Reloc) !void { |
| 838 | | switch (reloc) { |
| 839 | | .rel32 => |pos| { |
| 840 | | const amt = self.code.items.len - (pos + 4); |
| 841 | | const s32_amt = std.math.cast(i32, amt) catch |
| 842 | | return self.fail(src, "unable to perform relocation: jump too far", .{}); |
| 843 | | mem.writeIntLittle(i32, self.code.items[pos..][0..4], s32_amt); |
| 844 | | }, |
| 897 | return MCValue.none; |
| 845 | 898 | } |
| 846 | | } |
| 847 | 899 | |
| 848 | | fn genBr(self: *Function, inst: *ir.Inst.Br, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 849 | | if (!inst.args.operand.ty.hasCodeGenBits()) |
| 850 | | return self.brVoid(inst.base.src, inst.args.block, arch); |
| 851 | | |
| 852 | | const operand = try self.resolveInst(inst.args.operand); |
| 853 | | switch (arch) { |
| 854 | | else => return self.fail(inst.base.src, "TODO implement br for {}", .{self.target.cpu.arch}), |
| 900 | fn performReloc(self: *Self, src: usize, reloc: Reloc) !void { |
| 901 | switch (reloc) { |
| 902 | .rel32 => |pos| { |
| 903 | const amt = self.code.items.len - (pos + 4); |
| 904 | const s32_amt = std.math.cast(i32, amt) catch |
| 905 | return self.fail(src, "unable to perform relocation: jump too far", .{}); |
| 906 | mem.writeIntLittle(i32, self.code.items[pos..][0..4], s32_amt); |
| 907 | }, |
| 908 | } |
| 855 | 909 | } |
| 856 | | } |
| 857 | 910 | |
| 858 | | fn genBrVoid(self: *Function, inst: *ir.Inst.BrVoid, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 859 | | return self.brVoid(inst.base.src, inst.args.block, arch); |
| 860 | | } |
| 911 | fn genBr(self: *Self, inst: *ir.Inst.Br) !MCValue { |
| 912 | if (!inst.operand.ty.hasCodeGenBits()) |
| 913 | return self.brVoid(inst.base.src, inst.block); |
| 861 | 914 | |
| 862 | | fn brVoid(self: *Function, src: usize, block: *ir.Inst.Block, comptime arch: std.Target.Cpu.Arch) !MCValue { |
| 863 | | // Emit a jump with a relocation. It will be patched up after the block ends. |
| 864 | | try block.codegen.relocs.ensureCapacity(self.gpa, block.codegen.relocs.items.len + 1); |
| 865 | | |
| 866 | | switch (arch) { |
| 867 | | .i386, .x86_64 => { |
| 868 | | // TODO optimization opportunity: figure out when we can emit this as a 2 byte instruction |
| 869 | | // which is available if the jump is 127 bytes or less forward. |
| 870 | | try self.code.resize(self.code.items.len + 5); |
| 871 | | self.code.items[self.code.items.len - 5] = 0xe9; // jmp rel32 |
| 872 | | // Leave the jump offset undefined |
| 873 | | block.codegen.relocs.appendAssumeCapacity(.{ .rel32 = self.code.items.len - 4 }); |
| 874 | | }, |
| 875 | | else => return self.fail(src, "TODO implement brvoid for {}", .{self.target.cpu.arch}), |
| 915 | const operand = try self.resolveInst(inst.operand); |
| 916 | switch (arch) { |
| 917 | else => return self.fail(inst.base.src, "TODO implement br for {}", .{self.target.cpu.arch}), |
| 918 | } |
| 876 | 919 | } |
| 877 | | return .none; |
| 878 | | } |
| 879 | 920 | |
| 880 | | fn genAsm(self: *Function, inst: *ir.Inst.Assembly, comptime arch: Target.Cpu.Arch) !MCValue { |
| 881 | | if (!inst.args.is_volatile and inst.base.isUnused()) |
| 882 | | return MCValue.dead; |
| 883 | | if (arch != .x86_64 and arch != .i386) { |
| 884 | | return self.fail(inst.base.src, "TODO implement inline asm support for more architectures", .{}); |
| 921 | fn genBrVoid(self: *Self, inst: *ir.Inst.BrVoid) !MCValue { |
| 922 | return self.brVoid(inst.base.src, inst.block); |
| 885 | 923 | } |
| 886 | | for (inst.args.inputs) |input, i| { |
| 887 | | if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') { |
| 888 | | return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input}); |
| 924 | |
| 925 | fn brVoid(self: *Self, src: usize, block: *ir.Inst.Block) !MCValue { |
| 926 | // Emit a jump with a relocation. It will be patched up after the block ends. |
| 927 | try block.codegen.relocs.ensureCapacity(self.gpa, block.codegen.relocs.items.len + 1); |
| 928 | |
| 929 | switch (arch) { |
| 930 | .i386, .x86_64 => { |
| 931 | // TODO optimization opportunity: figure out when we can emit this as a 2 byte instruction |
| 932 | // which is available if the jump is 127 bytes or less forward. |
| 933 | try self.code.resize(self.code.items.len + 5); |
| 934 | self.code.items[self.code.items.len - 5] = 0xe9; // jmp rel32 |
| 935 | // Leave the jump offset undefined |
| 936 | block.codegen.relocs.appendAssumeCapacity(.{ .rel32 = self.code.items.len - 4 }); |
| 937 | }, |
| 938 | else => return self.fail(src, "TODO implement brvoid for {}", .{self.target.cpu.arch}), |
| 889 | 939 | } |
| 890 | | const reg_name = input[1 .. input.len - 1]; |
| 891 | | const reg = parseRegName(arch, reg_name) orelse |
| 892 | | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 893 | | const arg = try self.resolveInst(inst.args.args[i]); |
| 894 | | try self.genSetReg(inst.base.src, arch, reg, arg); |
| 940 | return .none; |
| 895 | 941 | } |
| 896 | 942 | |
| 897 | | if (mem.eql(u8, inst.args.asm_source, "syscall")) { |
| 898 | | try self.code.appendSlice(&[_]u8{ 0x0f, 0x05 }); |
| 899 | | } else { |
| 900 | | return self.fail(inst.base.src, "TODO implement support for more x86 assembly instructions", .{}); |
| 901 | | } |
| 943 | fn genAsm(self: *Self, inst: *ir.Inst.Assembly) !MCValue { |
| 944 | if (!inst.is_volatile and inst.base.isUnused()) |
| 945 | return MCValue.dead; |
| 946 | if (arch != .x86_64 and arch != .i386) { |
| 947 | return self.fail(inst.base.src, "TODO implement inline asm support for more architectures", .{}); |
| 948 | } |
| 949 | for (inst.inputs) |input, i| { |
| 950 | if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') { |
| 951 | return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input}); |
| 952 | } |
| 953 | const reg_name = input[1 .. input.len - 1]; |
| 954 | const reg = parseRegName(reg_name) orelse |
| 955 | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 956 | const arg = try self.resolveInst(inst.args[i]); |
| 957 | try self.genSetReg(inst.base.src, reg, arg); |
| 958 | } |
| 902 | 959 | |
| 903 | | if (inst.args.output) |output| { |
| 904 | | if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') { |
| 905 | | return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output}); |
| 960 | if (mem.eql(u8, inst.asm_source, "syscall")) { |
| 961 | try self.code.appendSlice(&[_]u8{ 0x0f, 0x05 }); |
| 962 | } else { |
| 963 | return self.fail(inst.base.src, "TODO implement support for more x86 assembly instructions", .{}); |
| 906 | 964 | } |
| 907 | | const reg_name = output[2 .. output.len - 1]; |
| 908 | | const reg = parseRegName(arch, reg_name) orelse |
| 909 | | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 910 | | return MCValue{ .register = @enumToInt(reg) }; |
| 911 | | } else { |
| 912 | | return MCValue.none; |
| 913 | | } |
| 914 | | } |
| 915 | 965 | |
| 916 | | /// Encodes a REX prefix as specified, and appends it to the instruction |
| 917 | | /// stream. This only modifies the instruction stream if at least one bit |
| 918 | | /// is set true, which has a few implications: |
| 919 | | /// |
| 920 | | /// * The length of the instruction buffer will be modified *if* the |
| 921 | | /// resulting REX is meaningful, but will remain the same if it is not. |
| 922 | | /// * Deliberately inserting a "meaningless REX" requires explicit usage of |
| 923 | | /// 0x40, and cannot be done via this function. |
| 924 | | fn rex(self: *Function, arg: struct { b: bool = false, w: bool = false, x: bool = false, r: bool = false }) void { |
| 925 | | // From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB. |
| 926 | | var value: u8 = 0x40; |
| 927 | | if (arg.b) { |
| 928 | | value |= 0x1; |
| 929 | | } |
| 930 | | if (arg.x) { |
| 931 | | value |= 0x2; |
| 932 | | } |
| 933 | | if (arg.r) { |
| 934 | | value |= 0x4; |
| 935 | | } |
| 936 | | if (arg.w) { |
| 937 | | value |= 0x8; |
| 966 | if (inst.output) |output| { |
| 967 | if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') { |
| 968 | return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output}); |
| 969 | } |
| 970 | const reg_name = output[2 .. output.len - 1]; |
| 971 | const reg = parseRegName(reg_name) orelse |
| 972 | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 973 | return MCValue{ .register = reg }; |
| 974 | } else { |
| 975 | return MCValue.none; |
| 976 | } |
| 938 | 977 | } |
| 939 | | if (value != 0x40) { |
| 940 | | self.code.appendAssumeCapacity(value); |
| 978 | |
| 979 | /// Encodes a REX prefix as specified, and appends it to the instruction |
| 980 | /// stream. This only modifies the instruction stream if at least one bit |
| 981 | /// is set true, which has a few implications: |
| 982 | /// |
| 983 | /// * The length of the instruction buffer will be modified *if* the |
| 984 | /// resulting REX is meaningful, but will remain the same if it is not. |
| 985 | /// * Deliberately inserting a "meaningless REX" requires explicit usage of |
| 986 | /// 0x40, and cannot be done via this function. |
| 987 | fn rex(self: *Self, arg: struct { b: bool = false, w: bool = false, x: bool = false, r: bool = false }) void { |
| 988 | // From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB. |
| 989 | var value: u8 = 0x40; |
| 990 | if (arg.b) { |
| 991 | value |= 0x1; |
| 992 | } |
| 993 | if (arg.x) { |
| 994 | value |= 0x2; |
| 995 | } |
| 996 | if (arg.r) { |
| 997 | value |= 0x4; |
| 998 | } |
| 999 | if (arg.w) { |
| 1000 | value |= 0x8; |
| 1001 | } |
| 1002 | if (value != 0x40) { |
| 1003 | self.code.appendAssumeCapacity(value); |
| 1004 | } |
| 941 | 1005 | } |
| 942 | | } |
| 943 | 1006 | |
| 944 | | fn genSetReg(self: *Function, src: usize, comptime arch: Target.Cpu.Arch, reg: Reg(arch), mcv: MCValue) error{ CodegenFail, OutOfMemory }!void { |
| 945 | | switch (arch) { |
| 946 | | .x86_64 => switch (mcv) { |
| 947 | | .dead => unreachable, |
| 948 | | .none => unreachable, |
| 949 | | .unreach => unreachable, |
| 950 | | .compare_flags_unsigned => |op| { |
| 951 | | try self.code.ensureCapacity(self.code.items.len + 3); |
| 952 | | self.rex(.{ .b = reg.isExtended(), .w = reg.size() == 64 }); |
| 953 | | const opcode: u8 = switch (op) { |
| 954 | | .gte => 0x93, |
| 955 | | .gt => 0x97, |
| 956 | | .neq => 0x95, |
| 957 | | .lt => 0x92, |
| 958 | | .lte => 0x96, |
| 959 | | .eq => 0x94, |
| 960 | | }; |
| 961 | | const id = @as(u8, reg.id() & 0b111); |
| 962 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x0f, opcode, 0xC0 | id }); |
| 963 | | }, |
| 964 | | .compare_flags_signed => |op| { |
| 965 | | return self.fail(src, "TODO set register with compare flags value (signed)", .{}); |
| 966 | | }, |
| 967 | | .immediate => |x| { |
| 968 | | if (reg.size() != 64) { |
| 969 | | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 970 | | } |
| 971 | | // 32-bit moves zero-extend to 64-bit, so xoring the 32-bit |
| 972 | | // register is the fastest way to zero a register. |
| 973 | | if (x == 0) { |
| 974 | | // The encoding for `xor r32, r32` is `0x31 /r`. |
| 975 | | // Section 3.1.1.1 of the Intel x64 Manual states that "/r indicates that the |
| 976 | | // ModR/M byte of the instruction contains a register operand and an r/m operand." |
| 977 | | // |
| 978 | | // R/M bytes are composed of two bits for the mode, then three bits for the register, |
| 979 | | // then three bits for the operand. Since we're zeroing a register, the two three-bit |
| 980 | | // values will be identical, and the mode is three (the raw register value). |
| 981 | | // |
| 982 | | // If we're accessing e.g. r8d, we need to use a REX prefix before the actual operation. Since |
| 983 | | // this is a 32-bit operation, the W flag is set to zero. X is also zero, as we're not using a SIB. |
| 984 | | // Both R and B are set, as we're extending, in effect, the register bits *and* the operand. |
| 1007 | fn genSetReg(self: *Self, src: usize, reg: Register, mcv: MCValue) error{ CodegenFail, OutOfMemory }!void { |
| 1008 | switch (arch) { |
| 1009 | .x86_64 => switch (mcv) { |
| 1010 | .dead => unreachable, |
| 1011 | .none => unreachable, |
| 1012 | .unreach => unreachable, |
| 1013 | .compare_flags_unsigned => |op| { |
| 985 | 1014 | try self.code.ensureCapacity(self.code.items.len + 3); |
| 986 | | self.rex(.{ .r = reg.isExtended(), .b = reg.isExtended() }); |
| 1015 | self.rex(.{ .b = reg.isExtended(), .w = reg.size() == 64 }); |
| 1016 | const opcode: u8 = switch (op) { |
| 1017 | .gte => 0x93, |
| 1018 | .gt => 0x97, |
| 1019 | .neq => 0x95, |
| 1020 | .lt => 0x92, |
| 1021 | .lte => 0x96, |
| 1022 | .eq => 0x94, |
| 1023 | }; |
| 987 | 1024 | const id = @as(u8, reg.id() & 0b111); |
| 988 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x31, 0xC0 | id << 3 | id }); |
| 989 | | return; |
| 990 | | } |
| 991 | | if (x <= std.math.maxInt(u32)) { |
| 992 | | // Next best case: if we set the lower four bytes, the upper four will be zeroed. |
| 993 | | // |
| 994 | | // The encoding for `mov IMM32 -> REG` is (0xB8 + R) IMM. |
| 995 | | if (reg.isExtended()) { |
| 996 | | // Just as with XORing, we need a REX prefix. This time though, we only |
| 997 | | // need the B bit set, as we're extending the opcode's register field, |
| 998 | | // and there is no Mod R/M byte. |
| 999 | | // |
| 1000 | | // Thus, we need b01000001, or 0x41. |
| 1001 | | try self.code.resize(self.code.items.len + 6); |
| 1002 | | self.code.items[self.code.items.len - 6] = 0x41; |
| 1003 | | } else { |
| 1004 | | try self.code.resize(self.code.items.len + 5); |
| 1025 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x0f, opcode, 0xC0 | id }); |
| 1026 | }, |
| 1027 | .compare_flags_signed => |op| { |
| 1028 | return self.fail(src, "TODO set register with compare flags value (signed)", .{}); |
| 1029 | }, |
| 1030 | .immediate => |x| { |
| 1031 | if (reg.size() != 64) { |
| 1032 | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1005 | 1033 | } |
| 1006 | | self.code.items[self.code.items.len - 5] = 0xB8 | @as(u8, reg.id() & 0b111); |
| 1007 | | const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4]; |
| 1008 | | mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x)); |
| 1009 | | return; |
| 1010 | | } |
| 1011 | | // Worst case: we need to load the 64-bit register with the IMM. GNU's assemblers calls |
| 1012 | | // this `movabs`, though this is officially just a different variant of the plain `mov` |
| 1013 | | // instruction. |
| 1014 | | // |
| 1015 | | // This encoding is, in fact, the *same* as the one used for 32-bit loads. The only |
| 1016 | | // difference is that we set REX.W before the instruction, which extends the load to |
| 1017 | | // 64-bit and uses the full bit-width of the register. |
| 1018 | | // |
| 1019 | | // Since we always need a REX here, let's just check if we also need to set REX.B. |
| 1020 | | // |
| 1021 | | // In this case, the encoding of the REX byte is 0b0100100B |
| 1022 | | try self.code.ensureCapacity(self.code.items.len + 10); |
| 1023 | | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1024 | | self.code.items.len += 9; |
| 1025 | | self.code.items[self.code.items.len - 9] = 0xB8 | @as(u8, reg.id() & 0b111); |
| 1026 | | const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8]; |
| 1027 | | mem.writeIntLittle(u64, imm_ptr, x); |
| 1028 | | }, |
| 1029 | | .embedded_in_code => |code_offset| { |
| 1030 | | if (reg.size() != 64) { |
| 1031 | | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1032 | | } |
| 1033 | | // We need the offset from RIP in a signed i32 twos complement. |
| 1034 | | // The instruction is 7 bytes long and RIP points to the next instruction. |
| 1035 | | try self.code.ensureCapacity(self.code.items.len + 7); |
| 1036 | | // 64-bit LEA is encoded as REX.W 8D /r. If the register is extended, the REX byte is modified, |
| 1037 | | // but the operation size is unchanged. Since we're using a disp32, we want mode 0 and lower three |
| 1038 | | // bits as five. |
| 1039 | | // REX 0x8D 0b00RRR101, where RRR is the lower three bits of the id. |
| 1040 | | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1041 | | self.code.items.len += 6; |
| 1042 | | const rip = self.code.items.len; |
| 1043 | | const big_offset = @intCast(i64, code_offset) - @intCast(i64, rip); |
| 1044 | | const offset = @intCast(i32, big_offset); |
| 1045 | | self.code.items[self.code.items.len - 6] = 0x8D; |
| 1046 | | self.code.items[self.code.items.len - 5] = 0b101 | (@as(u8, reg.id() & 0b111) << 3); |
| 1047 | | const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4]; |
| 1048 | | mem.writeIntLittle(i32, imm_ptr, offset); |
| 1049 | | }, |
| 1050 | | .register => |r| { |
| 1051 | | if (reg.size() != 64) { |
| 1052 | | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1053 | | } |
| 1054 | | const src_reg = @intToEnum(Reg(arch), @intCast(u8, r)); |
| 1055 | | // This is a variant of 8B /r. Since we're using 64-bit moves, we require a REX. |
| 1056 | | // This is thus three bytes: REX 0x8B R/M. |
| 1057 | | // If the destination is extended, the R field must be 1. |
| 1058 | | // If the *source* is extended, the B field must be 1. |
| 1059 | | // Since the register is being accessed directly, the R/M mode is three. The reg field (the middle |
| 1060 | | // three bits) contain the destination, and the R/M field (the lower three bits) contain the source. |
| 1061 | | try self.code.ensureCapacity(self.code.items.len + 3); |
| 1062 | | self.rex(.{ .w = true, .r = reg.isExtended(), .b = src_reg.isExtended() }); |
| 1063 | | const R = 0xC0 | (@as(u8, reg.id() & 0b111) << 3) | @as(u8, src_reg.id() & 0b111); |
| 1064 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, R }); |
| 1065 | | }, |
| 1066 | | .memory => |x| { |
| 1067 | | if (reg.size() != 64) { |
| 1068 | | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1069 | | } |
| 1070 | | if (x <= std.math.maxInt(u32)) { |
| 1071 | | // Moving from memory to a register is a variant of `8B /r`. |
| 1072 | | // Since we're using 64-bit moves, we require a REX. |
| 1073 | | // This variant also requires a SIB, as it would otherwise be RIP-relative. |
| 1074 | | // We want mode zero with the lower three bits set to four to indicate an SIB with no other displacement. |
| 1075 | | // The SIB must be 0x25, to indicate a disp32 with no scaled index. |
| 1076 | | // 0b00RRR100, where RRR is the lower three bits of the register ID. |
| 1077 | | // The instruction is thus eight bytes; REX 0x8B 0b00RRR100 0x25 followed by a four-byte disp32. |
| 1078 | | try self.code.ensureCapacity(self.code.items.len + 8); |
| 1079 | | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1080 | | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 1081 | | 0x8B, |
| 1082 | | 0x04 | (@as(u8, reg.id() & 0b111) << 3), // R |
| 1083 | | 0x25, |
| 1084 | | }); |
| 1085 | | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), @intCast(u32, x)); |
| 1086 | | } else { |
| 1087 | | // If this is RAX, we can use a direct load; otherwise, we need to load the address, then indirectly load |
| 1088 | | // the value. |
| 1089 | | if (reg.id() == 0) { |
| 1090 | | // REX.W 0xA1 moffs64* |
| 1091 | | // moffs64* is a 64-bit offset "relative to segment base", which really just means the |
| 1092 | | // absolute address for all practical purposes. |
| 1093 | | try self.code.resize(self.code.items.len + 10); |
| 1094 | | // REX.W == 0x48 |
| 1095 | | self.code.items[self.code.items.len - 10] = 0x48; |
| 1096 | | self.code.items[self.code.items.len - 9] = 0xA1; |
| 1097 | | const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8]; |
| 1098 | | mem.writeIntLittle(u64, imm_ptr, x); |
| 1099 | | } else { |
| 1100 | | // This requires two instructions; a move imm as used above, followed by an indirect load using the register |
| 1101 | | // as the address and the register as the destination. |
| 1034 | // 32-bit moves zero-extend to 64-bit, so xoring the 32-bit |
| 1035 | // register is the fastest way to zero a register. |
| 1036 | if (x == 0) { |
| 1037 | // The encoding for `xor r32, r32` is `0x31 /r`. |
| 1038 | // Section 3.1.1.1 of the Intel x64 Manual states that "/r indicates that the |
| 1039 | // ModR/M byte of the instruction contains a register operand and an r/m operand." |
| 1040 | // |
| 1041 | // R/M bytes are composed of two bits for the mode, then three bits for the register, |
| 1042 | // then three bits for the operand. Since we're zeroing a register, the two three-bit |
| 1043 | // values will be identical, and the mode is three (the raw register value). |
| 1102 | 1044 | // |
| 1103 | | // This cannot be used if the lower three bits of the id are equal to four or five, as there |
| 1104 | | // is no way to possibly encode it. This means that RSP, RBP, R12, and R13 cannot be used with |
| 1105 | | // this instruction. |
| 1106 | | const id3 = @truncate(u3, reg.id()); |
| 1107 | | std.debug.assert(id3 != 4 and id3 != 5); |
| 1108 | | |
| 1109 | | // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue. |
| 1110 | | try self.genSetReg(src, arch, reg, MCValue{ .immediate = x }); |
| 1111 | | |
| 1112 | | // Now, the register contains the address of the value to load into it |
| 1113 | | // Currently, we're only allowing 64-bit registers, so we need the `REX.W 8B /r` variant. |
| 1114 | | // TODO: determine whether to allow other sized registers, and if so, handle them properly. |
| 1115 | | // This operation requires three bytes: REX 0x8B R/M |
| 1045 | // If we're accessing e.g. r8d, we need to use a REX prefix before the actual operation. Since |
| 1046 | // this is a 32-bit operation, the W flag is set to zero. X is also zero, as we're not using a SIB. |
| 1047 | // Both R and B are set, as we're extending, in effect, the register bits *and* the operand. |
| 1116 | 1048 | try self.code.ensureCapacity(self.code.items.len + 3); |
| 1117 | | // For this operation, we want R/M mode *zero* (use register indirectly), and the two register |
| 1118 | | // values must match. Thus, it's 00ABCABC where ABC is the lower three bits of the register ID. |
| 1049 | self.rex(.{ .r = reg.isExtended(), .b = reg.isExtended() }); |
| 1050 | const id = @as(u8, reg.id() & 0b111); |
| 1051 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x31, 0xC0 | id << 3 | id }); |
| 1052 | return; |
| 1053 | } |
| 1054 | if (x <= std.math.maxInt(u32)) { |
| 1055 | // Next best case: if we set the lower four bytes, the upper four will be zeroed. |
| 1119 | 1056 | // |
| 1120 | | // Furthermore, if this is an extended register, both B and R must be set in the REX byte, as *both* |
| 1121 | | // register operands need to be marked as extended. |
| 1122 | | self.rex(.{ .w = true, .b = reg.isExtended(), .r = reg.isExtended() }); |
| 1123 | | const RM = (@as(u8, reg.id() & 0b111) << 3) | @truncate(u3, reg.id()); |
| 1124 | | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, RM }); |
| 1057 | // The encoding for `mov IMM32 -> REG` is (0xB8 + R) IMM. |
| 1058 | if (reg.isExtended()) { |
| 1059 | // Just as with XORing, we need a REX prefix. This time though, we only |
| 1060 | // need the B bit set, as we're extending the opcode's register field, |
| 1061 | // and there is no Mod R/M byte. |
| 1062 | // |
| 1063 | // Thus, we need b01000001, or 0x41. |
| 1064 | try self.code.resize(self.code.items.len + 6); |
| 1065 | self.code.items[self.code.items.len - 6] = 0x41; |
| 1066 | } else { |
| 1067 | try self.code.resize(self.code.items.len + 5); |
| 1068 | } |
| 1069 | self.code.items[self.code.items.len - 5] = 0xB8 | @as(u8, reg.id() & 0b111); |
| 1070 | const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4]; |
| 1071 | mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x)); |
| 1072 | return; |
| 1125 | 1073 | } |
| 1126 | | } |
| 1127 | | }, |
| 1128 | | .stack_offset => |off| { |
| 1129 | | return self.fail(src, "TODO implement genSetReg for stack variables", .{}); |
| 1074 | // Worst case: we need to load the 64-bit register with the IMM. GNU's assemblers calls |
| 1075 | // this `movabs`, though this is officially just a different variant of the plain `mov` |
| 1076 | // instruction. |
| 1077 | // |
| 1078 | // This encoding is, in fact, the *same* as the one used for 32-bit loads. The only |
| 1079 | // difference is that we set REX.W before the instruction, which extends the load to |
| 1080 | // 64-bit and uses the full bit-width of the register. |
| 1081 | // |
| 1082 | // Since we always need a REX here, let's just check if we also need to set REX.B. |
| 1083 | // |
| 1084 | // In this case, the encoding of the REX byte is 0b0100100B |
| 1085 | try self.code.ensureCapacity(self.code.items.len + 10); |
| 1086 | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1087 | self.code.items.len += 9; |
| 1088 | self.code.items[self.code.items.len - 9] = 0xB8 | @as(u8, reg.id() & 0b111); |
| 1089 | const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8]; |
| 1090 | mem.writeIntLittle(u64, imm_ptr, x); |
| 1091 | }, |
| 1092 | .embedded_in_code => |code_offset| { |
| 1093 | if (reg.size() != 64) { |
| 1094 | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1095 | } |
| 1096 | // We need the offset from RIP in a signed i32 twos complement. |
| 1097 | // The instruction is 7 bytes long and RIP points to the next instruction. |
| 1098 | try self.code.ensureCapacity(self.code.items.len + 7); |
| 1099 | // 64-bit LEA is encoded as REX.W 8D /r. If the register is extended, the REX byte is modified, |
| 1100 | // but the operation size is unchanged. Since we're using a disp32, we want mode 0 and lower three |
| 1101 | // bits as five. |
| 1102 | // REX 0x8D 0b00RRR101, where RRR is the lower three bits of the id. |
| 1103 | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1104 | self.code.items.len += 6; |
| 1105 | const rip = self.code.items.len; |
| 1106 | const big_offset = @intCast(i64, code_offset) - @intCast(i64, rip); |
| 1107 | const offset = @intCast(i32, big_offset); |
| 1108 | self.code.items[self.code.items.len - 6] = 0x8D; |
| 1109 | self.code.items[self.code.items.len - 5] = 0b101 | (@as(u8, reg.id() & 0b111) << 3); |
| 1110 | const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4]; |
| 1111 | mem.writeIntLittle(i32, imm_ptr, offset); |
| 1112 | }, |
| 1113 | .register => |src_reg| { |
| 1114 | if (reg.size() != 64) { |
| 1115 | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1116 | } |
| 1117 | // This is a variant of 8B /r. Since we're using 64-bit moves, we require a REX. |
| 1118 | // This is thus three bytes: REX 0x8B R/M. |
| 1119 | // If the destination is extended, the R field must be 1. |
| 1120 | // If the *source* is extended, the B field must be 1. |
| 1121 | // Since the register is being accessed directly, the R/M mode is three. The reg field (the middle |
| 1122 | // three bits) contain the destination, and the R/M field (the lower three bits) contain the source. |
| 1123 | try self.code.ensureCapacity(self.code.items.len + 3); |
| 1124 | self.rex(.{ .w = true, .r = reg.isExtended(), .b = src_reg.isExtended() }); |
| 1125 | const R = 0xC0 | (@as(u8, reg.id() & 0b111) << 3) | @as(u8, src_reg.id() & 0b111); |
| 1126 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, R }); |
| 1127 | }, |
| 1128 | .memory => |x| { |
| 1129 | if (reg.size() != 64) { |
| 1130 | return self.fail(src, "TODO decide whether to implement non-64-bit loads", .{}); |
| 1131 | } |
| 1132 | if (x <= std.math.maxInt(u32)) { |
| 1133 | // Moving from memory to a register is a variant of `8B /r`. |
| 1134 | // Since we're using 64-bit moves, we require a REX. |
| 1135 | // This variant also requires a SIB, as it would otherwise be RIP-relative. |
| 1136 | // We want mode zero with the lower three bits set to four to indicate an SIB with no other displacement. |
| 1137 | // The SIB must be 0x25, to indicate a disp32 with no scaled index. |
| 1138 | // 0b00RRR100, where RRR is the lower three bits of the register ID. |
| 1139 | // The instruction is thus eight bytes; REX 0x8B 0b00RRR100 0x25 followed by a four-byte disp32. |
| 1140 | try self.code.ensureCapacity(self.code.items.len + 8); |
| 1141 | self.rex(.{ .w = true, .b = reg.isExtended() }); |
| 1142 | self.code.appendSliceAssumeCapacity(&[_]u8{ |
| 1143 | 0x8B, |
| 1144 | 0x04 | (@as(u8, reg.id() & 0b111) << 3), // R |
| 1145 | 0x25, |
| 1146 | }); |
| 1147 | mem.writeIntLittle(u32, self.code.addManyAsArrayAssumeCapacity(4), @intCast(u32, x)); |
| 1148 | } else { |
| 1149 | // If this is RAX, we can use a direct load; otherwise, we need to load the address, then indirectly load |
| 1150 | // the value. |
| 1151 | if (reg.id() == 0) { |
| 1152 | // REX.W 0xA1 moffs64* |
| 1153 | // moffs64* is a 64-bit offset "relative to segment base", which really just means the |
| 1154 | // absolute address for all practical purposes. |
| 1155 | try self.code.resize(self.code.items.len + 10); |
| 1156 | // REX.W == 0x48 |
| 1157 | self.code.items[self.code.items.len - 10] = 0x48; |
| 1158 | self.code.items[self.code.items.len - 9] = 0xA1; |
| 1159 | const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8]; |
| 1160 | mem.writeIntLittle(u64, imm_ptr, x); |
| 1161 | } else { |
| 1162 | // This requires two instructions; a move imm as used above, followed by an indirect load using the register |
| 1163 | // as the address and the register as the destination. |
| 1164 | // |
| 1165 | // This cannot be used if the lower three bits of the id are equal to four or five, as there |
| 1166 | // is no way to possibly encode it. This means that RSP, RBP, R12, and R13 cannot be used with |
| 1167 | // this instruction. |
| 1168 | const id3 = @truncate(u3, reg.id()); |
| 1169 | std.debug.assert(id3 != 4 and id3 != 5); |
| 1170 | |
| 1171 | // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue. |
| 1172 | try self.genSetReg(src, reg, MCValue{ .immediate = x }); |
| 1173 | |
| 1174 | // Now, the register contains the address of the value to load into it |
| 1175 | // Currently, we're only allowing 64-bit registers, so we need the `REX.W 8B /r` variant. |
| 1176 | // TODO: determine whether to allow other sized registers, and if so, handle them properly. |
| 1177 | // This operation requires three bytes: REX 0x8B R/M |
| 1178 | try self.code.ensureCapacity(self.code.items.len + 3); |
| 1179 | // For this operation, we want R/M mode *zero* (use register indirectly), and the two register |
| 1180 | // values must match. Thus, it's 00ABCABC where ABC is the lower three bits of the register ID. |
| 1181 | // |
| 1182 | // Furthermore, if this is an extended register, both B and R must be set in the REX byte, as *both* |
| 1183 | // register operands need to be marked as extended. |
| 1184 | self.rex(.{ .w = true, .b = reg.isExtended(), .r = reg.isExtended() }); |
| 1185 | const RM = (@as(u8, reg.id() & 0b111) << 3) | @truncate(u3, reg.id()); |
| 1186 | self.code.appendSliceAssumeCapacity(&[_]u8{ 0x8B, RM }); |
| 1187 | } |
| 1188 | } |
| 1189 | }, |
| 1190 | .stack_offset => |off| { |
| 1191 | return self.fail(src, "TODO implement genSetReg for stack variables", .{}); |
| 1192 | }, |
| 1130 | 1193 | }, |
| 1131 | | }, |
| 1132 | | else => return self.fail(src, "TODO implement genSetReg for more architectures", .{}), |
| 1194 | else => return self.fail(src, "TODO implement genSetReg for more architectures", .{}), |
| 1195 | } |
| 1133 | 1196 | } |
| 1134 | | } |
| 1135 | 1197 | |
| 1136 | | fn genPtrToInt(self: *Function, inst: *ir.Inst.PtrToInt) !MCValue { |
| 1137 | | // no-op |
| 1138 | | return self.resolveInst(inst.args.ptr); |
| 1139 | | } |
| 1198 | fn genPtrToInt(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 1199 | // no-op |
| 1200 | return self.resolveInst(inst.operand); |
| 1201 | } |
| 1140 | 1202 | |
| 1141 | | fn genBitCast(self: *Function, inst: *ir.Inst.BitCast) !MCValue { |
| 1142 | | const operand = try self.resolveInst(inst.args.operand); |
| 1143 | | return operand; |
| 1144 | | } |
| 1203 | fn genBitCast(self: *Self, inst: *ir.Inst.UnOp) !MCValue { |
| 1204 | const operand = try self.resolveInst(inst.operand); |
| 1205 | return operand; |
| 1206 | } |
| 1145 | 1207 | |
| 1146 | | fn resolveInst(self: *Function, inst: *ir.Inst) !MCValue { |
| 1147 | | // Constants have static lifetimes, so they are always memoized in the outer most table. |
| 1148 | | if (inst.cast(ir.Inst.Constant)) |const_inst| { |
| 1149 | | const branch = &self.branch_stack.items[0]; |
| 1150 | | const gop = try branch.inst_table.getOrPut(self.gpa, inst); |
| 1151 | | if (!gop.found_existing) { |
| 1152 | | gop.entry.value = try self.genTypedValue(inst.src, .{ .ty = inst.ty, .val = const_inst.val }); |
| 1208 | fn resolveInst(self: *Self, inst: *ir.Inst) !MCValue { |
| 1209 | // Constants have static lifetimes, so they are always memoized in the outer most table. |
| 1210 | if (inst.cast(ir.Inst.Constant)) |const_inst| { |
| 1211 | const branch = &self.branch_stack.items[0]; |
| 1212 | const gop = try branch.inst_table.getOrPut(self.gpa, inst); |
| 1213 | if (!gop.found_existing) { |
| 1214 | gop.entry.value = try self.genTypedValue(inst.src, .{ .ty = inst.ty, .val = const_inst.val }); |
| 1215 | } |
| 1216 | return gop.entry.value; |
| 1153 | 1217 | } |
| 1154 | | return gop.entry.value; |
| 1155 | | } |
| 1156 | 1218 | |
| 1157 | | // Treat each stack item as a "layer" on top of the previous one. |
| 1158 | | var i: usize = self.branch_stack.items.len; |
| 1159 | | while (true) { |
| 1160 | | i -= 1; |
| 1161 | | if (self.branch_stack.items[i].inst_table.get(inst)) |mcv| { |
| 1162 | | return mcv; |
| 1219 | // Treat each stack item as a "layer" on top of the previous one. |
| 1220 | var i: usize = self.branch_stack.items.len; |
| 1221 | while (true) { |
| 1222 | i -= 1; |
| 1223 | if (self.branch_stack.items[i].inst_table.get(inst)) |mcv| { |
| 1224 | assert(mcv != .dead); |
| 1225 | return mcv; |
| 1226 | } |
| 1163 | 1227 | } |
| 1164 | 1228 | } |
| 1165 | | } |
| 1166 | 1229 | |
| 1167 | | fn copyToNewRegister(self: *Function, inst: *ir.Inst) !MCValue { |
| 1168 | | return self.fail(inst.src, "TODO implement copyToNewRegister", .{}); |
| 1169 | | } |
| 1230 | /// Does not "move" the instruction. |
| 1231 | fn copyToNewRegister(self: *Self, inst: *ir.Inst) !MCValue { |
| 1232 | const branch = &self.branch_stack.items[self.branch_stack.items.len - 1]; |
| 1233 | try branch.registers.ensureCapacity(self.gpa, branch.registers.items().len + 1); |
| 1234 | try branch.inst_table.ensureCapacity(self.gpa, branch.inst_table.items().len + 1); |
| 1235 | |
| 1236 | const free_index = @ctz(FreeRegInt, branch.free_registers); |
| 1237 | if (free_index >= callee_preserved_regs.len) |
| 1238 | return self.fail(inst.src, "TODO implement spilling register to stack", .{}); |
| 1239 | branch.free_registers &= ~(@as(FreeRegInt, 1) << free_index); |
| 1240 | const reg = callee_preserved_regs[free_index]; |
| 1241 | branch.registers.putAssumeCapacityNoClobber(reg, .{ .inst = inst }); |
| 1242 | const old_mcv = branch.inst_table.get(inst).?; |
| 1243 | const new_mcv: MCValue = .{ .register = reg }; |
| 1244 | try self.genSetReg(inst.src, reg, old_mcv); |
| 1245 | return new_mcv; |
| 1246 | } |
| 1170 | 1247 | |
| 1171 | | /// If the MCValue is an immediate, and it does not fit within this type, |
| 1172 | | /// we put it in a register. |
| 1173 | | /// A potential opportunity for future optimization here would be keeping track |
| 1174 | | /// of the fact that the instruction is available both as an immediate |
| 1175 | | /// and as a register. |
| 1176 | | fn limitImmediateType(self: *Function, inst: *ir.Inst, comptime T: type) !MCValue { |
| 1177 | | const mcv = try self.resolveInst(inst); |
| 1178 | | const ti = @typeInfo(T).Int; |
| 1179 | | switch (mcv) { |
| 1180 | | .immediate => |imm| { |
| 1181 | | // This immediate is unsigned. |
| 1182 | | const U = @Type(.{ |
| 1183 | | .Int = .{ |
| 1184 | | .bits = ti.bits - @boolToInt(ti.is_signed), |
| 1185 | | .is_signed = false, |
| 1186 | | }, |
| 1187 | | }); |
| 1188 | | if (imm >= std.math.maxInt(U)) { |
| 1189 | | return self.copyToNewRegister(inst); |
| 1190 | | } |
| 1191 | | }, |
| 1192 | | else => {}, |
| 1248 | /// If the MCValue is an immediate, and it does not fit within this type, |
| 1249 | /// we put it in a register. |
| 1250 | /// A potential opportunity for future optimization here would be keeping track |
| 1251 | /// of the fact that the instruction is available both as an immediate |
| 1252 | /// and as a register. |
| 1253 | fn limitImmediateType(self: *Self, inst: *ir.Inst, comptime T: type) !MCValue { |
| 1254 | const mcv = try self.resolveInst(inst); |
| 1255 | const ti = @typeInfo(T).Int; |
| 1256 | switch (mcv) { |
| 1257 | .immediate => |imm| { |
| 1258 | // This immediate is unsigned. |
| 1259 | const U = @Type(.{ |
| 1260 | .Int = .{ |
| 1261 | .bits = ti.bits - @boolToInt(ti.is_signed), |
| 1262 | .is_signed = false, |
| 1263 | }, |
| 1264 | }); |
| 1265 | if (imm >= std.math.maxInt(U)) { |
| 1266 | return self.copyToNewRegister(inst); |
| 1267 | } |
| 1268 | }, |
| 1269 | else => {}, |
| 1270 | } |
| 1271 | return mcv; |
| 1193 | 1272 | } |
| 1194 | | return mcv; |
| 1195 | | } |
| 1196 | 1273 | |
| 1197 | | fn genTypedValue(self: *Function, src: usize, typed_value: TypedValue) !MCValue { |
| 1198 | | const ptr_bits = self.target.cpu.arch.ptrBitWidth(); |
| 1199 | | const ptr_bytes: u64 = @divExact(ptr_bits, 8); |
| 1200 | | switch (typed_value.ty.zigTypeTag()) { |
| 1201 | | .Pointer => { |
| 1202 | | if (typed_value.val.cast(Value.Payload.DeclRef)) |payload| { |
| 1203 | | const got = &self.bin_file.program_headers.items[self.bin_file.phdr_got_index.?]; |
| 1204 | | const decl = payload.decl; |
| 1205 | | const got_addr = got.p_vaddr + decl.link.offset_table_index * ptr_bytes; |
| 1206 | | return MCValue{ .memory = got_addr }; |
| 1207 | | } |
| 1208 | | return self.fail(src, "TODO codegen more kinds of const pointers", .{}); |
| 1209 | | }, |
| 1210 | | .Int => { |
| 1211 | | const info = typed_value.ty.intInfo(self.target.*); |
| 1212 | | if (info.bits > ptr_bits or info.signed) { |
| 1213 | | return self.fail(src, "TODO const int bigger than ptr and signed int", .{}); |
| 1214 | | } |
| 1215 | | return MCValue{ .immediate = typed_value.val.toUnsignedInt() }; |
| 1216 | | }, |
| 1217 | | .Bool => { |
| 1218 | | return MCValue{ .immediate = @boolToInt(typed_value.val.toBool()) }; |
| 1219 | | }, |
| 1220 | | .ComptimeInt => unreachable, // semantic analysis prevents this |
| 1221 | | .ComptimeFloat => unreachable, // semantic analysis prevents this |
| 1222 | | else => return self.fail(src, "TODO implement const of type '{}'", .{typed_value.ty}), |
| 1274 | fn genTypedValue(self: *Self, src: usize, typed_value: TypedValue) !MCValue { |
| 1275 | const ptr_bits = self.target.cpu.arch.ptrBitWidth(); |
| 1276 | const ptr_bytes: u64 = @divExact(ptr_bits, 8); |
| 1277 | switch (typed_value.ty.zigTypeTag()) { |
| 1278 | .Pointer => { |
| 1279 | if (typed_value.val.cast(Value.Payload.DeclRef)) |payload| { |
| 1280 | const got = &self.bin_file.program_headers.items[self.bin_file.phdr_got_index.?]; |
| 1281 | const decl = payload.decl; |
| 1282 | const got_addr = got.p_vaddr + decl.link.offset_table_index * ptr_bytes; |
| 1283 | return MCValue{ .memory = got_addr }; |
| 1284 | } |
| 1285 | return self.fail(src, "TODO codegen more kinds of const pointers", .{}); |
| 1286 | }, |
| 1287 | .Int => { |
| 1288 | const info = typed_value.ty.intInfo(self.target.*); |
| 1289 | if (info.bits > ptr_bits or info.signed) { |
| 1290 | return self.fail(src, "TODO const int bigger than ptr and signed int", .{}); |
| 1291 | } |
| 1292 | return MCValue{ .immediate = typed_value.val.toUnsignedInt() }; |
| 1293 | }, |
| 1294 | .Bool => { |
| 1295 | return MCValue{ .immediate = @boolToInt(typed_value.val.toBool()) }; |
| 1296 | }, |
| 1297 | .ComptimeInt => unreachable, // semantic analysis prevents this |
| 1298 | .ComptimeFloat => unreachable, // semantic analysis prevents this |
| 1299 | else => return self.fail(src, "TODO implement const of type '{}'", .{typed_value.ty}), |
| 1300 | } |
| 1223 | 1301 | } |
| 1224 | | } |
| 1225 | 1302 | |
| 1226 | | fn resolveParameters( |
| 1227 | | self: *Function, |
| 1228 | | src: usize, |
| 1229 | | cc: std.builtin.CallingConvention, |
| 1230 | | param_types: []const Type, |
| 1231 | | results: []MCValue, |
| 1232 | | ) !u32 { |
| 1233 | | switch (self.target.cpu.arch) { |
| 1234 | | .x86_64 => { |
| 1235 | | switch (cc) { |
| 1236 | | .Naked => { |
| 1237 | | assert(results.len == 0); |
| 1238 | | return 0; |
| 1239 | | }, |
| 1240 | | .Unspecified, .C => { |
| 1241 | | var next_int_reg: usize = 0; |
| 1242 | | var next_stack_offset: u32 = 0; |
| 1243 | | |
| 1244 | | const integer_registers = [_]Reg(.x86_64){ .rdi, .rsi, .rdx, .rcx, .r8, .r9 }; |
| 1245 | | for (param_types) |ty, i| { |
| 1246 | | switch (ty.zigTypeTag()) { |
| 1247 | | .Bool, .Int => { |
| 1248 | | if (next_int_reg >= integer_registers.len) { |
| 1249 | | results[i] = .{ .stack_offset = next_stack_offset }; |
| 1250 | | next_stack_offset += @intCast(u32, ty.abiSize(self.target.*)); |
| 1251 | | } else { |
| 1252 | | results[i] = .{ .register = @enumToInt(integer_registers[next_int_reg]) }; |
| 1253 | | next_int_reg += 1; |
| 1254 | | } |
| 1255 | | }, |
| 1256 | | else => return self.fail(src, "TODO implement function parameters of type {}", .{@tagName(ty.zigTypeTag())}), |
| 1303 | fn resolveParameters( |
| 1304 | self: *Self, |
| 1305 | src: usize, |
| 1306 | cc: std.builtin.CallingConvention, |
| 1307 | param_types: []const Type, |
| 1308 | results: []MCValue, |
| 1309 | ) !u32 { |
| 1310 | switch (arch) { |
| 1311 | .x86_64 => { |
| 1312 | switch (cc) { |
| 1313 | .Naked => { |
| 1314 | assert(results.len == 0); |
| 1315 | return 0; |
| 1316 | }, |
| 1317 | .Unspecified, .C => { |
| 1318 | var next_int_reg: usize = 0; |
| 1319 | var next_stack_offset: u32 = 0; |
| 1320 | |
| 1321 | for (param_types) |ty, i| { |
| 1322 | switch (ty.zigTypeTag()) { |
| 1323 | .Bool, .Int => { |
| 1324 | if (next_int_reg >= c_abi_int_param_regs.len) { |
| 1325 | results[i] = .{ .stack_offset = next_stack_offset }; |
| 1326 | next_stack_offset += @intCast(u32, ty.abiSize(self.target.*)); |
| 1327 | } else { |
| 1328 | results[i] = .{ .register = c_abi_int_param_regs[next_int_reg] }; |
| 1329 | next_int_reg += 1; |
| 1330 | } |
| 1331 | }, |
| 1332 | else => return self.fail(src, "TODO implement function parameters of type {}", .{@tagName(ty.zigTypeTag())}), |
| 1333 | } |
| 1257 | 1334 | } |
| 1258 | | } |
| 1259 | | return next_stack_offset; |
| 1260 | | }, |
| 1261 | | else => return self.fail(src, "TODO implement function parameters for {}", .{cc}), |
| 1262 | | } |
| 1263 | | }, |
| 1264 | | else => return self.fail(src, "TODO implement C ABI support for {}", .{self.target.cpu.arch}), |
| 1335 | return next_stack_offset; |
| 1336 | }, |
| 1337 | else => return self.fail(src, "TODO implement function parameters for {}", .{cc}), |
| 1338 | } |
| 1339 | }, |
| 1340 | else => return self.fail(src, "TODO implement C ABI support for {}", .{self.target.cpu.arch}), |
| 1341 | } |
| 1265 | 1342 | } |
| 1266 | | } |
| 1267 | 1343 | |
| 1268 | | fn fail(self: *Function, src: usize, comptime format: []const u8, args: anytype) error{ CodegenFail, OutOfMemory } { |
| 1269 | | @setCold(true); |
| 1270 | | assert(self.err_msg == null); |
| 1271 | | self.err_msg = try ErrorMsg.create(self.bin_file.allocator, src, format, args); |
| 1272 | | return error.CodegenFail; |
| 1273 | | } |
| 1274 | | }; |
| 1344 | fn fail(self: *Self, src: usize, comptime format: []const u8, args: anytype) error{ CodegenFail, OutOfMemory } { |
| 1345 | @setCold(true); |
| 1346 | assert(self.err_msg == null); |
| 1347 | self.err_msg = try ErrorMsg.create(self.bin_file.allocator, src, format, args); |
| 1348 | return error.CodegenFail; |
| 1349 | } |
| 1275 | 1350 | |
| 1276 | | const x86_64 = @import("codegen/x86_64.zig"); |
| 1277 | | const x86 = @import("codegen/x86.zig"); |
| 1351 | usingnamespace switch (arch) { |
| 1352 | .i386 => @import("codegen/x86.zig"), |
| 1353 | .x86_64 => @import("codegen/x86_64.zig"), |
| 1354 | else => struct { |
| 1355 | pub const Register = enum { |
| 1356 | dummy, |
| 1278 | 1357 | |
| 1279 | | fn Reg(comptime arch: Target.Cpu.Arch) type { |
| 1280 | | return switch (arch) { |
| 1281 | | .i386 => x86.Register, |
| 1282 | | .x86_64 => x86_64.Register, |
| 1283 | | else => @compileError("TODO add more register enums"), |
| 1284 | | }; |
| 1285 | | } |
| 1358 | pub fn allocIndex(self: Register) ?u4 { |
| 1359 | return null; |
| 1360 | } |
| 1361 | }; |
| 1362 | pub const callee_preserved_regs = [_]Register{}; |
| 1363 | }, |
| 1364 | }; |
| 1286 | 1365 | |
| 1287 | | fn parseRegName(comptime arch: Target.Cpu.Arch, name: []const u8) ?Reg(arch) { |
| 1288 | | return std.meta.stringToEnum(Reg(arch), name); |
| 1366 | /// An integer whose bits represent all the registers and whether they are free. |
| 1367 | const FreeRegInt = @Type(.{ .Int = .{ .is_signed = false, .bits = callee_preserved_regs.len } }); |
| 1368 | |
| 1369 | fn parseRegName(name: []const u8) ?Register { |
| 1370 | return std.meta.stringToEnum(Register, name); |
| 1371 | } |
| 1372 | }; |
| 1289 | 1373 | } |
Andrew Kelley <andrew@ziglang.org> 2020-07-20 13:12:25-07:00
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