authorgravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-01 19:29:09+07:00
committergravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-06 20:34:53+07:00
log4d50e52c37cad45bd3d8fd520359cdaee70aaf1f
treee15c7de8e57c7848bbc0ebe2a9a40cad71764003
parent97f9bf7e90ab10119b8225799590886e911775db

stage2: sparc64: Implement SPARCv9 xor, xnor, & not

2 files changed, 25 insertions(+), 3 deletions(-)

src/arch/sparc64/Emit.zig+9-3
...@@ -94,8 +94,8 @@ pub fn emitMir(...@@ -94,8 +94,8 @@ pub fn emitMir(
94 .ldx => try emit.mirArithmetic3Op(inst),94 .ldx => try emit.mirArithmetic3Op(inst),
9595
96 .@"or" => try emit.mirArithmetic3Op(inst),96 .@"or" => try emit.mirArithmetic3Op(inst),
97 .xor => @panic("TODO implement sparc64 xor"),97 .xor => try emit.mirArithmetic3Op(inst),
98 .xnor => @panic("TODO implement sparc64 xnor"),98 .xnor => try emit.mirArithmetic3Op(inst),
9999
100 .movcc => try emit.mirConditionalMove(inst),100 .movcc => try emit.mirConditionalMove(inst),
101101
...@@ -131,7 +131,7 @@ pub fn emitMir(...@@ -131,7 +131,7 @@ pub fn emitMir(
131131
132 .mov => try emit.mirArithmetic2Op(inst),132 .mov => try emit.mirArithmetic2Op(inst),
133133
134 .not => @panic("TODO implement sparc64 not"),134 .not => try emit.mirArithmetic2Op(inst),
135 }135 }
136 }136 }
137}137}
...@@ -192,6 +192,7 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -192,6 +192,7 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {
192 .@"return" => try emit.writeInstruction(Instruction.@"return"(i13, rs1, imm)),192 .@"return" => try emit.writeInstruction(Instruction.@"return"(i13, rs1, imm)),
193 .cmp => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, .g0)),193 .cmp => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, .g0)),
194 .mov => try emit.writeInstruction(Instruction.@"or"(i13, .g0, imm, rs1)),194 .mov => try emit.writeInstruction(Instruction.@"or"(i13, .g0, imm, rs1)),
195 .not => try emit.writeInstruction(Instruction.xnor(i13, .g0, imm, rs1)),
195 else => unreachable,196 else => unreachable,
196 }197 }
197 } else {198 } else {
...@@ -200,6 +201,7 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -200,6 +201,7 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {
200 .@"return" => try emit.writeInstruction(Instruction.@"return"(Register, rs1, rs2)),201 .@"return" => try emit.writeInstruction(Instruction.@"return"(Register, rs1, rs2)),
201 .cmp => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, .g0)),202 .cmp => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, .g0)),
202 .mov => try emit.writeInstruction(Instruction.@"or"(Register, .g0, rs2, rs1)),203 .mov => try emit.writeInstruction(Instruction.@"or"(Register, .g0, rs2, rs1)),
204 .not => try emit.writeInstruction(Instruction.xnor(Register, .g0, rs2, rs1)),
203 else => unreachable,205 else => unreachable,
204 }206 }
205 }207 }
...@@ -223,6 +225,8 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -223,6 +225,8 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
223 .lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),225 .lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),
224 .ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),226 .ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),
225 .@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),227 .@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),
228 .xor => try emit.writeInstruction(Instruction.xor(i13, rs1, imm, rd)),
229 .xnor => try emit.writeInstruction(Instruction.xnor(i13, rs1, imm, rd)),
226 .mulx => try emit.writeInstruction(Instruction.mulx(i13, rs1, imm, rd)),230 .mulx => try emit.writeInstruction(Instruction.mulx(i13, rs1, imm, rd)),
227 .save => try emit.writeInstruction(Instruction.save(i13, rs1, imm, rd)),231 .save => try emit.writeInstruction(Instruction.save(i13, rs1, imm, rd)),
228 .restore => try emit.writeInstruction(Instruction.restore(i13, rs1, imm, rd)),232 .restore => try emit.writeInstruction(Instruction.restore(i13, rs1, imm, rd)),
...@@ -245,6 +249,8 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -245,6 +249,8 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
245 .lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),249 .lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),
246 .ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),250 .ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),
247 .@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),251 .@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),
252 .xor => try emit.writeInstruction(Instruction.xor(Register, rs1, rs2, rd)),
253 .xnor => try emit.writeInstruction(Instruction.xnor(Register, rs1, rs2, rd)),
248 .mulx => try emit.writeInstruction(Instruction.mulx(Register, rs1, rs2, rd)),254 .mulx => try emit.writeInstruction(Instruction.mulx(Register, rs1, rs2, rd)),
249 .save => try emit.writeInstruction(Instruction.save(Register, rs1, rs2, rd)),255 .save => try emit.writeInstruction(Instruction.save(Register, rs1, rs2, rd)),
250 .restore => try emit.writeInstruction(Instruction.restore(Register, rs1, rs2, rd)),256 .restore => try emit.writeInstruction(Instruction.restore(Register, rs1, rs2, rd)),
src/arch/sparc64/bits.zig+16
...@@ -1205,6 +1205,22 @@ pub const Instruction = union(enum) {...@@ -1205,6 +1205,22 @@ pub const Instruction = union(enum) {
1205 };1205 };
1206 }1206 }
12071207
1208 pub fn xor(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1209 return switch (s2) {
1210 Register => format3a(0b10, 0b00_0011, rs1, rs2, rd),
1211 i13 => format3b(0b10, 0b00_0011, rs1, rs2, rd),
1212 else => unreachable,
1213 };
1214 }
1215
1216 pub fn xnor(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1217 return switch (s2) {
1218 Register => format3a(0b10, 0b00_0111, rs1, rs2, rd),
1219 i13 => format3b(0b10, 0b00_0111, rs1, rs2, rd),
1220 else => unreachable,
1221 };
1222 }
1223
1208 pub fn movcc(comptime s2: type, cond: Condition, ccr: CCR, rs2: s2, rd: Register) Instruction {1224 pub fn movcc(comptime s2: type, cond: Condition, ccr: CCR, rs2: s2, rd: Register) Instruction {
1209 return switch (s2) {1225 return switch (s2) {
1210 Register => format4c(0b10_1100, cond, ccr, rs2, rd),1226 Register => format4c(0b10_1100, cond, ccr, rs2, rd),