| author |  Veikka Tuominen <git@vexu.eu> 2020-10-30 15:47:12+02:00 |
| committer | Veikka Tuominen <git@vexu.eu> 2020-10-30 15:58:13+02:00 |
| log | 4ed2c52fb7b3b6d541235b6e9096a6e72b99ca2a |
| tree | 0804f2e4daa396672f9c03f7dbe49b31e8a1dfe5 |
| parent | e2e0b6272b98ef2ec810fbabcdc91a21e54a71a3 |
| signature |  Commit is signed but in an unrecognized format. |
stage2: switch put swap condbr and block
condbr is noreturn so having the other way around caused
subsequent cases to be eliminated as dead3 files changed, 20 insertions(+), 14 deletions(-)
src/astgen.zig+9-13
| ... | ... | @@ -1733,32 +1733,28 @@ fn switchExpr(mod: *Module, scope: *Scope, rl: ResultLoc, switch_node: *ast.Node |
| 1733 | 1733 | } |
| 1734 | 1734 | } |
| 1735 | 1735 | |
| 1736 | const condbr = try addZIRInstSpecial(mod, &else_scope.base, case_src, zir.Inst.CondBr, .{ | |
| 1736 | const condbr = try addZIRInstSpecial(mod, &case_scope.base, case_src, zir.Inst.CondBr, .{ | |
| 1737 | 1737 | .condition = any_ok.?, |
| 1738 | 1738 | .then_body = undefined, // populated below |
| 1739 | 1739 | .else_body = undefined, // populated below |
| 1740 | 1740 | }, .{}); |
| 1741 | ||
| 1742 | try switchCaseExpr(mod, &case_scope.base, case_rl, block, case); | |
| 1743 | condbr.positionals.then_body = .{ | |
| 1741 | const cond_block = try addZIRInstBlock(mod, &else_scope.base, case_src, .block, .{ | |
| 1744 | 1742 | .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items), |
| 1745 | }; | |
| 1743 | }); | |
| 1746 | 1744 | |
| 1747 | // reset to add the empty block | |
| 1745 | // reset cond_scope for then_body | |
| 1748 | 1746 | case_scope.instructions.items.len = 0; |
| 1749 | const empty_block = try addZIRInstBlock(mod, &case_scope.base, case_src, .block, .{ | |
| 1750 | .instructions = undefined, // populated below | |
| 1751 | }); | |
| 1752 | condbr.positionals.else_body = .{ | |
| 1747 | try switchCaseExpr(mod, &case_scope.base, case_rl, block, case); | |
| 1748 | condbr.positionals.then_body = .{ | |
| 1753 | 1749 | .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items), |
| 1754 | 1750 | }; |
| 1755 | 1751 | |
| 1756 | // reset to add a break to the empty block | |
| 1752 | // reset cond_scope for else_body | |
| 1757 | 1753 | case_scope.instructions.items.len = 0; |
| 1758 | 1754 | _ = try addZIRInst(mod, &case_scope.base, case_src, zir.Inst.BreakVoid, .{ |
| 1759 | .block = empty_block, | |
| 1755 | .block = cond_block, | |
| 1760 | 1756 | }, .{}); |
| 1761 | empty_block.positionals.body = .{ | |
| 1757 | condbr.positionals.else_body = .{ | |
| 1762 | 1758 | .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items), |
| 1763 | 1759 | }; |
| 1764 | 1760 | } |
src/codegen.zig+10-1
| ... | ... | @@ -2033,8 +2033,17 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 2033 | 2033 | } |
| 2034 | 2034 | |
| 2035 | 2035 | fn genBoolOp(self: *Self, inst: *ir.Inst.BinOp) !MCValue { |
| 2036 | if (inst.base.isUnused()) | |
| 2037 | return MCValue.dead; | |
| 2036 | 2038 | switch (arch) { |
| 2037 | else => return self.fail(inst.base.src, "TODO genBoolOp for {}", .{self.target.cpu.arch}), | |
| 2039 | .x86_64 => if (inst.base.tag == .booland) { | |
| 2040 | // lhs AND rhs | |
| 2041 | return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20); | |
| 2042 | } else { | |
| 2043 | // lhs OR rhs | |
| 2044 | return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08); | |
| 2045 | }, | |
| 2046 | else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}), | |
| 2038 | 2047 | } |
| 2039 | 2048 | } |
| 2040 | 2049 |
src/main.zig+1
| ... | ... | @@ -2421,6 +2421,7 @@ pub fn cmdFmt(gpa: *Allocator, args: []const []const u8) !void { |
| 2421 | 2421 | var stdin_flag: bool = false; |
| 2422 | 2422 | var check_flag: bool = false; |
| 2423 | 2423 | var input_files = ArrayList([]const u8).init(gpa); |
| 2424 | defer input_files.deinit(); | |
| 2424 | 2425 | |
| 2425 | 2426 | { |
| 2426 | 2427 | var i: usize = 0; |