| ... | @@ -5781,8 +5781,9 @@ fn airAsm(f: *Function, inst: Air.Inst.Index) !CValue { | ... | @@ -5781,8 +5781,9 @@ fn airAsm(f: *Function, inst: Air.Inst.Index) !CValue { |
| 5781 | c_name_buf[0] = '$'; | 5781 | c_name_buf[0] = '$'; |
| 5782 | break :name c_name; | 5782 | break :name c_name; |
| 5783 | } else if ((target.cpu.arch.isMIPS() and (mem.startsWith(u8, field_name, "fcc") or field_name[0] == 'w')) or | 5783 | } else if ((target.cpu.arch.isMIPS() and (mem.startsWith(u8, field_name, "fcc") or field_name[0] == 'w')) or |
| 5784 | ((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f')) name: { | 5784 | ((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f') or |
| 5785 | // "$" prefix for FCC, W and F registers | 5785 | (target.cpu.arch == .kvx and !mem.eql(u8, field_name, "memory"))) name: { |
| | 5786 | // "$" prefix for these registers |
| 5786 | c_name_buf[0] = '$'; | 5787 | c_name_buf[0] = '$'; |
| 5787 | @memcpy((&c_name_buf)[1..][0..field_name.len], field_name); | 5788 | @memcpy((&c_name_buf)[1..][0..field_name.len], field_name); |
| 5788 | break :name (&c_name_buf)[0 .. 1 + field_name.len]; | 5789 | break :name (&c_name_buf)[0 .. 1 + field_name.len]; |