authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 01:05:53-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 01:05:53-07:00
log50a5fc98dc7d458cb731980d1231ee6e1a7eb880
tree4cba5d87033ebda58a1fe95d41375dcd35686eea
parent59b4facd34dc525d2258bde8f5d94049d02355dc

update most target CPU features to llvm12

The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.

12 files changed, 117 insertions(+), 190 deletions(-)

lib/std/target.zig+6-6
......@@ -1070,17 +1070,13 @@ pub const Target = struct {
10701070 }
10711071 }
10721072
1073 /// Returns a name that matches the lib/std/target/* directory name.
1073 /// Returns a name that matches the lib/std/target/* source file name.
10741074 pub fn genericName(arch: Arch) []const u8 {
10751075 return switch (arch) {
10761076 .arm, .armeb, .thumb, .thumbeb => "arm",
10771077 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
1078 .avr => "avr",
10791078 .bpfel, .bpfeb => "bpf",
1080 .csky => "csky",
1081 .hexagon => "hexagon",
10821079 .mips, .mipsel, .mips64, .mips64el => "mips",
1083 .msp430 => "msp430",
10841080 .powerpc, .powerpc64, .powerpc64le => "powerpc",
10851081 .amdgcn => "amdgpu",
10861082 .riscv32, .riscv64 => "riscv",
......@@ -1111,6 +1107,7 @@ pub const Target = struct {
11111107 .s390x => &systemz.all_features,
11121108 .i386, .x86_64 => &x86.all_features,
11131109 .nvptx, .nvptx64 => &nvptx.all_features,
1110 .ve => &ve.all_features,
11141111 .wasm32, .wasm64 => &wasm.all_features,
11151112
11161113 else => &[0]Cpu.Feature{},
......@@ -1134,6 +1131,7 @@ pub const Target = struct {
11341131 .s390x => comptime allCpusFromDecls(systemz.cpu),
11351132 .i386, .x86_64 => comptime allCpusFromDecls(x86.cpu),
11361133 .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
1134 .ve => comptime allCpusFromDecls(ve.cpu),
11371135 .wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
11381136
11391137 else => &[0]*const Model{},
......@@ -1188,12 +1186,13 @@ pub const Target = struct {
11881186 .amdgcn => &amdgpu.cpu.generic,
11891187 .riscv32 => &riscv.cpu.generic_rv32,
11901188 .riscv64 => &riscv.cpu.generic_rv64,
1191 .sparc, .sparcel => &sparc.cpu.v8,
1189 .sparc, .sparcel => &sparc.cpu.generic,
11921190 .sparcv9 => &sparc.cpu.v9,
11931191 .s390x => &systemz.cpu.generic,
11941192 .i386 => &x86.cpu._i386,
11951193 .x86_64 => &x86.cpu.x86_64,
11961194 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1195 .ve => &ve.cpu.generic,
11971196 .wasm32, .wasm64 => &wasm.cpu.generic,
11981197
11991198 else => &S.generic_model,
......@@ -1207,6 +1206,7 @@ pub const Target = struct {
12071206 .riscv64 => &riscv.cpu.baseline_rv64,
12081207 .i386 => &x86.cpu.pentium4,
12091208 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1209 .sparc, .sparcel => &sparc.cpu.v8,
12101210
12111211 else => generic(arch),
12121212 };
lib/std/target/avr.zig+3-7
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
......@@ -163,7 +160,6 @@ pub const all_features = blk: {
163160 .dependencies = featureSet(&[_]Feature{
164161 .avr0,
165162 .@"break",
166 .memmappedregs,
167163 .sram,
168164 .tinyencoding,
169165 }),
......@@ -1859,7 +1855,7 @@ pub const cpu = struct {
18591855 .name = "atxmega16e5",
18601856 .llvm_name = "atxmega16e5",
18611857 .features = featureSet(&[_]Feature{
1862 .xmega,
1858 .xmegau,
18631859 }),
18641860 };
18651861 pub const atxmega192a3 = CpuModel{
lib/std/target/bpf.zig+2-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
lib/std/target/hexagon.zig+2-23
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
......@@ -92,7 +89,6 @@ pub const all_features = blk: {
9289 .llvm_name = "hvxv62",
9390 .description = "Hexagon HVX instructions",
9491 .dependencies = featureSet(&[_]Feature{
95 .hvx,
9692 .hvxv60,
9793 }),
9894 };
......@@ -100,8 +96,6 @@ pub const all_features = blk: {
10096 .llvm_name = "hvxv65",
10197 .description = "Hexagon HVX instructions",
10298 .dependencies = featureSet(&[_]Feature{
103 .hvx,
104 .hvxv60,
10599 .hvxv62,
106100 }),
107101 };
......@@ -109,9 +103,6 @@ pub const all_features = blk: {
109103 .llvm_name = "hvxv66",
110104 .description = "Hexagon HVX instructions",
111105 .dependencies = featureSet(&[_]Feature{
112 .hvx,
113 .hvxv60,
114 .hvxv62,
115106 .hvxv65,
116107 .zreg,
117108 }),
......@@ -120,9 +111,6 @@ pub const all_features = blk: {
120111 .llvm_name = "hvxv67",
121112 .description = "Hexagon HVX instructions",
122113 .dependencies = featureSet(&[_]Feature{
123 .hvxv60,
124 .hvxv62,
125 .hvxv65,
126114 .hvxv66,
127115 }),
128116 };
......@@ -248,7 +236,6 @@ pub const cpu = struct {
248236 .memops,
249237 .nvj,
250238 .nvs,
251 .packets,
252239 .prev65,
253240 .small_data,
254241 .v5,
......@@ -265,7 +252,6 @@ pub const cpu = struct {
265252 .memops,
266253 .nvj,
267254 .nvs,
268 .packets,
269255 .prev65,
270256 .small_data,
271257 .v5,
......@@ -280,7 +266,6 @@ pub const cpu = struct {
280266 .memops,
281267 .nvj,
282268 .nvs,
283 .packets,
284269 .prev65,
285270 .small_data,
286271 .v5,
......@@ -296,7 +281,6 @@ pub const cpu = struct {
296281 .memops,
297282 .nvj,
298283 .nvs,
299 .packets,
300284 .prev65,
301285 .small_data,
302286 .v5,
......@@ -313,7 +297,6 @@ pub const cpu = struct {
313297 .memops,
314298 .nvj,
315299 .nvs,
316 .packets,
317300 .prev65,
318301 .small_data,
319302 .v5,
......@@ -332,7 +315,6 @@ pub const cpu = struct {
332315 .memops,
333316 .nvj,
334317 .nvs,
335 .packets,
336318 .small_data,
337319 .v5,
338320 .v55,
......@@ -351,7 +333,6 @@ pub const cpu = struct {
351333 .memops,
352334 .nvj,
353335 .nvs,
354 .packets,
355336 .small_data,
356337 .v5,
357338 .v55,
......@@ -371,7 +352,6 @@ pub const cpu = struct {
371352 .memops,
372353 .nvj,
373354 .nvs,
374 .packets,
375355 .small_data,
376356 .v5,
377357 .v55,
......@@ -391,7 +371,6 @@ pub const cpu = struct {
391371 .mem_noshuf,
392372 .memops,
393373 .nvs,
394 .packets,
395374 .small_data,
396375 .tinycore,
397376 .v5,
lib/std/target/mips.zig+2-11
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
......@@ -108,7 +105,6 @@ pub const all_features = blk: {
108105 .llvm_name = "dspr3",
109106 .description = "Mips DSP-R3 ASE",
110107 .dependencies = featureSet(&[_]Feature{
111 .dsp,
112108 .dspr2,
113109 }),
114110 };
......@@ -301,10 +297,8 @@ pub const all_features = blk: {
301297 .llvm_name = "mips64r6",
302298 .description = "Mips64r6 ISA Support [experimental]",
303299 .dependencies = featureSet(&[_]Feature{
304 .abs2008,
305300 .mips32r6,
306301 .mips64r5,
307 .nan2008,
308302 }),
309303 };
310304 result[@enumToInt(Feature.msa)] = .{
......@@ -515,16 +509,13 @@ pub const cpu = struct {
515509 .llvm_name = "octeon",
516510 .features = featureSet(&[_]Feature{
517511 .cnmips,
518 .mips64r2,
519512 }),
520513 };
521514 pub const @"octeon+" = CpuModel{
522515 .name = "octeon+",
523516 .llvm_name = "octeon+",
524517 .features = featureSet(&[_]Feature{
525 .cnmips,
526518 .cnmipsp,
527 .mips64r2,
528519 }),
529520 };
530521 pub const p5600 = CpuModel{
lib/std/target/msp430.zig+2-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
lib/std/target/nvptx.zig+2-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
lib/std/target/powerpc.zig+51-113
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
......@@ -10,6 +7,7 @@ const CpuModel = std.Target.Cpu.Model;
107pub const Feature = enum {
118 @"64bit",
129 @"64bitregs",
10 aix,
1311 allow_unaligned_fp_access,
1412 altivec,
1513 booke,
......@@ -19,6 +17,7 @@ pub const Feature = enum {
1917 crypto,
2018 direct_move,
2119 e500,
20 efpu2,
2221 extdiv,
2322 fcpsgn,
2423 float128,
......@@ -46,6 +45,7 @@ pub const Feature = enum {
4645 longcall,
4746 mfocrf,
4847 mma,
48 modern_aix_as,
4949 msync,
5050 paired_vector_memops,
5151 partword_atomics,
......@@ -62,7 +62,6 @@ pub const Feature = enum {
6262 ppc6xx,
6363 predictable_select_expensive,
6464 prefix_instrs,
65 qpx,
6665 recipprec,
6766 secure_plt,
6867 slow_popcntd,
......@@ -89,6 +88,11 @@ pub const all_features = blk: {
8988 .description = "Enable 64-bit registers usage for ppc32 [beta]",
9089 .dependencies = featureSet(&[_]Feature{}),
9190 };
91 result[@enumToInt(Feature.aix)] = .{
92 .llvm_name = "aix",
93 .description = "AIX OS",
94 .dependencies = featureSet(&[_]Feature{}),
95 };
9296 result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{
9397 .llvm_name = "allow-unaligned-fp-access",
9498 .description = "CPU does not trap on unaligned FP access",
......@@ -142,6 +146,13 @@ pub const all_features = blk: {
142146 .description = "Enable E500/E500mc instructions",
143147 .dependencies = featureSet(&[_]Feature{}),
144148 };
149 result[@enumToInt(Feature.efpu2)] = .{
150 .llvm_name = "efpu2",
151 .description = "Enable Embedded Floating-Point APU 2 instructions",
152 .dependencies = featureSet(&[_]Feature{
153 .spe,
154 }),
155 };
145156 result[@enumToInt(Feature.extdiv)] = .{
146157 .llvm_name = "extdiv",
147158 .description = "Enable extended divide instructions",
......@@ -311,6 +322,11 @@ pub const all_features = blk: {
311322 .power9_altivec,
312323 }),
313324 };
325 result[@enumToInt(Feature.modern_aix_as)] = .{
326 .llvm_name = "modern-aix-as",
327 .description = "AIX system assembler is modern enough to support new mnes",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
314330 result[@enumToInt(Feature.msync)] = .{
315331 .llvm_name = "msync",
316332 .description = "Has only the msync instruction instead of sync",
......@@ -334,7 +350,6 @@ pub const all_features = blk: {
334350 .llvm_name = "pcrelative-memops",
335351 .description = "Enable PC relative Memory Ops",
336352 .dependencies = featureSet(&[_]Feature{
337 .isa_v30_instructions,
338353 .prefix_instrs,
339354 }),
340355 };
......@@ -378,7 +393,6 @@ pub const all_features = blk: {
378393 .llvm_name = "power9-vector",
379394 .description = "Enable POWER9 vector instructions",
380395 .dependencies = featureSet(&[_]Feature{
381 .isa_v30_instructions,
382396 .power8_vector,
383397 .power9_altivec,
384398 }),
......@@ -412,18 +426,10 @@ pub const all_features = blk: {
412426 .llvm_name = "prefix-instrs",
413427 .description = "Enable prefixed instructions",
414428 .dependencies = featureSet(&[_]Feature{
415 .isa_v30_instructions,
416429 .power8_vector,
417430 .power9_altivec,
418431 }),
419432 };
420 result[@enumToInt(Feature.qpx)] = .{
421 .llvm_name = null,
422 .description = "Enable QPX instructions",
423 .dependencies = featureSet(&[_]Feature{
424 .fpu,
425 }),
426 };
427433 result[@enumToInt(Feature.recipprec)] = .{
428434 .llvm_name = "recipprec",
429435 .description = "Assume higher precision reciprocal estimates",
......@@ -479,94 +485,90 @@ pub const all_features = blk: {
479485};
480486
481487pub const cpu = struct {
482 pub const @"ppc440" = CpuModel{
483 .name = "ppc440",
488 pub const @"440" = CpuModel{
489 .name = "440",
484490 .llvm_name = "440",
485491 .features = featureSet(&[_]Feature{
486 .booke,
487492 .fres,
488493 .frsqrte,
489 .icbt,
490494 .isel,
491495 .msync,
492496 }),
493497 };
494 pub const @"ppc450" = CpuModel{
495 .name = "ppc450",
498 pub const @"450" = CpuModel{
499 .name = "450",
496500 .llvm_name = "450",
497501 .features = featureSet(&[_]Feature{
498 .booke,
499502 .fres,
500503 .frsqrte,
501 .icbt,
502504 .isel,
503505 .msync,
504506 }),
505507 };
506 pub const @"ppc601" = CpuModel{
507 .name = "ppc601",
508 pub const @"601" = CpuModel{
509 .name = "601",
508510 .llvm_name = "601",
509511 .features = featureSet(&[_]Feature{
510512 .fpu,
511513 }),
512514 };
513 pub const @"ppc602" = CpuModel{
514 .name = "ppc602",
515 pub const @"602" = CpuModel{
516 .name = "602",
515517 .llvm_name = "602",
516518 .features = featureSet(&[_]Feature{
517519 .fpu,
518520 }),
519521 };
520 pub const @"ppc603" = CpuModel{
521 .name = "ppc603",
522 pub const @"603" = CpuModel{
523 .name = "603",
522524 .llvm_name = "603",
523525 .features = featureSet(&[_]Feature{
524526 .fres,
525527 .frsqrte,
526528 }),
527529 };
528 pub const @"ppc603e" = CpuModel{
529 .name = "ppc603e",
530 pub const @"603e" = CpuModel{
531 .name = "603e",
530532 .llvm_name = "603e",
531533 .features = featureSet(&[_]Feature{
532534 .fres,
533535 .frsqrte,
534536 }),
535537 };
536 pub const @"ppc603ev" = CpuModel{
537 .name = "ppc603ev",
538 pub const @"603ev" = CpuModel{
539 .name = "603ev",
538540 .llvm_name = "603ev",
539541 .features = featureSet(&[_]Feature{
540542 .fres,
541543 .frsqrte,
542544 }),
543545 };
544 pub const @"ppc604" = CpuModel{
545 .name = "ppc604",
546 pub const @"604" = CpuModel{
547 .name = "604",
546548 .llvm_name = "604",
547549 .features = featureSet(&[_]Feature{
548550 .fres,
549551 .frsqrte,
550552 }),
551553 };
552 pub const @"ppc604e" = CpuModel{
553 .name = "ppc604e",
554 pub const @"604e" = CpuModel{
555 .name = "604e",
554556 .llvm_name = "604e",
555557 .features = featureSet(&[_]Feature{
556558 .fres,
557559 .frsqrte,
558560 }),
559561 };
560 pub const @"ppc620" = CpuModel{
561 .name = "ppc620",
562 pub const @"620" = CpuModel{
563 .name = "620",
562564 .llvm_name = "620",
563565 .features = featureSet(&[_]Feature{
564566 .fres,
565567 .frsqrte,
566568 }),
567569 };
568 pub const @"ppc7400" = CpuModel{
569 .name = "ppc7400",
570 pub const @"7400" = CpuModel{
571 .name = "7400",
570572 .llvm_name = "7400",
571573 .features = featureSet(&[_]Feature{
572574 .altivec,
......@@ -574,8 +576,8 @@ pub const cpu = struct {
574576 .frsqrte,
575577 }),
576578 };
577 pub const @"ppc7450" = CpuModel{
578 .name = "ppc7450",
579 pub const @"7450" = CpuModel{
580 .name = "7450",
579581 .llvm_name = "7450",
580582 .features = featureSet(&[_]Feature{
581583 .altivec,
......@@ -583,16 +585,16 @@ pub const cpu = struct {
583585 .frsqrte,
584586 }),
585587 };
586 pub const @"ppc750" = CpuModel{
587 .name = "ppc750",
588 pub const @"750" = CpuModel{
589 .name = "750",
588590 .llvm_name = "750",
589591 .features = featureSet(&[_]Feature{
590592 .fres,
591593 .frsqrte,
592594 }),
593595 };
594 pub const @"ppc970" = CpuModel{
595 .name = "ppc970",
596 pub const @"970" = CpuModel{
597 .name = "970",
596598 .llvm_name = "970",
597599 .features = featureSet(&[_]Feature{
598600 .@"64bit",
......@@ -619,7 +621,6 @@ pub const cpu = struct {
619621 .frsqrte,
620622 .frsqrtes,
621623 .fsqrt,
622 .icbt,
623624 .isel,
624625 .ldbrx,
625626 .lfiwax,
......@@ -629,38 +630,10 @@ pub const cpu = struct {
629630 .stfiwx,
630631 }),
631632 };
632 pub const a2q = CpuModel{
633 .name = "a2q",
634 .llvm_name = "a2q",
635 .features = featureSet(&[_]Feature{
636 .@"64bit",
637 .booke,
638 .cmpb,
639 .fcpsgn,
640 .fpcvt,
641 .fprnd,
642 .fre,
643 .fres,
644 .frsqrte,
645 .frsqrtes,
646 .fsqrt,
647 .icbt,
648 .isel,
649 .ldbrx,
650 .lfiwax,
651 .mfocrf,
652 .qpx,
653 .recipprec,
654 .slow_popcntd,
655 .stfiwx,
656 }),
657 };
658633 pub const e500 = CpuModel{
659634 .name = "e500",
660635 .llvm_name = "e500",
661636 .features = featureSet(&[_]Feature{
662 .booke,
663 .icbt,
664637 .isel,
665638 .msync,
666639 .spe,
......@@ -671,7 +644,6 @@ pub const cpu = struct {
671644 .llvm_name = "e500mc",
672645 .features = featureSet(&[_]Feature{
673646 .booke,
674 .icbt,
675647 .isel,
676648 .stfiwx,
677649 }),
......@@ -682,7 +654,6 @@ pub const cpu = struct {
682654 .features = featureSet(&[_]Feature{
683655 .@"64bit",
684656 .booke,
685 .icbt,
686657 .isel,
687658 .mfocrf,
688659 .stfiwx,
......@@ -694,7 +665,6 @@ pub const cpu = struct {
694665 .features = featureSet(&[_]Feature{
695666 .@"64bit",
696667 .allow_unaligned_fp_access,
697 .altivec,
698668 .bpermd,
699669 .cmpb,
700670 .crypto,
......@@ -711,30 +681,21 @@ pub const cpu = struct {
711681 .fuse_store,
712682 .htm,
713683 .icbt,
714 .isa_v30_instructions,
715 .isa_v31_instructions,
716684 .isel,
717685 .ldbrx,
718686 .lfiwax,
719687 .mfocrf,
720688 .mma,
721 .paired_vector_memops,
722689 .partword_atomics,
723690 .pcrelative_memops,
724691 .popcntd,
725692 .power10_vector,
726 .power8_altivec,
727 .power8_vector,
728 .power9_altivec,
729 .power9_vector,
730693 .ppc_postra_sched,
731694 .ppc_prera_sched,
732695 .predictable_select_expensive,
733 .prefix_instrs,
734696 .recipprec,
735697 .stfiwx,
736698 .two_const_nr,
737 .vsx,
738699 }),
739700 };
740701 pub const g3 = CpuModel{
......@@ -792,7 +753,7 @@ pub const cpu = struct {
792753 };
793754 pub const ppc32 = CpuModel{
794755 .name = "ppc32",
795 .llvm_name = "ppc",
756 .llvm_name = "ppc32",
796757 .features = featureSet(&[_]Feature{
797758 .hard_float,
798759 }),
......@@ -816,7 +777,6 @@ pub const cpu = struct {
816777 .features = featureSet(&[_]Feature{
817778 .@"64bit",
818779 .allow_unaligned_fp_access,
819 .altivec,
820780 .bpermd,
821781 .cmpb,
822782 .crypto,
......@@ -840,13 +800,11 @@ pub const cpu = struct {
840800 .mfocrf,
841801 .partword_atomics,
842802 .popcntd,
843 .power8_altivec,
844803 .power8_vector,
845804 .predictable_select_expensive,
846805 .recipprec,
847806 .stfiwx,
848807 .two_const_nr,
849 .vsx,
850808 }),
851809 };
852810 pub const pwr10 = CpuModel{
......@@ -855,7 +813,6 @@ pub const cpu = struct {
855813 .features = featureSet(&[_]Feature{
856814 .@"64bit",
857815 .allow_unaligned_fp_access,
858 .altivec,
859816 .bpermd,
860817 .cmpb,
861818 .crypto,
......@@ -872,30 +829,21 @@ pub const cpu = struct {
872829 .fuse_store,
873830 .htm,
874831 .icbt,
875 .isa_v30_instructions,
876 .isa_v31_instructions,
877832 .isel,
878833 .ldbrx,
879834 .lfiwax,
880835 .mfocrf,
881836 .mma,
882 .paired_vector_memops,
883837 .partword_atomics,
884838 .pcrelative_memops,
885839 .popcntd,
886840 .power10_vector,
887 .power8_altivec,
888 .power8_vector,
889 .power9_altivec,
890 .power9_vector,
891841 .ppc_postra_sched,
892842 .ppc_prera_sched,
893843 .predictable_select_expensive,
894 .prefix_instrs,
895844 .recipprec,
896845 .stfiwx,
897846 .two_const_nr,
898 .vsx,
899847 }),
900848 };
901849 pub const pwr3 = CpuModel{
......@@ -1000,7 +948,6 @@ pub const cpu = struct {
1000948 .features = featureSet(&[_]Feature{
1001949 .@"64bit",
1002950 .allow_unaligned_fp_access,
1003 .altivec,
1004951 .bpermd,
1005952 .cmpb,
1006953 .extdiv,
......@@ -1029,7 +976,6 @@ pub const cpu = struct {
1029976 .features = featureSet(&[_]Feature{
1030977 .@"64bit",
1031978 .allow_unaligned_fp_access,
1032 .altivec,
1033979 .bpermd,
1034980 .cmpb,
1035981 .crypto,
......@@ -1053,13 +999,11 @@ pub const cpu = struct {
1053999 .mfocrf,
10541000 .partword_atomics,
10551001 .popcntd,
1056 .power8_altivec,
10571002 .power8_vector,
10581003 .predictable_select_expensive,
10591004 .recipprec,
10601005 .stfiwx,
10611006 .two_const_nr,
1062 .vsx,
10631007 }),
10641008 };
10651009 pub const pwr9 = CpuModel{
......@@ -1068,7 +1012,6 @@ pub const cpu = struct {
10681012 .features = featureSet(&[_]Feature{
10691013 .@"64bit",
10701014 .allow_unaligned_fp_access,
1071 .altivec,
10721015 .bpermd,
10731016 .cmpb,
10741017 .crypto,
......@@ -1084,16 +1027,12 @@ pub const cpu = struct {
10841027 .fsqrt,
10851028 .htm,
10861029 .icbt,
1087 .isa_v30_instructions,
10881030 .isel,
10891031 .ldbrx,
10901032 .lfiwax,
10911033 .mfocrf,
10921034 .partword_atomics,
10931035 .popcntd,
1094 .power8_altivec,
1095 .power8_vector,
1096 .power9_altivec,
10971036 .power9_vector,
10981037 .ppc_postra_sched,
10991038 .ppc_prera_sched,
......@@ -1102,7 +1041,6 @@ pub const cpu = struct {
11021041 .stfiwx,
11031042 .two_const_nr,
11041043 .vectors_use_two_units,
1105 .vsx,
11061044 }),
11071045 };
11081046};
lib/std/target/sparc.zig+7-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
......@@ -160,6 +157,11 @@ pub const cpu = struct {
160157 .llvm_name = "f934",
161158 .features = featureSet(&[_]Feature{}),
162159 };
160 pub const generic = CpuModel{
161 .name = "generic",
162 .llvm_name = "generic",
163 .features = featureSet(&[_]Feature{}),
164 };
163165 pub const gr712rc = CpuModel{
164166 .name = "gr712rc",
165167 .llvm_name = "gr712rc",
lib/std/target/systemz.zig+2-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;
lib/std/target/ve.zig created+36
......@@ -0,0 +1,36 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 vpu,
9};
10
11pub usingnamespace CpuFeature.feature_set_fns(Feature);
12
13pub const all_features = blk: {
14 const len = @typeInfo(Feature).Enum.fields.len;
15 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
16 var result: [len]CpuFeature = undefined;
17 result[@enumToInt(Feature.vpu)] = .{
18 .llvm_name = "vpu",
19 .description = "Enable the VPU",
20 .dependencies = featureSet(&[_]Feature{}),
21 };
22 const ti = @typeInfo(Feature);
23 for (result) |*elem, i| {
24 elem.index = i;
25 elem.name = ti.Enum.fields[i].name;
26 }
27 break :blk result;
28};
29
30pub const cpu = struct {
31 pub const generic = CpuModel{
32 .name = "generic",
33 .llvm_name = "generic",
34 .features = featureSet(&[_]Feature{}),
35 };
36};
lib/std/target/wasm.zig+2-5
......@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT
2// Copyright (c) 2015-2021 Zig Contributors
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
63const std = @import("../std.zig");
74const CpuFeature = std.Target.Cpu.Feature;
85const CpuModel = std.Target.Cpu.Model;