authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 01:05:53-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 01:05:53-07:00
log50a5fc98dc7d458cb731980d1231ee6e1a7eb880
tree4cba5d87033ebda58a1fe95d41375dcd35686eea
parent59b4facd34dc525d2258bde8f5d94049d02355dc

update most target CPU features to llvm12

The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.

12 files changed, 117 insertions(+), 190 deletions(-)

lib/std/target.zig+6-6
...@@ -1070,17 +1070,13 @@ pub const Target = struct {...@@ -1070,17 +1070,13 @@ pub const Target = struct {
1070 }1070 }
1071 }1071 }
10721072
1073 /// Returns a name that matches the lib/std/target/* directory name.1073 /// Returns a name that matches the lib/std/target/* source file name.
1074 pub fn genericName(arch: Arch) []const u8 {1074 pub fn genericName(arch: Arch) []const u8 {
1075 return switch (arch) {1075 return switch (arch) {
1076 .arm, .armeb, .thumb, .thumbeb => "arm",1076 .arm, .armeb, .thumb, .thumbeb => "arm",
1077 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",1077 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
1078 .avr => "avr",
1079 .bpfel, .bpfeb => "bpf",1078 .bpfel, .bpfeb => "bpf",
1080 .csky => "csky",
1081 .hexagon => "hexagon",
1082 .mips, .mipsel, .mips64, .mips64el => "mips",1079 .mips, .mipsel, .mips64, .mips64el => "mips",
1083 .msp430 => "msp430",
1084 .powerpc, .powerpc64, .powerpc64le => "powerpc",1080 .powerpc, .powerpc64, .powerpc64le => "powerpc",
1085 .amdgcn => "amdgpu",1081 .amdgcn => "amdgpu",
1086 .riscv32, .riscv64 => "riscv",1082 .riscv32, .riscv64 => "riscv",
...@@ -1111,6 +1107,7 @@ pub const Target = struct {...@@ -1111,6 +1107,7 @@ pub const Target = struct {
1111 .s390x => &systemz.all_features,1107 .s390x => &systemz.all_features,
1112 .i386, .x86_64 => &x86.all_features,1108 .i386, .x86_64 => &x86.all_features,
1113 .nvptx, .nvptx64 => &nvptx.all_features,1109 .nvptx, .nvptx64 => &nvptx.all_features,
1110 .ve => &ve.all_features,
1114 .wasm32, .wasm64 => &wasm.all_features,1111 .wasm32, .wasm64 => &wasm.all_features,
11151112
1116 else => &[0]Cpu.Feature{},1113 else => &[0]Cpu.Feature{},
...@@ -1134,6 +1131,7 @@ pub const Target = struct {...@@ -1134,6 +1131,7 @@ pub const Target = struct {
1134 .s390x => comptime allCpusFromDecls(systemz.cpu),1131 .s390x => comptime allCpusFromDecls(systemz.cpu),
1135 .i386, .x86_64 => comptime allCpusFromDecls(x86.cpu),1132 .i386, .x86_64 => comptime allCpusFromDecls(x86.cpu),
1136 .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),1133 .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
1134 .ve => comptime allCpusFromDecls(ve.cpu),
1137 .wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),1135 .wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
11381136
1139 else => &[0]*const Model{},1137 else => &[0]*const Model{},
...@@ -1188,12 +1186,13 @@ pub const Target = struct {...@@ -1188,12 +1186,13 @@ pub const Target = struct {
1188 .amdgcn => &amdgpu.cpu.generic,1186 .amdgcn => &amdgpu.cpu.generic,
1189 .riscv32 => &riscv.cpu.generic_rv32,1187 .riscv32 => &riscv.cpu.generic_rv32,
1190 .riscv64 => &riscv.cpu.generic_rv64,1188 .riscv64 => &riscv.cpu.generic_rv64,
1191 .sparc, .sparcel => &sparc.cpu.v8,1189 .sparc, .sparcel => &sparc.cpu.generic,
1192 .sparcv9 => &sparc.cpu.v9,1190 .sparcv9 => &sparc.cpu.v9,
1193 .s390x => &systemz.cpu.generic,1191 .s390x => &systemz.cpu.generic,
1194 .i386 => &x86.cpu._i386,1192 .i386 => &x86.cpu._i386,
1195 .x86_64 => &x86.cpu.x86_64,1193 .x86_64 => &x86.cpu.x86_64,
1196 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,1194 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1195 .ve => &ve.cpu.generic,
1197 .wasm32, .wasm64 => &wasm.cpu.generic,1196 .wasm32, .wasm64 => &wasm.cpu.generic,
11981197
1199 else => &S.generic_model,1198 else => &S.generic_model,
...@@ -1207,6 +1206,7 @@ pub const Target = struct {...@@ -1207,6 +1206,7 @@ pub const Target = struct {
1207 .riscv64 => &riscv.cpu.baseline_rv64,1206 .riscv64 => &riscv.cpu.baseline_rv64,
1208 .i386 => &x86.cpu.pentium4,1207 .i386 => &x86.cpu.pentium4,
1209 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,1208 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1209 .sparc, .sparcel => &sparc.cpu.v8,
12101210
1211 else => generic(arch),1211 else => generic(arch),
1212 };1212 };
lib/std/target/avr.zig+3-7
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
...@@ -163,7 +160,6 @@ pub const all_features = blk: {...@@ -163,7 +160,6 @@ pub const all_features = blk: {
163 .dependencies = featureSet(&[_]Feature{160 .dependencies = featureSet(&[_]Feature{
164 .avr0,161 .avr0,
165 .@"break",162 .@"break",
166 .memmappedregs,
167 .sram,163 .sram,
168 .tinyencoding,164 .tinyencoding,
169 }),165 }),
...@@ -1859,7 +1855,7 @@ pub const cpu = struct {...@@ -1859,7 +1855,7 @@ pub const cpu = struct {
1859 .name = "atxmega16e5",1855 .name = "atxmega16e5",
1860 .llvm_name = "atxmega16e5",1856 .llvm_name = "atxmega16e5",
1861 .features = featureSet(&[_]Feature{1857 .features = featureSet(&[_]Feature{
1862 .xmega,1858 .xmegau,
1863 }),1859 }),
1864 };1860 };
1865 pub const atxmega192a3 = CpuModel{1861 pub const atxmega192a3 = CpuModel{
lib/std/target/bpf.zig+2-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
lib/std/target/hexagon.zig+2-23
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
...@@ -92,7 +89,6 @@ pub const all_features = blk: {...@@ -92,7 +89,6 @@ pub const all_features = blk: {
92 .llvm_name = "hvxv62",89 .llvm_name = "hvxv62",
93 .description = "Hexagon HVX instructions",90 .description = "Hexagon HVX instructions",
94 .dependencies = featureSet(&[_]Feature{91 .dependencies = featureSet(&[_]Feature{
95 .hvx,
96 .hvxv60,92 .hvxv60,
97 }),93 }),
98 };94 };
...@@ -100,8 +96,6 @@ pub const all_features = blk: {...@@ -100,8 +96,6 @@ pub const all_features = blk: {
100 .llvm_name = "hvxv65",96 .llvm_name = "hvxv65",
101 .description = "Hexagon HVX instructions",97 .description = "Hexagon HVX instructions",
102 .dependencies = featureSet(&[_]Feature{98 .dependencies = featureSet(&[_]Feature{
103 .hvx,
104 .hvxv60,
105 .hvxv62,99 .hvxv62,
106 }),100 }),
107 };101 };
...@@ -109,9 +103,6 @@ pub const all_features = blk: {...@@ -109,9 +103,6 @@ pub const all_features = blk: {
109 .llvm_name = "hvxv66",103 .llvm_name = "hvxv66",
110 .description = "Hexagon HVX instructions",104 .description = "Hexagon HVX instructions",
111 .dependencies = featureSet(&[_]Feature{105 .dependencies = featureSet(&[_]Feature{
112 .hvx,
113 .hvxv60,
114 .hvxv62,
115 .hvxv65,106 .hvxv65,
116 .zreg,107 .zreg,
117 }),108 }),
...@@ -120,9 +111,6 @@ pub const all_features = blk: {...@@ -120,9 +111,6 @@ pub const all_features = blk: {
120 .llvm_name = "hvxv67",111 .llvm_name = "hvxv67",
121 .description = "Hexagon HVX instructions",112 .description = "Hexagon HVX instructions",
122 .dependencies = featureSet(&[_]Feature{113 .dependencies = featureSet(&[_]Feature{
123 .hvxv60,
124 .hvxv62,
125 .hvxv65,
126 .hvxv66,114 .hvxv66,
127 }),115 }),
128 };116 };
...@@ -248,7 +236,6 @@ pub const cpu = struct {...@@ -248,7 +236,6 @@ pub const cpu = struct {
248 .memops,236 .memops,
249 .nvj,237 .nvj,
250 .nvs,238 .nvs,
251 .packets,
252 .prev65,239 .prev65,
253 .small_data,240 .small_data,
254 .v5,241 .v5,
...@@ -265,7 +252,6 @@ pub const cpu = struct {...@@ -265,7 +252,6 @@ pub const cpu = struct {
265 .memops,252 .memops,
266 .nvj,253 .nvj,
267 .nvs,254 .nvs,
268 .packets,
269 .prev65,255 .prev65,
270 .small_data,256 .small_data,
271 .v5,257 .v5,
...@@ -280,7 +266,6 @@ pub const cpu = struct {...@@ -280,7 +266,6 @@ pub const cpu = struct {
280 .memops,266 .memops,
281 .nvj,267 .nvj,
282 .nvs,268 .nvs,
283 .packets,
284 .prev65,269 .prev65,
285 .small_data,270 .small_data,
286 .v5,271 .v5,
...@@ -296,7 +281,6 @@ pub const cpu = struct {...@@ -296,7 +281,6 @@ pub const cpu = struct {
296 .memops,281 .memops,
297 .nvj,282 .nvj,
298 .nvs,283 .nvs,
299 .packets,
300 .prev65,284 .prev65,
301 .small_data,285 .small_data,
302 .v5,286 .v5,
...@@ -313,7 +297,6 @@ pub const cpu = struct {...@@ -313,7 +297,6 @@ pub const cpu = struct {
313 .memops,297 .memops,
314 .nvj,298 .nvj,
315 .nvs,299 .nvs,
316 .packets,
317 .prev65,300 .prev65,
318 .small_data,301 .small_data,
319 .v5,302 .v5,
...@@ -332,7 +315,6 @@ pub const cpu = struct {...@@ -332,7 +315,6 @@ pub const cpu = struct {
332 .memops,315 .memops,
333 .nvj,316 .nvj,
334 .nvs,317 .nvs,
335 .packets,
336 .small_data,318 .small_data,
337 .v5,319 .v5,
338 .v55,320 .v55,
...@@ -351,7 +333,6 @@ pub const cpu = struct {...@@ -351,7 +333,6 @@ pub const cpu = struct {
351 .memops,333 .memops,
352 .nvj,334 .nvj,
353 .nvs,335 .nvs,
354 .packets,
355 .small_data,336 .small_data,
356 .v5,337 .v5,
357 .v55,338 .v55,
...@@ -371,7 +352,6 @@ pub const cpu = struct {...@@ -371,7 +352,6 @@ pub const cpu = struct {
371 .memops,352 .memops,
372 .nvj,353 .nvj,
373 .nvs,354 .nvs,
374 .packets,
375 .small_data,355 .small_data,
376 .v5,356 .v5,
377 .v55,357 .v55,
...@@ -391,7 +371,6 @@ pub const cpu = struct {...@@ -391,7 +371,6 @@ pub const cpu = struct {
391 .mem_noshuf,371 .mem_noshuf,
392 .memops,372 .memops,
393 .nvs,373 .nvs,
394 .packets,
395 .small_data,374 .small_data,
396 .tinycore,375 .tinycore,
397 .v5,376 .v5,
lib/std/target/mips.zig+2-11
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
...@@ -108,7 +105,6 @@ pub const all_features = blk: {...@@ -108,7 +105,6 @@ pub const all_features = blk: {
108 .llvm_name = "dspr3",105 .llvm_name = "dspr3",
109 .description = "Mips DSP-R3 ASE",106 .description = "Mips DSP-R3 ASE",
110 .dependencies = featureSet(&[_]Feature{107 .dependencies = featureSet(&[_]Feature{
111 .dsp,
112 .dspr2,108 .dspr2,
113 }),109 }),
114 };110 };
...@@ -301,10 +297,8 @@ pub const all_features = blk: {...@@ -301,10 +297,8 @@ pub const all_features = blk: {
301 .llvm_name = "mips64r6",297 .llvm_name = "mips64r6",
302 .description = "Mips64r6 ISA Support [experimental]",298 .description = "Mips64r6 ISA Support [experimental]",
303 .dependencies = featureSet(&[_]Feature{299 .dependencies = featureSet(&[_]Feature{
304 .abs2008,
305 .mips32r6,300 .mips32r6,
306 .mips64r5,301 .mips64r5,
307 .nan2008,
308 }),302 }),
309 };303 };
310 result[@enumToInt(Feature.msa)] = .{304 result[@enumToInt(Feature.msa)] = .{
...@@ -515,16 +509,13 @@ pub const cpu = struct {...@@ -515,16 +509,13 @@ pub const cpu = struct {
515 .llvm_name = "octeon",509 .llvm_name = "octeon",
516 .features = featureSet(&[_]Feature{510 .features = featureSet(&[_]Feature{
517 .cnmips,511 .cnmips,
518 .mips64r2,
519 }),512 }),
520 };513 };
521 pub const @"octeon+" = CpuModel{514 pub const @"octeon+" = CpuModel{
522 .name = "octeon+",515 .name = "octeon+",
523 .llvm_name = "octeon+",516 .llvm_name = "octeon+",
524 .features = featureSet(&[_]Feature{517 .features = featureSet(&[_]Feature{
525 .cnmips,
526 .cnmipsp,518 .cnmipsp,
527 .mips64r2,
528 }),519 }),
529 };520 };
530 pub const p5600 = CpuModel{521 pub const p5600 = CpuModel{
lib/std/target/msp430.zig+2-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
lib/std/target/nvptx.zig+2-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
lib/std/target/powerpc.zig+51-113
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
...@@ -10,6 +7,7 @@ const CpuModel = std.Target.Cpu.Model;...@@ -10,6 +7,7 @@ const CpuModel = std.Target.Cpu.Model;
10pub const Feature = enum {7pub const Feature = enum {
11 @"64bit",8 @"64bit",
12 @"64bitregs",9 @"64bitregs",
10 aix,
13 allow_unaligned_fp_access,11 allow_unaligned_fp_access,
14 altivec,12 altivec,
15 booke,13 booke,
...@@ -19,6 +17,7 @@ pub const Feature = enum {...@@ -19,6 +17,7 @@ pub const Feature = enum {
19 crypto,17 crypto,
20 direct_move,18 direct_move,
21 e500,19 e500,
20 efpu2,
22 extdiv,21 extdiv,
23 fcpsgn,22 fcpsgn,
24 float128,23 float128,
...@@ -46,6 +45,7 @@ pub const Feature = enum {...@@ -46,6 +45,7 @@ pub const Feature = enum {
46 longcall,45 longcall,
47 mfocrf,46 mfocrf,
48 mma,47 mma,
48 modern_aix_as,
49 msync,49 msync,
50 paired_vector_memops,50 paired_vector_memops,
51 partword_atomics,51 partword_atomics,
...@@ -62,7 +62,6 @@ pub const Feature = enum {...@@ -62,7 +62,6 @@ pub const Feature = enum {
62 ppc6xx,62 ppc6xx,
63 predictable_select_expensive,63 predictable_select_expensive,
64 prefix_instrs,64 prefix_instrs,
65 qpx,
66 recipprec,65 recipprec,
67 secure_plt,66 secure_plt,
68 slow_popcntd,67 slow_popcntd,
...@@ -89,6 +88,11 @@ pub const all_features = blk: {...@@ -89,6 +88,11 @@ pub const all_features = blk: {
89 .description = "Enable 64-bit registers usage for ppc32 [beta]",88 .description = "Enable 64-bit registers usage for ppc32 [beta]",
90 .dependencies = featureSet(&[_]Feature{}),89 .dependencies = featureSet(&[_]Feature{}),
91 };90 };
91 result[@enumToInt(Feature.aix)] = .{
92 .llvm_name = "aix",
93 .description = "AIX OS",
94 .dependencies = featureSet(&[_]Feature{}),
95 };
92 result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{96 result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{
93 .llvm_name = "allow-unaligned-fp-access",97 .llvm_name = "allow-unaligned-fp-access",
94 .description = "CPU does not trap on unaligned FP access",98 .description = "CPU does not trap on unaligned FP access",
...@@ -142,6 +146,13 @@ pub const all_features = blk: {...@@ -142,6 +146,13 @@ pub const all_features = blk: {
142 .description = "Enable E500/E500mc instructions",146 .description = "Enable E500/E500mc instructions",
143 .dependencies = featureSet(&[_]Feature{}),147 .dependencies = featureSet(&[_]Feature{}),
144 };148 };
149 result[@enumToInt(Feature.efpu2)] = .{
150 .llvm_name = "efpu2",
151 .description = "Enable Embedded Floating-Point APU 2 instructions",
152 .dependencies = featureSet(&[_]Feature{
153 .spe,
154 }),
155 };
145 result[@enumToInt(Feature.extdiv)] = .{156 result[@enumToInt(Feature.extdiv)] = .{
146 .llvm_name = "extdiv",157 .llvm_name = "extdiv",
147 .description = "Enable extended divide instructions",158 .description = "Enable extended divide instructions",
...@@ -311,6 +322,11 @@ pub const all_features = blk: {...@@ -311,6 +322,11 @@ pub const all_features = blk: {
311 .power9_altivec,322 .power9_altivec,
312 }),323 }),
313 };324 };
325 result[@enumToInt(Feature.modern_aix_as)] = .{
326 .llvm_name = "modern-aix-as",
327 .description = "AIX system assembler is modern enough to support new mnes",
328 .dependencies = featureSet(&[_]Feature{}),
329 };
314 result[@enumToInt(Feature.msync)] = .{330 result[@enumToInt(Feature.msync)] = .{
315 .llvm_name = "msync",331 .llvm_name = "msync",
316 .description = "Has only the msync instruction instead of sync",332 .description = "Has only the msync instruction instead of sync",
...@@ -334,7 +350,6 @@ pub const all_features = blk: {...@@ -334,7 +350,6 @@ pub const all_features = blk: {
334 .llvm_name = "pcrelative-memops",350 .llvm_name = "pcrelative-memops",
335 .description = "Enable PC relative Memory Ops",351 .description = "Enable PC relative Memory Ops",
336 .dependencies = featureSet(&[_]Feature{352 .dependencies = featureSet(&[_]Feature{
337 .isa_v30_instructions,
338 .prefix_instrs,353 .prefix_instrs,
339 }),354 }),
340 };355 };
...@@ -378,7 +393,6 @@ pub const all_features = blk: {...@@ -378,7 +393,6 @@ pub const all_features = blk: {
378 .llvm_name = "power9-vector",393 .llvm_name = "power9-vector",
379 .description = "Enable POWER9 vector instructions",394 .description = "Enable POWER9 vector instructions",
380 .dependencies = featureSet(&[_]Feature{395 .dependencies = featureSet(&[_]Feature{
381 .isa_v30_instructions,
382 .power8_vector,396 .power8_vector,
383 .power9_altivec,397 .power9_altivec,
384 }),398 }),
...@@ -412,18 +426,10 @@ pub const all_features = blk: {...@@ -412,18 +426,10 @@ pub const all_features = blk: {
412 .llvm_name = "prefix-instrs",426 .llvm_name = "prefix-instrs",
413 .description = "Enable prefixed instructions",427 .description = "Enable prefixed instructions",
414 .dependencies = featureSet(&[_]Feature{428 .dependencies = featureSet(&[_]Feature{
415 .isa_v30_instructions,
416 .power8_vector,429 .power8_vector,
417 .power9_altivec,430 .power9_altivec,
418 }),431 }),
419 };432 };
420 result[@enumToInt(Feature.qpx)] = .{
421 .llvm_name = null,
422 .description = "Enable QPX instructions",
423 .dependencies = featureSet(&[_]Feature{
424 .fpu,
425 }),
426 };
427 result[@enumToInt(Feature.recipprec)] = .{433 result[@enumToInt(Feature.recipprec)] = .{
428 .llvm_name = "recipprec",434 .llvm_name = "recipprec",
429 .description = "Assume higher precision reciprocal estimates",435 .description = "Assume higher precision reciprocal estimates",
...@@ -479,94 +485,90 @@ pub const all_features = blk: {...@@ -479,94 +485,90 @@ pub const all_features = blk: {
479};485};
480486
481pub const cpu = struct {487pub const cpu = struct {
482 pub const @"ppc440" = CpuModel{488 pub const @"440" = CpuModel{
483 .name = "ppc440",489 .name = "440",
484 .llvm_name = "440",490 .llvm_name = "440",
485 .features = featureSet(&[_]Feature{491 .features = featureSet(&[_]Feature{
486 .booke,
487 .fres,492 .fres,
488 .frsqrte,493 .frsqrte,
489 .icbt,
490 .isel,494 .isel,
491 .msync,495 .msync,
492 }),496 }),
493 };497 };
494 pub const @"ppc450" = CpuModel{498 pub const @"450" = CpuModel{
495 .name = "ppc450",499 .name = "450",
496 .llvm_name = "450",500 .llvm_name = "450",
497 .features = featureSet(&[_]Feature{501 .features = featureSet(&[_]Feature{
498 .booke,
499 .fres,502 .fres,
500 .frsqrte,503 .frsqrte,
501 .icbt,
502 .isel,504 .isel,
503 .msync,505 .msync,
504 }),506 }),
505 };507 };
506 pub const @"ppc601" = CpuModel{508 pub const @"601" = CpuModel{
507 .name = "ppc601",509 .name = "601",
508 .llvm_name = "601",510 .llvm_name = "601",
509 .features = featureSet(&[_]Feature{511 .features = featureSet(&[_]Feature{
510 .fpu,512 .fpu,
511 }),513 }),
512 };514 };
513 pub const @"ppc602" = CpuModel{515 pub const @"602" = CpuModel{
514 .name = "ppc602",516 .name = "602",
515 .llvm_name = "602",517 .llvm_name = "602",
516 .features = featureSet(&[_]Feature{518 .features = featureSet(&[_]Feature{
517 .fpu,519 .fpu,
518 }),520 }),
519 };521 };
520 pub const @"ppc603" = CpuModel{522 pub const @"603" = CpuModel{
521 .name = "ppc603",523 .name = "603",
522 .llvm_name = "603",524 .llvm_name = "603",
523 .features = featureSet(&[_]Feature{525 .features = featureSet(&[_]Feature{
524 .fres,526 .fres,
525 .frsqrte,527 .frsqrte,
526 }),528 }),
527 };529 };
528 pub const @"ppc603e" = CpuModel{530 pub const @"603e" = CpuModel{
529 .name = "ppc603e",531 .name = "603e",
530 .llvm_name = "603e",532 .llvm_name = "603e",
531 .features = featureSet(&[_]Feature{533 .features = featureSet(&[_]Feature{
532 .fres,534 .fres,
533 .frsqrte,535 .frsqrte,
534 }),536 }),
535 };537 };
536 pub const @"ppc603ev" = CpuModel{538 pub const @"603ev" = CpuModel{
537 .name = "ppc603ev",539 .name = "603ev",
538 .llvm_name = "603ev",540 .llvm_name = "603ev",
539 .features = featureSet(&[_]Feature{541 .features = featureSet(&[_]Feature{
540 .fres,542 .fres,
541 .frsqrte,543 .frsqrte,
542 }),544 }),
543 };545 };
544 pub const @"ppc604" = CpuModel{546 pub const @"604" = CpuModel{
545 .name = "ppc604",547 .name = "604",
546 .llvm_name = "604",548 .llvm_name = "604",
547 .features = featureSet(&[_]Feature{549 .features = featureSet(&[_]Feature{
548 .fres,550 .fres,
549 .frsqrte,551 .frsqrte,
550 }),552 }),
551 };553 };
552 pub const @"ppc604e" = CpuModel{554 pub const @"604e" = CpuModel{
553 .name = "ppc604e",555 .name = "604e",
554 .llvm_name = "604e",556 .llvm_name = "604e",
555 .features = featureSet(&[_]Feature{557 .features = featureSet(&[_]Feature{
556 .fres,558 .fres,
557 .frsqrte,559 .frsqrte,
558 }),560 }),
559 };561 };
560 pub const @"ppc620" = CpuModel{562 pub const @"620" = CpuModel{
561 .name = "ppc620",563 .name = "620",
562 .llvm_name = "620",564 .llvm_name = "620",
563 .features = featureSet(&[_]Feature{565 .features = featureSet(&[_]Feature{
564 .fres,566 .fres,
565 .frsqrte,567 .frsqrte,
566 }),568 }),
567 };569 };
568 pub const @"ppc7400" = CpuModel{570 pub const @"7400" = CpuModel{
569 .name = "ppc7400",571 .name = "7400",
570 .llvm_name = "7400",572 .llvm_name = "7400",
571 .features = featureSet(&[_]Feature{573 .features = featureSet(&[_]Feature{
572 .altivec,574 .altivec,
...@@ -574,8 +576,8 @@ pub const cpu = struct {...@@ -574,8 +576,8 @@ pub const cpu = struct {
574 .frsqrte,576 .frsqrte,
575 }),577 }),
576 };578 };
577 pub const @"ppc7450" = CpuModel{579 pub const @"7450" = CpuModel{
578 .name = "ppc7450",580 .name = "7450",
579 .llvm_name = "7450",581 .llvm_name = "7450",
580 .features = featureSet(&[_]Feature{582 .features = featureSet(&[_]Feature{
581 .altivec,583 .altivec,
...@@ -583,16 +585,16 @@ pub const cpu = struct {...@@ -583,16 +585,16 @@ pub const cpu = struct {
583 .frsqrte,585 .frsqrte,
584 }),586 }),
585 };587 };
586 pub const @"ppc750" = CpuModel{588 pub const @"750" = CpuModel{
587 .name = "ppc750",589 .name = "750",
588 .llvm_name = "750",590 .llvm_name = "750",
589 .features = featureSet(&[_]Feature{591 .features = featureSet(&[_]Feature{
590 .fres,592 .fres,
591 .frsqrte,593 .frsqrte,
592 }),594 }),
593 };595 };
594 pub const @"ppc970" = CpuModel{596 pub const @"970" = CpuModel{
595 .name = "ppc970",597 .name = "970",
596 .llvm_name = "970",598 .llvm_name = "970",
597 .features = featureSet(&[_]Feature{599 .features = featureSet(&[_]Feature{
598 .@"64bit",600 .@"64bit",
...@@ -619,7 +621,6 @@ pub const cpu = struct {...@@ -619,7 +621,6 @@ pub const cpu = struct {
619 .frsqrte,621 .frsqrte,
620 .frsqrtes,622 .frsqrtes,
621 .fsqrt,623 .fsqrt,
622 .icbt,
623 .isel,624 .isel,
624 .ldbrx,625 .ldbrx,
625 .lfiwax,626 .lfiwax,
...@@ -629,38 +630,10 @@ pub const cpu = struct {...@@ -629,38 +630,10 @@ pub const cpu = struct {
629 .stfiwx,630 .stfiwx,
630 }),631 }),
631 };632 };
632 pub const a2q = CpuModel{
633 .name = "a2q",
634 .llvm_name = "a2q",
635 .features = featureSet(&[_]Feature{
636 .@"64bit",
637 .booke,
638 .cmpb,
639 .fcpsgn,
640 .fpcvt,
641 .fprnd,
642 .fre,
643 .fres,
644 .frsqrte,
645 .frsqrtes,
646 .fsqrt,
647 .icbt,
648 .isel,
649 .ldbrx,
650 .lfiwax,
651 .mfocrf,
652 .qpx,
653 .recipprec,
654 .slow_popcntd,
655 .stfiwx,
656 }),
657 };
658 pub const e500 = CpuModel{633 pub const e500 = CpuModel{
659 .name = "e500",634 .name = "e500",
660 .llvm_name = "e500",635 .llvm_name = "e500",
661 .features = featureSet(&[_]Feature{636 .features = featureSet(&[_]Feature{
662 .booke,
663 .icbt,
664 .isel,637 .isel,
665 .msync,638 .msync,
666 .spe,639 .spe,
...@@ -671,7 +644,6 @@ pub const cpu = struct {...@@ -671,7 +644,6 @@ pub const cpu = struct {
671 .llvm_name = "e500mc",644 .llvm_name = "e500mc",
672 .features = featureSet(&[_]Feature{645 .features = featureSet(&[_]Feature{
673 .booke,646 .booke,
674 .icbt,
675 .isel,647 .isel,
676 .stfiwx,648 .stfiwx,
677 }),649 }),
...@@ -682,7 +654,6 @@ pub const cpu = struct {...@@ -682,7 +654,6 @@ pub const cpu = struct {
682 .features = featureSet(&[_]Feature{654 .features = featureSet(&[_]Feature{
683 .@"64bit",655 .@"64bit",
684 .booke,656 .booke,
685 .icbt,
686 .isel,657 .isel,
687 .mfocrf,658 .mfocrf,
688 .stfiwx,659 .stfiwx,
...@@ -694,7 +665,6 @@ pub const cpu = struct {...@@ -694,7 +665,6 @@ pub const cpu = struct {
694 .features = featureSet(&[_]Feature{665 .features = featureSet(&[_]Feature{
695 .@"64bit",666 .@"64bit",
696 .allow_unaligned_fp_access,667 .allow_unaligned_fp_access,
697 .altivec,
698 .bpermd,668 .bpermd,
699 .cmpb,669 .cmpb,
700 .crypto,670 .crypto,
...@@ -711,30 +681,21 @@ pub const cpu = struct {...@@ -711,30 +681,21 @@ pub const cpu = struct {
711 .fuse_store,681 .fuse_store,
712 .htm,682 .htm,
713 .icbt,683 .icbt,
714 .isa_v30_instructions,
715 .isa_v31_instructions,
716 .isel,684 .isel,
717 .ldbrx,685 .ldbrx,
718 .lfiwax,686 .lfiwax,
719 .mfocrf,687 .mfocrf,
720 .mma,688 .mma,
721 .paired_vector_memops,
722 .partword_atomics,689 .partword_atomics,
723 .pcrelative_memops,690 .pcrelative_memops,
724 .popcntd,691 .popcntd,
725 .power10_vector,692 .power10_vector,
726 .power8_altivec,
727 .power8_vector,
728 .power9_altivec,
729 .power9_vector,
730 .ppc_postra_sched,693 .ppc_postra_sched,
731 .ppc_prera_sched,694 .ppc_prera_sched,
732 .predictable_select_expensive,695 .predictable_select_expensive,
733 .prefix_instrs,
734 .recipprec,696 .recipprec,
735 .stfiwx,697 .stfiwx,
736 .two_const_nr,698 .two_const_nr,
737 .vsx,
738 }),699 }),
739 };700 };
740 pub const g3 = CpuModel{701 pub const g3 = CpuModel{
...@@ -792,7 +753,7 @@ pub const cpu = struct {...@@ -792,7 +753,7 @@ pub const cpu = struct {
792 };753 };
793 pub const ppc32 = CpuModel{754 pub const ppc32 = CpuModel{
794 .name = "ppc32",755 .name = "ppc32",
795 .llvm_name = "ppc",756 .llvm_name = "ppc32",
796 .features = featureSet(&[_]Feature{757 .features = featureSet(&[_]Feature{
797 .hard_float,758 .hard_float,
798 }),759 }),
...@@ -816,7 +777,6 @@ pub const cpu = struct {...@@ -816,7 +777,6 @@ pub const cpu = struct {
816 .features = featureSet(&[_]Feature{777 .features = featureSet(&[_]Feature{
817 .@"64bit",778 .@"64bit",
818 .allow_unaligned_fp_access,779 .allow_unaligned_fp_access,
819 .altivec,
820 .bpermd,780 .bpermd,
821 .cmpb,781 .cmpb,
822 .crypto,782 .crypto,
...@@ -840,13 +800,11 @@ pub const cpu = struct {...@@ -840,13 +800,11 @@ pub const cpu = struct {
840 .mfocrf,800 .mfocrf,
841 .partword_atomics,801 .partword_atomics,
842 .popcntd,802 .popcntd,
843 .power8_altivec,
844 .power8_vector,803 .power8_vector,
845 .predictable_select_expensive,804 .predictable_select_expensive,
846 .recipprec,805 .recipprec,
847 .stfiwx,806 .stfiwx,
848 .two_const_nr,807 .two_const_nr,
849 .vsx,
850 }),808 }),
851 };809 };
852 pub const pwr10 = CpuModel{810 pub const pwr10 = CpuModel{
...@@ -855,7 +813,6 @@ pub const cpu = struct {...@@ -855,7 +813,6 @@ pub const cpu = struct {
855 .features = featureSet(&[_]Feature{813 .features = featureSet(&[_]Feature{
856 .@"64bit",814 .@"64bit",
857 .allow_unaligned_fp_access,815 .allow_unaligned_fp_access,
858 .altivec,
859 .bpermd,816 .bpermd,
860 .cmpb,817 .cmpb,
861 .crypto,818 .crypto,
...@@ -872,30 +829,21 @@ pub const cpu = struct {...@@ -872,30 +829,21 @@ pub const cpu = struct {
872 .fuse_store,829 .fuse_store,
873 .htm,830 .htm,
874 .icbt,831 .icbt,
875 .isa_v30_instructions,
876 .isa_v31_instructions,
877 .isel,832 .isel,
878 .ldbrx,833 .ldbrx,
879 .lfiwax,834 .lfiwax,
880 .mfocrf,835 .mfocrf,
881 .mma,836 .mma,
882 .paired_vector_memops,
883 .partword_atomics,837 .partword_atomics,
884 .pcrelative_memops,838 .pcrelative_memops,
885 .popcntd,839 .popcntd,
886 .power10_vector,840 .power10_vector,
887 .power8_altivec,
888 .power8_vector,
889 .power9_altivec,
890 .power9_vector,
891 .ppc_postra_sched,841 .ppc_postra_sched,
892 .ppc_prera_sched,842 .ppc_prera_sched,
893 .predictable_select_expensive,843 .predictable_select_expensive,
894 .prefix_instrs,
895 .recipprec,844 .recipprec,
896 .stfiwx,845 .stfiwx,
897 .two_const_nr,846 .two_const_nr,
898 .vsx,
899 }),847 }),
900 };848 };
901 pub const pwr3 = CpuModel{849 pub const pwr3 = CpuModel{
...@@ -1000,7 +948,6 @@ pub const cpu = struct {...@@ -1000,7 +948,6 @@ pub const cpu = struct {
1000 .features = featureSet(&[_]Feature{948 .features = featureSet(&[_]Feature{
1001 .@"64bit",949 .@"64bit",
1002 .allow_unaligned_fp_access,950 .allow_unaligned_fp_access,
1003 .altivec,
1004 .bpermd,951 .bpermd,
1005 .cmpb,952 .cmpb,
1006 .extdiv,953 .extdiv,
...@@ -1029,7 +976,6 @@ pub const cpu = struct {...@@ -1029,7 +976,6 @@ pub const cpu = struct {
1029 .features = featureSet(&[_]Feature{976 .features = featureSet(&[_]Feature{
1030 .@"64bit",977 .@"64bit",
1031 .allow_unaligned_fp_access,978 .allow_unaligned_fp_access,
1032 .altivec,
1033 .bpermd,979 .bpermd,
1034 .cmpb,980 .cmpb,
1035 .crypto,981 .crypto,
...@@ -1053,13 +999,11 @@ pub const cpu = struct {...@@ -1053,13 +999,11 @@ pub const cpu = struct {
1053 .mfocrf,999 .mfocrf,
1054 .partword_atomics,1000 .partword_atomics,
1055 .popcntd,1001 .popcntd,
1056 .power8_altivec,
1057 .power8_vector,1002 .power8_vector,
1058 .predictable_select_expensive,1003 .predictable_select_expensive,
1059 .recipprec,1004 .recipprec,
1060 .stfiwx,1005 .stfiwx,
1061 .two_const_nr,1006 .two_const_nr,
1062 .vsx,
1063 }),1007 }),
1064 };1008 };
1065 pub const pwr9 = CpuModel{1009 pub const pwr9 = CpuModel{
...@@ -1068,7 +1012,6 @@ pub const cpu = struct {...@@ -1068,7 +1012,6 @@ pub const cpu = struct {
1068 .features = featureSet(&[_]Feature{1012 .features = featureSet(&[_]Feature{
1069 .@"64bit",1013 .@"64bit",
1070 .allow_unaligned_fp_access,1014 .allow_unaligned_fp_access,
1071 .altivec,
1072 .bpermd,1015 .bpermd,
1073 .cmpb,1016 .cmpb,
1074 .crypto,1017 .crypto,
...@@ -1084,16 +1027,12 @@ pub const cpu = struct {...@@ -1084,16 +1027,12 @@ pub const cpu = struct {
1084 .fsqrt,1027 .fsqrt,
1085 .htm,1028 .htm,
1086 .icbt,1029 .icbt,
1087 .isa_v30_instructions,
1088 .isel,1030 .isel,
1089 .ldbrx,1031 .ldbrx,
1090 .lfiwax,1032 .lfiwax,
1091 .mfocrf,1033 .mfocrf,
1092 .partword_atomics,1034 .partword_atomics,
1093 .popcntd,1035 .popcntd,
1094 .power8_altivec,
1095 .power8_vector,
1096 .power9_altivec,
1097 .power9_vector,1036 .power9_vector,
1098 .ppc_postra_sched,1037 .ppc_postra_sched,
1099 .ppc_prera_sched,1038 .ppc_prera_sched,
...@@ -1102,7 +1041,6 @@ pub const cpu = struct {...@@ -1102,7 +1041,6 @@ pub const cpu = struct {
1102 .stfiwx,1041 .stfiwx,
1103 .two_const_nr,1042 .two_const_nr,
1104 .vectors_use_two_units,1043 .vectors_use_two_units,
1105 .vsx,
1106 }),1044 }),
1107 };1045 };
1108};1046};
lib/std/target/sparc.zig+7-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
...@@ -160,6 +157,11 @@ pub const cpu = struct {...@@ -160,6 +157,11 @@ pub const cpu = struct {
160 .llvm_name = "f934",157 .llvm_name = "f934",
161 .features = featureSet(&[_]Feature{}),158 .features = featureSet(&[_]Feature{}),
162 };159 };
160 pub const generic = CpuModel{
161 .name = "generic",
162 .llvm_name = "generic",
163 .features = featureSet(&[_]Feature{}),
164 };
163 pub const gr712rc = CpuModel{165 pub const gr712rc = CpuModel{
164 .name = "gr712rc",166 .name = "gr712rc",
165 .llvm_name = "gr712rc",167 .llvm_name = "gr712rc",
lib/std/target/systemz.zig+2-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
lib/std/target/ve.zig created+36
...@@ -0,0 +1,36 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 vpu,
9};
10
11pub usingnamespace CpuFeature.feature_set_fns(Feature);
12
13pub const all_features = blk: {
14 const len = @typeInfo(Feature).Enum.fields.len;
15 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
16 var result: [len]CpuFeature = undefined;
17 result[@enumToInt(Feature.vpu)] = .{
18 .llvm_name = "vpu",
19 .description = "Enable the VPU",
20 .dependencies = featureSet(&[_]Feature{}),
21 };
22 const ti = @typeInfo(Feature);
23 for (result) |*elem, i| {
24 elem.index = i;
25 elem.name = ti.Enum.fields[i].name;
26 }
27 break :blk result;
28};
29
30pub const cpu = struct {
31 pub const generic = CpuModel{
32 .name = "generic",
33 .llvm_name = "generic",
34 .features = featureSet(&[_]Feature{}),
35 };
36};
lib/std/target/wasm.zig+2-5
...@@ -1,8 +1,5 @@...@@ -1,8 +1,5 @@
1// SPDX-License-Identifier: MIT1//! This file is auto-generated by tools/update_cpu_features.zig.
2// Copyright (c) 2015-2021 Zig Contributors2
3// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
4// The MIT license requires this copyright notice to be included in all copies
5// and substantial portions of the software.
6const std = @import("../std.zig");3const std = @import("../std.zig");
7const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
8const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;