authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2019-09-24 20:56:04-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2019-09-24 20:56:04-04:00
log53210b2304990e9b3b0f35f847e13d4ea4ae4ced
tree271d7690eebee3cb87ee4bcc3b62d0719b235856
parent9983501ff2cccf828bb357dddefb21e36813046d
signaturelock-open Commit is signed but in an unrecognized format.

better default enabled features for riscv

Until ability to specify target CPU features (#2883) is done, this commit gives riscv target better default features. This side-steps #3275 which is a deficiency in compiler-rt when features do not include 32 bit integer division. With this commit, RISC-V compiler-rt tests pass and Hello World works both pure-zig and with musl libc.

1 files changed, 8 insertions(+), 2 deletions(-)

src/codegen.cpp+8-2
...@@ -30,6 +30,11 @@ enum ResumeId {...@@ -30,6 +30,11 @@ enum ResumeId {
30 ResumeIdCall,30 ResumeIdCall,
31};31};
3232
33// TODO https://github.com/ziglang/zig/issues/2883
34// Until then we have this same default as Clang.
35// This avoids https://github.com/ziglang/zig/issues/3275
36static const char *riscv_default_features = "+a,+c,+d,+f,+m,+relax";
37
33static void init_darwin_native(CodeGen *g) {38static void init_darwin_native(CodeGen *g) {
34 char *osx_target = getenv("MACOSX_DEPLOYMENT_TARGET");39 char *osx_target = getenv("MACOSX_DEPLOYMENT_TARGET");
35 char *ios_target = getenv("IPHONEOS_DEPLOYMENT_TARGET");40 char *ios_target = getenv("IPHONEOS_DEPLOYMENT_TARGET");
...@@ -8720,8 +8725,9 @@ static void init(CodeGen *g) {...@@ -8720,8 +8725,9 @@ static void init(CodeGen *g) {
8720 }8725 }
8721 } else if (target_is_riscv(g->zig_target)) {8726 } else if (target_is_riscv(g->zig_target)) {
8722 // TODO https://github.com/ziglang/zig/issues/28838727 // TODO https://github.com/ziglang/zig/issues/2883
8728 // Be aware of https://github.com/ziglang/zig/issues/3275
8723 target_specific_cpu_args = "";8729 target_specific_cpu_args = "";
8724 target_specific_features = "+a";8730 target_specific_features = riscv_default_features;
8725 } else {8731 } else {
8726 target_specific_cpu_args = "";8732 target_specific_cpu_args = "";
8727 target_specific_features = "";8733 target_specific_features = "";
...@@ -9007,7 +9013,7 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa...@@ -9007,7 +9013,7 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa
9007 args.append("-Xclang");9013 args.append("-Xclang");
9008 args.append("-target-feature");9014 args.append("-target-feature");
9009 args.append("-Xclang");9015 args.append("-Xclang");
9010 args.append("+a");9016 args.append(riscv_default_features);
9011 }9017 }
9012 }9018 }
9013 if (g->zig_target->os == OsFreestanding) {9019 if (g->zig_target->os == OsFreestanding) {