Commit 587eddda283dbe0bd1d6529d1c5924acfe252c9c | zig

author	Alex Rønne Petersen <alex@alexrp.com> 2025-07-16 06:33:25+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2025-08-30 06:36:41+02:00
log	587eddda283dbe0bd1d6529d1c5924acfe252c9c
tree	5564bb1e8efeb28a8158f55b3d96685e96be33fe
parent	94f95fefe346977ff47858a003cb22cae984fbb8
signature	Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: update CPU features to LLVM 21

13 files changed, 2227 insertions(+), 212 deletions(-)

lib
- std
  - Target
    aarch64.zig
    amdgcn.zig
    arm.zig
    avr.zig
    loongarch.zig
    mips.zig
    nvptx.zig
    powerpc.zig
    riscv.zig
    s390x.zig
    sparc.zig
    x86.zig
    xtensa.zig

lib/std/Target/aarch64.zig+369-28

...	...	@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
	8	a320,
8	9	addr_lsl_slow_14,
9	10	aes,
10	11	aggressive_fma,
...	...	@@ -44,6 +45,7 @@ pub const Feature = enum {
44	45	crypto,
45	46	cssc,
46	47	d128,
	48	disable_fast_inc_vl,
47	49	disable_latency_sched_heuristic,
48	50	disable_ldp,
49	51	disable_stp,
...	...	@@ -54,6 +56,7 @@ pub const Feature = enum {
54	56	el3,
55	57	enable_select_opt,
56	58	ete,
	59	execute_only,
57	60	exynos_cheap_as_move,
58	61	f32mm,
59	62	f64mm,
...	...	@@ -114,6 +117,7 @@ pub const Feature = enum {
114	117	no_zcz_fp,
115	118	nv,
116	119	occmo,
	120	olympus,
117	121	outline_atomics,
118	122	pan,
119	123	pan_rwv,
...	...	@@ -187,6 +191,7 @@ pub const Feature = enum {
187	191	ssbs,
188	192	ssve_aes,
189	193	ssve_bitperm,
	194	ssve_fexpa,
190	195	ssve_fp8dot2,
191	196	ssve_fp8dot4,
192	197	ssve_fp8fma,
...	...	@@ -207,6 +212,8 @@ pub const Feature = enum {
207	212	sve_bfscale,
208	213	sve_bitperm,
209	214	sve_f16f32mm,
	215	sve_sha3,
	216	sve_sm4,
210	217	tagged_globals,
211	218	the,
212	219	tlb_rmi,
...	...	@@ -244,7 +251,10 @@ pub const Feature = enum {
244	251	vh,
245	252	wfxt,
246	253	xs,
247		zcm,
	254	zcm_fpr32,
	255	zcm_fpr64,
	256	zcm_gpr32,
	257	zcm_gpr64,
248	258	zcz,
249	259	zcz_fp_workaround,
250	260	zcz_gp,
...	...	@@ -260,6 +270,15 @@ pub const all_features = blk: {
260	270	const len = @typeInfo(Feature).@"enum".fields.len;
261	271	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
262	272	var result: [len]CpuFeature = undefined;
	273	result[@intFromEnum(Feature.a320)] = .{
	274	.llvm_name = "a320",
	275	.description = "Cortex-A320 ARM processors",
	276	.dependencies = featureSet(&[_]Feature{
	277	.fuse_adrp_add,
	278	.fuse_aes,
	279	.use_postra_scheduler,
	280	}),
	281	};
263	282	result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{
264	283	.llvm_name = "addr-lsl-slow-14",
265	284	.description = "Address operands with shift amount of 1 or 4 are slow",
...	...	@@ -472,6 +491,11 @@ pub const all_features = blk: {
472	491	.lse128,
473	492	}),
474	493	};
	494	result[@intFromEnum(Feature.disable_fast_inc_vl)] = .{
	495	.llvm_name = "disable-fast-inc-vl",
	496	.description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL",
	497	.dependencies = featureSet(&[_]Feature{}),
	498	};
475	499	result[@intFromEnum(Feature.disable_latency_sched_heuristic)] = .{
476	500	.llvm_name = "disable-latency-sched-heuristic",
477	501	.description = "Disable latency scheduling heuristic",
...	...	@@ -526,6 +550,11 @@ pub const all_features = blk: {
526	550	.trbe,
527	551	}),
528	552	};
	553	result[@intFromEnum(Feature.execute_only)] = .{
	554	.llvm_name = "execute-only",
	555	.description = "Enable the generation of execute only code.",
	556	.dependencies = featureSet(&[_]Feature{}),
	557	};
529	558	result[@intFromEnum(Feature.exynos_cheap_as_move)] = .{
530	559	.llvm_name = "exynos-cheap-as-move",
531	560	.description = "Use Exynos specific handling of cheap instructions",
...	...	@@ -876,6 +905,20 @@ pub const all_features = blk: {
876	905	.description = "Enable Armv9.6-A Outer cacheable cache maintenance operations",
877	906	.dependencies = featureSet(&[_]Feature{}),
878	907	};
	908	result[@intFromEnum(Feature.olympus)] = .{
	909	.llvm_name = "olympus",
	910	.description = "NVIDIA Olympus processors",
	911	.dependencies = featureSet(&[_]Feature{
	912	.alu_lsl_fast,
	913	.cmp_bcc_fusion,
	914	.enable_select_opt,
	915	.fuse_adrp_add,
	916	.fuse_aes,
	917	.predictable_select_expensive,
	918	.use_fixed_over_scalable_if_equal_cost,
	919	.use_postra_scheduler,
	920	}),
	921	};
879	922	result[@intFromEnum(Feature.outline_atomics)] = .{
880	923	.llvm_name = "outline-atomics",
881	924	.description = "Enable out of line atomics to support LSE instructions",
...	...	@@ -1298,6 +1341,13 @@ pub const all_features = blk: {
1298	1341	.sve_bitperm,
1299	1342	}),
1300	1343	};
	1344	result[@intFromEnum(Feature.ssve_fexpa)] = .{
	1345	.llvm_name = "ssve-fexpa",
	1346	.description = "Enable SVE FEXPA instruction in Streaming SVE mode",
	1347	.dependencies = featureSet(&[_]Feature{
	1348	.sme2,
	1349	}),
	1350	};
1301	1351	result[@intFromEnum(Feature.ssve_fp8dot2)] = .{
1302	1352	.llvm_name = "ssve-fp8dot2",
1303	1353	.description = "Enable SVE2 FP8 2-way dot product instructions",
...	...	@@ -1369,18 +1419,18 @@ pub const all_features = blk: {
1369	1419	};
1370	1420	result[@intFromEnum(Feature.sve2_sha3)] = .{
1371	1421	.llvm_name = "sve2-sha3",
1372		.description = "Enable SHA3 SVE2 instructions",
	1422	.description = "Shorthand for +sve2+sve-sha3",
1373	1423	.dependencies = featureSet(&[_]Feature{
1374		.sha3,
1375	1424	.sve2,
	1425	.sve_sha3,
1376	1426	}),
1377	1427	};
1378	1428	result[@intFromEnum(Feature.sve2_sm4)] = .{
1379	1429	.llvm_name = "sve2-sm4",
1380		.description = "Enable SM4 SVE2 instructions",
	1430	.description = "Shorthand for +sve2+sve-sm4",
1381	1431	.dependencies = featureSet(&[_]Feature{
1382		.sm4,
1383	1432	.sve2,
	1433	.sve_sm4,
1384	1434	}),
1385	1435	};
1386	1436	result[@intFromEnum(Feature.sve2p1)] = .{
...	...	@@ -1431,6 +1481,20 @@ pub const all_features = blk: {
1431	1481	.sve,
1432	1482	}),
1433	1483	};
	1484	result[@intFromEnum(Feature.sve_sha3)] = .{
	1485	.llvm_name = "sve-sha3",
	1486	.description = "Enable SVE SHA3 instructions",
	1487	.dependencies = featureSet(&[_]Feature{
	1488	.sha3,
	1489	}),
	1490	};
	1491	result[@intFromEnum(Feature.sve_sm4)] = .{
	1492	.llvm_name = "sve-sm4",
	1493	.description = "Enable SVE SM4 instructions",
	1494	.dependencies = featureSet(&[_]Feature{
	1495	.sm4,
	1496	}),
	1497	};
1434	1498	result[@intFromEnum(Feature.tagged_globals)] = .{
1435	1499	.llvm_name = "tagged-globals",
1436	1500	.description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
...	...	@@ -1746,9 +1810,24 @@ pub const all_features = blk: {
1746	1810	.description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
1747	1811	.dependencies = featureSet(&[_]Feature{}),
1748	1812	};
1749		result[@intFromEnum(Feature.zcm)] = .{
1750		.llvm_name = "zcm",
1751		.description = "Has zero-cycle register moves",
	1813	result[@intFromEnum(Feature.zcm_fpr32)] = .{
	1814	.llvm_name = "zcm-fpr32",
	1815	.description = "Has zero-cycle register moves for FPR32 registers",
	1816	.dependencies = featureSet(&[_]Feature{}),
	1817	};
	1818	result[@intFromEnum(Feature.zcm_fpr64)] = .{
	1819	.llvm_name = "zcm-fpr64",
	1820	.description = "Has zero-cycle register moves for FPR64 registers",
	1821	.dependencies = featureSet(&[_]Feature{}),
	1822	};
	1823	result[@intFromEnum(Feature.zcm_gpr32)] = .{
	1824	.llvm_name = "zcm-gpr32",
	1825	.description = "Has zero-cycle register moves for GPR32 registers",
	1826	.dependencies = featureSet(&[_]Feature{}),
	1827	};
	1828	result[@intFromEnum(Feature.zcm_gpr64)] = .{
	1829	.llvm_name = "zcm-gpr64",
	1830	.description = "Has zero-cycle register moves for GPR64 registers",
1752	1831	.dependencies = featureSet(&[_]Feature{}),
1753	1832	};
1754	1833	result[@intFromEnum(Feature.zcz)] = .{
...	...	@@ -1894,7 +1973,8 @@ pub const cpu = struct {
1894	1973	.store_pair_suppress,
1895	1974	.v8a,
1896	1975	.vh,
1897		.zcm,
	1976	.zcm_fpr64,
	1977	.zcm_gpr64,
1898	1978	.zcz,
1899	1979	}),
1900	1980	};
...	...	@@ -1914,7 +1994,8 @@ pub const cpu = struct {
1914	1994	.sha2,
1915	1995	.store_pair_suppress,
1916	1996	.v8_2a,
1917		.zcm,
	1997	.zcm_fpr64,
	1998	.zcm_gpr64,
1918	1999	.zcz,
1919	2000	}),
1920	2001	};
...	...	@@ -1934,7 +2015,8 @@ pub const cpu = struct {
1934	2015	.sha2,
1935	2016	.store_pair_suppress,
1936	2017	.v8_3a,
1937		.zcm,
	2018	.zcm_fpr64,
	2019	.zcm_gpr64,
1938	2020	.zcz,
1939	2021	}),
1940	2022	};
...	...	@@ -1954,7 +2036,8 @@ pub const cpu = struct {
1954	2036	.sha3,
1955	2037	.store_pair_suppress,
1956	2038	.v8_4a,
1957		.zcm,
	2039	.zcm_fpr64,
	2040	.zcm_gpr64,
1958	2041	.zcz,
1959	2042	}),
1960	2043	};
...	...	@@ -1986,7 +2069,8 @@ pub const cpu = struct {
1986	2069	.ssbs,
1987	2070	.store_pair_suppress,
1988	2071	.v8_4a,
1989		.zcm,
	2072	.zcm_fpr64,
	2073	.zcm_gpr64,
1990	2074	.zcz,
1991	2075	}),
1992	2076	};
...	...	@@ -2012,7 +2096,8 @@ pub const cpu = struct {
2012	2096	.sha3,
2013	2097	.store_pair_suppress,
2014	2098	.v8_6a,
2015		.zcm,
	2099	.zcm_fpr64,
	2100	.zcm_gpr64,
2016	2101	.zcz,
2017	2102	}),
2018	2103	};
...	...	@@ -2039,7 +2124,8 @@ pub const cpu = struct {
2039	2124	.sha3,
2040	2125	.store_pair_suppress,
2041	2126	.v8_6a,
2042		.zcm,
	2127	.zcm_fpr64,
	2128	.zcm_gpr64,
2043	2129	.zcz,
2044	2130	}),
2045	2131	};
...	...	@@ -2066,7 +2152,37 @@ pub const cpu = struct {
2066	2152	.sha3,
2067	2153	.store_pair_suppress,
2068	2154	.v8_6a,
2069		.zcm,
	2155	.zcm_fpr64,
	2156	.zcm_gpr64,
	2157	.zcz,
	2158	}),
	2159	};
	2160	pub const apple_a18: CpuModel = .{
	2161	.name = "apple_a18",
	2162	.llvm_name = "apple-a18",
	2163	.features = featureSet(&[_]Feature{
	2164	.aes,
	2165	.alternate_sextload_cvt_f32_pattern,
	2166	.arith_bcc_fusion,
	2167	.arith_cbz_fusion,
	2168	.disable_latency_sched_heuristic,
	2169	.fp16fml,
	2170	.fpac,
	2171	.fuse_address,
	2172	.fuse_adrp_add,
	2173	.fuse_aes,
	2174	.fuse_arith_logic,
	2175	.fuse_crypto_eor,
	2176	.fuse_csel,
	2177	.fuse_literals,
	2178	.perfmon,
	2179	.sha3,
	2180	.sme2,
	2181	.sme_f64f64,
	2182	.sme_i16i64,
	2183	.v8_7a,
	2184	.zcm_fpr64,
	2185	.zcm_gpr64,
2070	2186	.zcz,
2071	2187	}),
2072	2188	};
...	...	@@ -2085,7 +2201,8 @@ pub const cpu = struct {
2085	2201	.sha2,
2086	2202	.store_pair_suppress,
2087	2203	.v8a,
2088		.zcm,
	2204	.zcm_fpr64,
	2205	.zcm_gpr64,
2089	2206	.zcz,
2090	2207	.zcz_fp_workaround,
2091	2208	}),
...	...	@@ -2105,7 +2222,8 @@ pub const cpu = struct {
2105	2222	.sha2,
2106	2223	.store_pair_suppress,
2107	2224	.v8a,
2108		.zcm,
	2225	.zcm_fpr64,
	2226	.zcm_gpr64,
2109	2227	.zcz,
2110	2228	.zcz_fp_workaround,
2111	2229	}),
...	...	@@ -2125,7 +2243,8 @@ pub const cpu = struct {
2125	2243	.sha2,
2126	2244	.store_pair_suppress,
2127	2245	.v8a,
2128		.zcm,
	2246	.zcm_fpr64,
	2247	.zcm_gpr64,
2129	2248	.zcz,
2130	2249	.zcz_fp_workaround,
2131	2250	}),
...	...	@@ -2158,7 +2277,8 @@ pub const cpu = struct {
2158	2277	.ssbs,
2159	2278	.store_pair_suppress,
2160	2279	.v8_4a,
2161		.zcm,
	2280	.zcm_fpr64,
	2281	.zcm_gpr64,
2162	2282	.zcz,
2163	2283	}),
2164	2284	};
...	...	@@ -2184,7 +2304,8 @@ pub const cpu = struct {
2184	2304	.sha3,
2185	2305	.store_pair_suppress,
2186	2306	.v8_6a,
2187		.zcm,
	2307	.zcm_fpr64,
	2308	.zcm_gpr64,
2188	2309	.zcz,
2189	2310	}),
2190	2311	};
...	...	@@ -2211,7 +2332,8 @@ pub const cpu = struct {
2211	2332	.sha3,
2212	2333	.store_pair_suppress,
2213	2334	.v8_6a,
2214		.zcm,
	2335	.zcm_fpr64,
	2336	.zcm_gpr64,
2215	2337	.zcz,
2216	2338	}),
2217	2339	};
...	...	@@ -2239,7 +2361,36 @@ pub const cpu = struct {
2239	2361	.sme_f64f64,
2240	2362	.sme_i16i64,
2241	2363	.v8_7a,
2242		.zcm,
	2364	.zcm_fpr64,
	2365	.zcm_gpr64,
	2366	.zcz,
	2367	}),
	2368	};
	2369	pub const apple_s10: CpuModel = .{
	2370	.name = "apple_s10",
	2371	.llvm_name = "apple-s10",
	2372	.features = featureSet(&[_]Feature{
	2373	.aes,
	2374	.alternate_sextload_cvt_f32_pattern,
	2375	.arith_bcc_fusion,
	2376	.arith_cbz_fusion,
	2377	.disable_latency_sched_heuristic,
	2378	.fp16fml,
	2379	.fpac,
	2380	.fuse_address,
	2381	.fuse_adrp_add,
	2382	.fuse_aes,
	2383	.fuse_arith_logic,
	2384	.fuse_crypto_eor,
	2385	.fuse_csel,
	2386	.fuse_literals,
	2387	.hcx,
	2388	.perfmon,
	2389	.sha3,
	2390	.store_pair_suppress,
	2391	.v8_6a,
	2392	.zcm_fpr64,
	2393	.zcm_gpr64,
2243	2394	.zcz,
2244	2395	}),
2245	2396	};
...	...	@@ -2259,7 +2410,8 @@ pub const cpu = struct {
2259	2410	.sha2,
2260	2411	.store_pair_suppress,
2261	2412	.v8_3a,
2262		.zcm,
	2413	.zcm_fpr64,
	2414	.zcm_gpr64,
2263	2415	.zcz,
2264	2416	}),
2265	2417	};
...	...	@@ -2279,7 +2431,99 @@ pub const cpu = struct {
2279	2431	.sha2,
2280	2432	.store_pair_suppress,
2281	2433	.v8_3a,
2282		.zcm,
	2434	.zcm_fpr64,
	2435	.zcm_gpr64,
	2436	.zcz,
	2437	}),
	2438	};
	2439	pub const apple_s6: CpuModel = .{
	2440	.name = "apple_s6",
	2441	.llvm_name = "apple-s6",
	2442	.features = featureSet(&[_]Feature{
	2443	.aes,
	2444	.alternate_sextload_cvt_f32_pattern,
	2445	.arith_bcc_fusion,
	2446	.arith_cbz_fusion,
	2447	.disable_latency_sched_heuristic,
	2448	.fp16fml,
	2449	.fuse_aes,
	2450	.fuse_crypto_eor,
	2451	.perfmon,
	2452	.sha3,
	2453	.store_pair_suppress,
	2454	.v8_4a,
	2455	.zcm_fpr64,
	2456	.zcm_gpr64,
	2457	.zcz,
	2458	}),
	2459	};
	2460	pub const apple_s7: CpuModel = .{
	2461	.name = "apple_s7",
	2462	.llvm_name = "apple-s7",
	2463	.features = featureSet(&[_]Feature{
	2464	.aes,
	2465	.alternate_sextload_cvt_f32_pattern,
	2466	.arith_bcc_fusion,
	2467	.arith_cbz_fusion,
	2468	.disable_latency_sched_heuristic,
	2469	.fp16fml,
	2470	.fuse_aes,
	2471	.fuse_crypto_eor,
	2472	.perfmon,
	2473	.sha3,
	2474	.store_pair_suppress,
	2475	.v8_4a,
	2476	.zcm_fpr64,
	2477	.zcm_gpr64,
	2478	.zcz,
	2479	}),
	2480	};
	2481	pub const apple_s8: CpuModel = .{
	2482	.name = "apple_s8",
	2483	.llvm_name = "apple-s8",
	2484	.features = featureSet(&[_]Feature{
	2485	.aes,
	2486	.alternate_sextload_cvt_f32_pattern,
	2487	.arith_bcc_fusion,
	2488	.arith_cbz_fusion,
	2489	.disable_latency_sched_heuristic,
	2490	.fp16fml,
	2491	.fuse_aes,
	2492	.fuse_crypto_eor,
	2493	.perfmon,
	2494	.sha3,
	2495	.store_pair_suppress,
	2496	.v8_4a,
	2497	.zcm_fpr64,
	2498	.zcm_gpr64,
	2499	.zcz,
	2500	}),
	2501	};
	2502	pub const apple_s9: CpuModel = .{
	2503	.name = "apple_s9",
	2504	.llvm_name = "apple-s9",
	2505	.features = featureSet(&[_]Feature{
	2506	.aes,
	2507	.alternate_sextload_cvt_f32_pattern,
	2508	.arith_bcc_fusion,
	2509	.arith_cbz_fusion,
	2510	.disable_latency_sched_heuristic,
	2511	.fp16fml,
	2512	.fpac,
	2513	.fuse_address,
	2514	.fuse_adrp_add,
	2515	.fuse_aes,
	2516	.fuse_arith_logic,
	2517	.fuse_crypto_eor,
	2518	.fuse_csel,
	2519	.fuse_literals,
	2520	.hcx,
	2521	.perfmon,
	2522	.sha3,
	2523	.store_pair_suppress,
	2524	.v8_6a,
	2525	.zcm_fpr64,
	2526	.zcm_gpr64,
2283	2527	.zcz,
2284	2528	}),
2285	2529	};
...	...	@@ -2302,6 +2546,7 @@ pub const cpu = struct {
2302	2546	.enable_select_opt,
2303	2547	.ete,
2304	2548	.fp16fml,
	2549	.fpac,
2305	2550	.fuse_adrp_add,
2306	2551	.fuse_aes,
2307	2552	.i8mm,
...	...	@@ -2313,6 +2558,19 @@ pub const cpu = struct {
2313	2558	.v9a,
2314	2559	}),
2315	2560	};
	2561	pub const cortex_a320: CpuModel = .{
	2562	.name = "cortex_a320",
	2563	.llvm_name = "cortex-a320",
	2564	.features = featureSet(&[_]Feature{
	2565	.a320,
	2566	.ete,
	2567	.fp16fml,
	2568	.mte,
	2569	.perfmon,
	2570	.sve_bitperm,
	2571	.v9_2a,
	2572	}),
	2573	};
2316	2574	pub const cortex_a34: CpuModel = .{
2317	2575	.name = "cortex_a34",
2318	2576	.llvm_name = "cortex-a34",
...	...	@@ -2342,12 +2600,14 @@ pub const cpu = struct {
2342	2600	.bf16,
2343	2601	.ete,
2344	2602	.fp16fml,
	2603	.fpac,
2345	2604	.fuse_adrp_add,
2346	2605	.fuse_aes,
2347	2606	.i8mm,
2348	2607	.mte,
2349	2608	.perfmon,
2350	2609	.sve_bitperm,
	2610	.use_fixed_over_scalable_if_equal_cost,
2351	2611	.use_postra_scheduler,
2352	2612	.v9a,
2353	2613	}),
...	...	@@ -2358,11 +2618,13 @@ pub const cpu = struct {
2358	2618	.features = featureSet(&[_]Feature{
2359	2619	.ete,
2360	2620	.fp16fml,
	2621	.fpac,
2361	2622	.fuse_adrp_add,
2362	2623	.fuse_aes,
2363	2624	.mte,
2364	2625	.perfmon,
2365	2626	.sve_bitperm,
	2627	.use_fixed_over_scalable_if_equal_cost,
2366	2628	.use_postra_scheduler,
2367	2629	.v9_2a,
2368	2630	}),
...	...	@@ -2373,6 +2635,7 @@ pub const cpu = struct {
2373	2635	.features = featureSet(&[_]Feature{
2374	2636	.ete,
2375	2637	.fp16fml,
	2638	.fpac,
2376	2639	.fuse_adrp_add,
2377	2640	.fuse_aes,
2378	2641	.mte,
...	...	@@ -2483,6 +2746,7 @@ pub const cpu = struct {
2483	2746	.enable_select_opt,
2484	2747	.ete,
2485	2748	.fp16fml,
	2749	.fpac,
2486	2750	.fuse_adrp_add,
2487	2751	.fuse_aes,
2488	2752	.i8mm,
...	...	@@ -2504,6 +2768,7 @@ pub const cpu = struct {
2504	2768	.enable_select_opt,
2505	2769	.ete,
2506	2770	.fp16fml,
	2771	.fpac,
2507	2772	.fuse_adrp_add,
2508	2773	.fuse_aes,
2509	2774	.i8mm,
...	...	@@ -2542,6 +2807,7 @@ pub const cpu = struct {
2542	2807	.enable_select_opt,
2543	2808	.ete,
2544	2809	.fp16fml,
	2810	.fpac,
2545	2811	.fuse_adrp_add,
2546	2812	.fuse_aes,
2547	2813	.mte,
...	...	@@ -2562,6 +2828,7 @@ pub const cpu = struct {
2562	2828	.enable_select_opt,
2563	2829	.ete,
2564	2830	.fp16fml,
	2831	.fpac,
2565	2832	.fuse_adrp_add,
2566	2833	.fuse_aes,
2567	2834	.mte,
...	...	@@ -2582,6 +2849,7 @@ pub const cpu = struct {
2582	2849	.enable_select_opt,
2583	2850	.ete,
2584	2851	.fp16fml,
	2852	.fpac,
2585	2853	.fuse_adrp_add,
2586	2854	.fuse_aes,
2587	2855	.mte,
...	...	@@ -2764,6 +3032,7 @@ pub const cpu = struct {
2764	3032	.llvm_name = "cortex-r82",
2765	3033	.features = featureSet(&[_]Feature{
2766	3034	.ccdp,
	3035	.fpac,
2767	3036	.perfmon,
2768	3037	.predres,
2769	3038	.use_postra_scheduler,
...	...	@@ -2775,6 +3044,7 @@ pub const cpu = struct {
2775	3044	.llvm_name = "cortex-r82ae",
2776	3045	.features = featureSet(&[_]Feature{
2777	3046	.ccdp,
	3047	.fpac,
2778	3048	.perfmon,
2779	3049	.predres,
2780	3050	.use_postra_scheduler,
...	...	@@ -2840,6 +3110,7 @@ pub const cpu = struct {
2840	3110	.enable_select_opt,
2841	3111	.ete,
2842	3112	.fp16fml,
	3113	.fpac,
2843	3114	.fuse_adrp_add,
2844	3115	.fuse_aes,
2845	3116	.i8mm,
...	...	@@ -2862,6 +3133,7 @@ pub const cpu = struct {
2862	3133	.enable_select_opt,
2863	3134	.ete,
2864	3135	.fp16fml,
	3136	.fpac,
2865	3137	.fuse_adrp_add,
2866	3138	.fuse_aes,
2867	3139	.i8mm,
...	...	@@ -2884,6 +3156,7 @@ pub const cpu = struct {
2884	3156	.enable_select_opt,
2885	3157	.ete,
2886	3158	.fp16fml,
	3159	.fpac,
2887	3160	.fuse_adrp_add,
2888	3161	.fuse_aes,
2889	3162	.mte,
...	...	@@ -2905,6 +3178,7 @@ pub const cpu = struct {
2905	3178	.enable_select_opt,
2906	3179	.ete,
2907	3180	.fp16fml,
	3181	.fpac,
2908	3182	.fuse_adrp_add,
2909	3183	.fuse_aes,
2910	3184	.mte,
...	...	@@ -2932,7 +3206,8 @@ pub const cpu = struct {
2932	3206	.sha2,
2933	3207	.store_pair_suppress,
2934	3208	.v8a,
2935		.zcm,
	3209	.zcm_fpr64,
	3210	.zcm_gpr64,
2936	3211	.zcz,
2937	3212	.zcz_fp_workaround,
2938	3213	}),
...	...	@@ -3081,6 +3356,8 @@ pub const cpu = struct {
3081	3356	.faminmax,
3082	3357	.fp16fml,
3083	3358	.fp8dot2,
	3359	.fp8dot4,
	3360	.fp8fma,
3084	3361	.fpac,
3085	3362	.fujitsu_monaka,
3086	3363	.ls64,
...	...	@@ -3088,13 +3365,38 @@ pub const cpu = struct {
3088	3365	.perfmon,
3089	3366	.rand,
3090	3367	.specres2,
3091		.sve2_sha3,
3092		.sve2_sm4,
3093	3368	.sve_aes,
3094	3369	.sve_bitperm,
	3370	.sve_sha3,
	3371	.sve_sm4,
3095	3372	.v9_3a,
3096	3373	}),
3097	3374	};
	3375	pub const gb10: CpuModel = .{
	3376	.name = "gb10",
	3377	.llvm_name = "gb10",
	3378	.features = featureSet(&[_]Feature{
	3379	.alu_lsl_fast,
	3380	.avoid_ldapur,
	3381	.enable_select_opt,
	3382	.ete,
	3383	.fp16fml,
	3384	.fpac,
	3385	.fuse_adrp_add,
	3386	.fuse_aes,
	3387	.mte,
	3388	.perfmon,
	3389	.predictable_select_expensive,
	3390	.spe,
	3391	.sve_aes,
	3392	.sve_bitperm,
	3393	.sve_sha3,
	3394	.sve_sm4,
	3395	.use_fixed_over_scalable_if_equal_cost,
	3396	.use_postra_scheduler,
	3397	.v9_2a,
	3398	}),
	3399	};
3098	3400	pub const generic: CpuModel = .{
3099	3401	.name = "generic",
3100	3402	.llvm_name = "generic",
...	...	@@ -3115,9 +3417,11 @@ pub const cpu = struct {
3115	3417	.avoid_ldapur,
3116	3418	.bf16,
3117	3419	.cmp_bcc_fusion,
	3420	.disable_latency_sched_heuristic,
3118	3421	.enable_select_opt,
3119	3422	.ete,
3120	3423	.fp16fml,
	3424	.fpac,
3121	3425	.fuse_adrp_add,
3122	3426	.fuse_aes,
3123	3427	.i8mm,
...	...	@@ -3126,7 +3430,10 @@ pub const cpu = struct {
3126	3430	.predictable_select_expensive,
3127	3431	.rand,
3128	3432	.spe,
	3433	.sve_aes,
3129	3434	.sve_bitperm,
	3435	.sve_sha3,
	3436	.sve_sm4,
3130	3437	.use_fixed_over_scalable_if_equal_cost,
3131	3438	.use_postra_scheduler,
3132	3439	.v9a,
...	...	@@ -3158,6 +3465,7 @@ pub const cpu = struct {
3158	3465	.ccdp,
3159	3466	.enable_select_opt,
3160	3467	.fp16fml,
	3468	.fpac,
3161	3469	.fuse_adrp_add,
3162	3470	.fuse_aes,
3163	3471	.i8mm,
...	...	@@ -3221,6 +3529,7 @@ pub const cpu = struct {
3221	3529	.enable_select_opt,
3222	3530	.ete,
3223	3531	.fp16fml,
	3532	.fpac,
3224	3533	.fuse_adrp_add,
3225	3534	.fuse_aes,
3226	3535	.i8mm,
...	...	@@ -3240,6 +3549,7 @@ pub const cpu = struct {
3240	3549	.enable_select_opt,
3241	3550	.ete,
3242	3551	.fp16fml,
	3552	.fpac,
3243	3553	.fuse_adrp_add,
3244	3554	.fuse_aes,
3245	3555	.mte,
...	...	@@ -3287,9 +3597,11 @@ pub const cpu = struct {
3287	3597	.avoid_ldapur,
3288	3598	.bf16,
3289	3599	.cmp_bcc_fusion,
	3600	.disable_latency_sched_heuristic,
3290	3601	.enable_select_opt,
3291	3602	.ete,
3292	3603	.fp16fml,
	3604	.fpac,
3293	3605	.fuse_adrp_add,
3294	3606	.fuse_aes,
3295	3607	.i8mm,
...	...	@@ -3314,6 +3626,7 @@ pub const cpu = struct {
3314	3626	.enable_select_opt,
3315	3627	.ete,
3316	3628	.fp16fml,
	3629	.fpac,
3317	3630	.fuse_adrp_add,
3318	3631	.fuse_aes,
3319	3632	.ls64,
...	...	@@ -3337,6 +3650,7 @@ pub const cpu = struct {
3337	3650	.enable_select_opt,
3338	3651	.ete,
3339	3652	.fp16fml,
	3653	.fpac,
3340	3654	.fuse_adrp_add,
3341	3655	.fuse_aes,
3342	3656	.ls64,
...	...	@@ -3350,6 +3664,33 @@ pub const cpu = struct {
3350	3664	.v9_2a,
3351	3665	}),
3352	3666	};
	3667	pub const olympus: CpuModel = .{
	3668	.name = "olympus",
	3669	.llvm_name = "olympus",
	3670	.features = featureSet(&[_]Feature{
	3671	.brbe,
	3672	.chk,
	3673	.ete,
	3674	.faminmax,
	3675	.fp16fml,
	3676	.fp8dot2,
	3677	.fp8dot4,
	3678	.fp8fma,
	3679	.fpac,
	3680	.ls64,
	3681	.lut,
	3682	.mte,
	3683	.olympus,
	3684	.perfmon,
	3685	.rand,
	3686	.spe,
	3687	.sve_aes,
	3688	.sve_bitperm,
	3689	.sve_sha3,
	3690	.sve_sm4,
	3691	.v9_2a,
	3692	}),
	3693	};
3353	3694	pub const oryon_1: CpuModel = .{
3354	3695	.name = "oryon_1",
3355	3696	.llvm_name = "oryon-1",

lib/std/Target/amdgcn.zig+183-108

...	...	@@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
8	8	@"16_bit_insts",
	9	@"64_bit_literals",
9	10	a16,
10	11	add_no_carry_insts,
11	12	addressablelocalmemorysize163840,
...	...	@@ -33,8 +34,11 @@ pub const Feature = enum {
33	34	auto_waitcnt_before_barrier,
34	35	back_off_barrier,
35	36	bf16_cvt_insts,
	37	bf16_trans_insts,
36	38	bf8_cvt_scale_insts,
37	39	bitop3_insts,
	40	block_vgpr_csr,
	41	bvh_dual_bvh_8_insts,
38	42	ci_insts,
39	43	cumode,
40	44	cvt_fp8_vop1_bug,
...	...	@@ -61,6 +65,8 @@ pub const Feature = enum {
61	65	dpp_src1_sgpr,
62	66	ds128,
63	67	ds_src2_insts,
	68	dynamic_vgpr,
	69	dynamic_vgpr_block_size_32,
64	70	extended_image_insts,
65	71	f16bf16_to_fp6bf6_cvt_scale_insts,
66	72	f32_to_f16bf16_cvt_sr_insts,
...	...	@@ -78,13 +84,13 @@ pub const Feature = enum {
78	84	fma_mix_insts,
79	85	fmacf64_inst,
80	86	fmaf,
81		force_store_sc0_sc1,
82	87	fp4_cvt_scale_insts,
83	88	fp64,
84	89	fp6bf6_cvt_scale_insts,
85	90	fp8_conversion_insts,
86	91	fp8_cvt_scale_insts,
87	92	fp8_insts,
	93	fp8e5m3_insts,
88	94	full_rate_64_ops,
89	95	g16,
90	96	gcn3_encoding,
...	...	@@ -98,6 +104,7 @@ pub const Feature = enum {
98	104	gfx11,
99	105	gfx11_insts,
100	106	gfx12,
	107	gfx1250_insts,
101	108	gfx12_insts,
102	109	gfx7_gfx8_gfx9_insts,
103	110	gfx8_insts,
...	...	@@ -108,6 +115,7 @@ pub const Feature = enum {
108	115	gfx9_insts,
109	116	gws,
110	117	half_rate_64_ops,
	118	ieee_minimum_maximum_insts,
111	119	image_gather4_d16_bug,
112	120	image_insts,
113	121	image_store_d16_bug,
...	...	@@ -115,11 +123,13 @@ pub const Feature = enum {
115	123	int_clamp_insts,
116	124	inv_2pi_inline_imm,
117	125	kernarg_preload,
	126	lds_barrier_arrive_atomic,
118	127	lds_branch_vmem_war_hazard,
119	128	lds_misaligned_bug,
120	129	ldsbankcount16,
121	130	ldsbankcount32,
122	131	load_store_opt,
	132	lshl_add_u64_inst,
123	133	mad_intra_fwd_bug,
124	134	mad_mac_f32_insts,
125	135	mad_mix_insts,
...	...	@@ -151,6 +161,7 @@ pub const Feature = enum {
151	161	permlane16_swap,
152	162	permlane32_swap,
153	163	pk_fmac_f16_inst,
	164	point_sample_accel,
154	165	precise_memory,
155	166	priv_enabled_trap2_nop_bug,
156	167	prng_inst,
...	...	@@ -159,11 +170,13 @@ pub const Feature = enum {
159	170	pseudo_scalar_trans,
160	171	r128_a16,
161	172	real_true16,
	173	relaxed_buffer_oob_mode,
162	174	required_export_priority,
163	175	requires_cov6,
164	176	restricted_soffset,
165	177	s_memrealtime,
166	178	s_memtime_inst,
	179	safe_smem_prefetch,
167	180	salu_float,
168	181	scalar_atomics,
169	182	scalar_dwordx3_loads,
...	...	@@ -176,6 +189,7 @@ pub const Feature = enum {
176	189	sdwa_scalar,
177	190	sdwa_sdst,
178	191	sea_islands,
	192	setprio_inc_wg_inst,
179	193	sgpr_init_bug,
180	194	shader_cycles_hi_lo_registers,
181	195	shader_cycles_register,
...	...	@@ -185,6 +199,7 @@ pub const Feature = enum {
185	199	sramecc,
186	200	sramecc_support,
187	201	tgsplit,
	202	transpose_load_f4f6_insts,
188	203	trap_handler,
189	204	trig_reduced_range,
190	205	true16,
...	...	@@ -199,6 +214,7 @@ pub const Feature = enum {
199	214	vcmpx_exec_war_hazard,
200	215	vcmpx_permlane_hazard,
201	216	vgpr_index_mode,
	217	vmem_to_lds_load_insts,
202	218	vmem_to_scalar_write_hazard,
203	219	vmem_write_vgpr_in_order,
204	220	volcanic_islands,
...	...	@@ -206,6 +222,7 @@ pub const Feature = enum {
206	222	vop3p,
207	223	vopd,
208	224	vscnt,
	225	wait_xcnt,
209	226	wavefrontsize16,
210	227	wavefrontsize32,
211	228	wavefrontsize64,
...	...	@@ -220,6 +237,7 @@ pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
220	237	pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
221	238
222	239	pub const all_features = blk: {
	240	@setEvalBranchQuota(2000);
223	241	const len = @typeInfo(Feature).@"enum".fields.len;
224	242	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
225	243	var result: [len]CpuFeature = undefined;
...	...	@@ -228,6 +246,11 @@ pub const all_features = blk: {
228	246	.description = "Has i16/f16 instructions",
229	247	.dependencies = featureSet(&[_]Feature{}),
230	248	};
	249	result[@intFromEnum(Feature.@"64_bit_literals")] = .{
	250	.llvm_name = "64-bit-literals",
	251	.description = "Can use 64-bit literals with single DWORD instructions",
	252	.dependencies = featureSet(&[_]Feature{}),
	253	};
231	254	result[@intFromEnum(Feature.a16)] = .{
232	255	.llvm_name = "a16",
233	256	.description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
...	...	@@ -373,6 +396,11 @@ pub const all_features = blk: {
373	396	.description = "Has bf16 conversion instructions",
374	397	.dependencies = featureSet(&[_]Feature{}),
375	398	};
	399	result[@intFromEnum(Feature.bf16_trans_insts)] = .{
	400	.llvm_name = "bf16-trans-insts",
	401	.description = "Has bf16 transcendental instructions",
	402	.dependencies = featureSet(&[_]Feature{}),
	403	};
376	404	result[@intFromEnum(Feature.bf8_cvt_scale_insts)] = .{
377	405	.llvm_name = "bf8-cvt-scale-insts",
378	406	.description = "Has bf8 conversion scale instructions",
...	...	@@ -383,6 +411,16 @@ pub const all_features = blk: {
383	411	.description = "Has v_bitop3_b32/v_bitop3_b16 instructions",
384	412	.dependencies = featureSet(&[_]Feature{}),
385	413	};
	414	result[@intFromEnum(Feature.block_vgpr_csr)] = .{
	415	.llvm_name = "block-vgpr-csr",
	416	.description = "Use block load/store for VGPR callee saved registers",
	417	.dependencies = featureSet(&[_]Feature{}),
	418	};
	419	result[@intFromEnum(Feature.bvh_dual_bvh_8_insts)] = .{
	420	.llvm_name = "bvh-dual-bvh-8-insts",
	421	.description = "Has image_bvh_dual_intersect_ray and image_bvh8_intersect_ray instructions",
	422	.dependencies = featureSet(&[_]Feature{}),
	423	};
386	424	result[@intFromEnum(Feature.ci_insts)] = .{
387	425	.llvm_name = "ci-insts",
388	426	.description = "Additional instructions for CI+",
...	...	@@ -515,6 +553,16 @@ pub const all_features = blk: {
515	553	.description = "Has ds_*_src2 instructions",
516	554	.dependencies = featureSet(&[_]Feature{}),
517	555	};
	556	result[@intFromEnum(Feature.dynamic_vgpr)] = .{
	557	.llvm_name = "dynamic-vgpr",
	558	.description = "Enable dynamic VGPR mode",
	559	.dependencies = featureSet(&[_]Feature{}),
	560	};
	561	result[@intFromEnum(Feature.dynamic_vgpr_block_size_32)] = .{
	562	.llvm_name = "dynamic-vgpr-block-size-32",
	563	.description = "Use a block size of 32 for dynamic VGPR allocation (default is 16)",
	564	.dependencies = featureSet(&[_]Feature{}),
	565	};
518	566	result[@intFromEnum(Feature.extended_image_insts)] = .{
519	567	.llvm_name = "extended-image-insts",
520	568	.description = "Support mips != 0, lod != 0, gather4, and get_lod",
...	...	@@ -600,11 +648,6 @@ pub const all_features = blk: {
600	648	.description = "Enable single precision FMA (not as fast as mul+add, but fused)",
601	649	.dependencies = featureSet(&[_]Feature{}),
602	650	};
603		result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
604		.llvm_name = "force-store-sc0-sc1",
605		.description = "Has SC0 and SC1 on stores",
606		.dependencies = featureSet(&[_]Feature{}),
607		};
608	651	result[@intFromEnum(Feature.fp4_cvt_scale_insts)] = .{
609	652	.llvm_name = "fp4-cvt-scale-insts",
610	653	.description = "Has fp4 conversion scale instructions",
...	...	@@ -635,6 +678,11 @@ pub const all_features = blk: {
635	678	.description = "Has fp8 and bf8 instructions",
636	679	.dependencies = featureSet(&[_]Feature{}),
637	680	};
	681	result[@intFromEnum(Feature.fp8e5m3_insts)] = .{
	682	.llvm_name = "fp8e5m3-insts",
	683	.description = "Has fp8 e5m3 format support",
	684	.dependencies = featureSet(&[_]Feature{}),
	685	};
638	686	result[@intFromEnum(Feature.full_rate_64_ops)] = .{
639	687	.llvm_name = "full-rate-64-ops",
640	688	.description = "Most fp64 instructions are full rate",
...	...	@@ -710,6 +758,7 @@ pub const all_features = blk: {
710	758	.unaligned_buffer_access,
711	759	.unaligned_ds_access,
712	760	.unaligned_scratch_access,
	761	.vmem_to_lds_load_insts,
713	762	.vmem_write_vgpr_in_order,
714	763	.vop3_literal,
715	764	.vop3p,
...	...	@@ -827,6 +876,7 @@ pub const all_features = blk: {
827	876	.gfx12_insts,
828	877	.gfx8_insts,
829	878	.gfx9_insts,
	879	.ieee_minimum_maximum_insts,
830	880	.int_clamp_insts,
831	881	.inv_2pi_inline_imm,
832	882	.max_hard_clause_length_32,
...	...	@@ -847,6 +897,11 @@ pub const all_features = blk: {
847	897	.vscnt,
848	898	}),
849	899	};
	900	result[@intFromEnum(Feature.gfx1250_insts)] = .{
	901	.llvm_name = "gfx1250-insts",
	902	.description = "Additional instructions for GFX1250+",
	903	.dependencies = featureSet(&[_]Feature{}),
	904	};
850	905	result[@intFromEnum(Feature.gfx12_insts)] = .{
851	906	.llvm_name = "gfx12-insts",
852	907	.description = "Additional instructions for GFX12+",
...	...	@@ -902,6 +957,7 @@ pub const all_features = blk: {
902	957	.unaligned_ds_access,
903	958	.unaligned_scratch_access,
904	959	.vgpr_index_mode,
	960	.vmem_to_lds_load_insts,
905	961	.vmem_write_vgpr_in_order,
906	962	.vop3p,
907	963	.wavefrontsize64,
...	...	@@ -951,6 +1007,11 @@ pub const all_features = blk: {
951	1007	.description = "Most fp64 instructions are half rate instead of quarter",
952	1008	.dependencies = featureSet(&[_]Feature{}),
953	1009	};
	1010	result[@intFromEnum(Feature.ieee_minimum_maximum_insts)] = .{
	1011	.llvm_name = "ieee-minimum-maximum-insts",
	1012	.description = "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 and v_pk_minimum/maximum_f16 instructions",
	1013	.dependencies = featureSet(&[_]Feature{}),
	1014	};
954	1015	result[@intFromEnum(Feature.image_gather4_d16_bug)] = .{
955	1016	.llvm_name = "image-gather4-d16-bug",
956	1017	.description = "Image Gather4 D16 hardware bug",
...	...	@@ -986,6 +1047,11 @@ pub const all_features = blk: {
986	1047	.description = "Hardware supports preloading of kernel arguments in user SGPRs.",
987	1048	.dependencies = featureSet(&[_]Feature{}),
988	1049	};
	1050	result[@intFromEnum(Feature.lds_barrier_arrive_atomic)] = .{
	1051	.llvm_name = "lds-barrier-arrive-atomic",
	1052	.description = "Has LDS barrier-arrive atomic instructions",
	1053	.dependencies = featureSet(&[_]Feature{}),
	1054	};
989	1055	result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{
990	1056	.llvm_name = "lds-branch-vmem-war-hazard",
991	1057	.description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
...	...	@@ -1011,6 +1077,11 @@ pub const all_features = blk: {
1011	1077	.description = "Enable SI load/store optimizer pass",
1012	1078	.dependencies = featureSet(&[_]Feature{}),
1013	1079	};
	1080	result[@intFromEnum(Feature.lshl_add_u64_inst)] = .{
	1081	.llvm_name = "lshl-add-u64-inst",
	1082	.description = "Has v_lshl_add_u64 instruction",
	1083	.dependencies = featureSet(&[_]Feature{}),
	1084	};
1014	1085	result[@intFromEnum(Feature.mad_intra_fwd_bug)] = .{
1015	1086	.llvm_name = "mad-intra-fwd-bug",
1016	1087	.description = "MAD_U64/I64 intra instruction forwarding bug",
...	...	@@ -1166,6 +1237,11 @@ pub const all_features = blk: {
1166	1237	.description = "Has v_pk_fmac_f16 instruction",
1167	1238	.dependencies = featureSet(&[_]Feature{}),
1168	1239	};
	1240	result[@intFromEnum(Feature.point_sample_accel)] = .{
	1241	.llvm_name = "point-sample-accel",
	1242	.description = "Has point sample acceleration feature",
	1243	.dependencies = featureSet(&[_]Feature{}),
	1244	};
1169	1245	result[@intFromEnum(Feature.precise_memory)] = .{
1170	1246	.llvm_name = "precise-memory",
1171	1247	.description = "Enable precise memory mode",
...	...	@@ -1206,6 +1282,11 @@ pub const all_features = blk: {
1206	1282	.description = "Use true 16-bit registers",
1207	1283	.dependencies = featureSet(&[_]Feature{}),
1208	1284	};
	1285	result[@intFromEnum(Feature.relaxed_buffer_oob_mode)] = .{
	1286	.llvm_name = "relaxed-buffer-oob-mode",
	1287	.description = "Disable strict out-of-bounds buffer guarantees. An OOB access may potentially cause an adjacent access to be treated as if it were also OOB",
	1288	.dependencies = featureSet(&[_]Feature{}),
	1289	};
1209	1290	result[@intFromEnum(Feature.required_export_priority)] = .{
1210	1291	.llvm_name = "required-export-priority",
1211	1292	.description = "Export priority must be explicitly manipulated on GFX11.5",
...	...	@@ -1231,6 +1312,11 @@ pub const all_features = blk: {
1231	1312	.description = "Has s_memtime instruction",
1232	1313	.dependencies = featureSet(&[_]Feature{}),
1233	1314	};
	1315	result[@intFromEnum(Feature.safe_smem_prefetch)] = .{
	1316	.llvm_name = "safe-smem-prefetch",
	1317	.description = "SMEM prefetches do not fail on illegal address",
	1318	.dependencies = featureSet(&[_]Feature{}),
	1319	};
1234	1320	result[@intFromEnum(Feature.salu_float)] = .{
1235	1321	.llvm_name = "salu-float",
1236	1322	.description = "Has SALU floating point instructions",
...	...	@@ -1315,6 +1401,11 @@ pub const all_features = blk: {
1315	1401	.wavefrontsize64,
1316	1402	}),
1317	1403	};
	1404	result[@intFromEnum(Feature.setprio_inc_wg_inst)] = .{
	1405	.llvm_name = "setprio-inc-wg-inst",
	1406	.description = "Has s_setprio_inc_wg instruction.",
	1407	.dependencies = featureSet(&[_]Feature{}),
	1408	};
1318	1409	result[@intFromEnum(Feature.sgpr_init_bug)] = .{
1319	1410	.llvm_name = "sgpr-init-bug",
1320	1411	.description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
...	...	@@ -1379,6 +1470,11 @@ pub const all_features = blk: {
1379	1470	.description = "Enable threadgroup split execution",
1380	1471	.dependencies = featureSet(&[_]Feature{}),
1381	1472	};
	1473	result[@intFromEnum(Feature.transpose_load_f4f6_insts)] = .{
	1474	.llvm_name = "transpose-load-f4f6-insts",
	1475	.description = "Has ds_load_tr4/tr6 and global_load_tr4/tr6 instructions",
	1476	.dependencies = featureSet(&[_]Feature{}),
	1477	};
1382	1478	result[@intFromEnum(Feature.trap_handler)] = .{
1383	1479	.llvm_name = "trap-handler",
1384	1480	.description = "Trap handler support",
...	...	@@ -1449,6 +1545,11 @@ pub const all_features = blk: {
1449	1545	.description = "Has VGPR mode register indexing",
1450	1546	.dependencies = featureSet(&[_]Feature{}),
1451	1547	};
	1548	result[@intFromEnum(Feature.vmem_to_lds_load_insts)] = .{
	1549	.llvm_name = "vmem-to-lds-load-insts",
	1550	.description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.",
	1551	.dependencies = featureSet(&[_]Feature{}),
	1552	};
1452	1553	result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{
1453	1554	.llvm_name = "vmem-to-scalar-write-hazard",
1454	1555	.description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
...	...	@@ -1517,6 +1618,11 @@ pub const all_features = blk: {
1517	1618	.description = "Has separate store vscnt counter",
1518	1619	.dependencies = featureSet(&[_]Feature{}),
1519	1620	};
	1621	result[@intFromEnum(Feature.wait_xcnt)] = .{
	1622	.llvm_name = "wait-xcnt",
	1623	.description = "Has s_wait_xcnt instruction",
	1624	.dependencies = featureSet(&[_]Feature{}),
	1625	};
1520	1626	result[@intFromEnum(Feature.wavefrontsize16)] = .{
1521	1627	.llvm_name = "wavefrontsize16",
1522	1628	.description = "The number of threads per wavefront",
...	...	@@ -1588,18 +1694,13 @@ pub const cpu = struct {
1588	1694	pub const generic: CpuModel = .{
1589	1695	.name = "generic",
1590	1696	.llvm_name = "generic",
1591		.features = featureSet(&[_]Feature{
1592		.gds,
1593		.gws,
1594		}),
	1697	.features = featureSet(&[_]Feature{}),
1595	1698	};
1596	1699	pub const generic_hsa: CpuModel = .{
1597	1700	.name = "generic_hsa",
1598	1701	.llvm_name = "generic-hsa",
1599	1702	.features = featureSet(&[_]Feature{
1600	1703	.flat_address_space,
1601		.gds,
1602		.gws,
1603	1704	}),
1604	1705	};
1605	1706	pub const gfx1010: CpuModel = .{
...	...	@@ -1961,6 +2062,7 @@ pub const cpu = struct {
1961	2062	.packed_tid,
1962	2063	.partial_nsa_encoding,
1963	2064	.priv_enabled_trap2_nop_bug,
	2065	.real_true16,
1964	2066	.shader_cycles_register,
1965	2067	.user_sgpr_init16_bug,
1966	2068	.valu_trans_use_hazard,
...	...	@@ -1993,6 +2095,7 @@ pub const cpu = struct {
1993	2095	.packed_tid,
1994	2096	.partial_nsa_encoding,
1995	2097	.priv_enabled_trap2_nop_bug,
	2098	.real_true16,
1996	2099	.shader_cycles_register,
1997	2100	.valu_trans_use_hazard,
1998	2101	.vcmpx_permlane_hazard,
...	...	@@ -2023,6 +2126,7 @@ pub const cpu = struct {
2023	2126	.packed_tid,
2024	2127	.partial_nsa_encoding,
2025	2128	.priv_enabled_trap2_nop_bug,
	2129	.real_true16,
2026	2130	.shader_cycles_register,
2027	2131	.user_sgpr_init16_bug,
2028	2132	.valu_trans_use_hazard,
...	...	@@ -2054,6 +2158,7 @@ pub const cpu = struct {
2054	2158	.packed_tid,
2055	2159	.partial_nsa_encoding,
2056	2160	.priv_enabled_trap2_nop_bug,
	2161	.real_true16,
2057	2162	.shader_cycles_register,
2058	2163	.valu_trans_use_hazard,
2059	2164	.vcmpx_permlane_hazard,
...	...	@@ -2082,6 +2187,7 @@ pub const cpu = struct {
2082	2187	.nsa_encoding,
2083	2188	.packed_tid,
2084	2189	.partial_nsa_encoding,
	2190	.point_sample_accel,
2085	2191	.required_export_priority,
2086	2192	.salu_float,
2087	2193	.shader_cycles_register,
...	...	@@ -2112,6 +2218,7 @@ pub const cpu = struct {
2112	2218	.nsa_encoding,
2113	2219	.packed_tid,
2114	2220	.partial_nsa_encoding,
	2221	.point_sample_accel,
2115	2222	.required_export_priority,
2116	2223	.salu_float,
2117	2224	.shader_cycles_register,
...	...	@@ -2141,6 +2248,7 @@ pub const cpu = struct {
2141	2248	.nsa_encoding,
2142	2249	.packed_tid,
2143	2250	.partial_nsa_encoding,
	2251	.point_sample_accel,
2144	2252	.required_export_priority,
2145	2253	.salu_float,
2146	2254	.shader_cycles_register,
...	...	@@ -2223,6 +2331,7 @@ pub const cpu = struct {
2223	2331	.atomic_fadd_rtn_insts,
2224	2332	.atomic_flat_pk_add_16_insts,
2225	2333	.atomic_global_pk_add_bf16_inst,
	2334	.bvh_dual_bvh_8_insts,
2226	2335	.dl_insts,
2227	2336	.dot10_insts,
2228	2337	.dot11_insts,
...	...	@@ -2263,6 +2372,7 @@ pub const cpu = struct {
2263	2372	.atomic_fadd_rtn_insts,
2264	2373	.atomic_flat_pk_add_16_insts,
2265	2374	.atomic_global_pk_add_bf16_inst,
	2375	.bvh_dual_bvh_8_insts,
2266	2376	.dl_insts,
2267	2377	.dot10_insts,
2268	2378	.dot11_insts,
...	...	@@ -2289,6 +2399,63 @@ pub const cpu = struct {
2289	2399	.vcmpx_permlane_hazard,
2290	2400	}),
2291	2401	};
	2402	pub const gfx1250: CpuModel = .{
	2403	.name = "gfx1250",
	2404	.llvm_name = "gfx1250",
	2405	.features = featureSet(&[_]Feature{
	2406	.@"64_bit_literals",
	2407	.architected_flat_scratch,
	2408	.architected_sgprs,
	2409	.ashr_pk_insts,
	2410	.atomic_buffer_global_pk_add_f16_insts,
	2411	.atomic_buffer_pk_add_bf16_inst,
	2412	.atomic_ds_pk_add_16_insts,
	2413	.atomic_fadd_no_rtn_insts,
	2414	.atomic_fadd_rtn_insts,
	2415	.atomic_flat_pk_add_16_insts,
	2416	.atomic_fmin_fmax_flat_f64,
	2417	.atomic_fmin_fmax_global_f64,
	2418	.atomic_global_pk_add_bf16_inst,
	2419	.bf16_cvt_insts,
	2420	.bf16_trans_insts,
	2421	.bitop3_insts,
	2422	.cumode,
	2423	.cvt_pk_f16_f32_inst,
	2424	.dl_insts,
	2425	.dot7_insts,
	2426	.dot8_insts,
	2427	.dpp_src1_sgpr,
	2428	.flat_atomic_fadd_f32_inst,
	2429	.flat_buffer_global_fadd_f64_inst,
	2430	.fmacf64_inst,
	2431	.fp8_conversion_insts,
	2432	.fp8e5m3_insts,
	2433	.gfx12,
	2434	.gfx1250_insts,
	2435	.kernarg_preload,
	2436	.lds_barrier_arrive_atomic,
	2437	.ldsbankcount32,
	2438	.lshl_add_u64_inst,
	2439	.max_hard_clause_length_63,
	2440	.memory_atomic_fadd_f32_denormal_support,
	2441	.minimum3_maximum3_pkf16,
	2442	.packed_fp32_ops,
	2443	.packed_tid,
	2444	.permlane16_swap,
	2445	.prng_inst,
	2446	.pseudo_scalar_trans,
	2447	.restricted_soffset,
	2448	.salu_float,
	2449	.scalar_dwordx3_loads,
	2450	.setprio_inc_wg_inst,
	2451	.shader_cycles_hi_lo_registers,
	2452	.sramecc_support,
	2453	.transpose_load_f4f6_insts,
	2454	.vcmpx_permlane_hazard,
	2455	.wait_xcnt,
	2456	.wavefrontsize32,
	2457	}),
	2458	};
2292	2459	pub const gfx12_generic: CpuModel = .{
2293	2460	.name = "gfx12_generic",
2294	2461	.llvm_name = "gfx12-generic",
...	...	@@ -2303,6 +2470,7 @@ pub const cpu = struct {
2303	2470	.atomic_fadd_rtn_insts,
2304	2471	.atomic_flat_pk_add_16_insts,
2305	2472	.atomic_global_pk_add_bf16_inst,
	2473	.bvh_dual_bvh_8_insts,
2306	2474	.dl_insts,
2307	2475	.dot10_insts,
2308	2476	.dot11_insts,
...	...	@@ -2629,102 +2797,6 @@ pub const cpu = struct {
2629	2797	.mad_mix_insts,
2630	2798	}),
2631	2799	};
2632		pub const gfx940: CpuModel = .{
2633		.name = "gfx940",
2634		.llvm_name = "gfx940",
2635		.features = featureSet(&[_]Feature{
2636		.addressablelocalmemorysize65536,
2637		.agent_scope_fine_grained_remote_memory_atomics,
2638		.architected_flat_scratch,
2639		.atomic_buffer_global_pk_add_f16_insts,
2640		.atomic_ds_pk_add_16_insts,
2641		.atomic_fadd_no_rtn_insts,
2642		.atomic_fadd_rtn_insts,
2643		.atomic_flat_pk_add_16_insts,
2644		.atomic_fmin_fmax_flat_f64,
2645		.atomic_fmin_fmax_global_f64,
2646		.atomic_global_pk_add_bf16_inst,
2647		.back_off_barrier,
2648		.cvt_fp8_vop1_bug,
2649		.dl_insts,
2650		.dot10_insts,
2651		.dot1_insts,
2652		.dot2_insts,
2653		.dot3_insts,
2654		.dot4_insts,
2655		.dot5_insts,
2656		.dot6_insts,
2657		.dot7_insts,
2658		.dpp_64bit,
2659		.flat_atomic_fadd_f32_inst,
2660		.flat_buffer_global_fadd_f64_inst,
2661		.fma_mix_insts,
2662		.fmacf64_inst,
2663		.force_store_sc0_sc1,
2664		.fp8_insts,
2665		.full_rate_64_ops,
2666		.gfx9,
2667		.gfx90a_insts,
2668		.gfx940_insts,
2669		.kernarg_preload,
2670		.ldsbankcount32,
2671		.mai_insts,
2672		.memory_atomic_fadd_f32_denormal_support,
2673		.packed_fp32_ops,
2674		.packed_tid,
2675		.pk_fmac_f16_inst,
2676		.sramecc_support,
2677		.xf32_insts,
2678		}),
2679		};
2680		pub const gfx941: CpuModel = .{
2681		.name = "gfx941",
2682		.llvm_name = "gfx941",
2683		.features = featureSet(&[_]Feature{
2684		.addressablelocalmemorysize65536,
2685		.agent_scope_fine_grained_remote_memory_atomics,
2686		.architected_flat_scratch,
2687		.atomic_buffer_global_pk_add_f16_insts,
2688		.atomic_ds_pk_add_16_insts,
2689		.atomic_fadd_no_rtn_insts,
2690		.atomic_fadd_rtn_insts,
2691		.atomic_flat_pk_add_16_insts,
2692		.atomic_fmin_fmax_flat_f64,
2693		.atomic_fmin_fmax_global_f64,
2694		.atomic_global_pk_add_bf16_inst,
2695		.back_off_barrier,
2696		.cvt_fp8_vop1_bug,
2697		.dl_insts,
2698		.dot10_insts,
2699		.dot1_insts,
2700		.dot2_insts,
2701		.dot3_insts,
2702		.dot4_insts,
2703		.dot5_insts,
2704		.dot6_insts,
2705		.dot7_insts,
2706		.dpp_64bit,
2707		.flat_atomic_fadd_f32_inst,
2708		.flat_buffer_global_fadd_f64_inst,
2709		.fma_mix_insts,
2710		.fmacf64_inst,
2711		.force_store_sc0_sc1,
2712		.fp8_insts,
2713		.full_rate_64_ops,
2714		.gfx9,
2715		.gfx90a_insts,
2716		.gfx940_insts,
2717		.kernarg_preload,
2718		.ldsbankcount32,
2719		.mai_insts,
2720		.memory_atomic_fadd_f32_denormal_support,
2721		.packed_fp32_ops,
2722		.packed_tid,
2723		.pk_fmac_f16_inst,
2724		.sramecc_support,
2725		.xf32_insts,
2726		}),
2727		};
2728	2800	pub const gfx942: CpuModel = .{
2729	2801	.name = "gfx942",
2730	2802	.llvm_name = "gfx942",
...	...	@@ -2763,6 +2835,7 @@ pub const cpu = struct {
2763	2835	.gfx940_insts,
2764	2836	.kernarg_preload,
2765	2837	.ldsbankcount32,
	2838	.lshl_add_u64_inst,
2766	2839	.mai_insts,
2767	2840	.memory_atomic_fadd_f32_denormal_support,
2768	2841	.packed_fp32_ops,
...	...	@@ -2816,6 +2889,7 @@ pub const cpu = struct {
2816	2889	.gfx950_insts,
2817	2890	.kernarg_preload,
2818	2891	.ldsbankcount32,
	2892	.lshl_add_u64_inst,
2819	2893	.mai_insts,
2820	2894	.memory_atomic_fadd_f32_denormal_support,
2821	2895	.packed_fp32_ops,
...	...	@@ -2861,6 +2935,7 @@ pub const cpu = struct {
2861	2935	.gfx940_insts,
2862	2936	.kernarg_preload,
2863	2937	.ldsbankcount32,
	2938	.lshl_add_u64_inst,
2864	2939	.mai_insts,
2865	2940	.memory_atomic_fadd_f32_denormal_support,
2866	2941	.packed_fp32_ops,

lib/std/Target/arm.zig+1

...	...	@@ -2646,6 +2646,7 @@ pub const cpu = struct {
2646	2646	.name = "star_mc1",
2647	2647	.llvm_name = "star-mc1",
2648	2648	.features = featureSet(&[_]Feature{
	2649	.avoid_muls,
2649	2650	.dsp,
2650	2651	.fix_cmse_cve_2021_35465,
2651	2652	.fp_armv8d16sp,

lib/std/Target/avr.zig+497

...	...	@@ -40,7 +40,9 @@ pub const Feature = enum {
40	40	tinyencoding,
41	41	wrappingrjmp,
42	42	xmega,
	43	xmega2,
43	44	xmega3,
	45	xmega4,
44	46	xmegau,
45	47	};
46	48
...	...	@@ -318,6 +320,25 @@ pub const all_features = blk: {
318	320	.sram,
319	321	}),
320	322	};
	323	result[@intFromEnum(Feature.xmega2)] = .{
	324	.llvm_name = "xmega2",
	325	.description = "The device is a part of the xmega2 family",
	326	.dependencies = featureSet(&[_]Feature{
	327	.addsubiw,
	328	.avr0,
	329	.@"break",
	330	.ijmpcall,
	331	.jmpcall,
	332	.lowbytefirst,
	333	.lpm,
	334	.lpmx,
	335	.movw,
	336	.mul,
	337	.spm,
	338	.spmx,
	339	.sram,
	340	}),
	341	};
321	342	result[@intFromEnum(Feature.xmega3)] = .{
322	343	.llvm_name = "xmega3",
323	344	.description = "The device is a part of the xmega3 family",
...	...	@@ -335,6 +356,27 @@ pub const all_features = blk: {
335	356	.sram,
336	357	}),
337	358	};
	359	result[@intFromEnum(Feature.xmega4)] = .{
	360	.llvm_name = "xmega4",
	361	.description = "The device is a part of the xmega4 family",
	362	.dependencies = featureSet(&[_]Feature{
	363	.addsubiw,
	364	.avr0,
	365	.@"break",
	366	.elpm,
	367	.elpmx,
	368	.ijmpcall,
	369	.jmpcall,
	370	.lowbytefirst,
	371	.lpm,
	372	.lpmx,
	373	.movw,
	374	.mul,
	375	.spm,
	376	.spmx,
	377	.sram,
	378	}),
	379	};
338	380	result[@intFromEnum(Feature.xmegau)] = .{
339	381	.llvm_name = "xmegau",
340	382	.description = "The device is a part of the xmegau family",
...	...	@@ -1927,6 +1969,27 @@ pub const cpu = struct {
1927	1969	.xmega3,
1928	1970	}),
1929	1971	};
	1972	pub const attiny3224: CpuModel = .{
	1973	.name = "attiny3224",
	1974	.llvm_name = "attiny3224",
	1975	.features = featureSet(&[_]Feature{
	1976	.xmega3,
	1977	}),
	1978	};
	1979	pub const attiny3226: CpuModel = .{
	1980	.name = "attiny3226",
	1981	.llvm_name = "attiny3226",
	1982	.features = featureSet(&[_]Feature{
	1983	.xmega3,
	1984	}),
	1985	};
	1986	pub const attiny3227: CpuModel = .{
	1987	.name = "attiny3227",
	1988	.llvm_name = "attiny3227",
	1989	.features = featureSet(&[_]Feature{
	1990	.xmega3,
	1991	}),
	1992	};
1930	1993	pub const attiny4: CpuModel = .{
1931	1994	.name = "attiny4",
1932	1995	.llvm_name = "attiny4",
...	...	@@ -2503,6 +2566,160 @@ pub const cpu = struct {
2503	2566	.avr1,
2504	2567	}),
2505	2568	};
	2569	pub const avr128da28: CpuModel = .{
	2570	.name = "avr128da28",
	2571	.llvm_name = "avr128da28",
	2572	.features = featureSet(&[_]Feature{
	2573	.xmega4,
	2574	}),
	2575	};
	2576	pub const avr128da32: CpuModel = .{
	2577	.name = "avr128da32",
	2578	.llvm_name = "avr128da32",
	2579	.features = featureSet(&[_]Feature{
	2580	.xmega4,
	2581	}),
	2582	};
	2583	pub const avr128da48: CpuModel = .{
	2584	.name = "avr128da48",
	2585	.llvm_name = "avr128da48",
	2586	.features = featureSet(&[_]Feature{
	2587	.xmega4,
	2588	}),
	2589	};
	2590	pub const avr128da64: CpuModel = .{
	2591	.name = "avr128da64",
	2592	.llvm_name = "avr128da64",
	2593	.features = featureSet(&[_]Feature{
	2594	.xmega4,
	2595	}),
	2596	};
	2597	pub const avr128db28: CpuModel = .{
	2598	.name = "avr128db28",
	2599	.llvm_name = "avr128db28",
	2600	.features = featureSet(&[_]Feature{
	2601	.xmega4,
	2602	}),
	2603	};
	2604	pub const avr128db32: CpuModel = .{
	2605	.name = "avr128db32",
	2606	.llvm_name = "avr128db32",
	2607	.features = featureSet(&[_]Feature{
	2608	.xmega4,
	2609	}),
	2610	};
	2611	pub const avr128db48: CpuModel = .{
	2612	.name = "avr128db48",
	2613	.llvm_name = "avr128db48",
	2614	.features = featureSet(&[_]Feature{
	2615	.xmega4,
	2616	}),
	2617	};
	2618	pub const avr128db64: CpuModel = .{
	2619	.name = "avr128db64",
	2620	.llvm_name = "avr128db64",
	2621	.features = featureSet(&[_]Feature{
	2622	.xmega4,
	2623	}),
	2624	};
	2625	pub const avr16dd20: CpuModel = .{
	2626	.name = "avr16dd20",
	2627	.llvm_name = "avr16dd20",
	2628	.features = featureSet(&[_]Feature{
	2629	.xmega3,
	2630	}),
	2631	};
	2632	pub const avr16dd28: CpuModel = .{
	2633	.name = "avr16dd28",
	2634	.llvm_name = "avr16dd28",
	2635	.features = featureSet(&[_]Feature{
	2636	.xmega3,
	2637	}),
	2638	};
	2639	pub const avr16dd32: CpuModel = .{
	2640	.name = "avr16dd32",
	2641	.llvm_name = "avr16dd32",
	2642	.features = featureSet(&[_]Feature{
	2643	.xmega3,
	2644	}),
	2645	};
	2646	pub const avr16du14: CpuModel = .{
	2647	.name = "avr16du14",
	2648	.llvm_name = "avr16du14",
	2649	.features = featureSet(&[_]Feature{
	2650	.xmega3,
	2651	}),
	2652	};
	2653	pub const avr16du20: CpuModel = .{
	2654	.name = "avr16du20",
	2655	.llvm_name = "avr16du20",
	2656	.features = featureSet(&[_]Feature{
	2657	.xmega3,
	2658	}),
	2659	};
	2660	pub const avr16du28: CpuModel = .{
	2661	.name = "avr16du28",
	2662	.llvm_name = "avr16du28",
	2663	.features = featureSet(&[_]Feature{
	2664	.xmega3,
	2665	}),
	2666	};
	2667	pub const avr16du32: CpuModel = .{
	2668	.name = "avr16du32",
	2669	.llvm_name = "avr16du32",
	2670	.features = featureSet(&[_]Feature{
	2671	.xmega3,
	2672	}),
	2673	};
	2674	pub const avr16ea28: CpuModel = .{
	2675	.name = "avr16ea28",
	2676	.llvm_name = "avr16ea28",
	2677	.features = featureSet(&[_]Feature{
	2678	.xmega3,
	2679	}),
	2680	};
	2681	pub const avr16ea32: CpuModel = .{
	2682	.name = "avr16ea32",
	2683	.llvm_name = "avr16ea32",
	2684	.features = featureSet(&[_]Feature{
	2685	.xmega3,
	2686	}),
	2687	};
	2688	pub const avr16ea48: CpuModel = .{
	2689	.name = "avr16ea48",
	2690	.llvm_name = "avr16ea48",
	2691	.features = featureSet(&[_]Feature{
	2692	.xmega3,
	2693	}),
	2694	};
	2695	pub const avr16eb14: CpuModel = .{
	2696	.name = "avr16eb14",
	2697	.llvm_name = "avr16eb14",
	2698	.features = featureSet(&[_]Feature{
	2699	.xmega3,
	2700	}),
	2701	};
	2702	pub const avr16eb20: CpuModel = .{
	2703	.name = "avr16eb20",
	2704	.llvm_name = "avr16eb20",
	2705	.features = featureSet(&[_]Feature{
	2706	.xmega3,
	2707	}),
	2708	};
	2709	pub const avr16eb28: CpuModel = .{
	2710	.name = "avr16eb28",
	2711	.llvm_name = "avr16eb28",
	2712	.features = featureSet(&[_]Feature{
	2713	.xmega3,
	2714	}),
	2715	};
	2716	pub const avr16eb32: CpuModel = .{
	2717	.name = "avr16eb32",
	2718	.llvm_name = "avr16eb32",
	2719	.features = featureSet(&[_]Feature{
	2720	.xmega3,
	2721	}),
	2722	};
2506	2723	pub const avr2: CpuModel = .{
2507	2724	.name = "avr2",
2508	2725	.llvm_name = "avr2",
...	...	@@ -2531,6 +2748,146 @@ pub const cpu = struct {
2531	2748	.avr31,
2532	2749	}),
2533	2750	};
	2751	pub const avr32da28: CpuModel = .{
	2752	.name = "avr32da28",
	2753	.llvm_name = "avr32da28",
	2754	.features = featureSet(&[_]Feature{
	2755	.xmega3,
	2756	}),
	2757	};
	2758	pub const avr32da32: CpuModel = .{
	2759	.name = "avr32da32",
	2760	.llvm_name = "avr32da32",
	2761	.features = featureSet(&[_]Feature{
	2762	.xmega3,
	2763	}),
	2764	};
	2765	pub const avr32da48: CpuModel = .{
	2766	.name = "avr32da48",
	2767	.llvm_name = "avr32da48",
	2768	.features = featureSet(&[_]Feature{
	2769	.xmega3,
	2770	}),
	2771	};
	2772	pub const avr32db28: CpuModel = .{
	2773	.name = "avr32db28",
	2774	.llvm_name = "avr32db28",
	2775	.features = featureSet(&[_]Feature{
	2776	.xmega3,
	2777	}),
	2778	};
	2779	pub const avr32db32: CpuModel = .{
	2780	.name = "avr32db32",
	2781	.llvm_name = "avr32db32",
	2782	.features = featureSet(&[_]Feature{
	2783	.xmega3,
	2784	}),
	2785	};
	2786	pub const avr32db48: CpuModel = .{
	2787	.name = "avr32db48",
	2788	.llvm_name = "avr32db48",
	2789	.features = featureSet(&[_]Feature{
	2790	.xmega3,
	2791	}),
	2792	};
	2793	pub const avr32dd14: CpuModel = .{
	2794	.name = "avr32dd14",
	2795	.llvm_name = "avr32dd14",
	2796	.features = featureSet(&[_]Feature{
	2797	.xmega3,
	2798	}),
	2799	};
	2800	pub const avr32dd20: CpuModel = .{
	2801	.name = "avr32dd20",
	2802	.llvm_name = "avr32dd20",
	2803	.features = featureSet(&[_]Feature{
	2804	.xmega3,
	2805	}),
	2806	};
	2807	pub const avr32dd28: CpuModel = .{
	2808	.name = "avr32dd28",
	2809	.llvm_name = "avr32dd28",
	2810	.features = featureSet(&[_]Feature{
	2811	.xmega3,
	2812	}),
	2813	};
	2814	pub const avr32dd32: CpuModel = .{
	2815	.name = "avr32dd32",
	2816	.llvm_name = "avr32dd32",
	2817	.features = featureSet(&[_]Feature{
	2818	.xmega3,
	2819	}),
	2820	};
	2821	pub const avr32du14: CpuModel = .{
	2822	.name = "avr32du14",
	2823	.llvm_name = "avr32du14",
	2824	.features = featureSet(&[_]Feature{
	2825	.xmega3,
	2826	}),
	2827	};
	2828	pub const avr32du20: CpuModel = .{
	2829	.name = "avr32du20",
	2830	.llvm_name = "avr32du20",
	2831	.features = featureSet(&[_]Feature{
	2832	.xmega3,
	2833	}),
	2834	};
	2835	pub const avr32du28: CpuModel = .{
	2836	.name = "avr32du28",
	2837	.llvm_name = "avr32du28",
	2838	.features = featureSet(&[_]Feature{
	2839	.xmega3,
	2840	}),
	2841	};
	2842	pub const avr32du32: CpuModel = .{
	2843	.name = "avr32du32",
	2844	.llvm_name = "avr32du32",
	2845	.features = featureSet(&[_]Feature{
	2846	.xmega3,
	2847	}),
	2848	};
	2849	pub const avr32ea28: CpuModel = .{
	2850	.name = "avr32ea28",
	2851	.llvm_name = "avr32ea28",
	2852	.features = featureSet(&[_]Feature{
	2853	.xmega3,
	2854	}),
	2855	};
	2856	pub const avr32ea32: CpuModel = .{
	2857	.name = "avr32ea32",
	2858	.llvm_name = "avr32ea32",
	2859	.features = featureSet(&[_]Feature{
	2860	.xmega3,
	2861	}),
	2862	};
	2863	pub const avr32ea48: CpuModel = .{
	2864	.name = "avr32ea48",
	2865	.llvm_name = "avr32ea48",
	2866	.features = featureSet(&[_]Feature{
	2867	.xmega3,
	2868	}),
	2869	};
	2870	pub const avr32sd20: CpuModel = .{
	2871	.name = "avr32sd20",
	2872	.llvm_name = "avr32sd20",
	2873	.features = featureSet(&[_]Feature{
	2874	.xmega3,
	2875	}),
	2876	};
	2877	pub const avr32sd28: CpuModel = .{
	2878	.name = "avr32sd28",
	2879	.llvm_name = "avr32sd28",
	2880	.features = featureSet(&[_]Feature{
	2881	.xmega3,
	2882	}),
	2883	};
	2884	pub const avr32sd32: CpuModel = .{
	2885	.name = "avr32sd32",
	2886	.llvm_name = "avr32sd32",
	2887	.features = featureSet(&[_]Feature{
	2888	.xmega3,
	2889	}),
	2890	};
2534	2891	pub const avr35: CpuModel = .{
2535	2892	.name = "avr35",
2536	2893	.llvm_name = "avr35",
...	...	@@ -2566,6 +2923,146 @@ pub const cpu = struct {
2566	2923	.avr6,
2567	2924	}),
2568	2925	};
	2926	pub const avr64da28: CpuModel = .{
	2927	.name = "avr64da28",
	2928	.llvm_name = "avr64da28",
	2929	.features = featureSet(&[_]Feature{
	2930	.xmega2,
	2931	}),
	2932	};
	2933	pub const avr64da32: CpuModel = .{
	2934	.name = "avr64da32",
	2935	.llvm_name = "avr64da32",
	2936	.features = featureSet(&[_]Feature{
	2937	.xmega2,
	2938	}),
	2939	};
	2940	pub const avr64da48: CpuModel = .{
	2941	.name = "avr64da48",
	2942	.llvm_name = "avr64da48",
	2943	.features = featureSet(&[_]Feature{
	2944	.xmega2,
	2945	}),
	2946	};
	2947	pub const avr64da64: CpuModel = .{
	2948	.name = "avr64da64",
	2949	.llvm_name = "avr64da64",
	2950	.features = featureSet(&[_]Feature{
	2951	.xmega2,
	2952	}),
	2953	};
	2954	pub const avr64db28: CpuModel = .{
	2955	.name = "avr64db28",
	2956	.llvm_name = "avr64db28",
	2957	.features = featureSet(&[_]Feature{
	2958	.xmega2,
	2959	}),
	2960	};
	2961	pub const avr64db32: CpuModel = .{
	2962	.name = "avr64db32",
	2963	.llvm_name = "avr64db32",
	2964	.features = featureSet(&[_]Feature{
	2965	.xmega2,
	2966	}),
	2967	};
	2968	pub const avr64db48: CpuModel = .{
	2969	.name = "avr64db48",
	2970	.llvm_name = "avr64db48",
	2971	.features = featureSet(&[_]Feature{
	2972	.xmega2,
	2973	}),
	2974	};
	2975	pub const avr64db64: CpuModel = .{
	2976	.name = "avr64db64",
	2977	.llvm_name = "avr64db64",
	2978	.features = featureSet(&[_]Feature{
	2979	.xmega2,
	2980	}),
	2981	};
	2982	pub const avr64dd14: CpuModel = .{
	2983	.name = "avr64dd14",
	2984	.llvm_name = "avr64dd14",
	2985	.features = featureSet(&[_]Feature{
	2986	.xmega2,
	2987	}),
	2988	};
	2989	pub const avr64dd20: CpuModel = .{
	2990	.name = "avr64dd20",
	2991	.llvm_name = "avr64dd20",
	2992	.features = featureSet(&[_]Feature{
	2993	.xmega2,
	2994	}),
	2995	};
	2996	pub const avr64dd28: CpuModel = .{
	2997	.name = "avr64dd28",
	2998	.llvm_name = "avr64dd28",
	2999	.features = featureSet(&[_]Feature{
	3000	.xmega2,
	3001	}),
	3002	};
	3003	pub const avr64dd32: CpuModel = .{
	3004	.name = "avr64dd32",
	3005	.llvm_name = "avr64dd32",
	3006	.features = featureSet(&[_]Feature{
	3007	.xmega2,
	3008	}),
	3009	};
	3010	pub const avr64du28: CpuModel = .{
	3011	.name = "avr64du28",
	3012	.llvm_name = "avr64du28",
	3013	.features = featureSet(&[_]Feature{
	3014	.xmega2,
	3015	}),
	3016	};
	3017	pub const avr64du32: CpuModel = .{
	3018	.name = "avr64du32",
	3019	.llvm_name = "avr64du32",
	3020	.features = featureSet(&[_]Feature{
	3021	.xmega2,
	3022	}),
	3023	};
	3024	pub const avr64ea28: CpuModel = .{
	3025	.name = "avr64ea28",
	3026	.llvm_name = "avr64ea28",
	3027	.features = featureSet(&[_]Feature{
	3028	.xmega2,
	3029	}),
	3030	};
	3031	pub const avr64ea32: CpuModel = .{
	3032	.name = "avr64ea32",
	3033	.llvm_name = "avr64ea32",
	3034	.features = featureSet(&[_]Feature{
	3035	.xmega2,
	3036	}),
	3037	};
	3038	pub const avr64ea48: CpuModel = .{
	3039	.name = "avr64ea48",
	3040	.llvm_name = "avr64ea48",
	3041	.features = featureSet(&[_]Feature{
	3042	.xmega2,
	3043	}),
	3044	};
	3045	pub const avr64sd28: CpuModel = .{
	3046	.name = "avr64sd28",
	3047	.llvm_name = "avr64sd28",
	3048	.features = featureSet(&[_]Feature{
	3049	.xmega2,
	3050	}),
	3051	};
	3052	pub const avr64sd32: CpuModel = .{
	3053	.name = "avr64sd32",
	3054	.llvm_name = "avr64sd32",
	3055	.features = featureSet(&[_]Feature{
	3056	.xmega2,
	3057	}),
	3058	};
	3059	pub const avr64sd48: CpuModel = .{
	3060	.name = "avr64sd48",
	3061	.llvm_name = "avr64sd48",
	3062	.features = featureSet(&[_]Feature{
	3063	.xmega2,
	3064	}),
	3065	};
2569	3066	pub const avrtiny: CpuModel = .{
2570	3067	.name = "avrtiny",
2571	3068	.llvm_name = "avrtiny",

lib/std/Target/loongarch.zig+13-5

...	...	@@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
8	8	@"32bit",
	9	@"32s",
9	10	@"64bit",
10	11	d,
11	12	div32,
...	...	@@ -41,10 +42,17 @@ pub const all_features = blk: {
41	42	.description = "LA32 Basic Integer and Privilege Instruction Set",
42	43	.dependencies = featureSet(&[_]Feature{}),
43	44	};
	45	result[@intFromEnum(Feature.@"32s")] = .{
	46	.llvm_name = "32s",
	47	.description = "LA32 Standard Basic Instruction Extension",
	48	.dependencies = featureSet(&[_]Feature{}),
	49	};
44	50	result[@intFromEnum(Feature.@"64bit")] = .{
45	51	.llvm_name = "64bit",
46	52	.description = "LA64 Basic Integer and Privilege Instruction Set",
47		.dependencies = featureSet(&[_]Feature{}),
	53	.dependencies = featureSet(&[_]Feature{
	54	.@"32s",
	55	}),
48	56	};
49	57	result[@intFromEnum(Feature.d)] = .{
50	58	.llvm_name = "d",
...	...	@@ -65,7 +73,7 @@ pub const all_features = blk: {
65	73	};
66	74	result[@intFromEnum(Feature.frecipe)] = .{
67	75	.llvm_name = "frecipe",
68		.description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions.",
	76	.description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions",
69	77	.dependencies = featureSet(&[_]Feature{}),
70	78	};
71	79	result[@intFromEnum(Feature.la_global_with_abs)] = .{
...	...	@@ -85,12 +93,12 @@ pub const all_features = blk: {
85	93	};
86	94	result[@intFromEnum(Feature.lam_bh)] = .{
87	95	.llvm_name = "lam-bh",
88		.description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions.",
	96	.description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions",
89	97	.dependencies = featureSet(&[_]Feature{}),
90	98	};
91	99	result[@intFromEnum(Feature.lamcas)] = .{
92	100	.llvm_name = "lamcas",
93		.description = "Support amcas[_db].{b/h/w/d}.",
	101	.description = "Support amcas[_db].{b/h/w/d}",
94	102	.dependencies = featureSet(&[_]Feature{}),
95	103	};
96	104	result[@intFromEnum(Feature.lasx)] = .{
...	...	@@ -107,7 +115,7 @@ pub const all_features = blk: {
107	115	};
108	116	result[@intFromEnum(Feature.ld_seq_sa)] = .{
109	117	.llvm_name = "ld-seq-sa",
110		.description = "Don't use load-load barrier (dbar 0x700).",
	118	.description = "Don't use a same-address load-load barrier (dbar 0x700)",
111	119	.dependencies = featureSet(&[_]Feature{}),
112	120	};
113	121	result[@intFromEnum(Feature.lsx)] = .{

lib/std/Target/mips.zig+32

...	...	@@ -17,6 +17,8 @@ pub const Feature = enum {
17	17	fpxx,
18	18	ginv,
19	19	gp64,
	20	i6400,
	21	i6500,
20	22	long_calls,
21	23	micromips,
22	24	mips1,
...	...	@@ -137,6 +139,22 @@ pub const all_features = blk: {
137	139	.description = "General Purpose Registers are 64-bit wide",
138	140	.dependencies = featureSet(&[_]Feature{}),
139	141	};
	142	result[@intFromEnum(Feature.i6400)] = .{
	143	.llvm_name = "i6400",
	144	.description = "MIPS I6400 Processor",
	145	.dependencies = featureSet(&[_]Feature{
	146	.mips64r6,
	147	.msa,
	148	}),
	149	};
	150	result[@intFromEnum(Feature.i6500)] = .{
	151	.llvm_name = "i6500",
	152	.description = "MIPS I6500 Processor",
	153	.dependencies = featureSet(&[_]Feature{
	154	.mips64r6,
	155	.msa,
	156	}),
	157	};
140	158	result[@intFromEnum(Feature.long_calls)] = .{
141	159	.llvm_name = "long-calls",
142	160	.description = "Disable use of the jal instruction",
...	...	@@ -408,6 +426,20 @@ pub const cpu = struct {
408	426	.mips32,
409	427	}),
410	428	};
	429	pub const @"i6400": CpuModel = .{
	430	.name = "i6400",
	431	.llvm_name = "i6400",
	432	.features = featureSet(&[_]Feature{
	433	.i6400,
	434	}),
	435	};
	436	pub const @"i6500": CpuModel = .{
	437	.name = "i6500",
	438	.llvm_name = "i6500",
	439	.features = featureSet(&[_]Feature{
	440	.i6500,
	441	}),
	442	};
411	443	pub const mips1: CpuModel = .{
412	444	.name = "mips1",
413	445	.llvm_name = "mips1",

lib/std/Target/nvptx.zig+132

...	...	@@ -34,12 +34,22 @@ pub const Feature = enum {
34	34	ptx85,
35	35	ptx86,
36	36	ptx87,
	37	ptx88,
37	38	sm_100,
38	39	sm_100a,
	40	sm_100f,
39	41	sm_101,
40	42	sm_101a,
	43	sm_101f,
	44	sm_103,
	45	sm_103a,
	46	sm_103f,
41	47	sm_120,
42	48	sm_120a,
	49	sm_120f,
	50	sm_121,
	51	sm_121a,
	52	sm_121f,
43	53	sm_20,
44	54	sm_21,
45	55	sm_30,
...	...	@@ -217,6 +227,11 @@ pub const all_features = blk: {
217	227	.description = "Use PTX version 87",
218	228	.dependencies = featureSet(&[_]Feature{}),
219	229	};
	230	result[@intFromEnum(Feature.ptx88)] = .{
	231	.llvm_name = "ptx88",
	232	.description = "Use PTX version 88",
	233	.dependencies = featureSet(&[_]Feature{}),
	234	};
220	235	result[@intFromEnum(Feature.sm_100)] = .{
221	236	.llvm_name = "sm_100",
222	237	.description = "Target SM 100",
...	...	@@ -227,6 +242,11 @@ pub const all_features = blk: {
227	242	.description = "Target SM 100a",
228	243	.dependencies = featureSet(&[_]Feature{}),
229	244	};
	245	result[@intFromEnum(Feature.sm_100f)] = .{
	246	.llvm_name = "sm_100f",
	247	.description = "Target SM 100f",
	248	.dependencies = featureSet(&[_]Feature{}),
	249	};
230	250	result[@intFromEnum(Feature.sm_101)] = .{
231	251	.llvm_name = "sm_101",
232	252	.description = "Target SM 101",
...	...	@@ -237,6 +257,26 @@ pub const all_features = blk: {
237	257	.description = "Target SM 101a",
238	258	.dependencies = featureSet(&[_]Feature{}),
239	259	};
	260	result[@intFromEnum(Feature.sm_101f)] = .{
	261	.llvm_name = "sm_101f",
	262	.description = "Target SM 101f",
	263	.dependencies = featureSet(&[_]Feature{}),
	264	};
	265	result[@intFromEnum(Feature.sm_103)] = .{
	266	.llvm_name = "sm_103",
	267	.description = "Target SM 103",
	268	.dependencies = featureSet(&[_]Feature{}),
	269	};
	270	result[@intFromEnum(Feature.sm_103a)] = .{
	271	.llvm_name = "sm_103a",
	272	.description = "Target SM 103a",
	273	.dependencies = featureSet(&[_]Feature{}),
	274	};
	275	result[@intFromEnum(Feature.sm_103f)] = .{
	276	.llvm_name = "sm_103f",
	277	.description = "Target SM 103f",
	278	.dependencies = featureSet(&[_]Feature{}),
	279	};
240	280	result[@intFromEnum(Feature.sm_120)] = .{
241	281	.llvm_name = "sm_120",
242	282	.description = "Target SM 120",
...	...	@@ -247,6 +287,26 @@ pub const all_features = blk: {
247	287	.description = "Target SM 120a",
248	288	.dependencies = featureSet(&[_]Feature{}),
249	289	};
	290	result[@intFromEnum(Feature.sm_120f)] = .{
	291	.llvm_name = "sm_120f",
	292	.description = "Target SM 120f",
	293	.dependencies = featureSet(&[_]Feature{}),
	294	};
	295	result[@intFromEnum(Feature.sm_121)] = .{
	296	.llvm_name = "sm_121",
	297	.description = "Target SM 121",
	298	.dependencies = featureSet(&[_]Feature{}),
	299	};
	300	result[@intFromEnum(Feature.sm_121a)] = .{
	301	.llvm_name = "sm_121a",
	302	.description = "Target SM 121a",
	303	.dependencies = featureSet(&[_]Feature{}),
	304	};
	305	result[@intFromEnum(Feature.sm_121f)] = .{
	306	.llvm_name = "sm_121f",
	307	.description = "Target SM 121f",
	308	.dependencies = featureSet(&[_]Feature{}),
	309	};
250	310	result[@intFromEnum(Feature.sm_20)] = .{
251	311	.llvm_name = "sm_20",
252	312	.description = "Target SM 20",
...	...	@@ -377,6 +437,14 @@ pub const cpu = struct {
377	437	.sm_100a,
378	438	}),
379	439	};
	440	pub const sm_100f: CpuModel = .{
	441	.name = "sm_100f",
	442	.llvm_name = "sm_100f",
	443	.features = featureSet(&[_]Feature{
	444	.ptx88,
	445	.sm_100f,
	446	}),
	447	};
380	448	pub const sm_101: CpuModel = .{
381	449	.name = "sm_101",
382	450	.llvm_name = "sm_101",
...	...	@@ -393,6 +461,38 @@ pub const cpu = struct {
393	461	.sm_101a,
394	462	}),
395	463	};
	464	pub const sm_101f: CpuModel = .{
	465	.name = "sm_101f",
	466	.llvm_name = "sm_101f",
	467	.features = featureSet(&[_]Feature{
	468	.ptx88,
	469	.sm_101f,
	470	}),
	471	};
	472	pub const sm_103: CpuModel = .{
	473	.name = "sm_103",
	474	.llvm_name = "sm_103",
	475	.features = featureSet(&[_]Feature{
	476	.ptx88,
	477	.sm_103,
	478	}),
	479	};
	480	pub const sm_103a: CpuModel = .{
	481	.name = "sm_103a",
	482	.llvm_name = "sm_103a",
	483	.features = featureSet(&[_]Feature{
	484	.ptx88,
	485	.sm_103a,
	486	}),
	487	};
	488	pub const sm_103f: CpuModel = .{
	489	.name = "sm_103f",
	490	.llvm_name = "sm_103f",
	491	.features = featureSet(&[_]Feature{
	492	.ptx88,
	493	.sm_103f,
	494	}),
	495	};
396	496	pub const sm_120: CpuModel = .{
397	497	.name = "sm_120",
398	498	.llvm_name = "sm_120",
...	...	@@ -409,6 +509,38 @@ pub const cpu = struct {
409	509	.sm_120a,
410	510	}),
411	511	};
	512	pub const sm_120f: CpuModel = .{
	513	.name = "sm_120f",
	514	.llvm_name = "sm_120f",
	515	.features = featureSet(&[_]Feature{
	516	.ptx88,
	517	.sm_120f,
	518	}),
	519	};
	520	pub const sm_121: CpuModel = .{
	521	.name = "sm_121",
	522	.llvm_name = "sm_121",
	523	.features = featureSet(&[_]Feature{
	524	.ptx88,
	525	.sm_121,
	526	}),
	527	};
	528	pub const sm_121a: CpuModel = .{
	529	.name = "sm_121a",
	530	.llvm_name = "sm_121a",
	531	.features = featureSet(&[_]Feature{
	532	.ptx88,
	533	.sm_121a,
	534	}),
	535	};
	536	pub const sm_121f: CpuModel = .{
	537	.name = "sm_121f",
	538	.llvm_name = "sm_121f",
	539	.features = featureSet(&[_]Feature{
	540	.ptx88,
	541	.sm_121f,
	542	}),
	543	};
412	544	pub const sm_20: CpuModel = .{
413	545	.name = "sm_20",
414	546	.llvm_name = "sm_20",

lib/std/Target/powerpc.zig-3

...	...	@@ -825,7 +825,6 @@ pub const cpu = struct {
825	825	.fuse_logical_add,
826	826	.fuse_sha3,
827	827	.fuse_store,
828		.htm,
829	828	.icbt,
830	829	.isa_future_instructions,
831	830	.isa_v206_instructions,
...	...	@@ -980,7 +979,6 @@ pub const cpu = struct {
980	979	.fuse_logical_add,
981	980	.fuse_sha3,
982	981	.fuse_store,
983		.htm,
984	982	.icbt,
985	983	.isa_v206_instructions,
986	984	.isel,
...	...	@@ -1028,7 +1026,6 @@ pub const cpu = struct {
1028	1026	.fuse_logical_add,
1029	1027	.fuse_sha3,
1030	1028	.fuse_store,
1031		.htm,
1032	1029	.icbt,
1033	1030	.isa_v206_instructions,
1034	1031	.isel,

lib/std/Target/riscv.zig+669-35

...	...	@@ -8,6 +8,7 @@ pub const Feature = enum {
8	8	@"32bit",
9	9	@"64bit",
10	10	a,
	11	andes45,
11	12	auipc_addi_fusion,
12	13	b,
13	14	c,
...	...	@@ -16,38 +17,52 @@ pub const Feature = enum {
16	17	disable_latency_sched_heuristic,
17	18	dlen_factor_2,
18	19	e,
	20	exact_asm,
19	21	experimental,
	22	experimental_p,
20	23	experimental_rvm23u32,
21		experimental_sdext,
22		experimental_sdtrig,
23	24	experimental_smctr,
24	25	experimental_ssctr,
25	26	experimental_svukte,
	27	experimental_xqccmp,
26	28	experimental_xqcia,
27	29	experimental_xqciac,
	30	experimental_xqcibi,
	31	experimental_xqcibm,
28	32	experimental_xqcicli,
29	33	experimental_xqcicm,
30	34	experimental_xqcics,
31	35	experimental_xqcicsr,
32	36	experimental_xqciint,
	37	experimental_xqciio,
	38	experimental_xqcilb,
	39	experimental_xqcili,
	40	experimental_xqcilia,
33	41	experimental_xqcilo,
34	42	experimental_xqcilsm,
	43	experimental_xqcisim,
35	44	experimental_xqcisls,
	45	experimental_xqcisync,
	46	experimental_xrivosvisni,
	47	experimental_xrivosvizip,
	48	experimental_xsfmclic,
	49	experimental_xsfsclic,
36	50	experimental_zalasr,
37	51	experimental_zicfilp,
38	52	experimental_zicfiss,
39	53	experimental_zvbc32e,
40	54	experimental_zvkgs,
	55	experimental_zvqdotq,
41	56	f,
42	57	forced_atomics,
43	58	h,
44	59	i,
45	60	ld_add_fusion,
	61	log_vrgather,
46	62	lui_addi_fusion,
47	63	m,
48	64	mips_p8700,
49	65	no_default_unroll,
50		no_rvc_hints,
51	66	no_sink_splat_operands,
52	67	no_trailing_seq_cst_fence,
53	68	optimized_nf2_segment_load_store,
...	...	@@ -59,7 +74,9 @@ pub const Feature = enum {
59	74	optimized_nf8_segment_load_store,
60	75	optimized_zero_stride_load,
61	76	predictable_select_expensive,
	77	prefer_vsetvli_over_read_vlenb,
62	78	prefer_w_inst,
	79	q,
63	80	relax,
64	81	reserve_x1,
65	82	reserve_x10,
...	...	@@ -103,10 +120,13 @@ pub const Feature = enum {
103	120	rvi20u32,
104	121	rvi20u64,
105	122	save_restore,
	123	sdext,
	124	sdtrig,
106	125	sha,
107	126	shcounterenw,
108	127	shgatpa,
109	128	shifted_zextw_fusion,
	129	shlcofideleg,
110	130	short_forward_branch_opt,
111	131	shtvala,
112	132	shvsatpa,
...	...	@@ -114,6 +134,7 @@ pub const Feature = enum {
114	134	shvstvecd,
115	135	smaia,
116	136	smcdeleg,
	137	smcntrpmf,
117	138	smcsrind,
118	139	smdbltrp,
119	140	smepmp,
...	...	@@ -151,7 +172,14 @@ pub const Feature = enum {
151	172	use_postra_scheduler,
152	173	v,
153	174	ventana_veyron,
	175	vl_dependent_latency,
154	176	vxrm_pipeline_flush,
	177	xandesbfhcvt,
	178	xandesperf,
	179	xandesvbfhcvt,
	180	xandesvdot,
	181	xandesvpackfph,
	182	xandesvsintload,
155	183	xcvalu,
156	184	xcvbi,
157	185	xcvbitmanip,
...	...	@@ -159,9 +187,20 @@ pub const Feature = enum {
159	187	xcvmac,
160	188	xcvmem,
161	189	xcvsimd,
162		xmipscmove,
	190	xmipscbop,
	191	xmipscmov,
163	192	xmipslsp,
164	193	xsfcease,
	194	xsfmm128t,
	195	xsfmm16t,
	196	xsfmm32a16f,
	197	xsfmm32a32f,
	198	xsfmm32a8f,
	199	xsfmm32a8i,
	200	xsfmm32t,
	201	xsfmm64a64f,
	202	xsfmm64t,
	203	xsfmmbase,
165	204	xsfvcp,
166	205	xsfvfnrclipxfqf,
167	206	xsfvfwmaccqqq,
...	...	@@ -202,6 +241,7 @@ pub const Feature = enum {
202	241	zcd,
203	242	zce,
204	243	zcf,
	244	zclsd,
205	245	zcmop,
206	246	zcmp,
207	247	zcmt,
...	...	@@ -220,6 +260,7 @@ pub const Feature = enum {
220	260	zicbop,
221	261	zicboz,
222	262	ziccamoa,
	263	ziccamoc,
223	264	ziccif,
224	265	zicclsm,
225	266	ziccrse,
...	...	@@ -230,6 +271,7 @@ pub const Feature = enum {
230	271	zihintntl,
231	272	zihintpause,
232	273	zihpm,
	274	zilsd,
233	275	zimop,
234	276	zk,
235	277	zkn,
...	...	@@ -310,6 +352,11 @@ pub const all_features = blk: {
310	352	.zalrsc,
311	353	}),
312	354	};
	355	result[@intFromEnum(Feature.andes45)] = .{
	356	.llvm_name = "andes45",
	357	.description = "Andes 45-Series processors",
	358	.dependencies = featureSet(&[_]Feature{}),
	359	};
313	360	result[@intFromEnum(Feature.auipc_addi_fusion)] = .{
314	361	.llvm_name = "auipc-addi-fusion",
315	362	.description = "Enable AUIPC+ADDI macrofusion",
...	...	@@ -327,7 +374,9 @@ pub const all_features = blk: {
327	374	result[@intFromEnum(Feature.c)] = .{
328	375	.llvm_name = "c",
329	376	.description = "'C' (Compressed Instructions)",
330		.dependencies = featureSet(&[_]Feature{}),
	377	.dependencies = featureSet(&[_]Feature{
	378	.zca,
	379	}),
331	380	};
332	381	result[@intFromEnum(Feature.conditional_cmv_fusion)] = .{
333	382	.llvm_name = "conditional-cmv-fusion",
...	...	@@ -356,11 +405,21 @@ pub const all_features = blk: {
356	405	.description = "'E' (Embedded Instruction Set with 16 GPRs)",
357	406	.dependencies = featureSet(&[_]Feature{}),
358	407	};
	408	result[@intFromEnum(Feature.exact_asm)] = .{
	409	.llvm_name = "exact-asm",
	410	.description = "Enable Exact Assembly (Disables Compression and Relaxation)",
	411	.dependencies = featureSet(&[_]Feature{}),
	412	};
359	413	result[@intFromEnum(Feature.experimental)] = .{
360	414	.llvm_name = "experimental",
361	415	.description = "Experimental intrinsics",
362	416	.dependencies = featureSet(&[_]Feature{}),
363	417	};
	418	result[@intFromEnum(Feature.experimental_p)] = .{
	419	.llvm_name = "experimental-p",
	420	.description = "'P' ('Base P' (Packed SIMD))",
	421	.dependencies = featureSet(&[_]Feature{}),
	422	};
364	423	result[@intFromEnum(Feature.experimental_rvm23u32)] = .{
365	424	.llvm_name = "experimental-rvm23u32",
366	425	.description = "RISC-V experimental-rvm23u32 profile",
...	...	@@ -378,16 +437,6 @@ pub const all_features = blk: {
378	437	.zimop,
379	438	}),
380	439	};
381		result[@intFromEnum(Feature.experimental_sdext)] = .{
382		.llvm_name = "experimental-sdext",
383		.description = "'Sdext' (External debugger)",
384		.dependencies = featureSet(&[_]Feature{}),
385		};
386		result[@intFromEnum(Feature.experimental_sdtrig)] = .{
387		.llvm_name = "experimental-sdtrig",
388		.description = "'Sdtrig' (Debugger triggers)",
389		.dependencies = featureSet(&[_]Feature{}),
390		};
391	440	result[@intFromEnum(Feature.experimental_smctr)] = .{
392	441	.llvm_name = "experimental-smctr",
393	442	.description = "'Smctr' (Control Transfer Records Machine Level)",
...	...	@@ -407,6 +456,13 @@ pub const all_features = blk: {
407	456	.description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
408	457	.dependencies = featureSet(&[_]Feature{}),
409	458	};
	459	result[@intFromEnum(Feature.experimental_xqccmp)] = .{
	460	.llvm_name = "experimental-xqccmp",
	461	.description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
	462	.dependencies = featureSet(&[_]Feature{
	463	.zca,
	464	}),
	465	};
410	466	result[@intFromEnum(Feature.experimental_xqcia)] = .{
411	467	.llvm_name = "experimental-xqcia",
412	468	.description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
...	...	@@ -419,6 +475,20 @@ pub const all_features = blk: {
419	475	.zca,
420	476	}),
421	477	};
	478	result[@intFromEnum(Feature.experimental_xqcibi)] = .{
	479	.llvm_name = "experimental-xqcibi",
	480	.description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
	481	.dependencies = featureSet(&[_]Feature{
	482	.zca,
	483	}),
	484	};
	485	result[@intFromEnum(Feature.experimental_xqcibm)] = .{
	486	.llvm_name = "experimental-xqcibm",
	487	.description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
	488	.dependencies = featureSet(&[_]Feature{
	489	.zca,
	490	}),
	491	};
422	492	result[@intFromEnum(Feature.experimental_xqcicli)] = .{
423	493	.llvm_name = "experimental-xqcicli",
424	494	.description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
...	...	@@ -448,6 +518,32 @@ pub const all_features = blk: {
448	518	.zca,
449	519	}),
450	520	};
	521	result[@intFromEnum(Feature.experimental_xqciio)] = .{
	522	.llvm_name = "experimental-xqciio",
	523	.description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
	524	.dependencies = featureSet(&[_]Feature{}),
	525	};
	526	result[@intFromEnum(Feature.experimental_xqcilb)] = .{
	527	.llvm_name = "experimental-xqcilb",
	528	.description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
	529	.dependencies = featureSet(&[_]Feature{
	530	.zca,
	531	}),
	532	};
	533	result[@intFromEnum(Feature.experimental_xqcili)] = .{
	534	.llvm_name = "experimental-xqcili",
	535	.description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
	536	.dependencies = featureSet(&[_]Feature{
	537	.zca,
	538	}),
	539	};
	540	result[@intFromEnum(Feature.experimental_xqcilia)] = .{
	541	.llvm_name = "experimental-xqcilia",
	542	.description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
	543	.dependencies = featureSet(&[_]Feature{
	544	.zca,
	545	}),
	546	};
451	547	result[@intFromEnum(Feature.experimental_xqcilo)] = .{
452	548	.llvm_name = "experimental-xqcilo",
453	549	.description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
...	...	@@ -460,11 +556,45 @@ pub const all_features = blk: {
460	556	.description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
461	557	.dependencies = featureSet(&[_]Feature{}),
462	558	};
	559	result[@intFromEnum(Feature.experimental_xqcisim)] = .{
	560	.llvm_name = "experimental-xqcisim",
	561	.description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
	562	.dependencies = featureSet(&[_]Feature{
	563	.zca,
	564	}),
	565	};
463	566	result[@intFromEnum(Feature.experimental_xqcisls)] = .{
464	567	.llvm_name = "experimental-xqcisls",
465	568	.description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
466	569	.dependencies = featureSet(&[_]Feature{}),
467	570	};
	571	result[@intFromEnum(Feature.experimental_xqcisync)] = .{
	572	.llvm_name = "experimental-xqcisync",
	573	.description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
	574	.dependencies = featureSet(&[_]Feature{
	575	.zca,
	576	}),
	577	};
	578	result[@intFromEnum(Feature.experimental_xrivosvisni)] = .{
	579	.llvm_name = "experimental-xrivosvisni",
	580	.description = "'XRivosVisni' (Rivos Vector Integer Small New)",
	581	.dependencies = featureSet(&[_]Feature{}),
	582	};
	583	result[@intFromEnum(Feature.experimental_xrivosvizip)] = .{
	584	.llvm_name = "experimental-xrivosvizip",
	585	.description = "'XRivosVizip' (Rivos Vector Register Zips)",
	586	.dependencies = featureSet(&[_]Feature{}),
	587	};
	588	result[@intFromEnum(Feature.experimental_xsfmclic)] = .{
	589	.llvm_name = "experimental-xsfmclic",
	590	.description = "'XSfmclic' (SiFive CLIC Machine-mode CSRs)",
	591	.dependencies = featureSet(&[_]Feature{}),
	592	};
	593	result[@intFromEnum(Feature.experimental_xsfsclic)] = .{
	594	.llvm_name = "experimental-xsfsclic",
	595	.description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
	596	.dependencies = featureSet(&[_]Feature{}),
	597	};
468	598	result[@intFromEnum(Feature.experimental_zalasr)] = .{
469	599	.llvm_name = "experimental-zalasr",
470	600	.description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
...	...	@@ -499,6 +629,13 @@ pub const all_features = blk: {
499	629	.zvkg,
500	630	}),
501	631	};
	632	result[@intFromEnum(Feature.experimental_zvqdotq)] = .{
	633	.llvm_name = "experimental-zvqdotq",
	634	.description = "'Zvqdotq' (Vector quad widening 4D Dot Product)",
	635	.dependencies = featureSet(&[_]Feature{
	636	.zve32x,
	637	}),
	638	};
502	639	result[@intFromEnum(Feature.f)] = .{
503	640	.llvm_name = "f",
504	641	.description = "'F' (Single-Precision Floating-Point)",
...	...	@@ -526,6 +663,11 @@ pub const all_features = blk: {
526	663	.description = "Enable LD+ADD macrofusion",
527	664	.dependencies = featureSet(&[_]Feature{}),
528	665	};
	666	result[@intFromEnum(Feature.log_vrgather)] = .{
	667	.llvm_name = "log-vrgather",
	668	.description = "Has vrgather.vv with LMUL*log2(LMUL) latency",
	669	.dependencies = featureSet(&[_]Feature{}),
	670	};
529	671	result[@intFromEnum(Feature.lui_addi_fusion)] = .{
530	672	.llvm_name = "lui-addi-fusion",
531	673	.description = "Enable LUI+ADDI macro fusion",
...	...	@@ -548,11 +690,6 @@ pub const all_features = blk: {
548	690	.description = "Disable default unroll preference.",
549	691	.dependencies = featureSet(&[_]Feature{}),
550	692	};
551		result[@intFromEnum(Feature.no_rvc_hints)] = .{
552		.llvm_name = "no-rvc-hints",
553		.description = "Disable RVC Hint Instructions.",
554		.dependencies = featureSet(&[_]Feature{}),
555		};
556	693	result[@intFromEnum(Feature.no_sink_splat_operands)] = .{
557	694	.llvm_name = "no-sink-splat-operands",
558	695	.description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions",
...	...	@@ -565,37 +702,37 @@ pub const all_features = blk: {
565	702	};
566	703	result[@intFromEnum(Feature.optimized_nf2_segment_load_store)] = .{
567	704	.llvm_name = "optimized-nf2-segment-load-store",
568		.description = "vlseg2eN.v and vsseg2eN.v areimplemented as a wide memory op and shuffle",
	705	.description = "vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle",
569	706	.dependencies = featureSet(&[_]Feature{}),
570	707	};
571	708	result[@intFromEnum(Feature.optimized_nf3_segment_load_store)] = .{
572	709	.llvm_name = "optimized-nf3-segment-load-store",
573		.description = "vlseg3eN.v and vsseg3eN.v areimplemented as a wide memory op and shuffle",
	710	.description = "vlseg3eN.v and vsseg3eN.v are implemented as a wide memory op and shuffle",
574	711	.dependencies = featureSet(&[_]Feature{}),
575	712	};
576	713	result[@intFromEnum(Feature.optimized_nf4_segment_load_store)] = .{
577	714	.llvm_name = "optimized-nf4-segment-load-store",
578		.description = "vlseg4eN.v and vsseg4eN.v areimplemented as a wide memory op and shuffle",
	715	.description = "vlseg4eN.v and vsseg4eN.v are implemented as a wide memory op and shuffle",
579	716	.dependencies = featureSet(&[_]Feature{}),
580	717	};
581	718	result[@intFromEnum(Feature.optimized_nf5_segment_load_store)] = .{
582	719	.llvm_name = "optimized-nf5-segment-load-store",
583		.description = "vlseg5eN.v and vsseg5eN.v areimplemented as a wide memory op and shuffle",
	720	.description = "vlseg5eN.v and vsseg5eN.v are implemented as a wide memory op and shuffle",
584	721	.dependencies = featureSet(&[_]Feature{}),
585	722	};
586	723	result[@intFromEnum(Feature.optimized_nf6_segment_load_store)] = .{
587	724	.llvm_name = "optimized-nf6-segment-load-store",
588		.description = "vlseg6eN.v and vsseg6eN.v areimplemented as a wide memory op and shuffle",
	725	.description = "vlseg6eN.v and vsseg6eN.v are implemented as a wide memory op and shuffle",
589	726	.dependencies = featureSet(&[_]Feature{}),
590	727	};
591	728	result[@intFromEnum(Feature.optimized_nf7_segment_load_store)] = .{
592	729	.llvm_name = "optimized-nf7-segment-load-store",
593		.description = "vlseg7eN.v and vsseg7eN.v areimplemented as a wide memory op and shuffle",
	730	.description = "vlseg7eN.v and vsseg7eN.v are implemented as a wide memory op and shuffle",
594	731	.dependencies = featureSet(&[_]Feature{}),
595	732	};
596	733	result[@intFromEnum(Feature.optimized_nf8_segment_load_store)] = .{
597	734	.llvm_name = "optimized-nf8-segment-load-store",
598		.description = "vlseg8eN.v and vsseg8eN.v areimplemented as a wide memory op and shuffle",
	735	.description = "vlseg8eN.v and vsseg8eN.v are implemented as a wide memory op and shuffle",
599	736	.dependencies = featureSet(&[_]Feature{}),
600	737	};
601	738	result[@intFromEnum(Feature.optimized_zero_stride_load)] = .{
...	...	@@ -608,11 +745,23 @@ pub const all_features = blk: {
608	745	.description = "Prefer likely predicted branches over selects",
609	746	.dependencies = featureSet(&[_]Feature{}),
610	747	};
	748	result[@intFromEnum(Feature.prefer_vsetvli_over_read_vlenb)] = .{
	749	.llvm_name = "prefer-vsetvli-over-read-vlenb",
	750	.description = "Prefer vsetvli over read vlenb CSR to calculate VLEN",
	751	.dependencies = featureSet(&[_]Feature{}),
	752	};
611	753	result[@intFromEnum(Feature.prefer_w_inst)] = .{
612	754	.llvm_name = "prefer-w-inst",
613	755	.description = "Prefer instructions with W suffix",
614	756	.dependencies = featureSet(&[_]Feature{}),
615	757	};
	758	result[@intFromEnum(Feature.q)] = .{
	759	.llvm_name = "q",
	760	.description = "'Q' (Quad-Precision Floating-Point)",
	761	.dependencies = featureSet(&[_]Feature{
	762	.d,
	763	}),
	764	};
616	765	result[@intFromEnum(Feature.relax)] = .{
617	766	.llvm_name = "relax",
618	767	.description = "Enable Linker relaxation.",
...	...	@@ -1069,6 +1218,16 @@ pub const all_features = blk: {
1069	1218	.description = "Enable save/restore.",
1070	1219	.dependencies = featureSet(&[_]Feature{}),
1071	1220	};
	1221	result[@intFromEnum(Feature.sdext)] = .{
	1222	.llvm_name = "sdext",
	1223	.description = "'Sdext' (External debugger)",
	1224	.dependencies = featureSet(&[_]Feature{}),
	1225	};
	1226	result[@intFromEnum(Feature.sdtrig)] = .{
	1227	.llvm_name = "sdtrig",
	1228	.description = "'Sdtrig' (Debugger triggers)",
	1229	.dependencies = featureSet(&[_]Feature{}),
	1230	};
1072	1231	result[@intFromEnum(Feature.sha)] = .{
1073	1232	.llvm_name = "sha",
1074	1233	.description = "'Sha' (Augmented Hypervisor)",
...	...	@@ -1098,6 +1257,11 @@ pub const all_features = blk: {
1098	1257	.description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
1099	1258	.dependencies = featureSet(&[_]Feature{}),
1100	1259	};
	1260	result[@intFromEnum(Feature.shlcofideleg)] = .{
	1261	.llvm_name = "shlcofideleg",
	1262	.description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
	1263	.dependencies = featureSet(&[_]Feature{}),
	1264	};
1101	1265	result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
1102	1266	.llvm_name = "short-forward-branch-opt",
1103	1267	.description = "Enable short forward branch optimization",
...	...	@@ -1133,6 +1297,11 @@ pub const all_features = blk: {
1133	1297	.description = "'Smcdeleg' (Counter Delegation Machine Level)",
1134	1298	.dependencies = featureSet(&[_]Feature{}),
1135	1299	};
	1300	result[@intFromEnum(Feature.smcntrpmf)] = .{
	1301	.llvm_name = "smcntrpmf",
	1302	.description = "'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)",
	1303	.dependencies = featureSet(&[_]Feature{}),
	1304	};
1136	1305	result[@intFromEnum(Feature.smcsrind)] = .{
1137	1306	.llvm_name = "smcsrind",
1138	1307	.description = "'Smcsrind' (Indirect CSR Access Machine Level)",
...	...	@@ -1141,7 +1310,9 @@ pub const all_features = blk: {
1141	1310	result[@intFromEnum(Feature.smdbltrp)] = .{
1142	1311	.llvm_name = "smdbltrp",
1143	1312	.description = "'Smdbltrp' (Double Trap Machine Level)",
1144		.dependencies = featureSet(&[_]Feature{}),
	1313	.dependencies = featureSet(&[_]Feature{
	1314	.zicsr,
	1315	}),
1145	1316	};
1146	1317	result[@intFromEnum(Feature.smepmp)] = .{
1147	1318	.llvm_name = "smepmp",
...	...	@@ -1201,7 +1372,9 @@ pub const all_features = blk: {
1201	1372	result[@intFromEnum(Feature.ssdbltrp)] = .{
1202	1373	.llvm_name = "ssdbltrp",
1203	1374	.description = "'Ssdbltrp' (Double Trap Supervisor Level)",
1204		.dependencies = featureSet(&[_]Feature{}),
	1375	.dependencies = featureSet(&[_]Feature{
	1376	.zicsr,
	1377	}),
1205	1378	};
1206	1379	result[@intFromEnum(Feature.ssnpm)] = .{
1207	1380	.llvm_name = "ssnpm",
...	...	@@ -1321,11 +1494,56 @@ pub const all_features = blk: {
1321	1494	.description = "Ventana Veyron-Series processors",
1322	1495	.dependencies = featureSet(&[_]Feature{}),
1323	1496	};
	1497	result[@intFromEnum(Feature.vl_dependent_latency)] = .{
	1498	.llvm_name = "vl-dependent-latency",
	1499	.description = "Latency of vector instructions is dependent on the dynamic value of vl",
	1500	.dependencies = featureSet(&[_]Feature{}),
	1501	};
1324	1502	result[@intFromEnum(Feature.vxrm_pipeline_flush)] = .{
1325	1503	.llvm_name = "vxrm-pipeline-flush",
1326	1504	.description = "VXRM writes causes pipeline flush",
1327	1505	.dependencies = featureSet(&[_]Feature{}),
1328	1506	};
	1507	result[@intFromEnum(Feature.xandesbfhcvt)] = .{
	1508	.llvm_name = "xandesbfhcvt",
	1509	.description = "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)",
	1510	.dependencies = featureSet(&[_]Feature{
	1511	.f,
	1512	}),
	1513	};
	1514	result[@intFromEnum(Feature.xandesperf)] = .{
	1515	.llvm_name = "xandesperf",
	1516	.description = "'XAndesPerf' (Andes Performance Extension)",
	1517	.dependencies = featureSet(&[_]Feature{}),
	1518	};
	1519	result[@intFromEnum(Feature.xandesvbfhcvt)] = .{
	1520	.llvm_name = "xandesvbfhcvt",
	1521	.description = "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)",
	1522	.dependencies = featureSet(&[_]Feature{
	1523	.zve32f,
	1524	}),
	1525	};
	1526	result[@intFromEnum(Feature.xandesvdot)] = .{
	1527	.llvm_name = "xandesvdot",
	1528	.description = "'XAndesVDot' (Andes Vector Dot Product Extension)",
	1529	.dependencies = featureSet(&[_]Feature{
	1530	.zve32x,
	1531	}),
	1532	};
	1533	result[@intFromEnum(Feature.xandesvpackfph)] = .{
	1534	.llvm_name = "xandesvpackfph",
	1535	.description = "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)",
	1536	.dependencies = featureSet(&[_]Feature{
	1537	.f,
	1538	}),
	1539	};
	1540	result[@intFromEnum(Feature.xandesvsintload)] = .{
	1541	.llvm_name = "xandesvsintload",
	1542	.description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
	1543	.dependencies = featureSet(&[_]Feature{
	1544	.zve32x,
	1545	}),
	1546	};
1329	1547	result[@intFromEnum(Feature.xcvalu)] = .{
1330	1548	.llvm_name = "xcvalu",
1331	1549	.description = "'XCValu' (CORE-V ALU Operations)",
...	...	@@ -1361,9 +1579,14 @@ pub const all_features = blk: {
1361	1579	.description = "'XCVsimd' (CORE-V SIMD ALU)",
1362	1580	.dependencies = featureSet(&[_]Feature{}),
1363	1581	};
1364		result[@intFromEnum(Feature.xmipscmove)] = .{
1365		.llvm_name = "xmipscmove",
1366		.description = "'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov))",
	1582	result[@intFromEnum(Feature.xmipscbop)] = .{
	1583	.llvm_name = "xmipscbop",
	1584	.description = "'XMIPSCBOP' (MIPS Software Prefetch)",
	1585	.dependencies = featureSet(&[_]Feature{}),
	1586	};
	1587	result[@intFromEnum(Feature.xmipscmov)] = .{
	1588	.llvm_name = "xmipscmov",
	1589	.description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
1367	1590	.dependencies = featureSet(&[_]Feature{}),
1368	1591	};
1369	1592	result[@intFromEnum(Feature.xmipslsp)] = .{
...	...	@@ -1376,6 +1599,84 @@ pub const all_features = blk: {
1376	1599	.description = "'XSfcease' (SiFive sf.cease Instruction)",
1377	1600	.dependencies = featureSet(&[_]Feature{}),
1378	1601	};
	1602	result[@intFromEnum(Feature.xsfmm128t)] = .{
	1603	.llvm_name = "xsfmm128t",
	1604	.description = "'XSfmm128t' (TE=128 configuration)",
	1605	.dependencies = featureSet(&[_]Feature{
	1606	.xsfmmbase,
	1607	.zvl512b,
	1608	}),
	1609	};
	1610	result[@intFromEnum(Feature.xsfmm16t)] = .{
	1611	.llvm_name = "xsfmm16t",
	1612	.description = "'XSfmm16t' (TE=16 configuration)",
	1613	.dependencies = featureSet(&[_]Feature{
	1614	.xsfmmbase,
	1615	.zvl64b,
	1616	}),
	1617	};
	1618	result[@intFromEnum(Feature.xsfmm32a16f)] = .{
	1619	.llvm_name = "xsfmm32a16f",
	1620	.description = "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))",
	1621	.dependencies = featureSet(&[_]Feature{
	1622	.xsfmmbase,
	1623	.zve32f,
	1624	}),
	1625	};
	1626	result[@intFromEnum(Feature.xsfmm32a32f)] = .{
	1627	.llvm_name = "xsfmm32a32f",
	1628	.description = "'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b)",
	1629	.dependencies = featureSet(&[_]Feature{
	1630	.xsfmmbase,
	1631	.zve32f,
	1632	}),
	1633	};
	1634	result[@intFromEnum(Feature.xsfmm32a8f)] = .{
	1635	.llvm_name = "xsfmm32a8f",
	1636	.description = "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)",
	1637	.dependencies = featureSet(&[_]Feature{
	1638	.xsfmmbase,
	1639	.zve32f,
	1640	}),
	1641	};
	1642	result[@intFromEnum(Feature.xsfmm32a8i)] = .{
	1643	.llvm_name = "xsfmm32a8i",
	1644	.description = "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)",
	1645	.dependencies = featureSet(&[_]Feature{
	1646	.xsfmmbase,
	1647	}),
	1648	};
	1649	result[@intFromEnum(Feature.xsfmm32t)] = .{
	1650	.llvm_name = "xsfmm32t",
	1651	.description = "'XSfmm32t' (TE=32 configuration)",
	1652	.dependencies = featureSet(&[_]Feature{
	1653	.xsfmmbase,
	1654	.zvl128b,
	1655	}),
	1656	};
	1657	result[@intFromEnum(Feature.xsfmm64a64f)] = .{
	1658	.llvm_name = "xsfmm64a64f",
	1659	.description = "'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)",
	1660	.dependencies = featureSet(&[_]Feature{
	1661	.xsfmmbase,
	1662	.zve64d,
	1663	}),
	1664	};
	1665	result[@intFromEnum(Feature.xsfmm64t)] = .{
	1666	.llvm_name = "xsfmm64t",
	1667	.description = "'XSfmm64t' (TE=64 configuration)",
	1668	.dependencies = featureSet(&[_]Feature{
	1669	.xsfmmbase,
	1670	.zvl256b,
	1671	}),
	1672	};
	1673	result[@intFromEnum(Feature.xsfmmbase)] = .{
	1674	.llvm_name = "xsfmmbase",
	1675	.description = "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)",
	1676	.dependencies = featureSet(&[_]Feature{
	1677	.zve32x,
	1678	}),
	1679	};
1379	1680	result[@intFromEnum(Feature.xsfvcp)] = .{
1380	1681	.llvm_name = "xsfvcp",
1381	1682	.description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
...	...	@@ -1392,7 +1693,7 @@ pub const all_features = blk: {
1392	1693	};
1393	1694	result[@intFromEnum(Feature.xsfvfwmaccqqq)] = .{
1394	1695	.llvm_name = "xsfvfwmaccqqq",
1395		.description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
	1696	.description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
1396	1697	.dependencies = featureSet(&[_]Feature{
1397	1698	.zvfbfmin,
1398	1699	}),
...	...	@@ -1486,7 +1787,9 @@ pub const all_features = blk: {
1486	1787	result[@intFromEnum(Feature.xwchc)] = .{
1487	1788	.llvm_name = "xwchc",
1488	1789	.description = "'Xwchc' (WCH/QingKe additional compressed opcodes)",
1489		.dependencies = featureSet(&[_]Feature{}),
	1790	.dependencies = featureSet(&[_]Feature{
	1791	.zca,
	1792	}),
1490	1793	};
1491	1794	result[@intFromEnum(Feature.za128rs)] = .{
1492	1795	.llvm_name = "za128rs",
...	...	@@ -1604,6 +1907,14 @@ pub const all_features = blk: {
1604	1907	.zca,
1605	1908	}),
1606	1909	};
	1910	result[@intFromEnum(Feature.zclsd)] = .{
	1911	.llvm_name = "zclsd",
	1912	.description = "'Zclsd' (Compressed Load/Store Pair Instructions)",
	1913	.dependencies = featureSet(&[_]Feature{
	1914	.zca,
	1915	.zilsd,
	1916	}),
	1917	};
1607	1918	result[@intFromEnum(Feature.zcmop)] = .{
1608	1919	.llvm_name = "zcmop",
1609	1920	.description = "'Zcmop' (Compressed May-Be-Operations)",
...	...	@@ -1717,6 +2028,11 @@ pub const all_features = blk: {
1717	2028	.description = "'Ziccamoa' (Main Memory Supports All Atomics in A)",
1718	2029	.dependencies = featureSet(&[_]Feature{}),
1719	2030	};
	2031	result[@intFromEnum(Feature.ziccamoc)] = .{
	2032	.llvm_name = "ziccamoc",
	2033	.description = "'Ziccamoc' (Main Memory Supports Atomics in Zacas)",
	2034	.dependencies = featureSet(&[_]Feature{}),
	2035	};
1720	2036	result[@intFromEnum(Feature.ziccif)] = .{
1721	2037	.llvm_name = "ziccif",
1722	2038	.description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)",
...	...	@@ -1771,6 +2087,11 @@ pub const all_features = blk: {
1771	2087	.zicsr,
1772	2088	}),
1773	2089	};
	2090	result[@intFromEnum(Feature.zilsd)] = .{
	2091	.llvm_name = "zilsd",
	2092	.description = "'Zilsd' (Load/Store Pair Instructions)",
	2093	.dependencies = featureSet(&[_]Feature{}),
	2094	};
1774	2095	result[@intFromEnum(Feature.zimop)] = .{
1775	2096	.llvm_name = "zimop",
1776	2097	.description = "'Zimop' (May-Be-Operations)",
...	...	@@ -2134,6 +2455,134 @@ pub const all_features = blk: {
2134	2455	};
2135	2456
2136	2457	pub const cpu = struct {
	2458	pub const andes_45_series: CpuModel = .{
	2459	.name = "andes_45_series",
	2460	.llvm_name = "andes-45-series",
	2461	.features = featureSet(&[_]Feature{
	2462	.andes45,
	2463	.no_default_unroll,
	2464	.short_forward_branch_opt,
	2465	.use_postra_scheduler,
	2466	}),
	2467	};
	2468	pub const andes_a25: CpuModel = .{
	2469	.name = "andes_a25",
	2470	.llvm_name = "andes-a25",
	2471	.features = featureSet(&[_]Feature{
	2472	.@"32bit",
	2473	.a,
	2474	.c,
	2475	.d,
	2476	.i,
	2477	.m,
	2478	.xandesperf,
	2479	.zifencei,
	2480	}),
	2481	};
	2482	pub const andes_a45: CpuModel = .{
	2483	.name = "andes_a45",
	2484	.llvm_name = "andes-a45",
	2485	.features = featureSet(&[_]Feature{
	2486	.@"32bit",
	2487	.a,
	2488	.andes45,
	2489	.c,
	2490	.d,
	2491	.i,
	2492	.m,
	2493	.no_default_unroll,
	2494	.short_forward_branch_opt,
	2495	.use_postra_scheduler,
	2496	.xandesperf,
	2497	.zifencei,
	2498	}),
	2499	};
	2500	pub const andes_ax25: CpuModel = .{
	2501	.name = "andes_ax25",
	2502	.llvm_name = "andes-ax25",
	2503	.features = featureSet(&[_]Feature{
	2504	.@"64bit",
	2505	.a,
	2506	.c,
	2507	.d,
	2508	.i,
	2509	.m,
	2510	.xandesperf,
	2511	.zifencei,
	2512	}),
	2513	};
	2514	pub const andes_ax45: CpuModel = .{
	2515	.name = "andes_ax45",
	2516	.llvm_name = "andes-ax45",
	2517	.features = featureSet(&[_]Feature{
	2518	.@"64bit",
	2519	.a,
	2520	.andes45,
	2521	.c,
	2522	.d,
	2523	.i,
	2524	.m,
	2525	.no_default_unroll,
	2526	.short_forward_branch_opt,
	2527	.use_postra_scheduler,
	2528	.xandesperf,
	2529	.zifencei,
	2530	}),
	2531	};
	2532	pub const andes_ax45mpv: CpuModel = .{
	2533	.name = "andes_ax45mpv",
	2534	.llvm_name = "andes-ax45mpv",
	2535	.features = featureSet(&[_]Feature{
	2536	.@"64bit",
	2537	.a,
	2538	.andes45,
	2539	.c,
	2540	.i,
	2541	.m,
	2542	.no_default_unroll,
	2543	.short_forward_branch_opt,
	2544	.use_postra_scheduler,
	2545	.v,
	2546	.xandesperf,
	2547	.zifencei,
	2548	}),
	2549	};
	2550	pub const andes_n45: CpuModel = .{
	2551	.name = "andes_n45",
	2552	.llvm_name = "andes-n45",
	2553	.features = featureSet(&[_]Feature{
	2554	.@"32bit",
	2555	.a,
	2556	.andes45,
	2557	.c,
	2558	.d,
	2559	.i,
	2560	.m,
	2561	.no_default_unroll,
	2562	.short_forward_branch_opt,
	2563	.use_postra_scheduler,
	2564	.xandesperf,
	2565	.zifencei,
	2566	}),
	2567	};
	2568	pub const andes_nx45: CpuModel = .{
	2569	.name = "andes_nx45",
	2570	.llvm_name = "andes-nx45",
	2571	.features = featureSet(&[_]Feature{
	2572	.@"64bit",
	2573	.a,
	2574	.andes45,
	2575	.c,
	2576	.d,
	2577	.i,
	2578	.m,
	2579	.no_default_unroll,
	2580	.short_forward_branch_opt,
	2581	.use_postra_scheduler,
	2582	.xandesperf,
	2583	.zifencei,
	2584	}),
	2585	};
2137	2586	pub const baseline_rv32: CpuModel = .{
2138	2587	.name = "baseline_rv32",
2139	2588	.llvm_name = null,
...	...	@@ -2163,6 +2612,11 @@ pub const cpu = struct {
2163	2612	.llvm_name = "generic",
2164	2613	.features = featureSet(&[_]Feature{}),
2165	2614	};
	2615	pub const generic_ooo: CpuModel = .{
	2616	.name = "generic_ooo",
	2617	.llvm_name = "generic-ooo",
	2618	.features = featureSet(&[_]Feature{}),
	2619	};
2166	2620	pub const generic_rv32: CpuModel = .{
2167	2621	.name = "generic_rv32",
2168	2622	.llvm_name = "generic-rv32",
...	...	@@ -2192,7 +2646,8 @@ pub const cpu = struct {
2192	2646	.i,
2193	2647	.m,
2194	2648	.mips_p8700,
2195		.xmipscmove,
	2649	.xmipscbop,
	2650	.xmipscmov,
2196	2651	.xmipslsp,
2197	2652	.zba,
2198	2653	.zbb,
...	...	@@ -2476,6 +2931,60 @@ pub const cpu = struct {
2476	2931	.zvksg,
2477	2932	}),
2478	2933	};
	2934	pub const sifive_p870: CpuModel = .{
	2935	.name = "sifive_p870",
	2936	.llvm_name = "sifive-p870",
	2937	.features = featureSet(&[_]Feature{
	2938	.@"64bit",
	2939	.a,
	2940	.auipc_addi_fusion,
	2941	.b,
	2942	.c,
	2943	.conditional_cmv_fusion,
	2944	.i,
	2945	.lui_addi_fusion,
	2946	.m,
	2947	.no_default_unroll,
	2948	.no_sink_splat_operands,
	2949	.supm,
	2950	.unaligned_scalar_mem,
	2951	.unaligned_vector_mem,
	2952	.use_postra_scheduler,
	2953	.v,
	2954	.vxrm_pipeline_flush,
	2955	.za64rs,
	2956	.zama16b,
	2957	.zawrs,
	2958	.zcb,
	2959	.zcmop,
	2960	.zfa,
	2961	.zfh,
	2962	.zic64b,
	2963	.zicbom,
	2964	.zicbop,
	2965	.zicboz,
	2966	.ziccamoa,
	2967	.ziccif,
	2968	.zicclsm,
	2969	.ziccrse,
	2970	.zicntr,
	2971	.zicond,
	2972	.zifencei,
	2973	.zihintntl,
	2974	.zihintpause,
	2975	.zihpm,
	2976	.zimop,
	2977	.zkr,
	2978	.zkt,
	2979	.zvbb,
	2980	.zvfbfwma,
	2981	.zvfh,
	2982	.zvknc,
	2983	.zvkng,
	2984	.zvksc,
	2985	.zvksg,
	2986	}),
	2987	};
2479	2988	pub const sifive_s21: CpuModel = .{
2480	2989	.name = "sifive_s21",
2481	2990	.llvm_name = "sifive-s21",
...	...	@@ -2577,6 +3086,7 @@ pub const cpu = struct {
2577	3086	.short_forward_branch_opt,
2578	3087	.use_postra_scheduler,
2579	3088	.v,
	3089	.vl_dependent_latency,
2580	3090	.zba,
2581	3091	.zbb,
2582	3092	.zfh,
...	...	@@ -2585,6 +3095,56 @@ pub const cpu = struct {
2585	3095	.zvl512b,
2586	3096	}),
2587	3097	};
	3098	pub const sifive_x390: CpuModel = .{
	3099	.name = "sifive_x390",
	3100	.llvm_name = "sifive-x390",
	3101	.features = featureSet(&[_]Feature{
	3102	.@"64bit",
	3103	.a,
	3104	.b,
	3105	.c,
	3106	.dlen_factor_2,
	3107	.experimental_zicfilp,
	3108	.experimental_zicfiss,
	3109	.i,
	3110	.m,
	3111	.no_default_unroll,
	3112	.optimized_nf2_segment_load_store,
	3113	.optimized_zero_stride_load,
	3114	.short_forward_branch_opt,
	3115	.use_postra_scheduler,
	3116	.v,
	3117	.vl_dependent_latency,
	3118	.xsifivecdiscarddlone,
	3119	.xsifivecflushdlone,
	3120	.za64rs,
	3121	.zawrs,
	3122	.zcb,
	3123	.zcmop,
	3124	.zfa,
	3125	.zfh,
	3126	.zic64b,
	3127	.zicbom,
	3128	.zicbop,
	3129	.zicboz,
	3130	.ziccamoa,
	3131	.ziccif,
	3132	.ziccrse,
	3133	.zicntr,
	3134	.zicond,
	3135	.zifencei,
	3136	.zihintntl,
	3137	.zihintpause,
	3138	.zihpm,
	3139	.zkr,
	3140	.zkt,
	3141	.zvbb,
	3142	.zvfbfwma,
	3143	.zvfh,
	3144	.zvkt,
	3145	.zvl1024b,
	3146	}),
	3147	};
2588	3148	pub const spacemit_x60: CpuModel = .{
2589	3149	.name = "spacemit_x60",
2590	3150	.llvm_name = "spacemit-x60",
...	...	@@ -2778,6 +3338,7 @@ pub const cpu = struct {
2778	3338	.b,
2779	3339	.c,
2780	3340	.i,
	3341	.log_vrgather,
2781	3342	.m,
2782	3343	.no_default_unroll,
2783	3344	.optimized_zero_stride_load,
...	...	@@ -2864,6 +3425,79 @@ pub const cpu = struct {
2864	3425	.zihpm,
2865	3426	}),
2866	3427	};
	3428	pub const xiangshan_kunminghu: CpuModel = .{
	3429	.name = "xiangshan_kunminghu",
	3430	.llvm_name = "xiangshan-kunminghu",
	3431	.features = featureSet(&[_]Feature{
	3432	.@"64bit",
	3433	.a,
	3434	.b,
	3435	.c,
	3436	.i,
	3437	.m,
	3438	.no_default_unroll,
	3439	.sha,
	3440	.shifted_zextw_fusion,
	3441	.smaia,
	3442	.smcsrind,
	3443	.smdbltrp,
	3444	.smmpm,
	3445	.smnpm,
	3446	.smrnmi,
	3447	.smstateen,
	3448	.ssaia,
	3449	.ssccptr,
	3450	.sscofpmf,
	3451	.sscounterenw,
	3452	.sscsrind,
	3453	.ssdbltrp,
	3454	.ssnpm,
	3455	.sspm,
	3456	.ssstrict,
	3457	.sstc,
	3458	.sstvala,
	3459	.sstvecd,
	3460	.ssu64xl,
	3461	.supm,
	3462	.svade,
	3463	.svbare,
	3464	.svinval,
	3465	.svnapot,
	3466	.svpbmt,
	3467	.v,
	3468	.za64rs,
	3469	.zacas,
	3470	.zawrs,
	3471	.zbc,
	3472	.zcb,
	3473	.zcmop,
	3474	.zexth_fusion,
	3475	.zextw_fusion,
	3476	.zfa,
	3477	.zfh,
	3478	.zic64b,
	3479	.zicbom,
	3480	.zicbop,
	3481	.zicboz,
	3482	.ziccamoa,
	3483	.ziccif,
	3484	.zicclsm,
	3485	.ziccrse,
	3486	.zicntr,
	3487	.zicond,
	3488	.zifencei,
	3489	.zihintntl,
	3490	.zihintpause,
	3491	.zihpm,
	3492	.zimop,
	3493	.zkn,
	3494	.zks,
	3495	.zkt,
	3496	.zvbb,
	3497	.zvfh,
	3498	.zvkt,
	3499	}),
	3500	};
2867	3501	pub const xiangshan_nanhu: CpuModel = .{
2868	3502	.name = "xiangshan_nanhu",
2869	3503	.llvm_name = "xiangshan-nanhu",

lib/std/Target/s390x.zig+52

...	...	@@ -731,6 +731,58 @@ pub const cpu = struct {
731	731	.vector_packed_decimal_enhancement_2,
732	732	}),
733	733	};
	734	pub const z17: CpuModel = .{
	735	.name = "z17",
	736	.llvm_name = "z17",
	737	.features = featureSet(&[_]Feature{
	738	.bear_enhancement,
	739	.concurrent_functions,
	740	.deflate_conversion,
	741	.dfp_packed_conversion,
	742	.dfp_zoned_conversion,
	743	.distinct_ops,
	744	.enhanced_dat_2,
	745	.enhanced_sort,
	746	.execution_hint,
	747	.fast_serialization,
	748	.fp_extension,
	749	.guarded_storage,
	750	.high_word,
	751	.insert_reference_bits_multiple,
	752	.interlocked_access1,
	753	.load_and_trap,
	754	.load_and_zero_rightmost_byte,
	755	.load_store_on_cond,
	756	.load_store_on_cond_2,
	757	.message_security_assist_extension12,
	758	.message_security_assist_extension3,
	759	.message_security_assist_extension4,
	760	.message_security_assist_extension5,
	761	.message_security_assist_extension7,
	762	.message_security_assist_extension8,
	763	.message_security_assist_extension9,
	764	.miscellaneous_extensions,
	765	.miscellaneous_extensions_2,
	766	.miscellaneous_extensions_3,
	767	.miscellaneous_extensions_4,
	768	.nnp_assist,
	769	.population_count,
	770	.processor_activity_instrumentation,
	771	.processor_assist,
	772	.reset_dat_protection,
	773	.reset_reference_bits_multiple,
	774	.test_pending_external_interruption,
	775	.transactional_execution,
	776	.vector,
	777	.vector_enhancements_1,
	778	.vector_enhancements_2,
	779	.vector_enhancements_3,
	780	.vector_packed_decimal,
	781	.vector_packed_decimal_enhancement,
	782	.vector_packed_decimal_enhancement_2,
	783	.vector_packed_decimal_enhancement_3,
	784	}),
	785	};
734	786	pub const z196: CpuModel = .{
735	787	.name = "z196",
736	788	.llvm_name = "z196",

lib/std/Target/sparc.zig+53-16

...	...	@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
	8	crypto,
8	9	deprecated_v8,
9	10	detectroundchange,
10	11	fix_tn0009,
...	...	@@ -22,6 +23,7 @@ pub const Feature = enum {
22	23	leonpwrpsr,
23	24	no_fmuls,
24	25	no_fsmuld,
	26	osa2011,
25	27	popc,
26	28	reserve_g1,
27	29	reserve_g2,
...	...	@@ -53,6 +55,8 @@ pub const Feature = enum {
53	55	slow_rdpc,
54	56	soft_float,
55	57	soft_mul_div,
	58	ua2005,
	59	ua2007,
56	60	v8plus,
57	61	v9,
58	62	vis,
...	...	@@ -69,6 +73,13 @@ pub const all_features = blk: {
69	73	const len = @typeInfo(Feature).@"enum".fields.len;
70	74	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
71	75	var result: [len]CpuFeature = undefined;
	76	result[@intFromEnum(Feature.crypto)] = .{
	77	.llvm_name = "crypto",
	78	.description = "Enable cryptographic extensions",
	79	.dependencies = featureSet(&[_]Feature{
	80	.osa2011,
	81	}),
	82	};
72	83	result[@intFromEnum(Feature.deprecated_v8)] = .{
73	84	.llvm_name = "deprecated-v8",
74	85	.description = "Enable deprecated V8 instructions in V9 mode",
...	...	@@ -154,6 +165,15 @@ pub const all_features = blk: {
154	165	.description = "Disable the fsmuld instruction.",
155	166	.dependencies = featureSet(&[_]Feature{}),
156	167	};
	168	result[@intFromEnum(Feature.osa2011)] = .{
	169	.llvm_name = "osa2011",
	170	.description = "Enable Oracle SPARC Architecture 2011 extensions",
	171	.dependencies = featureSet(&[_]Feature{
	172	.vis,
	173	.vis2,
	174	.vis3,
	175	}),
	176	};
157	177	result[@intFromEnum(Feature.popc)] = .{
158	178	.llvm_name = "popc",
159	179	.description = "Use the popc (population count) instruction",
...	...	@@ -311,6 +331,22 @@ pub const all_features = blk: {
311	331	.description = "Use software emulation for integer multiply and divide",
312	332	.dependencies = featureSet(&[_]Feature{}),
313	333	};
	334	result[@intFromEnum(Feature.ua2005)] = .{
	335	.llvm_name = "ua2005",
	336	.description = "Enable UltraSPARC Architecture 2005 extensions",
	337	.dependencies = featureSet(&[_]Feature{
	338	.vis,
	339	.vis2,
	340	}),
	341	};
	342	result[@intFromEnum(Feature.ua2007)] = .{
	343	.llvm_name = "ua2007",
	344	.description = "Enable UltraSPARC Architecture 2007 extensions",
	345	.dependencies = featureSet(&[_]Feature{
	346	.vis,
	347	.vis2,
	348	}),
	349	};
314	350	result[@intFromEnum(Feature.v8plus)] = .{
315	351	.llvm_name = "v8plus",
316	352	.description = "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code",
...	...	@@ -324,17 +360,23 @@ pub const all_features = blk: {
324	360	result[@intFromEnum(Feature.vis)] = .{
325	361	.llvm_name = "vis",
326	362	.description = "Enable UltraSPARC Visual Instruction Set extensions",
327		.dependencies = featureSet(&[_]Feature{}),
	363	.dependencies = featureSet(&[_]Feature{
	364	.v9,
	365	}),
328	366	};
329	367	result[@intFromEnum(Feature.vis2)] = .{
330	368	.llvm_name = "vis2",
331	369	.description = "Enable Visual Instruction Set extensions II",
332		.dependencies = featureSet(&[_]Feature{}),
	370	.dependencies = featureSet(&[_]Feature{
	371	.v9,
	372	}),
333	373	};
334	374	result[@intFromEnum(Feature.vis3)] = .{
335	375	.llvm_name = "vis3",
336	376	.description = "Enable Visual Instruction Set extensions III",
337		.dependencies = featureSet(&[_]Feature{}),
	377	.dependencies = featureSet(&[_]Feature{
	378	.v9,
	379	}),
338	380	};
339	381	const ti = @typeInfo(Feature);
340	382	for (&result, 0..) \|*elem, i\| {
...	...	@@ -544,9 +586,7 @@ pub const cpu = struct {
544	586	.llvm_name = "niagara",
545	587	.features = featureSet(&[_]Feature{
546	588	.deprecated_v8,
547		.v9,
548		.vis,
549		.vis2,
	589	.ua2005,
550	590	}),
551	591	};
552	592	pub const niagara2: CpuModel = .{
...	...	@@ -555,9 +595,7 @@ pub const cpu = struct {
555	595	.features = featureSet(&[_]Feature{
556	596	.deprecated_v8,
557	597	.popc,
558		.v9,
559		.vis,
560		.vis2,
	598	.ua2005,
561	599	}),
562	600	};
563	601	pub const niagara3: CpuModel = .{
...	...	@@ -566,21 +604,20 @@ pub const cpu = struct {
566	604	.features = featureSet(&[_]Feature{
567	605	.deprecated_v8,
568	606	.popc,
569		.v9,
570		.vis,
571		.vis2,
	607	.ua2005,
	608	.ua2007,
	609	.vis3,
572	610	}),
573	611	};
574	612	pub const niagara4: CpuModel = .{
575	613	.name = "niagara4",
576	614	.llvm_name = "niagara4",
577	615	.features = featureSet(&[_]Feature{
	616	.crypto,
578	617	.deprecated_v8,
579	618	.popc,
580		.v9,
581		.vis,
582		.vis2,
583		.vis3,
	619	.ua2005,
	620	.ua2007,
584	621	}),
585	622	};
586	623	pub const sparclet: CpuModel = .{

lib/std/Target/x86.zig+12-17

...	...	@@ -347,14 +347,14 @@ pub const all_features = blk: {
347	347	.avx512bf16,
348	348	.avx512bitalg,
349	349	.avx512cd,
	350	.avx512dq,
350	351	.avx512fp16,
351	352	.avx512ifma,
352	353	.avx512vbmi,
353	354	.avx512vbmi2,
	355	.avx512vl,
354	356	.avx512vnni,
355	357	.avx512vpopcntdq,
356		.vaes,
357		.vpclmulqdq,
358	358	}),
359	359	};
360	360	result[@intFromEnum(Feature.avx10_1_512)] = .{
...	...	@@ -443,8 +443,6 @@ pub const all_features = blk: {
443	443	.description = "Support 16-bit floating point",
444	444	.dependencies = featureSet(&[_]Feature{
445	445	.avx512bw,
446		.avx512dq,
447		.avx512vl,
448	446	}),
449	447	};
450	448	result[@intFromEnum(Feature.avx512ifma)] = .{
...	...	@@ -1406,7 +1404,6 @@ pub const cpu = struct {
1406	1404	.avxvnni,
1407	1405	.bmi,
1408	1406	.bmi2,
1409		.cldemote,
1410	1407	.clflushopt,
1411	1408	.clwb,
1412	1409	.cmov,
...	...	@@ -1502,7 +1499,6 @@ pub const cpu = struct {
1502	1499	.avxvnniint8,
1503	1500	.bmi,
1504	1501	.bmi2,
1505		.cldemote,
1506	1502	.clflushopt,
1507	1503	.clwb,
1508	1504	.cmov,
...	...	@@ -1579,7 +1575,6 @@ pub const cpu = struct {
1579	1575	.avxvnniint8,
1580	1576	.bmi,
1581	1577	.bmi2,
1582		.cldemote,
1583	1578	.clflushopt,
1584	1579	.clwb,
1585	1580	.cmov,
...	...	@@ -2371,7 +2366,6 @@ pub const cpu = struct {
2371	2366	.vpclmulqdq,
2372	2367	.vzeroupper,
2373	2368	.waitpkg,
2374		.widekl,
2375	2369	.x87,
2376	2370	.xsavec,
2377	2371	.xsaveopt,
...	...	@@ -2565,6 +2559,8 @@ pub const cpu = struct {
2565	2559	.tuning_fast_imm_vector_shift,
2566	2560	.uintr,
2567	2561	.usermsr,
	2562	.vaes,
	2563	.vpclmulqdq,
2568	2564	.vzeroupper,
2569	2565	.waitpkg,
2570	2566	.wbnoinvd,
...	...	@@ -2587,10 +2583,12 @@ pub const cpu = struct {
2587	2583	.avx512bf16,
2588	2584	.avx512bitalg,
2589	2585	.avx512cd,
	2586	.avx512dq,
2590	2587	.avx512fp16,
2591	2588	.avx512ifma,
2592	2589	.avx512vbmi,
2593	2590	.avx512vbmi2,
	2591	.avx512vl,
2594	2592	.avx512vnni,
2595	2593	.avx512vpopcntdq,
2596	2594	.avxvnni,
...	...	@@ -2774,7 +2772,6 @@ pub const cpu = struct {
2774	2772	.avxvnni,
2775	2773	.bmi,
2776	2774	.bmi2,
2777		.cldemote,
2778	2775	.clflushopt,
2779	2776	.clwb,
2780	2777	.cmov,
...	...	@@ -2898,10 +2895,12 @@ pub const cpu = struct {
2898	2895	.avx512bf16,
2899	2896	.avx512bitalg,
2900	2897	.avx512cd,
	2898	.avx512dq,
2901	2899	.avx512fp16,
2902	2900	.avx512ifma,
2903	2901	.avx512vbmi,
2904	2902	.avx512vbmi2,
	2903	.avx512vl,
2905	2904	.avx512vnni,
2906	2905	.avx512vpopcntdq,
2907	2906	.avxvnni,
...	...	@@ -2986,10 +2985,12 @@ pub const cpu = struct {
2986	2985	.avx512bf16,
2987	2986	.avx512bitalg,
2988	2987	.avx512cd,
	2988	.avx512dq,
2989	2989	.avx512fp16,
2990	2990	.avx512ifma,
2991	2991	.avx512vbmi,
2992	2992	.avx512vbmi2,
	2993	.avx512vl,
2993	2994	.avx512vnni,
2994	2995	.avx512vpopcntdq,
2995	2996	.avxvnni,
...	...	@@ -3486,7 +3487,6 @@ pub const cpu = struct {
3486	3487	.avxvnniint8,
3487	3488	.bmi,
3488	3489	.bmi2,
3489		.cldemote,
3490	3490	.clflushopt,
3491	3491	.clwb,
3492	3492	.cmov,
...	...	@@ -3560,7 +3560,6 @@ pub const cpu = struct {
3560	3560	.avxvnni,
3561	3561	.bmi,
3562	3562	.bmi2,
3563		.cldemote,
3564	3563	.clflushopt,
3565	3564	.clwb,
3566	3565	.cmov,
...	...	@@ -3710,7 +3709,6 @@ pub const cpu = struct {
3710	3709	.avxvnniint8,
3711	3710	.bmi,
3712	3711	.bmi2,
3713		.cldemote,
3714	3712	.clflushopt,
3715	3713	.clwb,
3716	3714	.cmov,
...	...	@@ -3768,7 +3766,6 @@ pub const cpu = struct {
3768	3766	.vpclmulqdq,
3769	3767	.vzeroupper,
3770	3768	.waitpkg,
3771		.widekl,
3772	3769	.x87,
3773	3770	.xsavec,
3774	3771	.xsaveopt,
...	...	@@ -3925,7 +3922,6 @@ pub const cpu = struct {
3925	3922	.avxvnni,
3926	3923	.bmi,
3927	3924	.bmi2,
3928		.cldemote,
3929	3925	.clflushopt,
3930	3926	.clwb,
3931	3927	.cmov,
...	...	@@ -4090,10 +4086,12 @@ pub const cpu = struct {
4090	4086	.avx512bf16,
4091	4087	.avx512bitalg,
4092	4088	.avx512cd,
	4089	.avx512dq,
4093	4090	.avx512fp16,
4094	4091	.avx512ifma,
4095	4092	.avx512vbmi,
4096	4093	.avx512vbmi2,
	4094	.avx512vl,
4097	4095	.avx512vnni,
4098	4096	.avx512vpopcntdq,
4099	4097	.avxvnni,
...	...	@@ -4907,7 +4905,6 @@ pub const cpu = struct {
4907	4905	.sahf,
4908	4906	.sbb_dep_breaking,
4909	4907	.sha,
4910		.slow_shld,
4911	4908	.smap,
4912	4909	.smep,
4913	4910	.sse4a,
...	...	@@ -4980,7 +4977,6 @@ pub const cpu = struct {
4980	4977	.sbb_dep_breaking,
4981	4978	.sha,
4982	4979	.shstk,
4983		.slow_shld,
4984	4980	.smap,
4985	4981	.smep,
4986	4982	.sse4a,
...	...	@@ -5058,7 +5054,6 @@ pub const cpu = struct {
5058	5054	.sbb_dep_breaking,
5059	5055	.sha,
5060	5056	.shstk,
5061		.slow_shld,
5062	5057	.smap,
5063	5058	.smep,
5064	5059	.sse4a,

lib/std/Target/xtensa.zig+214

...	...	@@ -5,7 +5,41 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
	8	bool,
	9	clamps,
	10	coprocessor,
	11	dcache,
	12	debug,
8	13	density,
	14	dfpaccel,
	15	div32,
	16	exception,
	17	extendedl32r,
	18	fp,
	19	highpriinterrupts,
	20	highpriinterrupts_level3,
	21	highpriinterrupts_level4,
	22	highpriinterrupts_level5,
	23	highpriinterrupts_level6,
	24	highpriinterrupts_level7,
	25	interrupt,
	26	loop,
	27	mac16,
	28	minmax,
	29	miscsr,
	30	mul16,
	31	mul32,
	32	mul32high,
	33	nsa,
	34	prid,
	35	regprotect,
	36	rvector,
	37	sext,
	38	threadptr,
	39	timers1,
	40	timers2,
	41	timers3,
	42	windowed,
9	43	};
10	44
11	45	pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
...	...	@@ -17,11 +51,191 @@ pub const all_features = blk: {
17	51	const len = @typeInfo(Feature).@"enum".fields.len;
18	52	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19	53	var result: [len]CpuFeature = undefined;
	54	result[@intFromEnum(Feature.bool)] = .{
	55	.llvm_name = "bool",
	56	.description = "Enable Xtensa Boolean extension",
	57	.dependencies = featureSet(&[_]Feature{}),
	58	};
	59	result[@intFromEnum(Feature.clamps)] = .{
	60	.llvm_name = "clamps",
	61	.description = "Enable Xtensa CLAMPS option",
	62	.dependencies = featureSet(&[_]Feature{}),
	63	};
	64	result[@intFromEnum(Feature.coprocessor)] = .{
	65	.llvm_name = "coprocessor",
	66	.description = "Enable Xtensa Coprocessor option",
	67	.dependencies = featureSet(&[_]Feature{}),
	68	};
	69	result[@intFromEnum(Feature.dcache)] = .{
	70	.llvm_name = "dcache",
	71	.description = "Enable Xtensa Data Cache option",
	72	.dependencies = featureSet(&[_]Feature{}),
	73	};
	74	result[@intFromEnum(Feature.debug)] = .{
	75	.llvm_name = "debug",
	76	.description = "Enable Xtensa Debug option",
	77	.dependencies = featureSet(&[_]Feature{}),
	78	};
20	79	result[@intFromEnum(Feature.density)] = .{
21	80	.llvm_name = "density",
22	81	.description = "Enable Density instructions",
23	82	.dependencies = featureSet(&[_]Feature{}),
24	83	};
	84	result[@intFromEnum(Feature.dfpaccel)] = .{
	85	.llvm_name = "dfpaccel",
	86	.description = "Enable Xtensa Double Precision FP acceleration",
	87	.dependencies = featureSet(&[_]Feature{}),
	88	};
	89	result[@intFromEnum(Feature.div32)] = .{
	90	.llvm_name = "div32",
	91	.description = "Enable Xtensa Div32 option",
	92	.dependencies = featureSet(&[_]Feature{}),
	93	};
	94	result[@intFromEnum(Feature.exception)] = .{
	95	.llvm_name = "exception",
	96	.description = "Enable Xtensa Exception option",
	97	.dependencies = featureSet(&[_]Feature{}),
	98	};
	99	result[@intFromEnum(Feature.extendedl32r)] = .{
	100	.llvm_name = "extendedl32r",
	101	.description = "Enable Xtensa Extended L32R option",
	102	.dependencies = featureSet(&[_]Feature{}),
	103	};
	104	result[@intFromEnum(Feature.fp)] = .{
	105	.llvm_name = "fp",
	106	.description = "Enable Xtensa Single FP instructions",
	107	.dependencies = featureSet(&[_]Feature{}),
	108	};
	109	result[@intFromEnum(Feature.highpriinterrupts)] = .{
	110	.llvm_name = "highpriinterrupts",
	111	.description = "Enable Xtensa HighPriInterrupts option",
	112	.dependencies = featureSet(&[_]Feature{}),
	113	};
	114	result[@intFromEnum(Feature.highpriinterrupts_level3)] = .{
	115	.llvm_name = "highpriinterrupts-level3",
	116	.description = "Enable Xtensa HighPriInterrupts Level3",
	117	.dependencies = featureSet(&[_]Feature{
	118	.highpriinterrupts,
	119	}),
	120	};
	121	result[@intFromEnum(Feature.highpriinterrupts_level4)] = .{
	122	.llvm_name = "highpriinterrupts-level4",
	123	.description = "Enable Xtensa HighPriInterrupts Level4",
	124	.dependencies = featureSet(&[_]Feature{
	125	.highpriinterrupts,
	126	}),
	127	};
	128	result[@intFromEnum(Feature.highpriinterrupts_level5)] = .{
	129	.llvm_name = "highpriinterrupts-level5",
	130	.description = "Enable Xtensa HighPriInterrupts Level5",
	131	.dependencies = featureSet(&[_]Feature{
	132	.highpriinterrupts,
	133	}),
	134	};
	135	result[@intFromEnum(Feature.highpriinterrupts_level6)] = .{
	136	.llvm_name = "highpriinterrupts-level6",
	137	.description = "Enable Xtensa HighPriInterrupts Level6",
	138	.dependencies = featureSet(&[_]Feature{
	139	.highpriinterrupts,
	140	}),
	141	};
	142	result[@intFromEnum(Feature.highpriinterrupts_level7)] = .{
	143	.llvm_name = "highpriinterrupts-level7",
	144	.description = "Enable Xtensa HighPriInterrupts Level7",
	145	.dependencies = featureSet(&[_]Feature{
	146	.highpriinterrupts,
	147	}),
	148	};
	149	result[@intFromEnum(Feature.interrupt)] = .{
	150	.llvm_name = "interrupt",
	151	.description = "Enable Xtensa Interrupt option",
	152	.dependencies = featureSet(&[_]Feature{}),
	153	};
	154	result[@intFromEnum(Feature.loop)] = .{
	155	.llvm_name = "loop",
	156	.description = "Enable Xtensa Loop extension",
	157	.dependencies = featureSet(&[_]Feature{}),
	158	};
	159	result[@intFromEnum(Feature.mac16)] = .{
	160	.llvm_name = "mac16",
	161	.description = "Enable Xtensa MAC16 instructions",
	162	.dependencies = featureSet(&[_]Feature{}),
	163	};
	164	result[@intFromEnum(Feature.minmax)] = .{
	165	.llvm_name = "minmax",
	166	.description = "Enable Xtensa MINMAX option",
	167	.dependencies = featureSet(&[_]Feature{}),
	168	};
	169	result[@intFromEnum(Feature.miscsr)] = .{
	170	.llvm_name = "miscsr",
	171	.description = "Enable Xtensa Miscellaneous SR option",
	172	.dependencies = featureSet(&[_]Feature{}),
	173	};
	174	result[@intFromEnum(Feature.mul16)] = .{
	175	.llvm_name = "mul16",
	176	.description = "Enable Xtensa Mul16 option",
	177	.dependencies = featureSet(&[_]Feature{}),
	178	};
	179	result[@intFromEnum(Feature.mul32)] = .{
	180	.llvm_name = "mul32",
	181	.description = "Enable Xtensa Mul32 option",
	182	.dependencies = featureSet(&[_]Feature{}),
	183	};
	184	result[@intFromEnum(Feature.mul32high)] = .{
	185	.llvm_name = "mul32high",
	186	.description = "Enable Xtensa Mul32High option",
	187	.dependencies = featureSet(&[_]Feature{}),
	188	};
	189	result[@intFromEnum(Feature.nsa)] = .{
	190	.llvm_name = "nsa",
	191	.description = "Enable Xtensa NSA option",
	192	.dependencies = featureSet(&[_]Feature{}),
	193	};
	194	result[@intFromEnum(Feature.prid)] = .{
	195	.llvm_name = "prid",
	196	.description = "Enable Xtensa Processor ID option",
	197	.dependencies = featureSet(&[_]Feature{}),
	198	};
	199	result[@intFromEnum(Feature.regprotect)] = .{
	200	.llvm_name = "regprotect",
	201	.description = "Enable Xtensa Region Protection option",
	202	.dependencies = featureSet(&[_]Feature{}),
	203	};
	204	result[@intFromEnum(Feature.rvector)] = .{
	205	.llvm_name = "rvector",
	206	.description = "Enable Xtensa Relocatable Vector option",
	207	.dependencies = featureSet(&[_]Feature{}),
	208	};
	209	result[@intFromEnum(Feature.sext)] = .{
	210	.llvm_name = "sext",
	211	.description = "Enable Xtensa Sign Extend option",
	212	.dependencies = featureSet(&[_]Feature{}),
	213	};
	214	result[@intFromEnum(Feature.threadptr)] = .{
	215	.llvm_name = "threadptr",
	216	.description = "Enable Xtensa THREADPTR option",
	217	.dependencies = featureSet(&[_]Feature{}),
	218	};
	219	result[@intFromEnum(Feature.timers1)] = .{
	220	.llvm_name = "timers1",
	221	.description = "Enable Xtensa Timers 1",
	222	.dependencies = featureSet(&[_]Feature{}),
	223	};
	224	result[@intFromEnum(Feature.timers2)] = .{
	225	.llvm_name = "timers2",
	226	.description = "Enable Xtensa Timers 2",
	227	.dependencies = featureSet(&[_]Feature{}),
	228	};
	229	result[@intFromEnum(Feature.timers3)] = .{
	230	.llvm_name = "timers3",
	231	.description = "Enable Xtensa Timers 3",
	232	.dependencies = featureSet(&[_]Feature{}),
	233	};
	234	result[@intFromEnum(Feature.windowed)] = .{
	235	.llvm_name = "windowed",
	236	.description = "Enable Xtensa Windowed Register option",
	237	.dependencies = featureSet(&[_]Feature{}),
	238	};
25	239	const ti = @typeInfo(Feature);
26	240	for (&result, 0..) \|*elem, i\| {
27	241	elem.index = i;