authorgravatar for tristan.ross@midstall.comTristan Ross <tristan.ross@midstall.com> 2024-02-07 13:44:34-08:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2024-02-19 10:12:17+02:00
log5c25ad0fda23eca4b98aad48d709b3b1b9caf2d6
tree462427de0866a9e6bf3a979cd9490428f2057991
parent7775e46e8179fd1f4e27ca45fc211ac2e23a6969

std.zig.system.linux: detect risc-v

1 files changed, 50 insertions(+), 0 deletions(-)

lib/std/zig/system/linux.zig+50
......@@ -71,6 +71,53 @@ test "cpuinfo: SPARC" {
7171 );
7272}
7373
74const RiscvCpuinfoImpl = struct {
75 model: ?*const Target.Cpu.Model = null,
76
77 const cpu_names = .{
78 .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
79 .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
80 .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
81 .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
82 };
83
84 fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
85 if (mem.eql(u8, key, "uarch")) {
86 inline for (cpu_names) |pair| {
87 if (mem.eql(u8, value, pair[0])) {
88 self.model = pair[1];
89 break;
90 }
91 }
92 return false;
93 }
94
95 return true;
96 }
97
98 fn finalize(self: *const RiscvCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
99 const model = self.model orelse return null;
100 return Target.Cpu{
101 .arch = arch,
102 .model = model,
103 .features = model.features,
104 };
105 }
106};
107
108const RiscvCpuinfoParser = CpuinfoParser(RiscvCpuinfoImpl);
109
110test "cpuinfo: RISC-V" {
111 try testParser(RiscvCpuinfoParser, .riscv64, &Target.riscv.cpu.sifive_u74,
112 \\processor : 0
113 \\hart : 1
114 \\isa : rv64imafdc
115 \\mmu : sv39
116 \\isa-ext :
117 \\uarch : sifive,u74-mc
118 );
119}
120
74121const PowerpcCpuinfoImpl = struct {
75122 model: ?*const Target.Cpu.Model = null,
76123
......@@ -344,6 +391,9 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
344391 .powerpc, .powerpcle, .powerpc64, .powerpc64le => {
345392 return PowerpcCpuinfoParser.parse(current_arch, f.reader()) catch null;
346393 },
394 .riscv64, .riscv32 => {
395 return RiscvCpuinfoParser.parse(current_arch, f.reader()) catch null;
396 },
347397 else => {},
348398 }
349399