Commit 5d260eb573132194e802680803f225404a06b00e | zig

author	Koakuma <koachan@protonmail.com> 2022-05-02 21:56:04+07:00
committer	Koakuma <koachan@protonmail.com> 2022-05-16 22:47:53+07:00
log	5d260eb573132194e802680803f225404a06b00e
tree	cb69d6f44adab99174cd4fd314c5dfbdabbe98f3
parent	2770f9a03464dee1e11134054598a6e07c30a6e4

stage2: sparc64: Implement SPARCv9 subcc

2 files changed, 11 insertions(+), 1 deletions(-)

src
- arch
  - sparc64
    Emit.zig
    bits.zig

src/arch/sparc64/Emit.zig+3-1

src/arch/sparc64/bits.zig+8

...	@@ -1261,6 +1261,14 @@ pub const Instruction = union(enum) {	...	@@ -1261,6 +1261,14 @@ pub const Instruction = union(enum) {
1261	};	1261	};
1262	}	1262	}
1263		1263
		1264	pub fn subcc(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
		1265	return switch (s2) {
		1266	Register => format3a(0b10, 0b01_0100, rs1, rs2, rd),
		1267	i13 => format3b(0b10, 0b01_0100, rs1, rs2, rd),
		1268	else => unreachable,
		1269	};
		1270	}
		1271
1264	pub fn trap(comptime s2: type, cond: ICondition, ccr: CCR, rs1: Register, rs2: s2) Instruction {	1272	pub fn trap(comptime s2: type, cond: ICondition, ccr: CCR, rs1: Register, rs2: s2) Instruction {
1265	// Tcc instructions abuse the rd field to store the conditionals.	1273	// Tcc instructions abuse the rd field to store the conditionals.
1266	return switch (s2) {	1274	return switch (s2) {

...	@@ -81,7 +81,7 @@ pub fn emitMir(	...	@@ -81,7 +81,7 @@ pub fn emitMir(
81	.stx => try emit.mirArithmetic3Op(inst),	81	.stx => try emit.mirArithmetic3Op(inst),
82		82
83	.sub => try emit.mirArithmetic3Op(inst),	83	.sub => try emit.mirArithmetic3Op(inst),
84	.subcc => @panic("TODO implement sparcv9 subcc"),	84	.subcc => try emit.mirArithmetic3Op(inst),
85		85
86	.tcc => try emit.mirTrap(inst),	86	.tcc => try emit.mirTrap(inst),
87	}	87	}
...	@@ -169,6 +169,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {	...	@@ -169,6 +169,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
169	.stw => try emit.writeInstruction(Instruction.stw(i13, rs1, imm, rd)),	169	.stw => try emit.writeInstruction(Instruction.stw(i13, rs1, imm, rd)),
170	.stx => try emit.writeInstruction(Instruction.stx(i13, rs1, imm, rd)),	170	.stx => try emit.writeInstruction(Instruction.stx(i13, rs1, imm, rd)),
171	.sub => try emit.writeInstruction(Instruction.sub(i13, rs1, imm, rd)),	171	.sub => try emit.writeInstruction(Instruction.sub(i13, rs1, imm, rd)),
		172	.subcc => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, rd)),
172	else => unreachable,	173	else => unreachable,
173	}	174	}
174	} else {	175	} else {
...	@@ -188,6 +189,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {	...	@@ -188,6 +189,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
188	.stw => try emit.writeInstruction(Instruction.stw(Register, rs1, rs2, rd)),	189	.stw => try emit.writeInstruction(Instruction.stw(Register, rs1, rs2, rd)),
189	.stx => try emit.writeInstruction(Instruction.stx(Register, rs1, rs2, rd)),	190	.stx => try emit.writeInstruction(Instruction.stx(Register, rs1, rs2, rd)),
190	.sub => try emit.writeInstruction(Instruction.sub(Register, rs1, rs2, rd)),	191	.sub => try emit.writeInstruction(Instruction.sub(Register, rs1, rs2, rd)),
		192	.subcc => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, rd)),
191	else => unreachable,	193	else => unreachable,
192	}	194	}
193	}	195	}