authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-15 09:44:05+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-15 18:21:50+02:00
log5f97652da8881773b823a0730e5791816668528a
treed40b03df8428404724c6eae998d4572623286362
parent5138856a72fc009ec799cb935d9117e3bd72f16a

x64: remove verbose_mir functionality

Originally I thought interleaving AIR with MIR will be useful, however as it stands, I have used it very sporadically, and recently, not at all, and I do not think anyone else is actually using it. If there is a simple error such as a wrong instruction emitted, `objdump` is perfectly capable of narrowing it down, while if there's something more subtle happening, regardless of having `--verbose-mir` functionality or not, you still gotta go via the debugger which offers a better view at interleaved source program with the emitted machine code. Finally, I believe `-femit-asm` when we add it will offer a more generic substitute.

4 files changed, 0 insertions(+), 497 deletions(-)

src/Compilation.zig-3
...@@ -82,7 +82,6 @@ clang_preprocessor_mode: ClangPreprocessorMode,...@@ -82,7 +82,6 @@ clang_preprocessor_mode: ClangPreprocessorMode,
82/// Whether to print clang argvs to stdout.82/// Whether to print clang argvs to stdout.
83verbose_cc: bool,83verbose_cc: bool,
84verbose_air: bool,84verbose_air: bool,
85verbose_mir: bool,
86verbose_llvm_ir: bool,85verbose_llvm_ir: bool,
87verbose_cimport: bool,86verbose_cimport: bool,
88verbose_llvm_cpu_features: bool,87verbose_llvm_cpu_features: bool,
...@@ -775,7 +774,6 @@ pub const InitOptions = struct {...@@ -775,7 +774,6 @@ pub const InitOptions = struct {
775 verbose_cc: bool = false,774 verbose_cc: bool = false,
776 verbose_link: bool = false,775 verbose_link: bool = false,
777 verbose_air: bool = false,776 verbose_air: bool = false,
778 verbose_mir: bool = false,
779 verbose_llvm_ir: bool = false,777 verbose_llvm_ir: bool = false,
780 verbose_cimport: bool = false,778 verbose_cimport: bool = false,
781 verbose_llvm_cpu_features: bool = false,779 verbose_llvm_cpu_features: bool = false,
...@@ -1683,7 +1681,6 @@ pub fn create(gpa: Allocator, options: InitOptions) !*Compilation {...@@ -1683,7 +1681,6 @@ pub fn create(gpa: Allocator, options: InitOptions) !*Compilation {
1683 .clang_preprocessor_mode = options.clang_preprocessor_mode,1681 .clang_preprocessor_mode = options.clang_preprocessor_mode,
1684 .verbose_cc = options.verbose_cc,1682 .verbose_cc = options.verbose_cc,
1685 .verbose_air = options.verbose_air,1683 .verbose_air = options.verbose_air,
1686 .verbose_mir = options.verbose_mir,
1687 .verbose_llvm_ir = options.verbose_llvm_ir,1684 .verbose_llvm_ir = options.verbose_llvm_ir,
1688 .verbose_cimport = options.verbose_cimport,1685 .verbose_cimport = options.verbose_cimport,
1689 .verbose_llvm_cpu_features = options.verbose_llvm_cpu_features,1686 .verbose_llvm_cpu_features = options.verbose_llvm_cpu_features,
src/arch/x86_64/CodeGen.zig-12
...@@ -348,18 +348,6 @@ pub fn generate(...@@ -348,18 +348,6 @@ pub fn generate(
348 else => |e| return e,348 else => |e| return e,
349 };349 };
350350
351 if (builtin.mode == .Debug and bin_file.options.module.?.comp.verbose_mir) {
352 const w = std.io.getStdErr().writer();
353 w.print("# Begin Function MIR: {s}:\n", .{fn_owner_decl.name}) catch {};
354 const PrintMir = @import("PrintMir.zig");
355 const print = PrintMir{
356 .mir = mir,
357 .bin_file = bin_file,
358 };
359 print.printMir(w, function.mir_to_air_map, air) catch {}; // we don't care if the debug printing fails
360 w.print("# End Function MIR: {s}\n\n", .{fn_owner_decl.name}) catch {};
361 }
362
363 if (function.err_msg) |em| {351 if (function.err_msg) |em| {
364 return FnResult{ .fail = em };352 return FnResult{ .fail = em };
365 } else {353 } else {
src/arch/x86_64/PrintMir.zig deleted-478
...@@ -1,478 +0,0 @@
1//! This file contains the functionality for print x86_64 MIR in a debug way, interleaved with AIR
2
3const Print = @This();
4
5const std = @import("std");
6const assert = std.debug.assert;
7const bits = @import("bits.zig");
8const abi = @import("abi.zig");
9const leb128 = std.leb;
10const link = @import("../../link.zig");
11const log = std.log.scoped(.codegen);
12const math = std.math;
13const mem = std.mem;
14
15const Air = @import("../../Air.zig");
16const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
17const DW = std.dwarf;
18const Encoder = bits.Encoder;
19const ErrorMsg = Module.ErrorMsg;
20const MCValue = @import("CodeGen.zig").MCValue;
21const Mir = @import("Mir.zig");
22const Module = @import("../../Module.zig");
23const Instruction = bits.Instruction;
24const Register = bits.Register;
25const Type = @import("../../type.zig").Type;
26const fmtIntSizeBin = std.fmt.fmtIntSizeBin;
27
28mir: Mir,
29bin_file: *link.File,
30
31pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index), air: Air) !void {
32 const instruction_bytes = print.mir.instructions.len *
33 // Here we don't use @sizeOf(Mir.Inst.Data) because it would include
34 // the debug safety tag but we want to measure release size.
35 (@sizeOf(Mir.Inst.Tag) + 2 + 8);
36 const extra_bytes = print.mir.extra.len * @sizeOf(u32);
37 const total_bytes = @sizeOf(Mir) + instruction_bytes + extra_bytes;
38
39 // zig fmt: off
40 std.debug.print(
41 \\# Total MIR bytes: {}
42 \\# MIR Instructions: {d} ({})
43 \\# MIR Extra Data: {d} ({})
44 \\
45 , .{
46 fmtIntSizeBin(total_bytes),
47 print.mir.instructions.len, fmtIntSizeBin(instruction_bytes),
48 print.mir.extra.len, fmtIntSizeBin(extra_bytes),
49 });
50 // zig fmt: on
51 const mir_tags = print.mir.instructions.items(.tag);
52
53 for (mir_tags) |tag, index| {
54 const inst = @intCast(u32, index);
55 if (mir_to_air_map.get(inst)) |air_index| {
56 try w.print("air index %{} ({}) for following mir inst(s)\n", .{ air_index, air.instructions.items(.tag)[air_index] });
57 }
58 try w.writeAll(" ");
59 switch (tag) {
60 .adc => try print.mirArith(.adc, inst, w),
61 .add => try print.mirArith(.add, inst, w),
62 .sub => try print.mirArith(.sub, inst, w),
63 .xor => try print.mirArith(.xor, inst, w),
64 .@"and" => try print.mirArith(.@"and", inst, w),
65 .@"or" => try print.mirArith(.@"or", inst, w),
66 .sbb => try print.mirArith(.sbb, inst, w),
67 .cmp => try print.mirArith(.cmp, inst, w),
68 .mov => try print.mirArith(.mov, inst, w),
69
70 .adc_mem_imm => try print.mirArithMemImm(.adc, inst, w),
71 .add_mem_imm => try print.mirArithMemImm(.add, inst, w),
72 .sub_mem_imm => try print.mirArithMemImm(.sub, inst, w),
73 .xor_mem_imm => try print.mirArithMemImm(.xor, inst, w),
74 .and_mem_imm => try print.mirArithMemImm(.@"and", inst, w),
75 .or_mem_imm => try print.mirArithMemImm(.@"or", inst, w),
76 .sbb_mem_imm => try print.mirArithMemImm(.sbb, inst, w),
77 .cmp_mem_imm => try print.mirArithMemImm(.cmp, inst, w),
78 .mov_mem_imm => try print.mirArithMemImm(.mov, inst, w),
79
80 .adc_scale_src => try print.mirArithScaleSrc(.adc, inst, w),
81 .add_scale_src => try print.mirArithScaleSrc(.add, inst, w),
82 .sub_scale_src => try print.mirArithScaleSrc(.sub, inst, w),
83 .xor_scale_src => try print.mirArithScaleSrc(.xor, inst, w),
84 .and_scale_src => try print.mirArithScaleSrc(.@"and", inst, w),
85 .or_scale_src => try print.mirArithScaleSrc(.@"or", inst, w),
86 .sbb_scale_src => try print.mirArithScaleSrc(.sbb, inst, w),
87 .cmp_scale_src => try print.mirArithScaleSrc(.cmp, inst, w),
88 .mov_scale_src => try print.mirArithScaleSrc(.mov, inst, w),
89
90 .adc_scale_dst => try print.mirArithScaleDst(.adc, inst, w),
91 .add_scale_dst => try print.mirArithScaleDst(.add, inst, w),
92 .sub_scale_dst => try print.mirArithScaleDst(.sub, inst, w),
93 .xor_scale_dst => try print.mirArithScaleDst(.xor, inst, w),
94 .and_scale_dst => try print.mirArithScaleDst(.@"and", inst, w),
95 .or_scale_dst => try print.mirArithScaleDst(.@"or", inst, w),
96 .sbb_scale_dst => try print.mirArithScaleDst(.sbb, inst, w),
97 .cmp_scale_dst => try print.mirArithScaleDst(.cmp, inst, w),
98 .mov_scale_dst => try print.mirArithScaleDst(.mov, inst, w),
99
100 .adc_scale_imm => try print.mirArithScaleImm(.adc, inst, w),
101 .add_scale_imm => try print.mirArithScaleImm(.add, inst, w),
102 .sub_scale_imm => try print.mirArithScaleImm(.sub, inst, w),
103 .xor_scale_imm => try print.mirArithScaleImm(.xor, inst, w),
104 .and_scale_imm => try print.mirArithScaleImm(.@"and", inst, w),
105 .or_scale_imm => try print.mirArithScaleImm(.@"or", inst, w),
106 .sbb_scale_imm => try print.mirArithScaleImm(.sbb, inst, w),
107 .cmp_scale_imm => try print.mirArithScaleImm(.cmp, inst, w),
108 .mov_scale_imm => try print.mirArithScaleImm(.mov, inst, w),
109
110 .adc_mem_index_imm => try print.mirArithMemIndexImm(.adc, inst, w),
111 .add_mem_index_imm => try print.mirArithMemIndexImm(.add, inst, w),
112 .sub_mem_index_imm => try print.mirArithMemIndexImm(.sub, inst, w),
113 .xor_mem_index_imm => try print.mirArithMemIndexImm(.xor, inst, w),
114 .and_mem_index_imm => try print.mirArithMemIndexImm(.@"and", inst, w),
115 .or_mem_index_imm => try print.mirArithMemIndexImm(.@"or", inst, w),
116 .sbb_mem_index_imm => try print.mirArithMemIndexImm(.sbb, inst, w),
117 .cmp_mem_index_imm => try print.mirArithMemIndexImm(.cmp, inst, w),
118 .mov_mem_index_imm => try print.mirArithMemIndexImm(.mov, inst, w),
119
120 .movabs => try print.mirMovabs(inst, w),
121
122 .lea => try print.mirLea(inst, w),
123 .lea_pie => try print.mirLeaPie(inst, w),
124
125 .imul_complex => try print.mirIMulComplex(inst, w),
126
127 .push => try print.mirPushPop(.push, inst, w),
128 .pop => try print.mirPushPop(.pop, inst, w),
129
130 .jmp => try print.mirJmpCall(.jmp, inst, w),
131 .call => try print.mirJmpCall(.call, inst, w),
132
133 .cond_jmp_greater_less => try print.mirCondJmp(.cond_jmp_greater_less, inst, w),
134 .cond_jmp_above_below => try print.mirCondJmp(.cond_jmp_above_below, inst, w),
135 .cond_jmp_eq_ne => try print.mirCondJmp(.cond_jmp_eq_ne, inst, w),
136
137 .cond_set_byte_greater_less => try print.mirCondSetByte(.cond_set_byte_greater_less, inst, w),
138 .cond_set_byte_above_below => try print.mirCondSetByte(.cond_set_byte_above_below, inst, w),
139 .cond_set_byte_eq_ne => try print.mirCondSetByte(.cond_set_byte_eq_ne, inst, w),
140
141 .@"test" => try print.mirTest(inst, w),
142
143 .brk => try w.writeAll("brk\n"),
144 .ret => try w.writeAll("ret\n"),
145 .nop => try w.writeAll("nop\n"),
146 .syscall => try w.writeAll("syscall\n"),
147
148 .call_extern => try print.mirCallExtern(inst, w),
149
150 .dbg_line, .dbg_prologue_end, .dbg_epilogue_begin => try w.print("{s}\n", .{@tagName(tag)}),
151
152 .push_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.push, inst, w),
153 .pop_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.pop, inst, w),
154
155 else => {
156 try w.print("TODO emit asm for {s}\n", .{@tagName(tag)});
157 },
158 }
159 }
160}
161
162fn mirPushPop(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
163 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
164 switch (ops.flags) {
165 0b00 => {
166 // PUSH/POP reg
167 try w.print("{s} {s}", .{ @tagName(tag), @tagName(ops.reg1) });
168 },
169 0b01 => {
170 // PUSH/POP r/m64
171 const imm = print.mir.instructions.items(.data)[inst].imm;
172 try w.print("{s} [{s} + {d}]", .{ @tagName(tag), @tagName(ops.reg1), imm });
173 },
174 0b10 => {
175 const imm = print.mir.instructions.items(.data)[inst].imm;
176 // PUSH imm32
177 assert(tag == .push);
178 try w.print("{s} {d}", .{ @tagName(tag), imm });
179 },
180 0b11 => unreachable,
181 }
182 try w.writeByte('\n');
183}
184fn mirPushPopRegsFromCalleePreservedRegs(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
185 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
186 const payload = print.mir.instructions.items(.data)[inst].payload;
187 const data = print.mir.extraData(Mir.RegsToPushOrPop, payload).data;
188 const regs = data.regs;
189 var disp: u32 = data.disp + 8;
190 if (regs == 0) return w.writeAll("no regs from callee_preserved_regs\n");
191 var printed_first_reg = false;
192 for (abi.callee_preserved_regs) |reg, i| {
193 if ((regs >> @intCast(u5, i)) & 1 == 0) continue;
194 if (printed_first_reg) try w.writeAll(" ");
195 printed_first_reg = true;
196 if (tag == .push) {
197 try w.print("mov qword ptr [{s} + {d}], {s}", .{
198 @tagName(ops.reg1),
199 @bitCast(u32, -@intCast(i32, disp)),
200 @tagName(reg.to64()),
201 });
202 } else {
203 try w.print("mov {s}, qword ptr [{s} + {d}]", .{
204 @tagName(reg.to64()),
205 @tagName(ops.reg1),
206 @bitCast(u32, -@intCast(i32, disp)),
207 });
208 }
209 disp += 8;
210 try w.writeByte('\n');
211 }
212}
213
214fn mirJmpCall(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
215 try w.print("{s} ", .{@tagName(tag)});
216 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
217 const flag = @truncate(u1, ops.flags);
218 if (flag == 0) {
219 return w.writeAll("TODO target\n");
220 }
221 if (ops.reg1 == .none) {
222 // JMP/CALL [imm]
223 const imm = print.mir.instructions.items(.data)[inst].imm;
224 try w.print("[{x}]\n", .{imm});
225 return;
226 }
227 // JMP/CALL reg
228 try w.print("{s}\n", .{@tagName(ops.reg1)});
229}
230
231fn mirCondJmp(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
232 _ = print;
233 _ = tag;
234 _ = inst;
235 try w.writeAll("TODO print mirCondJmp\n");
236}
237
238fn mirCondSetByte(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
239 _ = tag;
240 _ = inst;
241 _ = print;
242 try w.writeAll("TODO print mirCondSetByte\n");
243}
244
245fn mirTest(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
246 _ = print;
247 _ = inst;
248 try w.writeAll("TODO print mirTest\n");
249}
250
251fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
252 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
253 try w.writeAll(@tagName(tag));
254 try w.writeByte(' ');
255 switch (ops.flags) {
256 0b00 => {
257 if (ops.reg2 == .none) {
258 const imm = print.mir.instructions.items(.data)[inst].imm;
259 try w.print("{s}, {d}", .{ @tagName(ops.reg1), imm });
260 } else try w.print("{s}, {s}", .{ @tagName(ops.reg1), @tagName(ops.reg2) });
261 },
262 0b01 => {
263 const imm = print.mir.instructions.items(.data)[inst].imm;
264 if (ops.reg2 == .none) {
265 try w.print("{s}, ", .{@tagName(ops.reg1)});
266 switch (ops.reg1.size()) {
267 8 => try w.print("byte ptr ", .{}),
268 16 => try w.print("word ptr ", .{}),
269 32 => try w.print("dword ptr ", .{}),
270 64 => try w.print("qword ptr ", .{}),
271 else => unreachable,
272 }
273 try w.print("[ds:{d}]", .{imm});
274 } else {
275 try w.print("{s}, ", .{@tagName(ops.reg1)});
276 switch (ops.reg1.size()) {
277 8 => try w.print("byte ptr ", .{}),
278 16 => try w.print("word ptr ", .{}),
279 32 => try w.print("dword ptr ", .{}),
280 64 => try w.print("qword ptr ", .{}),
281 else => unreachable,
282 }
283 try w.print("[{s} + {d}]", .{ @tagName(ops.reg2), imm });
284 }
285 },
286 0b10 => {
287 const imm = print.mir.instructions.items(.data)[inst].imm;
288 if (ops.reg2 == .none) {
289 try w.writeAll("unused variant");
290 } else {
291 switch (ops.reg2.size()) {
292 8 => try w.print("byte ptr ", .{}),
293 16 => try w.print("word ptr ", .{}),
294 32 => try w.print("dword ptr ", .{}),
295 64 => try w.print("qword ptr ", .{}),
296 else => unreachable,
297 }
298 try w.print("[{s} + {d}], {s}", .{ @tagName(ops.reg1), imm, @tagName(ops.reg2) });
299 }
300 },
301 0b11 => {
302 try w.writeAll("unused variant");
303 },
304 }
305 try w.writeByte('\n');
306}
307
308fn mirArithMemImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
309 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
310 const payload = print.mir.instructions.items(.data)[inst].payload;
311 const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
312 try w.print("{s} ", .{@tagName(tag)});
313 switch (ops.flags) {
314 0b00 => try w.print("byte ptr ", .{}),
315 0b01 => try w.print("word ptr ", .{}),
316 0b10 => try w.print("dword ptr ", .{}),
317 0b11 => try w.print("qword ptr ", .{}),
318 }
319 try w.print("[{s} + {d}], {d}\n", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
320}
321
322fn mirArithScaleSrc(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
323 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
324 const scale = ops.flags;
325 // OP reg1, [reg2 + scale*rcx + imm32]
326 const imm = print.mir.instructions.items(.data)[inst].imm;
327 try w.print("{s} {s}, [{s} + {d}*rcx + {d}]\n", .{ @tagName(tag), @tagName(ops.reg1), @tagName(ops.reg2), scale, imm });
328}
329
330fn mirArithScaleDst(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
331 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
332 const scale = ops.flags;
333 const imm = print.mir.instructions.items(.data)[inst].imm;
334
335 if (ops.reg2 == .none) {
336 // OP [reg1 + scale*rax + 0], imm32
337 try w.print("{s} [{s} + {d}*rax + 0], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm });
338 }
339
340 // OP [reg1 + scale*rax + imm32], reg2
341 try w.print("{s} [{s} + {d}*rax + {d}], {s}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm, @tagName(ops.reg2) });
342}
343
344fn mirArithScaleImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
345 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
346 const scale = ops.flags;
347 const payload = print.mir.instructions.items(.data)[inst].payload;
348 const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
349 try w.print("{s} [{s} + {d}*rax + {d}], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm_pair.dest_off, imm_pair.operand });
350}
351
352fn mirArithMemIndexImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
353 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
354 const payload = print.mir.instructions.items(.data)[inst].payload;
355 const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
356 try w.print("{s} ", .{@tagName(tag)});
357 switch (ops.flags) {
358 0b00 => try w.print("byte ptr ", .{}),
359 0b01 => try w.print("word ptr ", .{}),
360 0b10 => try w.print("dword ptr ", .{}),
361 0b11 => try w.print("qword ptr ", .{}),
362 }
363 try w.print("[{s} + 1*rax + {d}], {d}\n", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
364}
365
366fn mirMovabs(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
367 const tag = print.mir.instructions.items(.tag)[inst];
368 assert(tag == .movabs);
369 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
370
371 const is_64 = ops.reg1.size() == 64;
372 const imm: i128 = if (is_64) blk: {
373 const payload = print.mir.instructions.items(.data)[inst].payload;
374 const imm64 = print.mir.extraData(Mir.Imm64, payload).data;
375 break :blk imm64.decode();
376 } else print.mir.instructions.items(.data)[inst].imm;
377 if (ops.flags == 0b00) {
378 // movabs reg, imm64
379 try w.print("movabs {s}, {d}\n", .{ @tagName(ops.reg1), imm });
380 }
381 if (ops.reg1 == .none) {
382 try w.writeAll("movabs moffs64, rax\n");
383 } else {
384 // movabs rax, moffs64
385 try w.writeAll("movabs rax, moffs64\n");
386 }
387}
388
389fn mirIMulComplex(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
390 const tag = print.mir.instructions.items(.tag)[inst];
391 assert(tag == .imul_complex);
392 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
393 switch (ops.flags) {
394 0b00 => {
395 try w.print("imul {s}, {s}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2) });
396 },
397 0b10 => {
398 const imm = print.mir.instructions.items(.data)[inst].imm;
399 try w.print("imul {s}, {s}, {d}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
400 },
401 else => return w.writeAll("TODO implement imul\n"),
402 }
403}
404
405fn mirLea(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
406 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
407 try w.writeAll("lea ");
408 switch (ops.flags) {
409 0b00 => {
410 const imm = print.mir.instructions.items(.data)[inst].imm;
411 try w.print("{s} [", .{@tagName(ops.reg1)});
412 if (ops.reg2 != .none) {
413 try w.print("{s} + ", .{@tagName(ops.reg2)});
414 } else {
415 try w.print("ds:", .{});
416 }
417 try w.print("{d}]", .{imm});
418 },
419 0b01 => {
420 try w.print("{s}, ", .{@tagName(ops.reg1)});
421 switch (ops.reg1.size()) {
422 8 => try w.print("byte ptr ", .{}),
423 16 => try w.print("word ptr ", .{}),
424 32 => try w.print("dword ptr ", .{}),
425 64 => try w.print("qword ptr ", .{}),
426 else => unreachable,
427 }
428 try w.print("[rip + 0x0] ", .{});
429 const payload = print.mir.instructions.items(.data)[inst].payload;
430 const imm = print.mir.extraData(Mir.Imm64, payload).data.decode();
431 try w.print("target@{x}", .{imm});
432 },
433 0b10 => {
434 const imm = print.mir.instructions.items(.data)[inst].imm;
435 try w.print("{s}, ", .{@tagName(ops.reg1)});
436 switch (ops.reg1.size()) {
437 8 => try w.print("byte ptr ", .{}),
438 16 => try w.print("word ptr ", .{}),
439 32 => try w.print("dword ptr ", .{}),
440 64 => try w.print("qword ptr ", .{}),
441 else => unreachable,
442 }
443 try w.print("[rbp + rcx + {d}]", .{imm});
444 },
445 0b11 => {
446 try w.writeAll("unused variant");
447 },
448 }
449 try w.writeAll("\n");
450}
451
452fn mirLeaPie(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
453 const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
454 const load_reloc = print.mir.instructions.items(.data)[inst].load_reloc;
455 try w.print("lea {s}, ", .{@tagName(ops.reg1)});
456 switch (ops.reg1.size()) {
457 8 => try w.print("byte ptr ", .{}),
458 16 => try w.print("word ptr ", .{}),
459 32 => try w.print("dword ptr ", .{}),
460 64 => try w.print("qword ptr ", .{}),
461 else => unreachable,
462 }
463 try w.print("[rip + 0x0] ", .{});
464 if (print.bin_file.cast(link.File.MachO)) |macho_file| {
465 const target = macho_file.locals.items[load_reloc.sym_index];
466 const target_name = macho_file.getString(target.n_strx);
467 try w.print("target@{s}", .{target_name});
468 } else {
469 try w.print("TODO lea PIE for other backends", .{});
470 }
471 return w.writeByte('\n');
472}
473
474fn mirCallExtern(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
475 _ = print;
476 _ = inst;
477 return w.writeAll("TODO call_extern");
478}
src/main.zig-4
...@@ -594,7 +594,6 @@ fn buildOutputType(...@@ -594,7 +594,6 @@ fn buildOutputType(
594 var verbose_link = std.process.hasEnvVarConstant("ZIG_VERBOSE_LINK");594 var verbose_link = std.process.hasEnvVarConstant("ZIG_VERBOSE_LINK");
595 var verbose_cc = std.process.hasEnvVarConstant("ZIG_VERBOSE_CC");595 var verbose_cc = std.process.hasEnvVarConstant("ZIG_VERBOSE_CC");
596 var verbose_air = false;596 var verbose_air = false;
597 var verbose_mir = false;
598 var verbose_llvm_ir = false;597 var verbose_llvm_ir = false;
599 var verbose_cimport = false;598 var verbose_cimport = false;
600 var verbose_llvm_cpu_features = false;599 var verbose_llvm_cpu_features = false;
...@@ -1233,8 +1232,6 @@ fn buildOutputType(...@@ -1233,8 +1232,6 @@ fn buildOutputType(
1233 verbose_cc = true;1232 verbose_cc = true;
1234 } else if (mem.eql(u8, arg, "--verbose-air")) {1233 } else if (mem.eql(u8, arg, "--verbose-air")) {
1235 verbose_air = true;1234 verbose_air = true;
1236 } else if (mem.eql(u8, arg, "--verbose-mir")) {
1237 verbose_mir = true;
1238 } else if (mem.eql(u8, arg, "--verbose-llvm-ir")) {1235 } else if (mem.eql(u8, arg, "--verbose-llvm-ir")) {
1239 verbose_llvm_ir = true;1236 verbose_llvm_ir = true;
1240 } else if (mem.eql(u8, arg, "--verbose-cimport")) {1237 } else if (mem.eql(u8, arg, "--verbose-cimport")) {
...@@ -2720,7 +2717,6 @@ fn buildOutputType(...@@ -2720,7 +2717,6 @@ fn buildOutputType(
2720 .verbose_cc = verbose_cc,2717 .verbose_cc = verbose_cc,
2721 .verbose_link = verbose_link,2718 .verbose_link = verbose_link,
2722 .verbose_air = verbose_air,2719 .verbose_air = verbose_air,
2723 .verbose_mir = verbose_mir,
2724 .verbose_llvm_ir = verbose_llvm_ir,2720 .verbose_llvm_ir = verbose_llvm_ir,
2725 .verbose_cimport = verbose_cimport,2721 .verbose_cimport = verbose_cimport,
2726 .verbose_llvm_cpu_features = verbose_llvm_cpu_features,2722 .verbose_llvm_cpu_features = verbose_llvm_cpu_features,