| ... | ... | @@ -5404,6 +5404,7 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In |
| 5404 | 5404 | |
| 5405 | 5405 | const limb_abi_size: u16 = @min(ptr_info.packed_offset.host_size, 8); |
| 5406 | 5406 | const limb_abi_bits = limb_abi_size * 8; |
| 5407 | const limb_ty = try mod.intType(.unsigned, limb_abi_bits); |
| 5407 | 5408 | |
| 5408 | 5409 | const src_bit_size = src_ty.bitSize(mod); |
| 5409 | 5410 | const src_byte_off = @as(i32, @intCast(ptr_info.packed_offset.bit_offset / limb_abi_bits * limb_abi_size)); |
| ... | ... | @@ -5443,23 +5444,23 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In |
| 5443 | 5444 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 5444 | 5445 | defer self.register_manager.unlockReg(tmp_lock); |
| 5445 | 5446 | |
| 5446 | | try self.genSetReg(tmp_reg, src_ty, src_mcv); |
| 5447 | try self.genSetReg(tmp_reg, limb_ty, src_mcv); |
| 5447 | 5448 | switch (limb_i) { |
| 5448 | 5449 | 0 => try self.genShiftBinOpMir( |
| 5449 | 5450 | .{ ._l, .sh }, |
| 5450 | | src_ty, |
| 5451 | limb_ty, |
| 5451 | 5452 | tmp_mcv, |
| 5452 | 5453 | .{ .immediate = src_bit_off }, |
| 5453 | 5454 | ), |
| 5454 | 5455 | 1 => try self.genShiftBinOpMir( |
| 5455 | 5456 | .{ ._r, .sh }, |
| 5456 | | src_ty, |
| 5457 | limb_ty, |
| 5457 | 5458 | tmp_mcv, |
| 5458 | 5459 | .{ .immediate = limb_abi_bits - src_bit_off }, |
| 5459 | 5460 | ), |
| 5460 | 5461 | else => unreachable, |
| 5461 | 5462 | } |
| 5462 | | try self.genBinOpMir(.{ ._, .@"and" }, src_ty, tmp_mcv, .{ .immediate = part_mask }); |
| 5463 | try self.genBinOpMir(.{ ._, .@"and" }, limb_ty, tmp_mcv, .{ .immediate = part_mask }); |
| 5463 | 5464 | try self.asmMemoryRegister( |
| 5464 | 5465 | .{ ._, .@"or" }, |
| 5465 | 5466 | limb_mem, |