| ... | ... | @@ -21,7 +21,7 @@ pub const cpu_models = struct { |
| 21 | 21 | }; |
| 22 | 22 | |
| 23 | 23 | // implementer = 0x41 |
| 24 | | const ARM = [_]E{ |
| 24 | const Arm = [_]E{ |
| 25 | 25 | E{ .part = 0x926, .m32 = &A32.arm926ej_s }, |
| 26 | 26 | E{ .part = 0xb02, .m32 = &A32.mpcore }, |
| 27 | 27 | E{ .part = 0xb36, .m32 = &A32.arm1136j_s }, |
| ... | ... | @@ -88,8 +88,12 @@ pub const cpu_models = struct { |
| 88 | 88 | E{ .part = 0xd87, .m64 = &A64.cortex_a725 }, |
| 89 | 89 | E{ .part = 0xd88, .m64 = &A64.cortex_a520ae }, |
| 90 | 90 | E{ .part = 0xd89, .m64 = &A64.cortex_a720ae }, |
| 91 | E{ .part = 0xd8a, .m64 = &A64.c1_nano }, |
| 92 | E{ .part = 0xd8b, .m64 = &A64.c1_pro }, |
| 93 | E{ .part = 0xd8c, .m64 = &A64.c1_ultra }, |
| 91 | 94 | E{ .part = 0xd8e, .m64 = &A64.neoverse_n3 }, |
| 92 | 95 | E{ .part = 0xd8f, .m64 = &A64.cortex_a320 }, |
| 96 | E{ .part = 0xd90, .m64 = &A64.c1_premium }, |
| 93 | 97 | }; |
| 94 | 98 | // implementer = 0x42 |
| 95 | 99 | const Broadcom = [_]E{ |
| ... | ... | @@ -102,10 +106,17 @@ pub const cpu_models = struct { |
| 102 | 106 | E{ .part = 0x0a3, .m64 = &A64.thunderxt83 }, |
| 103 | 107 | E{ .part = 0x0a1, .m64 = &A64.thunderxt88 }, |
| 104 | 108 | E{ .part = 0x0af, .m64 = &A64.thunderx2t99 }, |
| 109 | E{ .part = 0x0b0, .m64 = &A64.cortex_a57 }, |
| 110 | E{ .part = 0x0b1, .m64 = &A64.cortex_a57 }, |
| 111 | E{ .part = 0x0b2, .m64 = &A64.cortex_a57 }, |
| 112 | E{ .part = 0x0b3, .m64 = &A64.cortex_a57 }, |
| 113 | E{ .part = 0x0b4, .m64 = &A64.cortex_a57 }, |
| 114 | E{ .part = 0x0b5, .m64 = &A64.cortex_a57 }, |
| 105 | 115 | }; |
| 106 | 116 | // implementer = 0x46 |
| 107 | 117 | const Fujitsu = [_]E{ |
| 108 | 118 | E{ .part = 0x001, .m64 = &A64.a64fx }, |
| 119 | E{ .part = 0x003, .m64 = &A64.fujitsu_monaka }, |
| 109 | 120 | }; |
| 110 | 121 | // implementer = 0x48 |
| 111 | 122 | const HiSilicon = [_]E{ |
| ... | ... | @@ -137,8 +148,14 @@ pub const cpu_models = struct { |
| 137 | 148 | E{ .part = 0xc00, .m64 = &A64.falkor }, |
| 138 | 149 | E{ .part = 0xc01, .m64 = &A64.saphira }, |
| 139 | 150 | }; |
| 151 | // implementer = 0x53 |
| 152 | const Samsung = [_]E{ |
| 153 | E{ .part = 0x000, .m64 = &A64.exynos_m1 }, |
| 154 | }; |
| 140 | 155 | // implementer = 0x61 |
| 141 | 156 | const Apple = [_]E{ |
| 157 | E{ .part = 0x020, .m64 = &A64.apple_m1 }, |
| 158 | E{ .part = 0x021, .m64 = &A64.apple_m1 }, |
| 142 | 159 | E{ .part = 0x022, .m64 = &A64.apple_m1 }, |
| 143 | 160 | E{ .part = 0x023, .m64 = &A64.apple_m1 }, |
| 144 | 161 | E{ .part = 0x024, .m64 = &A64.apple_m1 }, |
| ... | ... | @@ -151,11 +168,43 @@ pub const cpu_models = struct { |
| 151 | 168 | E{ .part = 0x035, .m64 = &A64.apple_m2 }, |
| 152 | 169 | E{ .part = 0x038, .m64 = &A64.apple_m2 }, |
| 153 | 170 | E{ .part = 0x039, .m64 = &A64.apple_m2 }, |
| 171 | E{ .part = 0x042, .m64 = &A64.apple_m3 }, |
| 172 | E{ .part = 0x043, .m64 = &A64.apple_m3 }, |
| 173 | E{ .part = 0x044, .m64 = &A64.apple_m3 }, |
| 174 | E{ .part = 0x045, .m64 = &A64.apple_m3 }, |
| 175 | E{ .part = 0x048, .m64 = &A64.apple_m3 }, |
| 176 | E{ .part = 0x049, .m64 = &A64.apple_m3 }, |
| 177 | E{ .part = 0x052, .m64 = &A64.apple_m4 }, |
| 178 | E{ .part = 0x053, .m64 = &A64.apple_m4 }, |
| 179 | E{ .part = 0x054, .m64 = &A64.apple_m4 }, |
| 180 | E{ .part = 0x055, .m64 = &A64.apple_m4 }, |
| 181 | E{ .part = 0x058, .m64 = &A64.apple_m4 }, |
| 182 | E{ .part = 0x059, .m64 = &A64.apple_m4 }, |
| 183 | }; |
| 184 | // implementer = 0x63 |
| 185 | const ArmChina = [_]E{ |
| 186 | E{ .part = 0x132, .m32 = &A32.star_mc1 }, |
| 187 | E{ .part = 0xd25, .m32 = &A32.star_mc3 }, |
| 188 | }; |
| 189 | // implementer = 0x68 |
| 190 | const Hxt = [_]E{ |
| 191 | E{ .part = 0x000, .m64 = &A64.cortex_a57 }, |
| 192 | }; |
| 193 | // implementer = 0x6d |
| 194 | const Microsoft = [_]E{ |
| 195 | E{ .part = 0xd49, .m64 = &A64.neoverse_n2 }, |
| 196 | }; |
| 197 | // implementer = 0xC0 |
| 198 | const AmpereOne = [_]E{ |
| 199 | E{ .part = 0xac3, .m64 = &A64.ampere1 }, |
| 200 | E{ .part = 0xac4, .m64 = &A64.ampere1a }, |
| 201 | E{ .part = 0xac5, .m64 = &A64.ampere1b }, |
| 202 | E{ .part = 0xac7, .m64 = &A64.ampere1c }, |
| 154 | 203 | }; |
| 155 | 204 | |
| 156 | 205 | pub fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model { |
| 157 | 206 | const models = switch (core.implementer) { |
| 158 | | 0x41 => &ARM, |
| 207 | 0x41 => &Arm, |
| 159 | 208 | 0x42 => &Broadcom, |
| 160 | 209 | 0x43 => &Cavium, |
| 161 | 210 | 0x46 => &Fujitsu, |
| ... | ... | @@ -163,7 +212,12 @@ pub const cpu_models = struct { |
| 163 | 212 | 0x4e => &Nvidia, |
| 164 | 213 | 0x50 => &Ampere, |
| 165 | 214 | 0x51 => &Qualcomm, |
| 215 | 0x53 => &Samsung, |
| 166 | 216 | 0x61 => &Apple, |
| 217 | 0x63 => &ArmChina, |
| 218 | 0x68 => &Hxt, |
| 219 | 0x6d => &Microsoft, |
| 220 | 0xC0 => &AmpereOne, |
| 167 | 221 | else => return null, |
| 168 | 222 | }; |
| 169 | 223 | |
Alex Rønne Petersen <alex@alexrp.com> 2026-01-21 01:34:26+01:00
Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM
lib