authorgravatar for techatrix@mailbox.orgTechatrix <techatrix@mailbox.org> 2026-08-03 21:02:56+02:00
committergravatar for techatrix@mailbox.orgTechatrix <techatrix@mailbox.org> 2026-08-05 15:27:02+02:00
log6f7607c8e23fd8fd5d8fdbc28b119590f092dd0b
tree56d7682f1d93ad32b9d694be5a941cf3483be1a3
parentc80045cbe77c9cd044ab07b189003726169e0ace
signaturebadge-check Signed by SSH key SHA256:HYC3SjXQcAt6uwv9pu/6OoVQ2rUH8rb5zKiUHSe9uxk

c_abi: fix struct with single scalar array element on wasm

2 files changed, 19 insertions(+), 31 deletions(-)

src/codegen/wasm/abi.zig+7
...@@ -84,6 +84,13 @@ pub fn classifyTypeForLlvm(ty: Type, zcu: *const Zcu) LlvmClass {...@@ -84,6 +84,13 @@ pub fn classifyTypeForLlvm(ty: Type, zcu: *const Zcu) LlvmClass {
84 if (explicit_align.compareStrict(.gt, field_ty.abiAlignment(zcu)))84 if (explicit_align.compareStrict(.gt, field_ty.abiAlignment(zcu)))
85 return .indirect;85 return .indirect;
86 }86 }
87 if (field_ty.zigTypeTag(zcu) == .array) {
88 switch (field_ty.arrayLenIncludingSentinel(zcu)) {
89 0 => unreachable,
90 1 => return classifyTypeForLlvm(field_ty.childType(zcu), zcu),
91 else => {},
92 }
93 }
87 return classifyTypeForLlvm(field_ty, zcu);94 return classifyTypeForLlvm(field_ty, zcu);
88 },95 },
89 .@"union" => {96 .@"union" => {
test/c_abi/main.zig+12-31
...@@ -16107,20 +16107,12 @@ const Struct_array_1_f32 = extern struct {...@@ -16107,20 +16107,12 @@ const Struct_array_1_f32 = extern struct {
16107 a: [1]f32,16107 a: [1]f32,
16108};16108};
1610916109
16110comptime {16110export fn zig_ret_struct_array_1_f32() Struct_array_1_f32 {
16111 skip: {16111 return .{ .a = .{1} };
16112 if (builtin.cpu.arch.isWasm()) break :skip;16112}
1611316113export fn zig_struct_array_1_f32(s: Struct_array_1_f32, i: usize) void {
16114 _ = struct {16114 expect(s.a[0] == 2) catch @panic("test failure");
16115 export fn zig_ret_struct_array_1_f32() Struct_array_1_f32 {16115 expect(i == 3) catch @panic("test failure");
16116 return .{ .a = .{1} };
16117 }
16118 export fn zig_struct_array_1_f32(s: Struct_array_1_f32, i: usize) void {
16119 expect(s.a[0] == 2) catch @panic("test failure");
16120 expect(i == 3) catch @panic("test failure");
16121 }
16122 };
16123 }
16124}16116}
1612516117
16126extern fn c_ret_struct_array_1_f32() Struct_array_1_f32;16118extern fn c_ret_struct_array_1_f32() Struct_array_1_f32;
...@@ -16134,7 +16126,6 @@ test "struct [1]f32" {...@@ -16134,7 +16126,6 @@ test "struct [1]f32" {
16134 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16126 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16135 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16127 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16136 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;16128 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16137 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest;
1613816129
16139 const s = c_ret_struct_array_1_f32();16130 const s = c_ret_struct_array_1_f32();
16140 try expect(s.a[0] == 4);16131 try expect(s.a[0] == 4);
...@@ -16303,7 +16294,6 @@ test "struct [0:sentinel]f32" {...@@ -16303,7 +16294,6 @@ test "struct [0:sentinel]f32" {
16303 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16294 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16304 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16295 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16305 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;16296 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16306 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest;
1630716297
16308 var sentinel_index: usize = 0;16298 var sentinel_index: usize = 0;
16309 _ = &sentinel_index;16299 _ = &sentinel_index;
...@@ -16766,20 +16756,12 @@ const Struct_array_1_f64 = extern struct {...@@ -16766,20 +16756,12 @@ const Struct_array_1_f64 = extern struct {
16766 a: [1]f64,16756 a: [1]f64,
16767};16757};
1676816758
16769comptime {16759export fn zig_ret_struct_array_1_f64() Struct_array_1_f64 {
16770 skip: {16760 return .{ .a = .{1} };
16771 if (builtin.cpu.arch.isWasm()) break :skip;16761}
1677216762export fn zig_struct_array_1_f64(s: Struct_array_1_f64, i: usize) void {
16773 _ = struct {16763 expect(s.a[0] == 2) catch @panic("test failure");
16774 export fn zig_ret_struct_array_1_f64() Struct_array_1_f64 {16764 expect(i == 3) catch @panic("test failure");
16775 return .{ .a = .{1} };
16776 }
16777 export fn zig_struct_array_1_f64(s: Struct_array_1_f64, i: usize) void {
16778 expect(s.a[0] == 2) catch @panic("test failure");
16779 expect(i == 3) catch @panic("test failure");
16780 }
16781 };
16782 }
16783}16765}
1678416766
16785extern fn c_ret_struct_array_1_f64() Struct_array_1_f64;16767extern fn c_ret_struct_array_1_f64() Struct_array_1_f64;
...@@ -16793,7 +16775,6 @@ test "struct [1]f64" {...@@ -16793,7 +16775,6 @@ test "struct [1]f64" {
16793 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16775 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16794 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16776 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16795 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;16777 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16796 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest;
1679716778
16798 const s = c_ret_struct_array_1_f64();16779 const s = c_ret_struct_array_1_f64();
16799 try expect(s.a[0] == 4);16780 try expect(s.a[0] == 4);