authorgravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2023-02-20 22:40:08+07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2023-04-28 16:46:04-07:00
log75a1360cdd1745ac267c9a25b84ec7ee765d9262
tree4971860efa034a9e34942b225274a9bd67202452
parent83e6223192acd635275e67614e55b7a4c579a969

stage2: sparc64: Implement ASI load/store ops

3 files changed, 66 insertions(+), 11 deletions(-)

src/arch/sparc64/CodeGen.zig+3-3
...@@ -1254,7 +1254,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {...@@ -1254,7 +1254,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {
12541254
1255 try self.genStoreASI(reg, .sp, off_reg, abi_size, opposite_endian_asi);1255 try self.genStoreASI(reg, .sp, off_reg, abi_size, opposite_endian_asi);
1256 try self.genLoad(reg, .sp, Register, off_reg, abi_size);1256 try self.genLoad(reg, .sp, Register, off_reg, abi_size);
1257 break :result reg;1257 break :result .{ .register = reg };
1258 },1258 },
1259 .memory => {1259 .memory => {
1260 if (int_info.bits > 64 or @popCount(int_info.bits) != 1)1260 if (int_info.bits > 64 or @popCount(int_info.bits) != 1)
...@@ -1264,7 +1264,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {...@@ -1264,7 +1264,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {
1264 const dst_reg = try self.register_manager.allocReg(null, gp);1264 const dst_reg = try self.register_manager.allocReg(null, gp);
12651265
1266 try self.genLoadASI(dst_reg, addr_reg, .g0, abi_size, opposite_endian_asi);1266 try self.genLoadASI(dst_reg, addr_reg, .g0, abi_size, opposite_endian_asi);
1267 break :result dst_reg;1267 break :result .{ .register = dst_reg };
1268 },1268 },
1269 .stack_offset => |off| {1269 .stack_offset => |off| {
1270 if (int_info.bits > 64 or @popCount(int_info.bits) != 1)1270 if (int_info.bits > 64 or @popCount(int_info.bits) != 1)
...@@ -1274,7 +1274,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {...@@ -1274,7 +1274,7 @@ fn airByteSwap(self: *Self, inst: Air.Inst.Index) !void {
1274 const dst_reg = try self.register_manager.allocReg(null, gp);1274 const dst_reg = try self.register_manager.allocReg(null, gp);
12751275
1276 try self.genLoadASI(dst_reg, .sp, off_reg, abi_size, opposite_endian_asi);1276 try self.genLoadASI(dst_reg, .sp, off_reg, abi_size, opposite_endian_asi);
1277 break :result dst_reg;1277 break :result .{ .register = dst_reg };
1278 },1278 },
1279 else => unreachable,1279 else => unreachable,
1280 }1280 }
src/arch/sparc64/Emit.zig+31-8
...@@ -91,10 +91,10 @@ pub fn emitMir(...@@ -91,10 +91,10 @@ pub fn emitMir(
91 .lduw => try emit.mirArithmetic3Op(inst),91 .lduw => try emit.mirArithmetic3Op(inst),
92 .ldx => try emit.mirArithmetic3Op(inst),92 .ldx => try emit.mirArithmetic3Op(inst),
9393
94 .lduba => unreachable,94 .lduba => try emit.mirMemASI(inst),
95 .lduha => unreachable,95 .lduha => try emit.mirMemASI(inst),
96 .lduwa => unreachable,96 .lduwa => try emit.mirMemASI(inst),
97 .ldxa => unreachable,97 .ldxa => try emit.mirMemASI(inst),
9898
99 .@"and" => try emit.mirArithmetic3Op(inst),99 .@"and" => try emit.mirArithmetic3Op(inst),
100 .@"or" => try emit.mirArithmetic3Op(inst),100 .@"or" => try emit.mirArithmetic3Op(inst),
...@@ -132,10 +132,10 @@ pub fn emitMir(...@@ -132,10 +132,10 @@ pub fn emitMir(
132 .stw => try emit.mirArithmetic3Op(inst),132 .stw => try emit.mirArithmetic3Op(inst),
133 .stx => try emit.mirArithmetic3Op(inst),133 .stx => try emit.mirArithmetic3Op(inst),
134134
135 .stba => unreachable,135 .stba => try emit.mirMemASI(inst),
136 .stha => unreachable,136 .stha => try emit.mirMemASI(inst),
137 .stwa => unreachable,137 .stwa => try emit.mirMemASI(inst),
138 .stxa => unreachable,138 .stxa => try emit.mirMemASI(inst),
139139
140 .sub => try emit.mirArithmetic3Op(inst),140 .sub => try emit.mirArithmetic3Op(inst),
141 .subcc => try emit.mirArithmetic3Op(inst),141 .subcc => try emit.mirArithmetic3Op(inst),
...@@ -378,6 +378,29 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -378,6 +378,29 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void {
378 }378 }
379}379}
380380
381fn mirMemASI(emit: *Emit, inst: Mir.Inst.Index) !void {
382 const tag = emit.mir.instructions.items(.tag)[inst];
383 const data = emit.mir.instructions.items(.data)[inst].mem_asi;
384
385 const rd = data.rd;
386 const rs1 = data.rs1;
387 const rs2 = data.rs2;
388 const asi = data.asi;
389
390 switch (tag) {
391 .lduba => try emit.writeInstruction(Instruction.lduba(rs1, rs2, asi, rd)),
392 .lduha => try emit.writeInstruction(Instruction.lduha(rs1, rs2, asi, rd)),
393 .lduwa => try emit.writeInstruction(Instruction.lduwa(rs1, rs2, asi, rd)),
394 .ldxa => try emit.writeInstruction(Instruction.ldxa(rs1, rs2, asi, rd)),
395
396 .stba => try emit.writeInstruction(Instruction.stba(rs1, rs2, asi, rd)),
397 .stha => try emit.writeInstruction(Instruction.stha(rs1, rs2, asi, rd)),
398 .stwa => try emit.writeInstruction(Instruction.stwa(rs1, rs2, asi, rd)),
399 .stxa => try emit.writeInstruction(Instruction.stxa(rs1, rs2, asi, rd)),
400 else => unreachable,
401 }
402}
403
381fn mirMembar(emit: *Emit, inst: Mir.Inst.Index) !void {404fn mirMembar(emit: *Emit, inst: Mir.Inst.Index) !void {
382 const tag = emit.mir.instructions.items(.tag)[inst];405 const tag = emit.mir.instructions.items(.tag)[inst];
383 const mask = emit.mir.instructions.items(.data)[inst].membar_mask;406 const mask = emit.mir.instructions.items(.data)[inst].membar_mask;
src/arch/sparc64/bits.zig+32
...@@ -1229,6 +1229,22 @@ pub const Instruction = union(enum) {...@@ -1229,6 +1229,22 @@ pub const Instruction = union(enum) {
1229 };1229 };
1230 }1230 }
12311231
1232 pub fn lduba(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1233 return format3i(0b11, 0b01_0001, rs1, rs2, rd, asi);
1234 }
1235
1236 pub fn lduha(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1237 return format3i(0b11, 0b01_0010, rs1, rs2, rd, asi);
1238 }
1239
1240 pub fn lduwa(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1241 return format3i(0b11, 0b01_0000, rs1, rs2, rd, asi);
1242 }
1243
1244 pub fn ldxa(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1245 return format3i(0b11, 0b01_1011, rs1, rs2, rd, asi);
1246 }
1247
1232 pub fn @"and"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {1248 pub fn @"and"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1233 return switch (s2) {1249 return switch (s2) {
1234 Register => format3a(0b10, 0b00_0001, rs1, rs2, rd),1250 Register => format3a(0b10, 0b00_0001, rs1, rs2, rd),
...@@ -1417,6 +1433,22 @@ pub const Instruction = union(enum) {...@@ -1417,6 +1433,22 @@ pub const Instruction = union(enum) {
1417 };1433 };
1418 }1434 }
14191435
1436 pub fn stba(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1437 return format3i(0b11, 0b01_0101, rs1, rs2, rd, asi);
1438 }
1439
1440 pub fn stha(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1441 return format3i(0b11, 0b01_0110, rs1, rs2, rd, asi);
1442 }
1443
1444 pub fn stwa(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1445 return format3i(0b11, 0b01_0100, rs1, rs2, rd, asi);
1446 }
1447
1448 pub fn stxa(rs1: Register, rs2: Register, asi: ASI, rd: Register) Instruction {
1449 return format3i(0b11, 0b01_1110, rs1, rs2, rd, asi);
1450 }
1451
1420 pub fn sub(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {1452 pub fn sub(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1421 return switch (s2) {1453 return switch (s2) {
1422 Register => format3a(0b10, 0b00_0100, rs1, rs2, rd),1454 Register => format3a(0b10, 0b00_0100, rs1, rs2, rd),