| ... | ... | @@ -19,6 +19,7 @@ else switch (native_arch) { |
| 19 | 19 | .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv, |
| 20 | 20 | .ve => Ve, |
| 21 | 21 | .s390x => S390x, |
| 22 | .x86_16 => X86_16, |
| 22 | 23 | .x86 => X86, |
| 23 | 24 | .x86_64 => X86_64, |
| 24 | 25 | else => noreturn, |
| ... | ... | @@ -1350,6 +1351,46 @@ const Ve = extern struct { |
| 1350 | 1351 | } |
| 1351 | 1352 | }; |
| 1352 | 1353 | |
| 1354 | const X86_16 = struct { |
| 1355 | pub const Register = enum { |
| 1356 | // zig fmt: off |
| 1357 | sp, bp, ss, |
| 1358 | ip, cs, |
| 1359 | // zig fmt: on |
| 1360 | }; |
| 1361 | |
| 1362 | regs: std.enums.EnumArray(Register, u16), |
| 1363 | |
| 1364 | pub inline fn current() X86_16 { |
| 1365 | var ctx: X86_16 = undefined; |
| 1366 | asm volatile ( |
| 1367 | \\ movw %%sp, 0x00(%%di) |
| 1368 | \\ movw %%bp, 0x02(%%di) |
| 1369 | \\ movw %%ss, 0x04(%%di) |
| 1370 | \\ pushw %%cs |
| 1371 | \\ call 1f |
| 1372 | \\1: |
| 1373 | \\ popw 0x06(%%di) |
| 1374 | \\ popw 0x08(%%di) |
| 1375 | : |
| 1376 | : [gprs] "{di}" (&ctx.regs.values), |
| 1377 | : .{ .memory = true }); |
| 1378 | return ctx; |
| 1379 | } |
| 1380 | |
| 1381 | // NOTE: There doesn't seem to be any standard for DWARF x86-16 so we'll just reuse the ones for x86. |
| 1382 | pub fn dwarfRegisterBytes(ctx: *X86_16, register_num: u16) DwarfRegisterError![]u8 { |
| 1383 | switch (register_num) { |
| 1384 | 4 => return @ptrCast(ctx.regs.getPtr(.sp)), |
| 1385 | 5 => return @ptrCast(ctx.regs.getPtr(.bp)), |
| 1386 | 6 => return @ptrCast(ctx.regs.getPtr(.ip)), |
| 1387 | 41 => return @ptrCast(ctx.regs.getPtr(.cs)), |
| 1388 | 42 => return @ptrCast(ctx.regs.getPtr(.ss)), |
| 1389 | else => return error.InvalidRegister, |
| 1390 | } |
| 1391 | } |
| 1392 | }; |
| 1393 | |
| 1353 | 1394 | const X86 = struct { |
| 1354 | 1395 | /// The first 8 registers here intentionally match the order of registers in the x86 instruction |
| 1355 | 1396 | /// encoding. This order is inherited by the PUSHA instruction and the DWARF register mappings, |
Alex Rønne Petersen <alex@alexrp.com> 2025-10-30 01:41:32+01:00
GitHub <noreply@github.com> 2025-10-30 01:41:32+01:00
Signed by PGP key B5690EEEBB952194
lib