authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-01-20 22:16:33+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-04-25 21:54:48+02:00
log7c3d4642ae78545e0233dc24cf07690c07f4255f
treefe2d13e966eea6f48d42fa7d4765d20f6dd089b9
parent67fa822300acfc173371351ff7d2e7b514f516d8
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.os.windows: update PF feature flags from winnt.h

1 files changed, 130 insertions(+), 1 deletions(-)

lib/std/os/windows.zig+130-1
...@@ -5665,7 +5665,136 @@ pub const PF = enum(DWORD) {...@@ -5665,7 +5665,136 @@ pub const PF = enum(DWORD) {
5665 ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,5665 ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,
56665666
5667 /// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.5667 /// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
5668 ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE,5668 ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE = 45,
5669
5670 /// This Arm processor implements the SVE (Scalable Vector Extension) instructions (FEAT_SVE).
5671 ARM_SVE_INSTRUCTIONS_AVAILABLE = 46,
5672
5673 /// This Arm processor implements the SVE2 instructions (FEAT_SVE2).
5674 ARM_SVE2_INSTRUCTIONS_AVAILABLE = 47,
5675
5676 /// This Arm processor implements the SVE2.1 instructions (FEAT_SVE2p1).
5677 ARM_SVE2_1_INSTRUCTIONS_AVAILABLE = 48,
5678
5679 /// This Arm processor implements the SVE AES instructions (FEAT_SVE_AES).
5680 ARM_SVE_AES_INSTRUCTIONS_AVAILABLE = 49,
5681
5682 /// This Arm processor implements the SVE 128-bit polynomial multiply long instructions (FEAT_SVE_PMULL128).
5683 ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE = 50,
5684
5685 /// This Arm processor implements the SVE bit permute instructions (FEAT_SVE_BitPerm).
5686 ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE = 51,
5687
5688 /// This Arm processor implements the SVE BF16 (BFloat16) instructions (FEAT_BF16).
5689 ARM_SVE_BF16_INSTRUCTIONS_AVAILABLE = 52,
5690
5691 /// This Arm processor implements the SVE EBF16 (Extended BFloat16) instructions (FEAT_EBF16).
5692 ARM_SVE_EBF16_INSTRUCTIONS_AVAILABLE = 53,
5693
5694 /// This Arm processor implements the SVE B16B16 instructions (FEAT_SVE_B16B16).
5695 ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE = 54,
5696
5697 /// This Arm processor implements the SVE SHA-3 cryptographic instructions (FEAT_SVE_SHA3).
5698 ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE = 55,
5699
5700 /// This Arm processor implements the SVE SM4 cryptographic instructions (FEAT_SVE_SM4).
5701 ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE = 56,
5702
5703 /// This Arm processor implements the SVE I8MM (Int8 matrix multiply) instructions (FEAT_I8MM).
5704 ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE = 57,
5705
5706 /// This Arm processor implements the SVE F32MM (FP32 matrix multiply) instructions (FEAT_F32MM).
5707 ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE = 58,
5708
5709 /// This Arm processor implements the SVE F64MM (FP64 matrix multiply) instructions (FEAT_F64MM).
5710 ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE = 59,
5711
5712 /// This x64 processor implements the BMI2 instruction set.
5713 BMI2_INSTRUCTIONS_AVAILABLE = 60,
5714
5715 /// This x64 processor implements the MOVDIR64B instruction.
5716 MOVDIR64B_INSTRUCTION_AVAILABLE = 61,
5717
5718 /// This Arm processor implements the LSE2 atomic instructions (FEAT_LSE2).
5719 ARM_LSE2_AVAILABLE = 62,
5720
5721 /// This Arm processor implements the SHA-3 cryptographic instructions (FEAT_SHA3).
5722 ARM_SHA3_INSTRUCTIONS_AVAILABLE = 64,
5723
5724 /// This Arm processor implements the SHA-512 cryptographic instructions (FEAT_SHA512).
5725 ARM_SHA512_INSTRUCTIONS_AVAILABLE = 65,
5726
5727 /// This Arm processor implements the I8MM (Int8 matrix multiply) NEON instructions (FEAT_I8MM).
5728 ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE = 66,
5729
5730 /// This Arm processor implements the FP16 (half-precision floating point) NEON instructions (FEAT_FP16).
5731 ARM_V82_FP16_INSTRUCTIONS_AVAILABLE = 67,
5732
5733 /// This Arm processor implements the BF16 (BFloat16) NEON instructions (FEAT_BF16).
5734 ARM_V86_BF16_INSTRUCTIONS_AVAILABLE = 68,
5735
5736 /// This Arm processor implements the EBF16 (Extended BFloat16) NEON instructions (FEAT_EBF16).
5737 ARM_V86_EBF16_INSTRUCTIONS_AVAILABLE = 69,
5738
5739 /// This Arm processor implements the SME (Scalable Matrix Extension) instructions (FEAT_SME).
5740 ARM_SME_INSTRUCTIONS_AVAILABLE = 70,
5741
5742 /// This Arm processor implements the SME2 instructions (FEAT_SME2).
5743 ARM_SME2_INSTRUCTIONS_AVAILABLE = 71,
5744
5745 /// This Arm processor implements the SME2.1 instructions (FEAT_SME2p1).
5746 ARM_SME2_1_INSTRUCTIONS_AVAILABLE = 72,
5747
5748 /// This Arm processor implements the SME2.2 instructions (FEAT_SME2p2).
5749 ARM_SME2_2_INSTRUCTIONS_AVAILABLE = 73,
5750
5751 /// This Arm processor implements the SVE AES instructions when in Streaming SVE mode (FEAT_SSVE_AES).
5752 ARM_SME_AES_INSTRUCTIONS_AVAILABLE = 74,
5753
5754 /// This Arm processor implements the SVE bit permute instructions when in Streaming SVE mode (FEAT_SSVE_BitPerm).
5755 ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE = 75,
5756
5757 /// This Arm processor implements the SVE FMMLA (widening, 4-way, FP8 to FP16) instruction when in Streaming SVE mode (FEAT_SSVE_F8F16MM).
5758 ARM_SME_SF8MM4_INSTRUCTIONS_AVAILABLE = 76,
5759
5760 /// This Arm processor implements the SVE FMMLA (widening, 8-way, FP8 to FP32) instruction when in Streaming SVE mode (FEAT_SSVE_F8F32MM).
5761 ARM_SME_SF8MM8_INSTRUCTIONS_AVAILABLE = 77,
5762
5763 /// This Arm processor implements the SVE2 FP8DOT2 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT2).
5764 ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE = 78,
5765
5766 /// This Arm processor implements the SVE2 FP8DOT4 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT4).
5767 ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE = 79,
5768
5769 /// This Arm processor implements the SVE2 FP8FMA instructions when in Streaming SVE mode (FEAT_SSVE_FP8FMA).
5770 ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE = 80,
5771
5772 /// This Arm processor implements the SME F8F32 instructions (FEAT_SME_F8F32).
5773 ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE = 81,
5774
5775 /// This Arm processor implements the SME F8F16 instructions (FEAT_SME_F8F16).
5776 ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE = 82,
5777
5778 /// This Arm processor implements the SME F16F16 instructions (FEAT_SME_F16F16).
5779 ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE = 83,
5780
5781 /// This Arm processor implements the SME B16B16 instructions (FEAT_SME_B16B16).
5782 ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE = 84,
5783
5784 /// This Arm processor implements the SME F64F64 instructions (FEAT_SME_F64F64).
5785 ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE = 85,
5786
5787 /// This Arm processor implements the SME I16I64 instructions (FEAT_SME_I16I64).
5788 ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE = 86,
5789
5790 /// This Arm processor implements the SME LUTv2 instructions (FEAT_SME_LUTv2).
5791 ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE = 87,
5792
5793 /// This Arm processor implements SME FA64 (Full AArch64 instruction set when in Streaming SVE mode) (FEAT_SME_FA64).
5794 ARM_SME_FA64_INSTRUCTIONS_AVAILABLE = 88,
5795
5796 /// This x64 processor implements the UMONITOR instruction.
5797 UMONITOR_INSTRUCTION_AVAILABLE = 89,
5669};5798};
56705799
5671pub const MAX_WOW64_SHARED_ENTRIES = 16;5800pub const MAX_WOW64_SHARED_ENTRIES = 16;