authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-07-02 14:34:56-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-07-02 14:35:13-07:00
log80a9b8f326c8f2203bfd6452e9bd1c5eff0c9fe9
treebf0ef9049c2ea3b872393c6f1ba7d036db61cf69
parentedf785db0f30842b958f540a3aaf7205b8b82493

compiler: delete powerpc backend stub

nobody is currently working on this

3 files changed, 3 insertions(+), 64 deletions(-)

CMakeLists.txt-1
...@@ -559,7 +559,6 @@ set(ZIG_STAGE2_SOURCES...@@ -559,7 +559,6 @@ set(ZIG_STAGE2_SOURCES
559 src/arch/arm/Mir.zig559 src/arch/arm/Mir.zig
560 src/arch/arm/abi.zig560 src/arch/arm/abi.zig
561 src/arch/arm/bits.zig561 src/arch/arm/bits.zig
562 src/arch/powerpc/CodeGen.zig
563 src/arch/riscv64/abi.zig562 src/arch/riscv64/abi.zig
564 src/arch/riscv64/bits.zig563 src/arch/riscv64/bits.zig
565 src/arch/riscv64/CodeGen.zig564 src/arch/riscv64/CodeGen.zig
src/arch/powerpc/CodeGen.zig deleted-51
...@@ -1,51 +0,0 @@
1const builtin = @import("builtin");
2const std = @import("std");
3
4const Air = @import("../../Air.zig");
5const codegen = @import("../../codegen.zig");
6const InternPool = @import("../../InternPool.zig");
7const link = @import("../../link.zig");
8const Zcu = @import("../../Zcu.zig");
9
10const assert = std.debug.assert;
11const log = std.log.scoped(.codegen);
12
13pub fn legalizeFeatures(_: *const std.Target) ?*const Air.Legalize.Features {
14 return null;
15}
16
17pub fn generate(
18 bin_file: *link.File,
19 pt: Zcu.PerThread,
20 src_loc: Zcu.LazySrcLoc,
21 func_index: InternPool.Index,
22 air: *const Air,
23 liveness: *const Air.Liveness,
24) codegen.CodeGenError!noreturn {
25 _ = bin_file;
26 _ = pt;
27 _ = src_loc;
28 _ = func_index;
29 _ = air;
30 _ = liveness;
31
32 unreachable;
33}
34
35pub fn generateLazy(
36 bin_file: *link.File,
37 pt: Zcu.PerThread,
38 src_loc: Zcu.LazySrcLoc,
39 lazy_sym: link.File.LazySymbol,
40 code: *std.ArrayListUnmanaged(u8),
41 debug_output: link.File.DebugInfoOutput,
42) codegen.CodeGenError!void {
43 _ = bin_file;
44 _ = pt;
45 _ = src_loc;
46 _ = lazy_sym;
47 _ = code;
48 _ = debug_output;
49
50 unreachable;
51}
src/codegen.zig+3-12
...@@ -34,7 +34,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {...@@ -34,7 +34,7 @@ fn devFeatureForBackend(backend: std.builtin.CompilerBackend) dev.Feature {
34 .stage2_arm => .arm_backend,34 .stage2_arm => .arm_backend,
35 .stage2_c => .c_backend,35 .stage2_c => .c_backend,
36 .stage2_llvm => .llvm_backend,36 .stage2_llvm => .llvm_backend,
37 .stage2_powerpc => .powerpc_backend,37 .stage2_powerpc => unreachable,
38 .stage2_riscv64 => .riscv64_backend,38 .stage2_riscv64 => .riscv64_backend,
39 .stage2_sparc64 => .sparc64_backend,39 .stage2_sparc64 => .sparc64_backend,
40 .stage2_spirv => .spirv_backend,40 .stage2_spirv => .spirv_backend,
...@@ -52,7 +52,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {...@@ -52,7 +52,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
52 .stage2_arm => @import("arch/arm/CodeGen.zig"),52 .stage2_arm => @import("arch/arm/CodeGen.zig"),
53 .stage2_c => @import("codegen/c.zig"),53 .stage2_c => @import("codegen/c.zig"),
54 .stage2_llvm => @import("codegen/llvm.zig"),54 .stage2_llvm => @import("codegen/llvm.zig"),
55 .stage2_powerpc => @import("arch/powerpc/CodeGen.zig"),55 .stage2_powerpc => unreachable,
56 .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"),56 .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"),
57 .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"),57 .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"),
58 .stage2_spirv => @import("codegen/spirv.zig"),58 .stage2_spirv => @import("codegen/spirv.zig"),
...@@ -77,7 +77,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co...@@ -77,7 +77,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
77 .stage2_riscv64,77 .stage2_riscv64,
78 .stage2_sparc64,78 .stage2_sparc64,
79 .stage2_spirv,79 .stage2_spirv,
80 .stage2_powerpc,
81 => |backend| {80 => |backend| {
82 dev.check(devFeatureForBackend(backend));81 dev.check(devFeatureForBackend(backend));
83 return importBackend(backend).legalizeFeatures(target);82 return importBackend(backend).legalizeFeatures(target);
...@@ -91,7 +90,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co...@@ -91,7 +90,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
91pub const AnyMir = union {90pub const AnyMir = union {
92 aarch64: @import("arch/aarch64/Mir.zig"),91 aarch64: @import("arch/aarch64/Mir.zig"),
93 arm: @import("arch/arm/Mir.zig"),92 arm: @import("arch/arm/Mir.zig"),
94 powerpc: noreturn, //@import("arch/powerpc/Mir.zig"),
95 riscv64: @import("arch/riscv64/Mir.zig"),93 riscv64: @import("arch/riscv64/Mir.zig"),
96 sparc64: @import("arch/sparc64/Mir.zig"),94 sparc64: @import("arch/sparc64/Mir.zig"),
97 x86_64: @import("arch/x86_64/Mir.zig"),95 x86_64: @import("arch/x86_64/Mir.zig"),
...@@ -102,7 +100,6 @@ pub const AnyMir = union {...@@ -102,7 +100,6 @@ pub const AnyMir = union {
102 return switch (backend) {100 return switch (backend) {
103 .stage2_aarch64 => "aarch64",101 .stage2_aarch64 => "aarch64",
104 .stage2_arm => "arm",102 .stage2_arm => "arm",
105 .stage2_powerpc => "powerpc",
106 .stage2_riscv64 => "riscv64",103 .stage2_riscv64 => "riscv64",
107 .stage2_sparc64 => "sparc64",104 .stage2_sparc64 => "sparc64",
108 .stage2_x86_64 => "x86_64",105 .stage2_x86_64 => "x86_64",
...@@ -119,7 +116,6 @@ pub const AnyMir = union {...@@ -119,7 +116,6 @@ pub const AnyMir = union {
119 else => unreachable,116 else => unreachable,
120 inline .stage2_aarch64,117 inline .stage2_aarch64,
121 .stage2_arm,118 .stage2_arm,
122 .stage2_powerpc,
123 .stage2_riscv64,119 .stage2_riscv64,
124 .stage2_sparc64,120 .stage2_sparc64,
125 .stage2_x86_64,121 .stage2_x86_64,
...@@ -150,7 +146,6 @@ pub fn generateFunction(...@@ -150,7 +146,6 @@ pub fn generateFunction(
150 else => unreachable,146 else => unreachable,
151 inline .stage2_aarch64,147 inline .stage2_aarch64,
152 .stage2_arm,148 .stage2_arm,
153 .stage2_powerpc,
154 .stage2_riscv64,149 .stage2_riscv64,
155 .stage2_sparc64,150 .stage2_sparc64,
156 .stage2_x86_64,151 .stage2_x86_64,
...@@ -188,7 +183,6 @@ pub fn emitFunction(...@@ -188,7 +183,6 @@ pub fn emitFunction(
188 else => unreachable,183 else => unreachable,
189 inline .stage2_aarch64,184 inline .stage2_aarch64,
190 .stage2_arm,185 .stage2_arm,
191 .stage2_powerpc,
192 .stage2_riscv64,186 .stage2_riscv64,
193 .stage2_sparc64,187 .stage2_sparc64,
194 .stage2_x86_64,188 .stage2_x86_64,
...@@ -215,10 +209,7 @@ pub fn generateLazyFunction(...@@ -215,10 +209,7 @@ pub fn generateLazyFunction(
215 zcu.getTarget();209 zcu.getTarget();
216 switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) {210 switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) {
217 else => unreachable,211 else => unreachable,
218 inline .stage2_powerpc,212 inline .stage2_riscv64, .stage2_x86_64 => |backend| {
219 .stage2_riscv64,
220 .stage2_x86_64,
221 => |backend| {
222 dev.check(devFeatureForBackend(backend));213 dev.check(devFeatureForBackend(backend));
223 return importBackend(backend).generateLazy(lf, pt, src_loc, lazy_sym, code, debug_output);214 return importBackend(backend).generateLazy(lf, pt, src_loc, lazy_sym, code, debug_output);
224 },215 },