authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2026-02-17 13:58:26-08:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2026-02-20 05:34:54+01:00
log8259d8d63145260bff4faf1d4d48b28d4061dc5a
treeb226afd0bc20b5145a841d86c85d0a122d7216c2
parente95132476dfd26b28b55f7656f03dd1ec338b509

minimal

2 files changed, 157 insertions(+), 1 deletions(-)

lib/std/Io/Uring.zig+34
......@@ -872,6 +872,11 @@ pub fn init(ev: *Evented, backing_allocator: Allocator, options: InitOptions) !v
872872 .fp = @intFromPtr(ev),
873873 .pc = @intFromPtr(&mainIdleEntry),
874874 },
875 .riscv64 => .{
876 .sp = @intFromPtr(allocated_slice[idle_stack_end_offset..].ptr),
877 .fp = @intFromPtr(ev),
878 .pc = @intFromPtr(&mainIdleEntry),
879 },
875880 .x86_64 => .{
876881 .rsp = @intFromPtr(allocated_slice[idle_stack_end_offset..].ptr),
877882 .rbp = @intFromPtr(ev),
......@@ -1109,6 +1114,13 @@ fn mainIdleEntry() callconv(.naked) void {
11091114 :
11101115 : [mainIdle] "X" (&mainIdle),
11111116 ),
1117 .riscv64 => asm volatile (
1118 \\ mv a0, fp
1119 \\ mv fp, zero
1120 \\ tail %[mainIdle]@plt
1121 :
1122 : [mainIdle] "X" (&mainIdle),
1123 ),
11121124 .x86_64 => asm volatile (
11131125 \\ movq %%rbp, %%rdi
11141126 \\ xor %%ebp, %%ebp
......@@ -1383,6 +1395,12 @@ const AsyncClosure = struct {
13831395 :
13841396 : [call] "X" (&call),
13851397 ),
1398 .riscv64 => asm volatile (
1399 \\ mv a0, sp
1400 \\ tail %[call]@plt
1401 :
1402 : [call] "X" (&call),
1403 ),
13861404 .x86_64 => asm volatile (
13871405 \\ leaq 8(%%rsp), %%rdi
13881406 \\ jmp %[call:P]
......@@ -1448,6 +1466,11 @@ fn concurrent(
14481466 .fp = 0,
14491467 .pc = @intFromPtr(&AsyncClosure.entry),
14501468 },
1469 .riscv64 => .{
1470 .sp = @intFromPtr(closure),
1471 .fp = 0,
1472 .pc = @intFromPtr(&AsyncClosure.entry),
1473 },
14511474 .x86_64 => .{
14521475 .rsp = @intFromPtr(closure) - 8,
14531476 .rbp = 0,
......@@ -1737,6 +1760,12 @@ const Group = struct {
17371760 :
17381761 : [call] "X" (&call),
17391762 ),
1763 .riscv64 => asm volatile (
1764 \\ mv a0, sp
1765 \\ tail %[call]@plt
1766 :
1767 : [call] "X" (&call),
1768 ),
17401769 .x86_64 => asm volatile (
17411770 \\ leaq 8(%%rsp), %%rdi
17421771 \\ jmp %[call:P]
......@@ -1821,6 +1850,11 @@ fn groupConcurrent(
18211850 .fp = 0,
18221851 .pc = @intFromPtr(&Group.AsyncClosure.entry),
18231852 },
1853 .riscv64 => .{
1854 .sp = @intFromPtr(closure),
1855 .fp = 0,
1856 .pc = @intFromPtr(&Group.AsyncClosure.entry),
1857 },
18241858 .x86_64 => .{
18251859 .rsp = @intFromPtr(closure) - 8,
18261860 .rbp = 0,
lib/std/Io/fiber.zig+123-1
......@@ -1,5 +1,5 @@
11pub const supported = switch (builtin.cpu.arch) {
2 .aarch64, .x86_64 => true,
2 .aarch64, .riscv64, .x86_64 => true,
33 else => false,
44};
55
......@@ -10,6 +10,11 @@ pub const Context = switch (builtin.cpu.arch) {
1010 fp: u64,
1111 pc: u64,
1212 },
13 .riscv64 => extern struct {
14 sp: u64,
15 fp: u64,
16 pc: u64,
17 },
1318 .x86_64 => extern struct {
1419 rsp: u64,
1520 rbp: u64,
......@@ -119,6 +124,123 @@ pub inline fn contextSwitch(s: *const Switch) *const Switch {
119124 .ffr = true,
120125 .memory = true,
121126 }),
127 .riscv64 => asm volatile (
128 \\ ld a0, 0(a1)
129 \\ ld a2, 8(a1)
130 \\ lla a3, 0f
131 \\ sd sp, 0(a0)
132 \\ sd fp, 8(a0)
133 \\ sd a3, 16(a0)
134 \\ ld sp, 0(a2)
135 \\ ld fp, 8(a2)
136 \\ ld a3, 16(a2)
137 \\ jr a3
138 \\0:
139 : [received_message] "={a1}" (-> *const Switch),
140 : [message_to_send] "{a1}" (s),
141 : .{
142 .x1 = true,
143 .x3 = true,
144 .x4 = true,
145 .x5 = true,
146 .x6 = true,
147 .x7 = true,
148 .x9 = true,
149 .x10 = true,
150 .x11 = true,
151 .x12 = true,
152 .x13 = true,
153 .x14 = true,
154 .x15 = true,
155 .x16 = true,
156 .x17 = true,
157 .x18 = true,
158 .x19 = true,
159 .x20 = true,
160 .x21 = true,
161 .x22 = true,
162 .x23 = true,
163 .x24 = true,
164 .x25 = true,
165 .x26 = true,
166 .x27 = true,
167 .x28 = true,
168 .x29 = true,
169 .x30 = true,
170 .x31 = true,
171 .f0 = true,
172 .f1 = true,
173 .f2 = true,
174 .f3 = true,
175 .f4 = true,
176 .f5 = true,
177 .f6 = true,
178 .f7 = true,
179 .f8 = true,
180 .f9 = true,
181 .f10 = true,
182 .f11 = true,
183 .f12 = true,
184 .f13 = true,
185 .f14 = true,
186 .f15 = true,
187 .f16 = true,
188 .f17 = true,
189 .f18 = true,
190 .f19 = true,
191 .f20 = true,
192 .f21 = true,
193 .f22 = true,
194 .f23 = true,
195 .f24 = true,
196 .f25 = true,
197 .f26 = true,
198 .f27 = true,
199 .f28 = true,
200 .f29 = true,
201 .f30 = true,
202 .f31 = true,
203 .v0 = true,
204 .v1 = true,
205 .v2 = true,
206 .v3 = true,
207 .v4 = true,
208 .v5 = true,
209 .v6 = true,
210 .v7 = true,
211 .v8 = true,
212 .v9 = true,
213 .v10 = true,
214 .v11 = true,
215 .v12 = true,
216 .v13 = true,
217 .v14 = true,
218 .v15 = true,
219 .v16 = true,
220 .v17 = true,
221 .v18 = true,
222 .v19 = true,
223 .v20 = true,
224 .v21 = true,
225 .v22 = true,
226 .v23 = true,
227 .v24 = true,
228 .v25 = true,
229 .v26 = true,
230 .v27 = true,
231 .v28 = true,
232 .v29 = true,
233 .v30 = true,
234 .v31 = true,
235 .vtype = true,
236 .vl = true,
237 .vxsat = true,
238 .vxrm = true,
239 .vcsr = true,
240 .fflags = true,
241 .frm = true,
242 .memory = true,
243 }),
122244 .x86_64 => asm volatile (
123245 \\ movq 0(%%rsi), %%rax
124246 \\ movq 8(%%rsi), %%rcx