authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-09-24 23:32:05-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-10-01 15:09:52-04:00
log8470652f10a07f03b24746ffd786f6f5f4aabccc
tree80568b00172f68b5d112e1f2eccb848c5daf4f6e
parent6d5cbdb86394d517a3428242a7ab26384843fc0c

x86_64: implement float compare and cast builtins

11 files changed, 384 insertions(+), 239 deletions(-)

lib/compiler_rt/common.zig+2-2
......@@ -82,7 +82,7 @@ pub fn panic(msg: []const u8, error_return_trace: ?*std.builtin.StackTrace, _: ?
8282/// need for extending them to wider fp types.
8383/// TODO remove this; do this type selection in the language rather than
8484/// here in compiler-rt.
85pub fn F16T(comptime other_type: type) type {
85pub fn F16T(comptime OtherType: type) type {
8686 return switch (builtin.cpu.arch) {
8787 .arm, .armeb, .thumb, .thumbeb => if (std.Target.arm.featureSetHas(builtin.cpu.features, .has_v8))
8888 switch (builtin.abi.floatAbi()) {
......@@ -93,7 +93,7 @@ pub fn F16T(comptime other_type: type) type {
9393 u16,
9494 .aarch64, .aarch64_be, .aarch64_32 => f16,
9595 .riscv64 => if (builtin.zig_backend == .stage1) u16 else f16,
96 .x86, .x86_64 => if (builtin.target.isDarwin()) switch (other_type) {
96 .x86, .x86_64 => if (builtin.target.isDarwin()) switch (OtherType) {
9797 // Starting with LLVM 16, Darwin uses different abi for f16
9898 // depending on the type of the other return/argument..???
9999 f32, f64 => u16,
src/arch/x86_64/CodeGen.zig+378-200
......@@ -2515,63 +2515,96 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
25152515 const src_ty = self.typeOf(ty_op.operand);
25162516 const src_bits = src_ty.floatBits(self.target.*);
25172517
2518 const src_mcv = try self.resolveInst(ty_op.operand);
2519 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
2520 src_mcv
2521 else
2522 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2523 const dst_reg = dst_mcv.getReg().?.to128();
2524 const dst_lock = self.register_manager.lockReg(dst_reg);
2525 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
2518 const result = result: {
2519 if (switch (dst_bits) {
2520 16 => switch (src_bits) {
2521 32 => !self.hasFeature(.f16c),
2522 64, 80, 128 => true,
2523 else => unreachable,
2524 },
2525 32 => switch (src_bits) {
2526 64 => false,
2527 80, 128 => true,
2528 else => unreachable,
2529 },
2530 64 => switch (src_bits) {
2531 80, 128 => true,
2532 else => unreachable,
2533 },
2534 80 => switch (dst_bits) {
2535 128 => true,
2536 else => unreachable,
2537 },
2538 else => unreachable,
2539 }) {
2540 var callee: ["__trunc?f?f2".len]u8 = undefined;
2541 break :result try self.genCall(.{ .lib = .{
2542 .return_type = self.floatCompilerRtAbiType(dst_ty, src_ty).toIntern(),
2543 .param_types = &.{self.floatCompilerRtAbiType(src_ty, dst_ty).toIntern()},
2544 .callee = std.fmt.bufPrint(&callee, "__trunc{c}f{c}f2", .{
2545 floatCompilerRtAbiName(src_bits),
2546 floatCompilerRtAbiName(dst_bits),
2547 }) catch unreachable,
2548 } }, &.{ty_op.operand});
2549 }
2550
2551 const src_mcv = try self.resolveInst(ty_op.operand);
2552 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
2553 src_mcv
2554 else
2555 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2556 const dst_reg = dst_mcv.getReg().?.to128();
2557 const dst_lock = self.register_manager.lockReg(dst_reg);
2558 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
25262559
2527 if (dst_bits == 16 and self.hasFeature(.f16c)) {
2528 switch (src_bits) {
2529 32 => {
2530 const mat_src_reg = if (src_mcv.isRegister())
2560 if (dst_bits == 16) {
2561 assert(self.hasFeature(.f16c));
2562 switch (src_bits) {
2563 32 => {
2564 const mat_src_reg = if (src_mcv.isRegister())
2565 src_mcv.getReg().?
2566 else
2567 try self.copyToTmpRegister(src_ty, src_mcv);
2568 try self.asmRegisterRegisterImmediate(
2569 .{ .v_, .cvtps2ph },
2570 dst_reg,
2571 mat_src_reg.to128(),
2572 Immediate.u(0b1_00),
2573 );
2574 },
2575 else => unreachable,
2576 }
2577 } else {
2578 assert(src_bits == 64 and dst_bits == 32);
2579 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2580 .{ .v_ss, .cvtsd2 },
2581 dst_reg,
2582 dst_reg,
2583 src_mcv.mem(.qword),
2584 ) else try self.asmRegisterRegisterRegister(
2585 .{ .v_ss, .cvtsd2 },
2586 dst_reg,
2587 dst_reg,
2588 (if (src_mcv.isRegister())
25312589 src_mcv.getReg().?
25322590 else
2533 try self.copyToTmpRegister(src_ty, src_mcv);
2534 try self.asmRegisterRegisterImmediate(
2535 .{ .v_, .cvtps2ph },
2536 dst_reg,
2537 mat_src_reg.to128(),
2538 Immediate.u(0b1_00),
2539 );
2540 },
2541 else => return self.fail("TODO implement airFptrunc from {} to {}", .{
2542 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2543 }),
2591 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2592 ) else if (src_mcv.isMemory()) try self.asmRegisterMemory(
2593 .{ ._ss, .cvtsd2 },
2594 dst_reg,
2595 src_mcv.mem(.qword),
2596 ) else try self.asmRegisterRegister(
2597 .{ ._ss, .cvtsd2 },
2598 dst_reg,
2599 (if (src_mcv.isRegister())
2600 src_mcv.getReg().?
2601 else
2602 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2603 );
25442604 }
2545 } else if (src_bits == 64 and dst_bits == 32) {
2546 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2547 .{ .v_ss, .cvtsd2 },
2548 dst_reg,
2549 dst_reg,
2550 src_mcv.mem(.qword),
2551 ) else try self.asmRegisterRegisterRegister(
2552 .{ .v_ss, .cvtsd2 },
2553 dst_reg,
2554 dst_reg,
2555 (if (src_mcv.isRegister())
2556 src_mcv.getReg().?
2557 else
2558 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2559 ) else if (src_mcv.isMemory()) try self.asmRegisterMemory(
2560 .{ ._ss, .cvtsd2 },
2561 dst_reg,
2562 src_mcv.mem(.qword),
2563 ) else try self.asmRegisterRegister(
2564 .{ ._ss, .cvtsd2 },
2565 dst_reg,
2566 (if (src_mcv.isRegister())
2567 src_mcv.getReg().?
2568 else
2569 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2570 );
2571 } else return self.fail("TODO implement airFptrunc from {} to {}", .{
2572 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2573 });
2574 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
2605 break :result dst_mcv;
2606 };
2607 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
25752608}
25762609
25772610fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
......@@ -2581,58 +2614,96 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
25812614 const src_ty = self.typeOf(ty_op.operand);
25822615 const src_bits = src_ty.floatBits(self.target.*);
25832616
2584 const src_mcv = try self.resolveInst(ty_op.operand);
2585 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
2586 src_mcv
2587 else
2588 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2589 const dst_reg = dst_mcv.getReg().?.to128();
2590 const dst_lock = self.register_manager.lockReg(dst_reg);
2591 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
2617 const result = result: {
2618 if (switch (src_bits) {
2619 16 => switch (dst_bits) {
2620 32, 64 => !self.hasFeature(.f16c),
2621 80, 128 => true,
2622 else => unreachable,
2623 },
2624 32 => switch (dst_bits) {
2625 64 => false,
2626 80, 128 => true,
2627 else => unreachable,
2628 },
2629 64 => switch (dst_bits) {
2630 80, 128 => true,
2631 else => unreachable,
2632 },
2633 80 => switch (dst_bits) {
2634 128 => true,
2635 else => unreachable,
2636 },
2637 else => unreachable,
2638 }) {
2639 var callee: ["__extend?f?f2".len]u8 = undefined;
2640 break :result try self.genCall(.{ .lib = .{
2641 .return_type = self.floatCompilerRtAbiType(dst_ty, src_ty).toIntern(),
2642 .param_types = &.{self.floatCompilerRtAbiType(src_ty, dst_ty).toIntern()},
2643 .callee = std.fmt.bufPrint(&callee, "__extend{c}f{c}f2", .{
2644 floatCompilerRtAbiName(src_bits),
2645 floatCompilerRtAbiName(dst_bits),
2646 }) catch unreachable,
2647 } }, &.{ty_op.operand});
2648 }
25922649
2593 if (src_bits == 16 and self.hasFeature(.f16c)) {
2594 const mat_src_reg = if (src_mcv.isRegister())
2595 src_mcv.getReg().?
2650 const src_mcv = try self.resolveInst(ty_op.operand);
2651 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
2652 src_mcv
25962653 else
2597 try self.copyToTmpRegister(src_ty, src_mcv);
2598 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, mat_src_reg.to128());
2599 switch (dst_bits) {
2600 32 => {},
2601 64 => try self.asmRegisterRegisterRegister(.{ .v_sd, .cvtss2 }, dst_reg, dst_reg, dst_reg),
2602 else => return self.fail("TODO implement airFpext from {} to {}", .{
2603 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2604 }),
2605 }
2606 } else if (src_bits == 32 and dst_bits == 64) {
2607 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2608 .{ .v_sd, .cvtss2 },
2609 dst_reg,
2610 dst_reg,
2611 src_mcv.mem(.dword),
2612 ) else try self.asmRegisterRegisterRegister(
2613 .{ .v_sd, .cvtss2 },
2614 dst_reg,
2615 dst_reg,
2616 (if (src_mcv.isRegister())
2617 src_mcv.getReg().?
2618 else
2619 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2620 ) else if (src_mcv.isMemory()) try self.asmRegisterMemory(
2621 .{ ._sd, .cvtss2 },
2622 dst_reg,
2623 src_mcv.mem(.dword),
2624 ) else try self.asmRegisterRegister(
2625 .{ ._sd, .cvtss2 },
2626 dst_reg,
2627 (if (src_mcv.isRegister())
2654 try self.copyToRegisterWithInstTracking(inst, dst_ty, src_mcv);
2655 const dst_reg = dst_mcv.getReg().?.to128();
2656 const dst_lock = self.register_manager.lockReg(dst_reg);
2657 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
2658
2659 if (src_bits == 16) {
2660 assert(self.hasFeature(.f16c));
2661 const mat_src_reg = if (src_mcv.isRegister())
26282662 src_mcv.getReg().?
26292663 else
2630 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2631 );
2632 } else return self.fail("TODO implement airFpext from {} to {}", .{
2633 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2634 });
2635 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
2664 try self.copyToTmpRegister(src_ty, src_mcv);
2665 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, mat_src_reg.to128());
2666 switch (dst_bits) {
2667 32 => {},
2668 64 => try self.asmRegisterRegisterRegister(
2669 .{ .v_sd, .cvtss2 },
2670 dst_reg,
2671 dst_reg,
2672 dst_reg,
2673 ),
2674 else => unreachable,
2675 }
2676 } else {
2677 assert(src_bits == 32 and dst_bits == 64);
2678 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2679 .{ .v_sd, .cvtss2 },
2680 dst_reg,
2681 dst_reg,
2682 src_mcv.mem(.dword),
2683 ) else try self.asmRegisterRegisterRegister(
2684 .{ .v_sd, .cvtss2 },
2685 dst_reg,
2686 dst_reg,
2687 (if (src_mcv.isRegister())
2688 src_mcv.getReg().?
2689 else
2690 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2691 ) else if (src_mcv.isMemory()) try self.asmRegisterMemory(
2692 .{ ._sd, .cvtss2 },
2693 dst_reg,
2694 src_mcv.mem(.dword),
2695 ) else try self.asmRegisterRegister(
2696 .{ ._sd, .cvtss2 },
2697 dst_reg,
2698 (if (src_mcv.isRegister())
2699 src_mcv.getReg().?
2700 else
2701 try self.copyToTmpRegister(src_ty, src_mcv)).to128(),
2702 );
2703 }
2704 break :result dst_mcv;
2705 };
2706 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
26362707}
26372708
26382709fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
......@@ -8358,26 +8429,64 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
83588429 const bin_op = self.air.instructions.items(.data)[inst].bin_op;
83598430 const ty = self.typeOf(bin_op.lhs);
83608431
8361 try self.spillEflagsIfOccupied();
8362 self.eflags_inst = inst;
8432 const result: Condition = result: {
8433 switch (ty.zigTypeTag(mod)) {
8434 .Float => {
8435 const float_bits = ty.floatBits(self.target.*);
8436 if (switch (float_bits) {
8437 16 => !self.hasFeature(.f16c),
8438 32, 64 => false,
8439 80, 128 => true,
8440 else => unreachable,
8441 }) {
8442 var callee: ["__???f2".len]u8 = undefined;
8443 const ret = try self.genCall(.{ .lib = .{
8444 .return_type = .i32_type,
8445 .param_types = &.{ ty.toIntern(), ty.toIntern() },
8446 .callee = std.fmt.bufPrint(&callee, "__{s}{c}f2", .{
8447 switch (op) {
8448 .eq => "eq",
8449 .neq => "ne",
8450 .lt => "lt",
8451 .lte => "le",
8452 .gt => "gt",
8453 .gte => "ge",
8454 },
8455 floatCompilerRtAbiName(float_bits),
8456 }) catch unreachable,
8457 } }, &.{ bin_op.lhs, bin_op.rhs });
8458 try self.genBinOpMir(.{ ._, .@"test" }, Type.i32, ret, ret);
8459 break :result switch (op) {
8460 .eq => .e,
8461 .neq => .ne,
8462 .lt => .l,
8463 .lte => .le,
8464 .gt => .g,
8465 .gte => .ge,
8466 };
8467 }
8468 },
8469 else => {},
8470 }
83638471
8364 const lhs_mcv = try self.resolveInst(bin_op.lhs);
8365 const lhs_lock = switch (lhs_mcv) {
8366 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
8367 else => null,
8368 };
8369 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
8472 try self.spillEflagsIfOccupied();
83708473
8371 const rhs_mcv = try self.resolveInst(bin_op.rhs);
8372 const rhs_lock = switch (rhs_mcv) {
8373 .register => |reg| self.register_manager.lockReg(reg),
8374 else => null,
8375 };
8376 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
8474 const lhs_mcv = try self.resolveInst(bin_op.lhs);
8475 const lhs_lock = switch (lhs_mcv) {
8476 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
8477 else => null,
8478 };
8479 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
83778480
8378 const result = MCValue{
8379 .eflags = switch (ty.zigTypeTag(mod)) {
8380 else => result: {
8481 const rhs_mcv = try self.resolveInst(bin_op.rhs);
8482 const rhs_lock = switch (rhs_mcv) {
8483 .register => |reg| self.register_manager.lockReg(reg),
8484 else => null,
8485 };
8486 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
8487
8488 switch (ty.zigTypeTag(mod)) {
8489 else => {
83818490 const abi_size: u16 = @intCast(ty.abiSize(mod));
83828491 const may_flip: enum {
83838492 may_flip,
......@@ -8479,7 +8588,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
84798588 },
84808589 );
84818590 },
8482 .Float => result: {
8591 .Float => {
84838592 const flipped = switch (op) {
84848593 .lt, .lte => true,
84858594 .eq, .gte, .gt, .neq => false,
......@@ -8495,7 +8604,8 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
84958604 const src_mcv = if (flipped) lhs_mcv else rhs_mcv;
84968605
84978606 switch (ty.floatBits(self.target.*)) {
8498 16 => if (self.hasFeature(.f16c)) {
8607 16 => {
8608 assert(self.hasFeature(.f16c));
84998609 const tmp1_reg = (try self.register_manager.allocReg(null, sse)).to128();
85008610 const tmp1_mcv = MCValue{ .register = tmp1_reg };
85018611 const tmp1_lock = self.register_manager.lockRegAssumeUnused(tmp1_reg);
......@@ -8524,9 +8634,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
85248634 try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, tmp1_reg, tmp1_reg);
85258635 try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp2_reg, tmp1_reg);
85268636 try self.genBinOpMir(.{ ._ss, .ucomi }, ty, tmp1_mcv, tmp2_mcv);
8527 } else return self.fail("TODO implement airCmp for {}", .{
8528 ty.fmt(mod),
8529 }),
8637 },
85308638 32 => try self.genBinOpMir(
85318639 .{ ._ss, .ucomi },
85328640 ty,
......@@ -8539,9 +8647,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
85398647 .{ .register = dst_reg },
85408648 src_mcv,
85418649 ),
8542 else => return self.fail("TODO implement airCmp for {}", .{
8543 ty.fmt(mod),
8544 }),
8650 else => unreachable,
85458651 }
85468652
85478653 break :result switch (if (flipped) op.reverse() else op) {
......@@ -8552,9 +8658,11 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
85528658 .neq => .nz_or_p,
85538659 };
85548660 },
8555 },
8661 }
85568662 };
8557 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
8663
8664 self.eflags_inst = inst;
8665 return self.finishAir(inst, .{ .eflags = result }, .{ bin_op.lhs, bin_op.rhs, .none });
85588666}
85598667
85608668fn airCmpVector(self: *Self, inst: Air.Inst.Index) !void {
......@@ -8572,7 +8680,6 @@ fn airCmpLtErrorsLen(self: *Self, inst: Air.Inst.Index) !void {
85728680 try self.genLazySymbolRef(.lea, addr_reg, link.File.LazySymbol.initDecl(.const_data, null, mod));
85738681
85748682 try self.spillEflagsIfOccupied();
8575 self.eflags_inst = inst;
85768683
85778684 const op_ty = self.typeOf(un_op);
85788685 const op_abi_size: u32 = @intCast(op_ty.abiSize(mod));
......@@ -8586,8 +8693,9 @@ fn airCmpLtErrorsLen(self: *Self, inst: Air.Inst.Index) !void {
85868693 registerAlias(dst_reg, op_abi_size),
85878694 Memory.sib(Memory.PtrSize.fromSize(op_abi_size), .{ .base = .{ .reg = addr_reg } }),
85888695 );
8589 const result = MCValue{ .eflags = .b };
8590 return self.finishAir(inst, result, .{ un_op, .none, .none });
8696
8697 self.eflags_inst = inst;
8698 return self.finishAir(inst, .{ .eflags = .b }, .{ un_op, .none, .none });
85918699}
85928700
85938701fn airTry(self: *Self, inst: Air.Inst.Index) !void {
......@@ -8777,7 +8885,6 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
87778885 }
87788886
87798887 try self.spillEflagsIfOccupied();
8780 self.eflags_inst = inst;
87818888
87828889 const pl_ty = opt_ty.optionalChild(mod);
87838890
......@@ -8786,6 +8893,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
87868893 else
87878894 .{ .off = @intCast(pl_ty.abiSize(mod)), .ty = Type.bool };
87888895
8896 self.eflags_inst = inst;
87898897 switch (opt_mcv) {
87908898 .none,
87918899 .unreach,
......@@ -8867,7 +8975,6 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
88678975fn isNullPtr(self: *Self, inst: Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCValue) !MCValue {
88688976 const mod = self.bin_file.options.module.?;
88698977 try self.spillEflagsIfOccupied();
8870 self.eflags_inst = inst;
88718978
88728979 const opt_ty = ptr_ty.childType(mod);
88738980 const pl_ty = opt_ty.optionalChild(mod);
......@@ -8893,6 +9000,8 @@ fn isNullPtr(self: *Self, inst: Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCValue)
88939000 }),
88949001 Immediate.u(0),
88959002 );
9003
9004 self.eflags_inst = inst;
88969005 return .{ .eflags = .e };
88979006}
88989007
......@@ -8905,9 +9014,6 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, ty: Type, operand: MCValue) !
89059014 }
89069015
89079016 try self.spillEflagsIfOccupied();
8908 if (maybe_inst) |inst| {
8909 self.eflags_inst = inst;
8910 }
89119017
89129018 const err_off = errUnionErrorOffset(ty.errorUnionPayload(mod), mod);
89139019 switch (operand) {
......@@ -8945,6 +9051,7 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, ty: Type, operand: MCValue) !
89459051 else => return self.fail("TODO implement isErr for {}", .{operand}),
89469052 }
89479053
9054 if (maybe_inst) |inst| self.eflags_inst = inst;
89489055 return MCValue{ .eflags = .a };
89499056}
89509057
......@@ -10526,106 +10633,150 @@ fn airFloatFromInt(self: *Self, inst: Air.Inst.Index) !void {
1052610633 const mod = self.bin_file.options.module.?;
1052710634 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
1052810635
10636 const dst_ty = self.typeOfIndex(inst);
10637 const dst_bits = dst_ty.floatBits(self.target.*);
10638
1052910639 const src_ty = self.typeOf(ty_op.operand);
1053010640 const src_bits: u32 = @intCast(src_ty.bitSize(mod));
1053110641 const src_signedness =
1053210642 if (src_ty.isAbiInt(mod)) src_ty.intInfo(mod).signedness else .unsigned;
10533 const dst_ty = self.typeOfIndex(inst);
10534
1053510643 const src_size = math.divCeil(u32, @max(switch (src_signedness) {
1053610644 .signed => src_bits,
1053710645 .unsigned => src_bits + 1,
1053810646 }, 32), 8) catch unreachable;
10539 if (src_size > 8) return self.fail("TODO implement airFloatFromInt from {} to {}", .{
10540 src_ty.fmt(mod), dst_ty.fmt(mod),
10541 });
1054210647
10543 const src_mcv = try self.resolveInst(ty_op.operand);
10544 const src_reg = if (src_mcv.isRegister())
10545 src_mcv.getReg().?
10546 else
10547 try self.copyToTmpRegister(src_ty, src_mcv);
10548 const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
10549 defer self.register_manager.unlockReg(src_lock);
10648 const result = result: {
10649 if (switch (dst_bits) {
10650 16, 80, 128 => true,
10651 32, 64 => src_size > 8 and src_size < 16,
10652 else => unreachable,
10653 }) {
10654 var callee: ["__floatun?i?f".len]u8 = undefined;
10655 break :result try self.genCall(.{ .lib = .{
10656 .return_type = dst_ty.toIntern(),
10657 .param_types = &.{src_ty.toIntern()},
10658 .callee = std.fmt.bufPrint(&callee, "__float{s}{c}i{c}f", .{
10659 switch (src_signedness) {
10660 .signed => "",
10661 .unsigned => "un",
10662 },
10663 intCompilerRtAbiName(src_bits),
10664 floatCompilerRtAbiName(dst_bits),
10665 }) catch unreachable,
10666 } }, &.{ty_op.operand});
10667 }
1055010668
10551 if (src_bits < src_size * 8) try self.truncateRegister(src_ty, src_reg);
10669 if (src_size > 8) return self.fail("TODO implement airFloatFromInt from {} to {}", .{
10670 src_ty.fmt(mod), dst_ty.fmt(mod),
10671 });
1055210672
10553 const dst_reg = try self.register_manager.allocReg(inst, regClassForType(dst_ty, mod));
10554 const dst_mcv = MCValue{ .register = dst_reg };
10555 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
10556 defer self.register_manager.unlockReg(dst_lock);
10673 const src_mcv = try self.resolveInst(ty_op.operand);
10674 const src_reg = if (src_mcv.isRegister())
10675 src_mcv.getReg().?
10676 else
10677 try self.copyToTmpRegister(src_ty, src_mcv);
10678 const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
10679 defer self.register_manager.unlockReg(src_lock);
1055710680
10558 const mir_tag = @as(?Mir.Inst.FixedTag, switch (dst_ty.zigTypeTag(mod)) {
10559 .Float => switch (dst_ty.floatBits(self.target.*)) {
10560 32 => if (self.hasFeature(.avx)) .{ .v_ss, .cvtsi2 } else .{ ._ss, .cvtsi2 },
10561 64 => if (self.hasFeature(.avx)) .{ .v_sd, .cvtsi2 } else .{ ._sd, .cvtsi2 },
10562 16, 80, 128 => null,
10563 else => unreachable,
10564 },
10565 else => null,
10566 }) orelse return self.fail("TODO implement airFloatFromInt from {} to {}", .{
10567 src_ty.fmt(mod), dst_ty.fmt(mod),
10568 });
10569 const dst_alias = dst_reg.to128();
10570 const src_alias = registerAlias(src_reg, src_size);
10571 switch (mir_tag[0]) {
10572 .v_ss, .v_sd => try self.asmRegisterRegisterRegister(mir_tag, dst_alias, dst_alias, src_alias),
10573 else => try self.asmRegisterRegister(mir_tag, dst_alias, src_alias),
10574 }
10681 if (src_bits < src_size * 8) try self.truncateRegister(src_ty, src_reg);
1057510682
10576 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
10683 const dst_reg = try self.register_manager.allocReg(inst, regClassForType(dst_ty, mod));
10684 const dst_mcv = MCValue{ .register = dst_reg };
10685 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
10686 defer self.register_manager.unlockReg(dst_lock);
10687
10688 const mir_tag = @as(?Mir.Inst.FixedTag, switch (dst_ty.zigTypeTag(mod)) {
10689 .Float => switch (dst_ty.floatBits(self.target.*)) {
10690 32 => if (self.hasFeature(.avx)) .{ .v_ss, .cvtsi2 } else .{ ._ss, .cvtsi2 },
10691 64 => if (self.hasFeature(.avx)) .{ .v_sd, .cvtsi2 } else .{ ._sd, .cvtsi2 },
10692 16, 80, 128 => null,
10693 else => unreachable,
10694 },
10695 else => null,
10696 }) orelse return self.fail("TODO implement airFloatFromInt from {} to {}", .{
10697 src_ty.fmt(mod), dst_ty.fmt(mod),
10698 });
10699 const dst_alias = dst_reg.to128();
10700 const src_alias = registerAlias(src_reg, src_size);
10701 switch (mir_tag[0]) {
10702 .v_ss, .v_sd => try self.asmRegisterRegisterRegister(mir_tag, dst_alias, dst_alias, src_alias),
10703 else => try self.asmRegisterRegister(mir_tag, dst_alias, src_alias),
10704 }
10705
10706 break :result dst_mcv;
10707 };
10708 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
1057710709}
1057810710
1057910711fn airIntFromFloat(self: *Self, inst: Air.Inst.Index) !void {
1058010712 const mod = self.bin_file.options.module.?;
1058110713 const ty_op = self.air.instructions.items(.data)[inst].ty_op;
1058210714
10583 const src_ty = self.typeOf(ty_op.operand);
1058410715 const dst_ty = self.typeOfIndex(inst);
1058510716 const dst_bits: u32 = @intCast(dst_ty.bitSize(mod));
1058610717 const dst_signedness =
1058710718 if (dst_ty.isAbiInt(mod)) dst_ty.intInfo(mod).signedness else .unsigned;
10588
1058910719 const dst_size = math.divCeil(u32, @max(switch (dst_signedness) {
1059010720 .signed => dst_bits,
1059110721 .unsigned => dst_bits + 1,
1059210722 }, 32), 8) catch unreachable;
10593 if (dst_size > 8) return self.fail("TODO implement airIntFromFloat from {} to {}", .{
10594 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
10595 });
1059610723
10597 const src_mcv = try self.resolveInst(ty_op.operand);
10598 const src_reg = if (src_mcv.isRegister())
10599 src_mcv.getReg().?
10600 else
10601 try self.copyToTmpRegister(src_ty, src_mcv);
10602 const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
10603 defer self.register_manager.unlockReg(src_lock);
10724 const src_ty = self.typeOf(ty_op.operand);
10725 const src_bits = src_ty.floatBits(self.target.*);
1060410726
10605 const dst_reg = try self.register_manager.allocReg(inst, regClassForType(dst_ty, mod));
10606 const dst_mcv = MCValue{ .register = dst_reg };
10607 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
10608 defer self.register_manager.unlockReg(dst_lock);
10727 const result = result: {
10728 if (switch (src_bits) {
10729 16, 80, 128 => true,
10730 32, 64 => dst_size > 8 and dst_size < 16,
10731 else => unreachable,
10732 }) {
10733 var callee: ["__fixuns?f?i".len]u8 = undefined;
10734 break :result try self.genCall(.{ .lib = .{
10735 .return_type = dst_ty.toIntern(),
10736 .param_types = &.{src_ty.toIntern()},
10737 .callee = std.fmt.bufPrint(&callee, "__fix{s}{c}f{c}i", .{
10738 switch (dst_signedness) {
10739 .signed => "",
10740 .unsigned => "uns",
10741 },
10742 floatCompilerRtAbiName(src_bits),
10743 intCompilerRtAbiName(dst_bits),
10744 }) catch unreachable,
10745 } }, &.{ty_op.operand});
10746 }
1060910747
10610 try self.asmRegisterRegister(
10611 @as(?Mir.Inst.FixedTag, switch (src_ty.zigTypeTag(mod)) {
10612 .Float => switch (src_ty.floatBits(self.target.*)) {
10748 if (dst_size > 8) return self.fail("TODO implement airIntFromFloat from {} to {}", .{
10749 src_ty.fmt(mod), dst_ty.fmt(mod),
10750 });
10751
10752 const src_mcv = try self.resolveInst(ty_op.operand);
10753 const src_reg = if (src_mcv.isRegister())
10754 src_mcv.getReg().?
10755 else
10756 try self.copyToTmpRegister(src_ty, src_mcv);
10757 const src_lock = self.register_manager.lockRegAssumeUnused(src_reg);
10758 defer self.register_manager.unlockReg(src_lock);
10759
10760 const dst_reg = try self.register_manager.allocReg(inst, regClassForType(dst_ty, mod));
10761 const dst_mcv = MCValue{ .register = dst_reg };
10762 const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
10763 defer self.register_manager.unlockReg(dst_lock);
10764
10765 try self.asmRegisterRegister(
10766 switch (src_bits) {
1061310767 32 => if (self.hasFeature(.avx)) .{ .v_, .cvttss2si } else .{ ._, .cvttss2si },
1061410768 64 => if (self.hasFeature(.avx)) .{ .v_, .cvttsd2si } else .{ ._, .cvttsd2si },
10615 16, 80, 128 => null,
1061610769 else => unreachable,
1061710770 },
10618 else => null,
10619 }) orelse return self.fail("TODO implement airIntFromFloat from {} to {}", .{
10620 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
10621 }),
10622 registerAlias(dst_reg, dst_size),
10623 src_reg.to128(),
10624 );
10771 registerAlias(dst_reg, dst_size),
10772 src_reg.to128(),
10773 );
1062510774
10626 if (dst_bits < dst_size * 8) try self.truncateRegister(dst_ty, dst_reg);
10775 if (dst_bits < dst_size * 8) try self.truncateRegister(dst_ty, dst_reg);
1062710776
10628 return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
10777 break :result dst_mcv;
10778 };
10779 return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
1062910780}
1063010781
1063110782fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void {
......@@ -12276,3 +12427,30 @@ fn typeOfIndex(self: *Self, inst: Air.Inst.Index) Type {
1227612427 const mod = self.bin_file.options.module.?;
1227712428 return self.air.typeOfIndex(inst, &mod.intern_pool);
1227812429}
12430
12431fn intCompilerRtAbiName(int_bits: u32) u8 {
12432 return switch (int_bits) {
12433 1...32 => 's',
12434 33...64 => 'd',
12435 65...128 => 't',
12436 else => unreachable,
12437 };
12438}
12439
12440fn floatCompilerRtAbiName(float_bits: u32) u8 {
12441 return switch (float_bits) {
12442 16 => 'h',
12443 32 => 's',
12444 64 => 'd',
12445 80 => 'x',
12446 128 => 't',
12447 else => unreachable,
12448 };
12449}
12450
12451fn floatCompilerRtAbiType(self: *Self, ty: Type, other_ty: Type) Type {
12452 if (ty.toIntern() == .f16_type and
12453 (other_ty.toIntern() == .f32_type or other_ty.toIntern() == .f64_type) and
12454 self.target.isDarwin()) return Type.u16;
12455 return ty;
12456}
test/behavior/asm.zig-2
......@@ -85,7 +85,6 @@ test "alternative constraints" {
8585
8686test "sized integer/float in asm input" {
8787 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
88 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
8988 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
9089 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
9190 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -137,7 +136,6 @@ test "sized integer/float in asm input" {
137136
138137test "struct/array/union types as input values" {
139138 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
140 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
141139 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
142140 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
143141 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/bitcast.zig-2
......@@ -470,7 +470,6 @@ test "@bitCast of packed struct of bools all true" {
470470 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
471471 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
472472 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
473 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
474473 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
475474 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
476475
......@@ -492,7 +491,6 @@ test "@bitCast of packed struct of bools all false" {
492491 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
493492 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
494493 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
495 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
496494 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
497495 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
498496
test/behavior/bugs/12680.zig+2-1
......@@ -9,9 +9,10 @@ test "export a function twice" {
99 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
1010 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
1111 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
12 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1312 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1413 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
14 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
15
1516 if (builtin.os.tag == .macos and builtin.zig_backend == .stage2_c) {
1617 // TODO: test.c: error: aliases are not supported on darwin
1718 return error.SkipZigTest;
test/behavior/bugs/529.zig+1-1
......@@ -11,11 +11,11 @@ comptime {
1111const builtin = @import("builtin");
1212
1313test "issue 529 fixed" {
14 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1514 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1615 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1716 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1817 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
18 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
1919
2020 @import("529_other_file.zig").issue529(null);
2121 issue529(null);
test/behavior/cast.zig-23
......@@ -1611,7 +1611,6 @@ test "coercion from single-item pointer to @as to slice" {
16111611test "peer type resolution: const sentinel slice and mutable non-sentinel slice" {
16121612 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16131613 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1614 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16151614 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
16161615 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
16171616 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1664,7 +1663,6 @@ test "peer type resolution: float and comptime-known fixed-width integer" {
16641663test "peer type resolution: same array type with sentinel" {
16651664 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16661665 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1667 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16681666 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
16691667 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
16701668 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1687,7 +1685,6 @@ test "peer type resolution: same array type with sentinel" {
16871685test "peer type resolution: array with sentinel and array without sentinel" {
16881686 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16891687 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1690 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16911688 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
16921689 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
16931690 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1710,7 +1707,6 @@ test "peer type resolution: array with sentinel and array without sentinel" {
17101707test "peer type resolution: array and vector with same child type" {
17111708 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
17121709 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1713 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
17141710 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
17151711 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
17161712 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1756,7 +1752,6 @@ test "peer type resolution: array with smaller child type and vector with larger
17561752test "peer type resolution: error union and optional of same type" {
17571753 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
17581754 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1759 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
17601755 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
17611756 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
17621757 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1780,7 +1775,6 @@ test "peer type resolution: error union and optional of same type" {
17801775test "peer type resolution: C pointer and @TypeOf(null)" {
17811776 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
17821777 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1783 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
17841778 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
17851779 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
17861780 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1803,7 +1797,6 @@ test "peer type resolution: C pointer and @TypeOf(null)" {
18031797test "peer type resolution: three-way resolution combines error set and optional" {
18041798 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
18051799 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1806 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
18071800 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
18081801 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
18091802 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1846,7 +1839,6 @@ test "peer type resolution: three-way resolution combines error set and optional
18461839test "peer type resolution: vector and optional vector" {
18471840 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
18481841 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1849 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
18501842 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
18511843 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
18521844 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1869,7 +1861,6 @@ test "peer type resolution: vector and optional vector" {
18691861test "peer type resolution: optional fixed-width int and comptime_int" {
18701862 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
18711863 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1872 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
18731864 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
18741865 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
18751866 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1892,7 +1883,6 @@ test "peer type resolution: optional fixed-width int and comptime_int" {
18921883test "peer type resolution: array and tuple" {
18931884 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
18941885 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1895 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
18961886 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
18971887 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
18981888 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1916,7 +1906,6 @@ test "peer type resolution: array and tuple" {
19161906test "peer type resolution: vector and tuple" {
19171907 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
19181908 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1919 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
19201909 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
19211910 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
19221911 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1940,7 +1929,6 @@ test "peer type resolution: vector and tuple" {
19401929test "peer type resolution: vector and array and tuple" {
19411930 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
19421931 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1943 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
19441932 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
19451933 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
19461934 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -1983,7 +1971,6 @@ test "peer type resolution: vector and array and tuple" {
19831971test "peer type resolution: empty tuple pointer and slice" {
19841972 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
19851973 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1986 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
19871974 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
19881975 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
19891976 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2005,7 +1992,6 @@ test "peer type resolution: empty tuple pointer and slice" {
20051992test "peer type resolution: tuple pointer and slice" {
20061993 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
20071994 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2008 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
20091995 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
20101996 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
20111997 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2027,7 +2013,6 @@ test "peer type resolution: tuple pointer and slice" {
20272013test "peer type resolution: tuple pointer and optional slice" {
20282014 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
20292015 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2030 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
20312016 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
20322017 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
20332018 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2049,7 +2034,6 @@ test "peer type resolution: tuple pointer and optional slice" {
20492034test "peer type resolution: many compatible pointers" {
20502035 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
20512036 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2052 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
20532037 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
20542038 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
20552039 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2116,7 +2100,6 @@ test "peer type resolution: many compatible pointers" {
21162100test "peer type resolution: tuples with comptime fields" {
21172101 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
21182102 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2119 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
21202103 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
21212104 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
21222105 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2149,7 +2132,6 @@ test "peer type resolution: tuples with comptime fields" {
21492132test "peer type resolution: C pointer and many pointer" {
21502133 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
21512134 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2152 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
21532135 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
21542136 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
21552137 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2173,7 +2155,6 @@ test "peer type resolution: C pointer and many pointer" {
21732155test "peer type resolution: pointer attributes are combined correctly" {
21742156 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
21752157 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2176 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
21772158 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
21782159 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
21792160 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2218,7 +2199,6 @@ test "peer type resolution: pointer attributes are combined correctly" {
22182199test "cast builtins can wrap result in optional" {
22192200 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
22202201 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2221 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
22222202 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
22232203 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
22242204 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2258,7 +2238,6 @@ test "cast builtins can wrap result in optional" {
22582238test "cast builtins can wrap result in error union" {
22592239 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
22602240 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2261 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
22622241 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
22632242 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
22642243
......@@ -2298,7 +2277,6 @@ test "cast builtins can wrap result in error union" {
22982277test "cast builtins can wrap result in error union and optional" {
22992278 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
23002279 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
2301 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
23022280 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
23032281 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
23042282 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
......@@ -2496,7 +2474,6 @@ test "@as does not corrupt values with incompatible representations" {
24962474
24972475test "result information is preserved through many nested structures" {
24982476 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
2499 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
25002477 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
25012478 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
25022479 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/defer.zig-1
......@@ -133,7 +133,6 @@ test "errdefer with payload" {
133133}
134134
135135test "reference to errdefer payload" {
136 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
137136 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
138137 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
139138 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
test/behavior/floatop.zig+1-2
......@@ -23,7 +23,6 @@ test "cmp f16" {
2323 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
2424 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
2525 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
26 if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
2726
2827 try testCmp(f16);
2928 try comptime testCmp(f16);
......@@ -115,7 +114,7 @@ test "different sized float comparisons" {
115114 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
116115 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
117116 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
118 if (no_x86_64_hardware_f16_support) return error.SkipZigTest;
117 if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
119118
120119 try testDifferentSizedFloatComparisons();
121120 try comptime testDifferentSizedFloatComparisons();
test/behavior/struct.zig-2
......@@ -1651,7 +1651,6 @@ test "instantiate struct with comptime field" {
16511651test "struct field pointer has correct alignment" {
16521652 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
16531653 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1654 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16551654 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
16561655 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16571656 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -1684,7 +1683,6 @@ test "struct field pointer has correct alignment" {
16841683test "extern struct field pointer has correct alignment" {
16851684 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
16861685 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1687 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16881686 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
16891687 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16901688 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/union.zig-3
......@@ -1534,7 +1534,6 @@ test "coerce enum literal to union in result loc" {
15341534test "defined-layout union field pointer has correct alignment" {
15351535 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
15361536 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1537 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
15381537 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
15391538 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
15401539 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -1572,7 +1571,6 @@ test "defined-layout union field pointer has correct alignment" {
15721571test "undefined-layout union field pointer has correct alignment" {
15731572 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
15741573 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1575 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
15761574 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
15771575 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
15781576 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -1610,7 +1608,6 @@ test "undefined-layout union field pointer has correct alignment" {
16101608test "packed union field pointer has correct alignment" {
16111609 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
16121610 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1613 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16141611 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
16151612 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
16161613 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO