authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-20 23:14:35-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-20 23:14:35-05:00
log89e107ee4ecdc888007958bd353e293856f0766f
treec6c83389629b72c02e24e3d045c0d6c2ecb12ab8
parent6dd514ac8aa3ee2e5c6fd0374469d361ccfce5b9
signature Commit is signed but in an unrecognized format.

uncomment all the archs in target.zig

3 files changed, 59 insertions(+), 70 deletions(-)

BRANCH_TODO-31
......@@ -2,35 +2,4 @@ Finish these thigns before merging teh branch
22
33 * zig targets
44 - use non-reflection based cpu detection?
5 * finish refactoring target/arch/*
65
7
8const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
9 &std.target.riscv.feature_a,
10 &std.target.riscv.feature_c,
11 &std.target.riscv.feature_d,
12 &std.target.riscv.feature_f,
13 &std.target.riscv.feature_m,
14 &std.target.riscv.feature_relax,
15};
16
17const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
18 &std.target.riscv.feature_bit64,
19 &std.target.riscv.feature_a,
20 &std.target.riscv.feature_c,
21 &std.target.riscv.feature_d,
22 &std.target.riscv.feature_f,
23 &std.target.riscv.feature_m,
24 &std.target.riscv.feature_relax,
25};
26
27// Same as above but without sse.
28const i386_default_features_freestanding: []*const std.target.Feature = &[_]*const std.target.Feature{
29 &std.target.x86.feature_cmov,
30 &std.target.x86.feature_cx8,
31 &std.target.x86.feature_fxsr,
32 &std.target.x86.feature_mmx,
33 &std.target.x86.feature_nopl,
34 &std.target.x86.feature_slowUnalignedMem16,
35 &std.target.x86.feature_x87,
36};
lib/std/target.zig+40-39
......@@ -413,21 +413,21 @@ pub const Target = union(enum) {
413413 /// All CPU features Zig is aware of, sorted lexicographically by name.
414414 pub fn allFeaturesList(arch: Arch) []const Cpu.Feature {
415415 return switch (arch) {
416 // TODO .arm, .armeb, .thumb, .thumbeb => arm.all_features,
416 .arm, .armeb, .thumb, .thumbeb => arm.all_features,
417417 .aarch64, .aarch64_be, .aarch64_32 => &aarch64.all_features,
418 // TODO .avr => avr.all_features,
419 // TODO .bpfel, .bpfeb => bpf.all_features,
420 // TODO .hexagon => hexagon.all_features,
421 // TODO .mips, .mipsel, .mips64, .mips64el => mips.all_features,
422 // TODO .msp430 => msp430.all_features,
423 // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.all_features,
424 // TODO .amdgcn => amdgpu.all_features,
425 // TODO .riscv32, .riscv64 => riscv.all_features,
426 // TODO .sparc, .sparcv9, .sparcel => sparc.all_features,
427 // TODO .s390x => systemz.all_features,
418 .avr => avr.all_features,
419 .bpfel, .bpfeb => bpf.all_features,
420 .hexagon => hexagon.all_features,
421 .mips, .mipsel, .mips64, .mips64el => mips.all_features,
422 .msp430 => msp430.all_features,
423 .powerpc, .powerpc64, .powerpc64le => powerpc.all_features,
424 .amdgcn => amdgpu.all_features,
425 .riscv32, .riscv64 => riscv.all_features,
426 .sparc, .sparcv9, .sparcel => sparc.all_features,
427 .s390x => systemz.all_features,
428428 .i386, .x86_64 => &x86.all_features,
429 // TODO .nvptx, .nvptx64 => nvptx.all_features,
430 // TODO .wasm32, .wasm64 => wasm.all_features,
429 .nvptx, .nvptx64 => nvptx.all_features,
430 .wasm32, .wasm64 => wasm.all_features,
431431
432432 else => &[0]Cpu.Feature{},
433433 };
......@@ -437,22 +437,23 @@ pub const Target = union(enum) {
437437 /// of features that is expected to be supported on most available hardware.
438438 pub fn baselineFeatures(arch: Arch) Cpu.Feature.Set {
439439 return switch (arch) {
440 // TODO .arm, .armeb, .thumb, .thumbeb => arm.baseline_features,
440 .arm, .armeb, .thumb, .thumbeb => arm.cpu.generic.features,
441441 .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpu.generic.features,
442 // TODO .avr => avr.baseline_features,
443 // TODO .bpfel, .bpfeb => bpf.baseline_features,
444 // TODO .hexagon => hexagon.baseline_features,
445 // TODO .mips, .mipsel, .mips64, .mips64el => mips.baseline_features,
446 // TODO .msp430 => msp430.baseline_features,
447 // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.baseline_features,
448 // TODO .amdgcn => amdgpu.baseline_features,
449 // TODO .riscv32, .riscv64 => riscv.baseline_features,
450 // TODO .sparc, .sparcv9, .sparcel => sparc.baseline_features,
451 // TODO .s390x => systemz.baseline_features,
442 .avr => avr.cpu.generic.features,
443 .bpfel, .bpfeb => bpf.cpu.generic.features,
444 .hexagon => hexagon.cpu.generic.features,
445 .mips, .mipsel, .mips64, .mips64el => mips.cpu.generic.features,
446 .msp430 => msp430.cpu.generic.features,
447 .powerpc, .powerpc64, .powerpc64le => powerpc.cpu.generic.features,
448 .amdgcn => amdgpu.cpu.generic.features,
449 .riscv32 => riscv.baseline_32_features,
450 .riscv64 => riscv.baseline_64_features,
451 .sparc, .sparcv9, .sparcel => sparc.cpu.generic.features,
452 .s390x => systemz.cpu.generic.features,
452453 .i386 => x86.cpu.pentium4.features,
453454 .x86_64 => x86.cpu.x86_64.features,
454 // TODO .nvptx, .nvptx64 => nvptx.baseline_features,
455 // TODO .wasm32, .wasm64 => wasm.baseline_features,
455 .nvptx, .nvptx64 => nvptx.cpu.generic.features,
456 .wasm32, .wasm64 => wasm.cpu.generic.features,
456457
457458 else => 0,
458459 };
......@@ -461,21 +462,21 @@ pub const Target = union(enum) {
461462 /// All CPUs Zig is aware of, sorted lexicographically by name.
462463 pub fn allCpus(arch: Arch) []const *const Cpu {
463464 return switch (arch) {
464 // TODO .arm, .armeb, .thumb, .thumbeb => arm.all_cpus,
465 .arm, .armeb, .thumb, .thumbeb => arm.all_cpus,
465466 .aarch64, .aarch64_be, .aarch64_32 => aarch64.all_cpus,
466 // TODO .avr => avr.all_cpus,
467 // TODO .bpfel, .bpfeb => bpf.all_cpus,
468 // TODO .hexagon => hexagon.all_cpus,
469 // TODO .mips, .mipsel, .mips64, .mips64el => mips.all_cpus,
470 // TODO .msp430 => msp430.all_cpus,
471 // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.all_cpus,
472 // TODO .amdgcn => amdgpu.all_cpus,
473 // TODO .riscv32, .riscv64 => riscv.all_cpus,
474 // TODO .sparc, .sparcv9, .sparcel => sparc.all_cpus,
475 // TODO .s390x => systemz.all_cpus,
467 .avr => avr.all_cpus,
468 .bpfel, .bpfeb => bpf.all_cpus,
469 .hexagon => hexagon.all_cpus,
470 .mips, .mipsel, .mips64, .mips64el => mips.all_cpus,
471 .msp430 => msp430.all_cpus,
472 .powerpc, .powerpc64, .powerpc64le => powerpc.all_cpus,
473 .amdgcn => amdgpu.all_cpus,
474 .riscv32, .riscv64 => riscv.all_cpus,
475 .sparc, .sparcv9, .sparcel => sparc.all_cpus,
476 .s390x => systemz.all_cpus,
476477 .i386, .x86_64 => x86.all_cpus,
477 // TODO .nvptx, .nvptx64 => nvptx.all_cpus,
478 // TODO .wasm32, .wasm64 => wasm.all_cpus,
478 .nvptx, .nvptx64 => nvptx.all_cpus,
479 .wasm32, .wasm64 => wasm.all_cpus,
479480
480481 else => &[0]*const Cpu{},
481482 };
lib/std/target/riscv.zig+19
......@@ -101,3 +101,22 @@ pub const all_cpus = &[_]*const Cpu{
101101 &cpu.generic_rv32,
102102 &cpu.generic_rv64,
103103};
104
105pub const baseline_32_features = featureSet(&[_]Feature{
106 .a,
107 .c,
108 .d,
109 .f,
110 .m,
111 .relax,
112});
113
114pub const baseline_64_features = featureSet(&[_]Feature{
115 .@"64bit",
116 .a,
117 .c,
118 .d,
119 .f,
120 .m,
121 .relax,
122});