authorgravatar for xtex@astrafall.orgxtex <xtex@astrafall.org> 2026-03-08 09:40:23+08:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-05-22 21:15:32+02:00
log8b220cd746384c43e8406b70e93f76afe7a6db48
tree2a0a666acdbb3c7be02987d50672a41357692e64
parent34c2b5e9d1b15ab9d8988f7919df967f3c405187
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.loongarch: take HWCAP into consideration

We prefer information from HWCAP than CPUCFG and assume those features unavailable if HWCAP is not available. This is because many features require kernel support (e.g. context switching support). Follow-up: 37288e53ae4e ("std.zig.system.loongarch: implement individual cpu feature bit tests (#30915)") Change-Id: I0a610b2c4fc751f0f159e79e01bb9f6fb7588ccf Signed-off-by: xtex <xtex@astrafall.org>

1 files changed, 25 insertions(+), 9 deletions(-)

lib/std/zig/system/loongarch.zig+25-9
...@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(...@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(
3131
32 cpu.features.addFeatureSet(cpu.model.features);32 cpu.features.addFeatureSet(cpu.model.features);
3333
34 const cfg1 = cpucfg(1);
35 const cfg2 = cpucfg(2);34 const cfg2 = cpucfg(2);
36 const cfg3 = cpucfg(3);35 const cfg3 = cpucfg(3);
3736
38 setFeature(&cpu, .ual, bit(cfg1, 20));37 if (builtin.os.tag == .linux) {
38 const HWCAP = std.os.linux.HWCAP;
39 const hwcap_bits: usize = if (builtin.link_libc)
40 std.c.getauxval(std.elf.AT_HWCAP)
41 else
42 std.os.linux.getauxval(std.elf.AT_HWCAP);
3943
40 const has_fpu = bit(cfg2, 0);44 setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
41 setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
42 setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
4345
44 setFeature(&cpu, .lsx, bit(cfg2, 6));46 const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
45 setFeature(&cpu, .lasx, bit(cfg2, 7));47 setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
46 setFeature(&cpu, .lvz, bit(cfg2, 10));48 setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
49 setFeature(&cpu, .lsx, (hwcap_bits & HWCAP.LSX) != 0);
50 setFeature(&cpu, .lasx, (hwcap_bits & HWCAP.LASX) != 0);
4751
48 setFeature(&cpu, .lbt, bit(cfg2, 18) and bit(cfg2, 19) and bit(cfg2, 20));52 setFeature(&cpu, .lvz, (hwcap_bits & HWCAP.LVZ) != 0);
53 setFeature(&cpu, .lbt, (hwcap_bits & HWCAP.LBT_X86) != 0 and (hwcap_bits & HWCAP.LBT_ARM) != 0 and (hwcap_bits & HWCAP.LBT_MIPS) != 0);
54 } else {
55 setFeature(&cpu, .ual, false);
56
57 setFeature(&cpu, .f, false);
58 setFeature(&cpu, .d, false);
59 setFeature(&cpu, .lsx, false);
60 setFeature(&cpu, .lasx, false);
61
62 setFeature(&cpu, .lvz, false);
63 setFeature(&cpu, .lbt, false);
64 }
4965
50 setFeature(&cpu, .frecipe, bit(cfg2, 25));66 setFeature(&cpu, .frecipe, bit(cfg2, 25));
51 setFeature(&cpu, .div32, bit(cfg2, 26));67 setFeature(&cpu, .div32, bit(cfg2, 26));