| author |  Jacob Young <jacobly@ziglang.org> 2023-04-20 00:49:38-04:00 |
| committer | Jacob Young <jacobly@ziglang.org> 2023-04-21 16:36:31-04:00 |
| log | a1ed4bd7966b1a3283a2c03b1e0d7a1548dd3a0f |
| tree | ffed4a8f6c2053ec330f12b34f63c3d14f374bda |
| parent | d98974e826791e4546a72599a1a5fb24692d5acf |
cbe: fix remaining aarch64 issues
6 files changed, 25 insertions(+), 16 deletions(-)
lib
std
src
codegen
lib/std/crypto/aes.zig+1-1
| ... | @@ -8,7 +8,7 @@ const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes); | ... | @@ -8,7 +8,7 @@ const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes); |
| 8 | // C backend doesn't currently support passing vectors to inline asm. | 8 | // C backend doesn't currently support passing vectors to inline asm. |
| 9 | const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_aesni and has_avx) impl: { | 9 | const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_aesni and has_avx) impl: { |
| 10 | break :impl @import("aes/aesni.zig"); | 10 | break :impl @import("aes/aesni.zig"); |
| 11 | } else if (builtin.cpu.arch == .aarch64 and has_armaes) | 11 | } else if (builtin.cpu.arch == .aarch64 and builtin.zig_backend != .stage2_c and has_armaes) |
| 12 | impl: { | 12 | impl: { |
| 13 | break :impl @import("aes/armcrypto.zig"); | 13 | break :impl @import("aes/armcrypto.zig"); |
| 14 | } else impl: { | 14 | } else impl: { |
lib/std/crypto/ghash_polyval.zig+1-1
| ... | @@ -251,7 +251,7 @@ fn Hash(comptime endian: std.builtin.Endian, comptime shift_key: bool) type { | ... | @@ -251,7 +251,7 @@ fn Hash(comptime endian: std.builtin.Endian, comptime shift_key: bool) type { |
| 251 | // C backend doesn't currently support passing vectors to inline asm. | 251 | // C backend doesn't currently support passing vectors to inline asm. |
| 252 | const clmul = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_pclmul and has_avx) impl: { | 252 | const clmul = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_pclmul and has_avx) impl: { |
| 253 | break :impl clmulPclmul; | 253 | break :impl clmulPclmul; |
| 254 | } else if (builtin.cpu.arch == .aarch64 and has_armaes) impl: { | 254 | } else if (builtin.cpu.arch == .aarch64 and builtin.zig_backend != .stage2_c and has_armaes) impl: { |
| 255 | break :impl clmulPmull; | 255 | break :impl clmulPmull; |
| 256 | } else impl: { | 256 | } else impl: { |
| 257 | break :impl clmulSoft; | 257 | break :impl clmulSoft; |
lib/std/crypto/sha2.zig+1-1
| ... | @@ -205,7 +205,7 @@ fn Sha2x32(comptime params: Sha2Params32) type { | ... | @@ -205,7 +205,7 @@ fn Sha2x32(comptime params: Sha2Params32) type { |
| 205 | 205 | ||
| 206 | if (!isComptime()) { | 206 | if (!isComptime()) { |
| 207 | switch (builtin.cpu.arch) { | 207 | switch (builtin.cpu.arch) { |
| 208 | .aarch64 => if (comptime std.Target.aarch64.featureSetHas(builtin.cpu.features, .sha2)) { | 208 | .aarch64 => if (builtin.zig_backend != .stage2_c and comptime std.Target.aarch64.featureSetHas(builtin.cpu.features, .sha2)) { |
| 209 | var x: v4u32 = d.s[0..4].*; | 209 | var x: v4u32 = d.s[0..4].*; |
| 210 | var y: v4u32 = d.s[4..8].*; | 210 | var y: v4u32 = d.s[4..8].*; |
| 211 | const s_v = @ptrCast(*[16]v4u32, &s); | 211 | const s_v = @ptrCast(*[16]v4u32, &s); |
src/codegen/c.zig+12-3
| ... | @@ -6070,9 +6070,18 @@ fn airAtomicRmw(f: *Function, inst: Air.Inst.Index) !CValue { | ... | @@ -6070,9 +6070,18 @@ fn airAtomicRmw(f: *Function, inst: Air.Inst.Index) !CValue { |
| 6070 | if (is_float) try writer.writeAll("_float"); | 6070 | if (is_float) try writer.writeAll("_float"); |
| 6071 | try writer.writeByte('('); | 6071 | try writer.writeByte('('); |
| 6072 | try f.writeCValue(writer, local, .Other); | 6072 | try f.writeCValue(writer, local, .Other); |
| 6073 | try writer.writeAll(", (zig_atomic("); | 6073 | try writer.writeAll(", ("); |
| 6074 | try f.renderType(writer, ty); | 6074 | switch (extra.op()) { |
| 6075 | try writer.writeByte(')'); | 6075 | else => { |
| 6076 | try writer.writeAll("zig_atomic("); | ||
| 6077 | try f.renderType(writer, ty); | ||
| 6078 | try writer.writeByte(')'); | ||
| 6079 | }, | ||
| 6080 | .Nand, .Min, .Max => { | ||
| 6081 | // These are missing from stdatomic.h, so no atomic types for now. | ||
| 6082 | try f.renderType(writer, ty); | ||
| 6083 | }, | ||
| 6084 | } | ||
| 6076 | if (ptr_ty.isVolatilePtr()) try writer.writeAll(" volatile"); | 6085 | if (ptr_ty.isVolatilePtr()) try writer.writeAll(" volatile"); |
| 6077 | try writer.writeAll(" *)"); | 6086 | try writer.writeAll(" *)"); |
| 6078 | try f.writeCValue(writer, ptr, .Other); | 6087 | try f.writeCValue(writer, ptr, .Other); |
test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_.Sub_.Max_or_.Min.zig created+10
| ... | @@ -0,0 +1,10 @@ | ||
| 1 | export fn entry() void { | ||
| 2 | var x: f32 = 0; | ||
| 3 | _ = @atomicRmw(f32, &x, .And, 2, .SeqCst); | ||
| 4 | } | ||
| 5 | |||
| 6 | // error | ||
| 7 | // backend=stage2 | ||
| 8 | // target=native | ||
| 9 | // | ||
| 10 | // :3:30: error: @atomicRmw with float only allowed with .Xchg, .Add, .Sub, .Max, and .Min | ||
test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_or_.Sub.zig deleted-10
| ... | @@ -1,10 +0,0 @@ | ||
| 1 | export fn entry() void { | ||
| 2 | var x: f32 = 0; | ||
| 3 | _ = @atomicRmw(f32, &x, .And, 2, .SeqCst); | ||
| 4 | } | ||
| 5 | |||
| 6 | // error | ||
| 7 | // backend=stage2 | ||
| 8 | // target=native | ||
| 9 | // | ||
| 10 | // :3:30: error: @atomicRmw with float only allowed with .Xchg, .Add, and .Sub | ||