| author |  Andrew Kelley <andrew@ziglang.org> 2021-02-27 01:49:09-07:00 |
| committer | Andrew Kelley <andrew@ziglang.org> 2021-02-27 01:49:35-07:00 |
| log | a9f19221e99d9470d936f63ecfa20c735e175a2c |
| tree | a4fbff925d0cef1cce369b4e78b01690504f2e0e |
| parent | 50a5fc98dc7d458cb731980d1231ee6e1a7eb880 |
update RISC-V target CPU features
2 files changed, 68 insertions(+), 12 deletions(-)
lib
std
target
lib/std/target/riscv.zig+10-10
| ... | ... | @@ -1,8 +1,5 @@ |
| 1 | // SPDX-License-Identifier: MIT | |
| 2 | // Copyright (c) 2015-2021 Zig Contributors | |
| 3 | // This file is part of [zig](https://ziglang.org/), which is MIT licensed. | |
| 4 | // The MIT license requires this copyright notice to be included in all copies | |
| 5 | // and substantial portions of the software. | |
| 1 | //! This file is auto-generated by tools/update_cpu_features.zig. | |
| 2 | ||
| 6 | 3 | const std = @import("../std.zig"); |
| 7 | 4 | const CpuFeature = std.Target.Cpu.Feature; |
| 8 | 5 | const CpuModel = std.Target.Cpu.Model; |
| ... | ... | @@ -15,6 +12,7 @@ pub const Feature = enum { |
| 15 | 12 | e, |
| 16 | 13 | experimental_b, |
| 17 | 14 | experimental_v, |
| 15 | experimental_zba, | |
| 18 | 16 | experimental_zbb, |
| 19 | 17 | experimental_zbc, |
| 20 | 18 | experimental_zbe, |
| ... | ... | @@ -103,6 +101,7 @@ pub const all_features = blk: { |
| 103 | 101 | .llvm_name = "experimental-b", |
| 104 | 102 | .description = "'B' (Bit Manipulation Instructions)", |
| 105 | 103 | .dependencies = featureSet(&[_]Feature{ |
| 104 | .experimental_zba, | |
| 106 | 105 | .experimental_zbb, |
| 107 | 106 | .experimental_zbc, |
| 108 | 107 | .experimental_zbe, |
| ... | ... | @@ -117,9 +116,12 @@ pub const all_features = blk: { |
| 117 | 116 | result[@enumToInt(Feature.experimental_v)] = .{ |
| 118 | 117 | .llvm_name = "experimental-v", |
| 119 | 118 | .description = "'V' (Vector Instructions)", |
| 120 | .dependencies = featureSet(&[_]Feature{ | |
| 121 | .f, | |
| 122 | }), | |
| 119 | .dependencies = featureSet(&[_]Feature{}), | |
| 120 | }; | |
| 121 | result[@enumToInt(Feature.experimental_zba)] = .{ | |
| 122 | .llvm_name = "experimental-zba", | |
| 123 | .description = "'Zba' (Address calculation 'B' Instructions)", | |
| 124 | .dependencies = featureSet(&[_]Feature{}), | |
| 123 | 125 | }; |
| 124 | 126 | result[@enumToInt(Feature.experimental_zbb)] = .{ |
| 125 | 127 | .llvm_name = "experimental-zbb", |
| ... | ... | @@ -467,7 +469,6 @@ pub const cpu = struct { |
| 467 | 469 | .a, |
| 468 | 470 | .c, |
| 469 | 471 | .d, |
| 470 | .f, | |
| 471 | 472 | .m, |
| 472 | 473 | }), |
| 473 | 474 | }; |
| ... | ... | @@ -479,7 +480,6 @@ pub const cpu = struct { |
| 479 | 480 | .a, |
| 480 | 481 | .c, |
| 481 | 482 | .d, |
| 482 | .f, | |
| 483 | 483 | .m, |
| 484 | 484 | }), |
| 485 | 485 | }; |
tools/update_cpu_features.zig+58-2
| ... | ... | @@ -11,11 +11,18 @@ const FeatureOverride = struct { |
| 11 | 11 | desc: ?[]const u8 = null, |
| 12 | 12 | }; |
| 13 | 13 | |
| 14 | const ExtraCpu = struct { | |
| 15 | llvm_name: ?[]const u8, | |
| 16 | zig_name: []const u8, | |
| 17 | features: []const []const u8, | |
| 18 | }; | |
| 19 | ||
| 14 | 20 | const LlvmTarget = struct { |
| 15 | 21 | zig_name: []const u8, |
| 16 | 22 | llvm_name: []const u8, |
| 17 | 23 | td_name: []const u8, |
| 18 | 24 | feature_overrides: []const FeatureOverride = &.{}, |
| 25 | extra_cpus: []const ExtraCpu = &.{}, | |
| 19 | 26 | branch_quota: ?usize = null, |
| 20 | 27 | }; |
| 21 | 28 | |
| ... | ... | @@ -98,6 +105,18 @@ const llvm_targets = [_]LlvmTarget{ |
| 98 | 105 | .zig_name = "riscv", |
| 99 | 106 | .llvm_name = "RISCV", |
| 100 | 107 | .td_name = "RISCV.td", |
| 108 | .extra_cpus = &.{ | |
| 109 | .{ | |
| 110 | .llvm_name = null, | |
| 111 | .zig_name = "baseline_rv32", | |
| 112 | .features = &.{ "a", "c", "d", "f", "m" }, | |
| 113 | }, | |
| 114 | .{ | |
| 115 | .llvm_name = null, | |
| 116 | .zig_name = "baseline_rv64", | |
| 117 | .features = &.{ "64bit", "a", "c", "d", "f", "m" }, | |
| 118 | }, | |
| 119 | }, | |
| 101 | 120 | }, |
| 102 | 121 | .{ |
| 103 | 122 | .zig_name = "sparc", |
| ... | ... | @@ -433,7 +452,44 @@ fn processOneTarget(job: Job) anyerror!void { |
| 433 | 452 | \\pub const cpu = struct { |
| 434 | 453 | \\ |
| 435 | 454 | ); |
| 436 | ||
| 455 | for (llvm_target.extra_cpus) |extra_cpu| { | |
| 456 | try w.print( | |
| 457 | \\ pub const {} = CpuModel{{ | |
| 458 | \\ .name = "{}", | |
| 459 | \\ | |
| 460 | , .{ | |
| 461 | std.zig.fmtId(extra_cpu.zig_name), | |
| 462 | std.zig.fmtEscapes(extra_cpu.zig_name), | |
| 463 | }); | |
| 464 | if (extra_cpu.llvm_name) |llvm_name| { | |
| 465 | try w.print( | |
| 466 | \\ .llvm_name = "{}", | |
| 467 | \\ .features = featureSet(&[_]Feature{{ | |
| 468 | , .{std.zig.fmtEscapes(llvm_name)}); | |
| 469 | } else { | |
| 470 | try w.writeAll( | |
| 471 | \\ .llvm_name = null, | |
| 472 | \\ .features = featureSet(&[_]Feature{ | |
| 473 | ); | |
| 474 | } | |
| 475 | if (extra_cpu.features.len == 0) { | |
| 476 | try w.writeAll( | |
| 477 | \\}), | |
| 478 | \\ }; | |
| 479 | \\ | |
| 480 | ); | |
| 481 | } else { | |
| 482 | try w.writeAll("\n"); | |
| 483 | for (extra_cpu.features) |feature_zig_name| { | |
| 484 | try w.print(" .{},\n", .{std.zig.fmtId(feature_zig_name)}); | |
| 485 | } | |
| 486 | try w.writeAll( | |
| 487 | \\ }), | |
| 488 | \\ }; | |
| 489 | \\ | |
| 490 | ); | |
| 491 | } | |
| 492 | } | |
| 437 | 493 | for (all_cpus.items) |obj| { |
| 438 | 494 | const llvm_name = obj.get("Name").?.String; |
| 439 | 495 | var deps_set = std.StringHashMap(void).init(arena); |
| ... | ... | @@ -516,7 +572,7 @@ fn usageAndExit(file: fs.File, arg0: []const u8, code: u8) noreturn { |
| 516 | 572 | fn objectLessThan(context: void, a: *json.ObjectMap, b: *json.ObjectMap) bool { |
| 517 | 573 | const a_key = a.get("Name").?.String; |
| 518 | 574 | const b_key = b.get("Name").?.String; |
| 519 | return std.mem.lessThan(u8, a_key, b_key); | |
| 575 | return std.ascii.lessThanIgnoreCase(a_key, b_key); | |
| 520 | 576 | } |
| 521 | 577 | |
| 522 | 578 | fn llvmNameToZigName( |