authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2021-01-10 20:50:38+01:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-01-16 12:06:31-08:00
logd2a297c2b3eb293b393f41640892ff7a5a71027f
tree08f48ee321f3114ba6eebc71c592f40ca8247d1c
parentfbd5fbe729b7d3f085d2d479ed9957decc019332

stage2 ARM: add extra load/store instructions

2 files changed, 151 insertions(+), 25 deletions(-)

src/codegen.zig+51-25
......@@ -2630,21 +2630,34 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
26302630 .register => |reg| {
26312631 const abi_size = ty.abiSize(self.target.*);
26322632 const adj_off = stack_offset + abi_size;
2633 const offset = if (adj_off <= math.maxInt(u12)) blk: {
2634 break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
2635 } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
26362633
26372634 switch (abi_size) {
2638 1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.strb(.al, reg, .fp, .{
2639 .offset = offset,
2640 .positive = false,
2641 }).toU32()),
2642 2 => return self.fail(src, "TODO implement strh", .{}),
2643 4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{
2644 .offset = offset,
2645 .positive = false,
2646 }).toU32()),
2647 else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
2635 1, 4 => {
2636 const offset = if (adj_off <= math.maxInt(u12)) blk: {
2637 break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
2638 } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
2639 const str = switch (abi_size) {
2640 1 => Instruction.strb,
2641 4 => Instruction.str,
2642 else => unreachable,
2643 };
2644
2645 writeInt(u32, try self.code.addManyAsArray(4), str(.al, reg, .fp, .{
2646 .offset = offset,
2647 .positive = false,
2648 }).toU32());
2649 },
2650 2 => {
2651 const offset = if (adj_off <= math.maxInt(u8)) blk: {
2652 break :blk Instruction.ExtraLoadStoreOffset.imm(@intCast(u8, adj_off));
2653 } else Instruction.ExtraLoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }));
2654
2655 writeInt(u32, try self.code.addManyAsArray(4), Instruction.strh(.al, reg, .fp, .{
2656 .offset = offset,
2657 .positive = false,
2658 }).toU32());
2659 },
2660 else => return self.fail(src, "TODO implement storing other types abi_size={}", .{abi_size}),
26482661 }
26492662 },
26502663 .memory => |vaddr| {
......@@ -2836,20 +2849,33 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
28362849 // const abi_size = ty.abiSize(self.target.*);
28372850 const abi_size = 4;
28382851 const adj_off = unadjusted_off + abi_size;
2839 const offset = if (adj_off <= math.maxInt(u12)) blk: {
2840 break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
2841 } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
28422852
28432853 switch (abi_size) {
2844 1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrb(.al, reg, .fp, .{
2845 .offset = offset,
2846 .positive = false,
2847 }).toU32()),
2848 2 => return self.fail(src, "TODO implement ldrh", .{}),
2849 4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{
2850 .offset = offset,
2851 .positive = false,
2852 }).toU32()),
2854 1, 4 => {
2855 const offset = if (adj_off <= math.maxInt(u12)) blk: {
2856 break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
2857 } else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
2858 const ldr = switch (abi_size) {
2859 1 => Instruction.ldrb,
2860 4 => Instruction.ldr,
2861 else => unreachable,
2862 };
2863
2864 writeInt(u32, try self.code.addManyAsArray(4), ldr(.al, reg, .fp, .{
2865 .offset = offset,
2866 .positive = false,
2867 }).toU32());
2868 },
2869 2 => {
2870 const offset = if (adj_off <= math.maxInt(u8)) blk: {
2871 break :blk Instruction.ExtraLoadStoreOffset.imm(@intCast(u8, adj_off));
2872 } else Instruction.ExtraLoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }));
2873
2874 writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrh(.al, reg, .fp, .{
2875 .offset = offset,
2876 .positive = false,
2877 }).toU32());
2878 },
28532879 else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
28542880 }
28552881 },
src/codegen/arm.zig+100
......@@ -240,6 +240,22 @@ pub const Instruction = union(enum) {
240240 fixed: u2 = 0b01,
241241 cond: u4,
242242 },
243 ExtraLoadStore: packed struct {
244 imm4l: u4,
245 fixed_1: u1 = 0b1,
246 op2: u2,
247 fixed_2: u1 = 0b1,
248 imm4h: u4,
249 rt: u4,
250 rn: u4,
251 o1: u1,
252 write_back: u1,
253 imm: u1,
254 up_down: u1,
255 pre_index: u1,
256 fixed_3: u3 = 0b000,
257 cond: u4,
258 },
243259 BlockDataTransfer: packed struct {
244260 register_list: u16,
245261 rn: u4,
......@@ -468,6 +484,29 @@ pub const Instruction = union(enum) {
468484 }
469485 };
470486
487 /// Represents the offset operand of an extra load or store
488 /// instruction.
489 pub const ExtraLoadStoreOffset = union(enum) {
490 immediate: u8,
491 register: u4,
492
493 pub const none = ExtraLoadStoreOffset{
494 .immediate = 0,
495 };
496
497 pub fn reg(register: Register) ExtraLoadStoreOffset {
498 return ExtraLoadStoreOffset{
499 .register = register.id(),
500 };
501 }
502
503 pub fn imm(immediate: u8) ExtraLoadStoreOffset {
504 return ExtraLoadStoreOffset{
505 .immediate = immediate,
506 };
507 }
508 };
509
471510 /// Represents the register list operand to a block data transfer
472511 /// instruction
473512 pub const RegisterList = packed struct {
......@@ -495,6 +534,7 @@ pub const Instruction = union(enum) {
495534 .Multiply => |v| @bitCast(u32, v),
496535 .MultiplyLong => |v| @bitCast(u32, v),
497536 .SingleDataTransfer => |v| @bitCast(u32, v),
537 .ExtraLoadStore => |v| @bitCast(u32, v),
498538 .BlockDataTransfer => |v| @bitCast(u32, v),
499539 .Branch => |v| @bitCast(u32, v),
500540 .BranchExchange => |v| @bitCast(u32, v),
......@@ -617,6 +657,43 @@ pub const Instruction = union(enum) {
617657 };
618658 }
619659
660 fn extraLoadStore(
661 cond: Condition,
662 pre_index: bool,
663 positive: bool,
664 write_back: bool,
665 o1: u1,
666 op2: u2,
667 rn: Register,
668 rt: Register,
669 offset: ExtraLoadStoreOffset,
670 ) Instruction {
671 const imm4l: u4 = switch (offset) {
672 .immediate => |imm| @truncate(u4, imm),
673 .register => |reg| reg,
674 };
675 const imm4h: u4 = switch (offset) {
676 .immediate => |imm| @truncate(u4, imm >> 4),
677 .register => |reg| 0b0000,
678 };
679
680 return Instruction{
681 .ExtraLoadStore = .{
682 .imm4l = imm4l,
683 .op2 = op2,
684 .imm4h = imm4h,
685 .rt = rt.id(),
686 .rn = rn.id(),
687 .o1 = o1,
688 .write_back = @boolToInt(write_back),
689 .imm = @boolToInt(offset == .immediate),
690 .up_down = @boolToInt(positive),
691 .pre_index = @boolToInt(pre_index),
692 .cond = @enumToInt(cond),
693 },
694 };
695 }
696
620697 fn blockDataTransfer(
621698 cond: Condition,
622699 rn: Register,
......@@ -913,6 +990,23 @@ pub const Instruction = union(enum) {
913990 return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 0);
914991 }
915992
993 // Extra load/store
994
995 pub const ExtraLoadStoreOffsetArgs = struct {
996 pre_index: bool = true,
997 positive: bool = true,
998 offset: ExtraLoadStoreOffset,
999 write_back: bool = false,
1000 };
1001
1002 pub fn strh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
1003 return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 0, 0b01, rn, rt, args.offset);
1004 }
1005
1006 pub fn ldrh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
1007 return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 1, 0b01, rn, rt, args.offset);
1008 }
1009
9161010 // Block data transfer
9171011
9181012 pub fn ldmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
......@@ -1093,6 +1187,12 @@ test "serialize instructions" {
10931187 }),
10941188 .expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
10951189 },
1190 .{ // strh r1, [r5]
1191 .inst = Instruction.strh(.al, .r1, .r5, .{
1192 .offset = Instruction.ExtraLoadStoreOffset.none,
1193 }),
1194 .expected = 0b1110_000_1_1_1_0_0_0101_0001_0000_1011_0000,
1195 },
10961196 .{ // b #12
10971197 .inst = Instruction.b(.al, 12),
10981198 .expected = 0b1110_101_0_0000_0000_0000_0000_0000_0011,