| author | |
| committer | |
| log | d33766e6c7289b79256b2e50d0dc2344729ff710 |
| tree | 24da3981755618f82cfec5da88ebe5df791a708b |
| parent | ae6965a4e73cd5aad04e1c6831f48e7f0ecafc04 |
Throughout the stage1 code it is assumed that these have the same layout,
but that was not the case. This caused an issue on 32-bit hardware.4 files changed, 10 insertions(+), 3 deletions(-)
src/all_types.hpp+7-1| ... | ... | @@ -1324,6 +1324,7 @@ struct ZigTypeFloat { |
| 1324 | 1324 | size_t bit_count; |
| 1325 | 1325 | }; |
| 1326 | 1326 | |
| 1327 | // Needs to have the same memory layout as ZigTypeVector | |
| 1327 | 1328 | struct ZigTypeArray { |
| 1328 | 1329 | ZigType *child_type; |
| 1329 | 1330 | uint64_t len; |
| ... | ... | @@ -1512,12 +1513,17 @@ struct ZigTypeBoundFn { |
| 1512 | 1513 | ZigType *fn_type; |
| 1513 | 1514 | }; |
| 1514 | 1515 | |
| 1516 | // Needs to have the same memory layout as ZigTypeArray | |
| 1515 | 1517 | struct ZigTypeVector { |
| 1516 | 1518 | // The type must be a pointer, integer, bool, or float |
| 1517 | 1519 | ZigType *elem_type; |
| 1518 | uint32_t len; | |
| 1520 | uint64_t len; | |
| 1521 | size_t padding; | |
| 1519 | 1522 | }; |
| 1520 | 1523 | |
| 1524 | // A lot of code is relying on ZigTypeArray and ZigTypeVector having the same layout/size | |
| 1525 | static_assert(sizeof(ZigTypeVector) == sizeof(ZigTypeArray), "Size of ZigTypeVector and ZigTypeArray do not match!"); | |
| 1526 | ||
| 1521 | 1527 | enum ZigTypeId { |
| 1522 | 1528 | ZigTypeIdInvalid, |
| 1523 | 1529 | ZigTypeIdMetaType, |
src/analyze.cpp+1| ... | ... | @@ -5156,6 +5156,7 @@ ZigType *get_vector_type(CodeGen *g, uint32_t len, ZigType *elem_type) { |
| 5156 | 5156 | } |
| 5157 | 5157 | entry->data.vector.len = len; |
| 5158 | 5158 | entry->data.vector.elem_type = elem_type; |
| 5159 | entry->data.vector.padding = 0; | |
| 5159 | 5160 | |
| 5160 | 5161 | buf_resize(&entry->name, 0); |
| 5161 | 5162 | buf_appendf(&entry->name, "@Vector(%u, %s)", len, buf_ptr(&elem_type->name)); |
src/codegen.cpp+1-1| ... | ... | @@ -714,7 +714,7 @@ static LLVMValueRef get_arithmetic_overflow_fn(CodeGen *g, ZigType *operand_type |
| 714 | 714 | }; |
| 715 | 715 | |
| 716 | 716 | if (operand_type->id == ZigTypeIdVector) { |
| 717 | sprintf(fn_name, "llvm.%s.with.overflow.v%" PRIu32 "i%" PRIu32, signed_str, | |
| 717 | sprintf(fn_name, "llvm.%s.with.overflow.v%" PRIu64 "i%" PRIu32, signed_str, | |
| 718 | 718 | operand_type->data.vector.len, int_type->data.integral.bit_count); |
| 719 | 719 | |
| 720 | 720 | LLVMTypeRef return_elem_types[] = { |
src/ir.cpp+1-1| ... | ... | @@ -15953,7 +15953,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, IrInst *source_i |
| 15953 | 15953 | if (op1->value->type->id == ZigTypeIdVector && op2->value->type->id == ZigTypeIdVector) { |
| 15954 | 15954 | if (op1->value->type->data.vector.len != op2->value->type->data.vector.len) { |
| 15955 | 15955 | ir_add_error(ira, source_instr, |
| 15956 | buf_sprintf("vector length mismatch: %" PRIu32 " and %" PRIu32, | |
| 15956 | buf_sprintf("vector length mismatch: %" PRIu64 " and %" PRIu64, | |
| 15957 | 15957 | op1->value->type->data.vector.len, op2->value->type->data.vector.len)); |
| 15958 | 15958 | return ira->codegen->invalid_inst_gen; |
| 15959 | 15959 | } |