| ... | @@ -389,8 +389,6 @@ static void destroy_instruction_src(IrInstSrc *inst) { | ... | @@ -389,8 +389,6 @@ static void destroy_instruction_src(IrInstSrc *inst) { |
| 389 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatToInt *>(inst)); | 389 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcFloatToInt *>(inst)); |
| 390 | case IrInstSrcIdBoolToInt: | 390 | case IrInstSrcIdBoolToInt: |
| 391 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolToInt *>(inst)); | 391 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcBoolToInt *>(inst)); |
| 392 | case IrInstSrcIdIntType: | | |
| 393 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcIntType *>(inst)); | | |
| 394 | case IrInstSrcIdVectorType: | 392 | case IrInstSrcIdVectorType: |
| 395 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVectorType *>(inst)); | 393 | return heap::c_allocator.destroy(reinterpret_cast<IrInstSrcVectorType *>(inst)); |
| 396 | case IrInstSrcIdShuffleVector: | 394 | case IrInstSrcIdShuffleVector: |
| ... | @@ -1285,10 +1283,6 @@ static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolToInt *) { | ... | @@ -1285,10 +1283,6 @@ static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolToInt *) { |
| 1285 | return IrInstSrcIdBoolToInt; | 1283 | return IrInstSrcIdBoolToInt; |
| 1286 | } | 1284 | } |
| 1287 | | 1285 | |
| 1288 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntType *) { | | |
| 1289 | return IrInstSrcIdIntType; | | |
| 1290 | } | | |
| 1291 | | | |
| 1292 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcVectorType *) { | 1286 | static constexpr IrInstSrcId ir_inst_id(IrInstSrcVectorType *) { |
| 1293 | return IrInstSrcIdVectorType; | 1287 | return IrInstSrcIdVectorType; |
| 1294 | } | 1288 | } |
| ... | @@ -3518,19 +3512,6 @@ static IrInstSrc *ir_build_bool_to_int(IrBuilderSrc *irb, Scope *scope, AstNode | ... | @@ -3518,19 +3512,6 @@ static IrInstSrc *ir_build_bool_to_int(IrBuilderSrc *irb, Scope *scope, AstNode |
| 3518 | return &instruction->base; | 3512 | return &instruction->base; |
| 3519 | } | 3513 | } |
| 3520 | | 3514 | |
| 3521 | static IrInstSrc *ir_build_int_type(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *is_signed, | | |
| 3522 | IrInstSrc *bit_count) | | |
| 3523 | { | | |
| 3524 | IrInstSrcIntType *instruction = ir_build_instruction<IrInstSrcIntType>(irb, scope, source_node); | | |
| 3525 | instruction->is_signed = is_signed; | | |
| 3526 | instruction->bit_count = bit_count; | | |
| 3527 | | | |
| 3528 | ir_ref_instruction(is_signed, irb->current_basic_block); | | |
| 3529 | ir_ref_instruction(bit_count, irb->current_basic_block); | | |
| 3530 | | | |
| 3531 | return &instruction->base; | | |
| 3532 | } | | |
| 3533 | | | |
| 3534 | static IrInstSrc *ir_build_vector_type(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *len, | 3515 | static IrInstSrc *ir_build_vector_type(IrBuilderSrc *irb, Scope *scope, AstNode *source_node, IrInstSrc *len, |
| 3535 | IrInstSrc *elem_type) | 3516 | IrInstSrc *elem_type) |
| 3536 | { | 3517 | { |
| ... | @@ -6530,21 +6511,6 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod | ... | @@ -6530,21 +6511,6 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod |
| 6530 | IrInstSrc *result = ir_build_bool_to_int(irb, scope, node, arg0_value); | 6511 | IrInstSrc *result = ir_build_bool_to_int(irb, scope, node, arg0_value); |
| 6531 | return ir_lval_wrap(irb, scope, result, lval, result_loc); | 6512 | return ir_lval_wrap(irb, scope, result, lval, result_loc); |
| 6532 | } | 6513 | } |
| 6533 | case BuiltinFnIdIntType: | | |
| 6534 | { | | |
| 6535 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); | | |
| 6536 | IrInstSrc *arg0_value = ir_gen_node(irb, arg0_node, scope); | | |
| 6537 | if (arg0_value == irb->codegen->invalid_inst_src) | | |
| 6538 | return arg0_value; | | |
| 6539 | | | |
| 6540 | AstNode *arg1_node = node->data.fn_call_expr.params.at(1); | | |
| 6541 | IrInstSrc *arg1_value = ir_gen_node(irb, arg1_node, scope); | | |
| 6542 | if (arg1_value == irb->codegen->invalid_inst_src) | | |
| 6543 | return arg1_value; | | |
| 6544 | | | |
| 6545 | IrInstSrc *int_type = ir_build_int_type(irb, scope, node, arg0_value, arg1_value); | | |
| 6546 | return ir_lval_wrap(irb, scope, int_type, lval, result_loc); | | |
| 6547 | } | | |
| 6548 | case BuiltinFnIdVectorType: | 6514 | case BuiltinFnIdVectorType: |
| 6549 | { | 6515 | { |
| 6550 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); | 6516 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); |
| ... | @@ -7074,21 +7040,6 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod | ... | @@ -7074,21 +7040,6 @@ static IrInstSrc *ir_gen_builtin_fn_call(IrBuilderSrc *irb, Scope *scope, AstNod |
| 7074 | IrInstSrc *set_align_stack = ir_build_set_align_stack(irb, scope, node, arg0_value); | 7040 | IrInstSrc *set_align_stack = ir_build_set_align_stack(irb, scope, node, arg0_value); |
| 7075 | return ir_lval_wrap(irb, scope, set_align_stack, lval, result_loc); | 7041 | return ir_lval_wrap(irb, scope, set_align_stack, lval, result_loc); |
| 7076 | } | 7042 | } |
| 7077 | case BuiltinFnIdArgType: | | |
| 7078 | { | | |
| 7079 | AstNode *arg0_node = node->data.fn_call_expr.params.at(0); | | |
| 7080 | IrInstSrc *arg0_value = ir_gen_node(irb, arg0_node, scope); | | |
| 7081 | if (arg0_value == irb->codegen->invalid_inst_src) | | |
| 7082 | return arg0_value; | | |
| 7083 | | | |
| 7084 | AstNode *arg1_node = node->data.fn_call_expr.params.at(1); | | |
| 7085 | IrInstSrc *arg1_value = ir_gen_node(irb, arg1_node, scope); | | |
| 7086 | if (arg1_value == irb->codegen->invalid_inst_src) | | |
| 7087 | return arg1_value; | | |
| 7088 | | | |
| 7089 | IrInstSrc *arg_type = ir_build_arg_type(irb, scope, node, arg0_value, arg1_value, false); | | |
| 7090 | return ir_lval_wrap(irb, scope, arg_type, lval, result_loc); | | |
| 7091 | } | | |
| 7092 | case BuiltinFnIdExport: | 7043 | case BuiltinFnIdExport: |
| 7093 | { | 7044 | { |
| 7094 | // Cast the options parameter to the options type | 7045 | // Cast the options parameter to the options type |
| ... | @@ -25385,20 +25336,6 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo | ... | @@ -25385,20 +25336,6 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo |
| 25385 | return ir_resolve_cast(ira, &instruction->base.base, target, u1_type, CastOpBoolToInt); | 25336 | return ir_resolve_cast(ira, &instruction->base.base, target, u1_type, CastOpBoolToInt); |
| 25386 | } | 25337 | } |
| 25387 | | 25338 | |
| 25388 | static IrInstGen *ir_analyze_instruction_int_type(IrAnalyze *ira, IrInstSrcIntType *instruction) { | | |
| 25389 | IrInstGen *is_signed_value = instruction->is_signed->child; | | |
| 25390 | bool is_signed; | | |
| 25391 | if (!ir_resolve_bool(ira, is_signed_value, &is_signed)) | | |
| 25392 | return ira->codegen->invalid_inst_gen; | | |
| 25393 | | | |
| 25394 | IrInstGen *bit_count_value = instruction->bit_count->child; | | |
| 25395 | uint64_t bit_count; | | |
| 25396 | if (!ir_resolve_unsigned(ira, bit_count_value, ira->codegen->builtin_types.entry_u16, &bit_count)) | | |
| 25397 | return ira->codegen->invalid_inst_gen; | | |
| 25398 | | | |
| 25399 | return ir_const_type(ira, &instruction->base.base, get_int_type(ira->codegen, is_signed, (uint32_t)bit_count)); | | |
| 25400 | } | | |
| 25401 | | | |
| 25402 | static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVectorType *instruction) { | 25339 | static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVectorType *instruction) { |
| 25403 | uint64_t len; | 25340 | uint64_t len; |
| 25404 | if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len)) | 25341 | if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len)) |
| ... | @@ -29270,8 +29207,6 @@ static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruc | ... | @@ -29270,8 +29207,6 @@ static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruc |
| 29270 | return ir_analyze_instruction_float_to_int(ira, (IrInstSrcFloatToInt *)instruction); | 29207 | return ir_analyze_instruction_float_to_int(ira, (IrInstSrcFloatToInt *)instruction); |
| 29271 | case IrInstSrcIdBoolToInt: | 29208 | case IrInstSrcIdBoolToInt: |
| 29272 | return ir_analyze_instruction_bool_to_int(ira, (IrInstSrcBoolToInt *)instruction); | 29209 | return ir_analyze_instruction_bool_to_int(ira, (IrInstSrcBoolToInt *)instruction); |
| 29273 | case IrInstSrcIdIntType: | | |
| 29274 | return ir_analyze_instruction_int_type(ira, (IrInstSrcIntType *)instruction); | | |
| 29275 | case IrInstSrcIdVectorType: | 29210 | case IrInstSrcIdVectorType: |
| 29276 | return ir_analyze_instruction_vector_type(ira, (IrInstSrcVectorType *)instruction); | 29211 | return ir_analyze_instruction_vector_type(ira, (IrInstSrcVectorType *)instruction); |
| 29277 | case IrInstSrcIdShuffleVector: | 29212 | case IrInstSrcIdShuffleVector: |
| ... | @@ -29754,7 +29689,6 @@ bool ir_inst_src_has_side_effects(IrInstSrc *instruction) { | ... | @@ -29754,7 +29689,6 @@ bool ir_inst_src_has_side_effects(IrInstSrc *instruction) { |
| 29754 | case IrInstSrcIdRef: | 29689 | case IrInstSrcIdRef: |
| 29755 | case IrInstSrcIdEmbedFile: | 29690 | case IrInstSrcIdEmbedFile: |
| 29756 | case IrInstSrcIdTruncate: | 29691 | case IrInstSrcIdTruncate: |
| 29757 | case IrInstSrcIdIntType: | | |
| 29758 | case IrInstSrcIdVectorType: | 29692 | case IrInstSrcIdVectorType: |
| 29759 | case IrInstSrcIdShuffleVector: | 29693 | case IrInstSrcIdShuffleVector: |
| 29760 | case IrInstSrcIdSplat: | 29694 | case IrInstSrcIdSplat: |