authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2025-07-29 07:40:16-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-08-11 15:47:51-07:00
logd625158354a02a18e9ae7975a144f30838884d5c
tree1bbf76812c30408509dbd8f6da756986530fbee9
parent59de7e3a5725f0c4eeb64bc464db85e019af7446

aarch64: implement more assembler instructions

8 files changed, 7899 insertions(+), 1787 deletions(-)

lib/std/mem.zig+10-14
......@@ -674,7 +674,7 @@ test lessThan {
674674 try testing.expect(lessThan(u8, "", "a"));
675675}
676676
677const eqlBytes_allowed = switch (builtin.zig_backend) {
677const use_vectors = switch (builtin.zig_backend) {
678678 // These backends don't support vectors yet.
679679 .stage2_aarch64,
680680 .stage2_powerpc,
......@@ -682,16 +682,17 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
682682 => false,
683683 // The SPIR-V backend does not support the optimized path yet.
684684 .stage2_spirv => false,
685 // The naive memory comparison implementation is more useful for fuzzers to
686 // find interesting inputs.
687 else => !builtin.fuzz,
685 else => true,
688686};
689687
688// The naive memory comparison implementation is more useful for fuzzers to find interesting inputs.
689const use_vectors_for_comparison = use_vectors and !builtin.fuzz;
690
690691/// Returns true if and only if the slices have the same length and all elements
691692/// compare true using equality operator.
692693pub fn eql(comptime T: type, a: []const T, b: []const T) bool {
693694 if (!@inComptime() and @sizeOf(T) != 0 and std.meta.hasUniqueRepresentation(T) and
694 eqlBytes_allowed)
695 use_vectors_for_comparison)
695696 {
696697 return eqlBytes(sliceAsBytes(a), sliceAsBytes(b));
697698 }
......@@ -726,7 +727,7 @@ test eql {
726727
727728/// std.mem.eql heavily optimized for slices of bytes.
728729fn eqlBytes(a: []const u8, b: []const u8) bool {
729 comptime assert(eqlBytes_allowed);
730 comptime assert(use_vectors_for_comparison);
730731
731732 if (a.len != b.len) return false;
732733 if (a.len == 0 or a.ptr == b.ptr) return true;
......@@ -1088,15 +1089,10 @@ test len {
10881089 try testing.expect(len(c_ptr) == 2);
10891090}
10901091
1091const backend_supports_vectors = switch (builtin.zig_backend) {
1092 .stage2_llvm, .stage2_c => true,
1093 else => false,
1094};
1095
10961092pub fn indexOfSentinel(comptime T: type, comptime sentinel: T, p: [*:sentinel]const T) usize {
10971093 var i: usize = 0;
10981094
1099 if (backend_supports_vectors and
1095 if (use_vectors_for_comparison and
11001096 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/17717
11011097 !@inComptime() and
11021098 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))
......@@ -1263,7 +1259,7 @@ pub fn indexOfScalarPos(comptime T: type, slice: []const T, start_index: usize,
12631259 if (start_index >= slice.len) return null;
12641260
12651261 var i: usize = start_index;
1266 if (backend_supports_vectors and
1262 if (use_vectors_for_comparison and
12671263 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/17717
12681264 !@inComptime() and
12691265 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))
......@@ -3609,7 +3605,7 @@ inline fn reverseVector(comptime N: usize, comptime T: type, a: []T) [N]T {
36093605pub fn reverse(comptime T: type, items: []T) void {
36103606 var i: usize = 0;
36113607 const end = items.len / 2;
3612 if (backend_supports_vectors and
3608 if (use_vectors and
36133609 !@inComptime() and
36143610 @bitSizeOf(T) > 0 and
36153611 std.math.isPowerOfTwo(@bitSizeOf(T)))
src/codegen/aarch64/Assemble.zig+1280-25
......@@ -6,7 +6,7 @@ pub const Operand = union(enum) {
66};
77
88pub fn nextInstruction(as: *Assemble) !?Instruction {
9 @setEvalBranchQuota(42_000);
9 @setEvalBranchQuota(140_000);
1010 comptime var ct_token_buf: [token_buf_len]u8 = undefined;
1111 var token_buf: [token_buf_len]u8 = undefined;
1212 const original_source = while (true) {
......@@ -30,8 +30,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
3030 inline for (instructions) |instruction| {
3131 next_pattern: {
3232 as.source = original_source;
33 const Symbols = @TypeOf(instruction.symbols);
3334 var symbols: Symbols: {
34 const symbols = @typeInfo(@TypeOf(instruction.symbols)).@"struct".fields;
35 const symbols = @typeInfo(Symbols).@"struct".fields;
3536 var symbol_fields: [symbols.len]std.builtin.Type.StructField = undefined;
3637 for (&symbol_fields, symbols) |*symbol_field, symbol| {
3738 const Storage = zonCast(SymbolSpec, @field(instruction.symbols, symbol.name), .{}).Storage();
......@@ -50,6 +51,8 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
5051 .is_tuple = false,
5152 } });
5253 } = undefined;
54 const Symbol = std.meta.FieldEnum(Symbols);
55 comptime var unused_symbols: std.enums.EnumSet(Symbol) = .initFull();
5356 comptime var pattern_as: Assemble = .{ .source = instruction.pattern, .operands = undefined };
5457 inline while (true) {
5558 const pattern_token = comptime pattern_as.nextToken(&ct_token_buf, .{ .placeholders = true }) catch |err|
......@@ -60,6 +63,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
6063 std.zig.fmtString(source_token),
6164 });
6265 if (pattern_token.len == 0) {
66 comptime var unused_symbol_it = unused_symbols.iterator();
67 inline while (comptime unused_symbol_it.next()) |unused_symbol|
68 @compileError(@tagName(unused_symbol) ++ " unused while parsing '" ++ instruction.pattern ++ "'");
6369 switch (source_token.len) {
6470 0 => {},
6571 else => switch (source_token[0]) {
......@@ -76,9 +82,14 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
7682 } else if (pattern_token[0] == '<') {
7783 const symbol_name = comptime pattern_token[1 .. std.mem.indexOfScalarPos(u8, pattern_token, 1, '|') orelse
7884 pattern_token.len - 1];
79 const symbol = &@field(symbols, symbol_name);
80 symbol.* = zonCast(SymbolSpec, @field(instruction.symbols, symbol_name), .{}).parse(source_token) orelse break :next_pattern;
81 log.debug("{s} = {any}", .{ symbol_name, symbol.* });
85 const symbol = @field(Symbol, symbol_name);
86 const symbol_ptr = &@field(symbols, symbol_name);
87 const symbol_value = zonCast(SymbolSpec, @field(instruction.symbols, symbol_name), .{}).parse(source_token) orelse break :next_pattern;
88 if (comptime unused_symbols.contains(symbol)) {
89 log.debug("{s} = {any}", .{ symbol_name, symbol_value });
90 symbol_ptr.* = symbol_value;
91 comptime unused_symbols.remove(symbol);
92 } else if (symbol_ptr.* != symbol_value) break :next_pattern;
8293 } else if (!toUpperEqlAssertUpper(source_token, pattern_token)) break :next_pattern;
8394 }
8495 }
......@@ -121,9 +132,9 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {
121132 const Symbol = @TypeOf(symbol);
122133 switch (@typeInfo(Result)) {
123134 .@"enum" => switch (@typeInfo(Symbol)) {
124 .int => |symbol_int| {
135 .int => |info| {
125136 var buf: [
126 std.fmt.count("{d}", .{switch (symbol_int.signedness) {
137 std.fmt.count("{d}", .{switch (info.signedness) {
127138 .signed => std.math.minInt(Symbol),
128139 .unsigned => std.math.maxInt(Symbol),
129140 }})
......@@ -134,7 +145,15 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {
134145 },
135146 else => return symbol,
136147 }
137 } else return if (@hasDecl(Result, @tagName(zon_value))) @field(Result, @tagName(zon_value)) else zon_value,
148 } else {
149 const Container = switch (@typeInfo(Result)) {
150 else => struct {},
151 .@"struct", .@"enum", .@"union", .@"opaque" => Result,
152 .optional => |info| info.child,
153 .error_union => |info| info.payload,
154 };
155 return if (@hasDecl(Container, @tagName(zon_value))) @field(Container, @tagName(zon_value)) else zon_value;
156 },
138157 else => @compileError(std.fmt.comptimePrint("unsupported zon type: {} <- {any}", .{ Result, zon_value })),
139158 }
140159}
......@@ -210,10 +229,22 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {
210229 },
211230 }
212231 } else continue :c invalid_syntax,
213 '-', '0'...'9', 'A'...'Z', '_', 'a'...'z' => {
232 '+', '-', '.', '0'...'9', 'A'...'Z', '_', 'a'...'z' => {
214233 var index: usize = 1;
215 while (switch (as.source[index]) {
216 '0'...'9', 'A'...'Z', '_', 'a'...'z' => true,
234 while (more: switch (as.source[index]) {
235 '0'...'9' => true,
236 'A'...'Z', '_', 'a'...'z' => switch (as.source[0]) {
237 else => true,
238 '.' => {
239 index = 1;
240 break :more false;
241 },
242 },
243 '.' => switch (as.source[0]) {
244 else => unreachable,
245 '+', '-', '.', '0'...'9' => true,
246 'A'...'Z', '_', 'a'...'z' => false,
247 },
217248 else => false,
218249 }) index += 1;
219250 defer as.source = as.source[index..];
......@@ -237,22 +268,33 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {
237268}
238269
239270const SymbolSpec = union(enum) {
271 reg_alias: aarch64.encoding.Register.Format.Alias,
240272 reg: struct { format: aarch64.encoding.Register.Format, allow_sp: bool = false },
273 arrangement: struct {
274 elem_size: ?Instruction.DataProcessingVector.Size = null,
275 allow_double: bool = true,
276 min_valid_len: comptime_int = 0,
277 },
241278 systemreg,
242279 imm: struct {
243280 type: std.builtin.Type.Int,
244 multiple_of: comptime_int = 1,
281 multiple_of: ?comptime_int = null,
282 min_valid: ?comptime_int = null,
245283 max_valid: ?comptime_int = null,
246284 },
247 extend: struct { size: aarch64.encoding.Register.IntegerSize },
285 fimm: struct { only_valid: ?f16 = null },
286 extend: struct { size: aarch64.encoding.Register.GeneralSize },
248287 shift: struct { allow_ror: bool = true },
249288 barrier: struct { only_sy: bool = false },
250289
251290 fn Storage(comptime spec: SymbolSpec) type {
252291 return switch (spec) {
292 .reg_alias => aarch64.encoding.Register.Alias,
253293 .reg => aarch64.encoding.Register,
294 .arrangement => aarch64.encoding.Register.Arrangement,
254295 .systemreg => aarch64.encoding.Register.System,
255296 .imm => |imm| @Type(.{ .int = imm.type }),
297 .fimm => f16,
256298 .extend => Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option,
257299 .shift => Instruction.DataProcessingRegister.Shift.Op,
258300 .barrier => Instruction.BranchExceptionGeneratingSystem.Barriers.Option,
......@@ -262,12 +304,27 @@ const SymbolSpec = union(enum) {
262304 fn parse(comptime spec: SymbolSpec, token: []const u8) ?Storage(spec) {
263305 const Result = Storage(spec);
264306 switch (spec) {
307 .reg_alias => |reg_alias_spec| {
308 const reg = aarch64.encoding.Register.parse(token) orelse {
309 log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});
310 return null;
311 };
312 if (reg.format != .alias or reg.format.alias != reg_alias_spec) {
313 log.debug("invalid register size: \"{f}\"", .{std.zig.fmtString(token)});
314 return null;
315 }
316 return reg.alias;
317 },
265318 .reg => |reg_spec| {
266319 const reg = Result.parse(token) orelse {
267320 log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});
268321 return null;
269322 };
270 if (reg.format.integer != reg_spec.format.integer) {
323 if (switch (reg_spec.format) {
324 .alias, .vector, .element, .scalable => comptime unreachable,
325 .general => |general_spec| reg.format != .general or reg.format.general != general_spec,
326 .scalar => |scalar_spec| reg.format != .scalar or reg.format.scalar != scalar_spec,
327 }) {
271328 log.debug("invalid register size: \"{f}\"", .{std.zig.fmtString(token)});
272329 return null;
273330 }
......@@ -277,6 +334,35 @@ const SymbolSpec = union(enum) {
277334 }
278335 return reg;
279336 },
337 .arrangement => |arrangement_spec| {
338 var buf: [
339 max_len: {
340 var max_len = 0;
341 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
342 break :max_len max_len;
343 } + 1
344 ]u8 = undefined;
345 const arrangement = std.meta.stringToEnum(Result, std.ascii.lowerString(
346 &buf,
347 token[0..@min(token.len, buf.len)],
348 )) orelse {
349 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
350 return null;
351 };
352 if (arrangement_spec.elem_size) |elem_size| if (arrangement.elemSize() != elem_size) {
353 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
354 return null;
355 };
356 if (!arrangement_spec.allow_double and arrangement.elemSize() == .double) {
357 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
358 return null;
359 }
360 if (arrangement.len() < arrangement_spec.min_valid_len) {
361 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
362 return null;
363 }
364 return arrangement;
365 },
280366 .systemreg => {
281367 const systemreg = Result.parse(token) orelse {
282368 log.debug("invalid system register: \"{f}\"", .{std.zig.fmtString(token)});
......@@ -290,26 +376,57 @@ const SymbolSpec = union(enum) {
290376 log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});
291377 return null;
292378 };
293 if (@rem(imm, imm_spec.multiple_of) != 0) {
379 if (imm_spec.multiple_of) |multiple_of| if (@rem(imm, multiple_of) != 0) {
294380 log.debug("invalid immediate usage: \"{f}\"", .{std.zig.fmtString(token)});
295381 return null;
296 }
382 };
383 if (imm_spec.min_valid) |min_valid| if (imm < min_valid) {
384 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
385 return null;
386 };
297387 if (imm_spec.max_valid) |max_valid| if (imm > max_valid) {
298388 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
299389 return null;
300390 };
301391 return imm;
302392 },
393 .fimm => |fimm_spec| {
394 const full_fimm = std.fmt.parseFloat(f128, token) catch {
395 log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});
396 return null;
397 };
398 const fimm: f16 = @floatCast(full_fimm);
399 if (fimm != full_fimm) {
400 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
401 return null;
402 }
403 if (fimm_spec.only_valid) |only_valid| {
404 if (@as(u16, @bitCast(fimm)) != @as(u16, @bitCast(only_valid))) {
405 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
406 return null;
407 }
408 } else {
409 const Repr = std.math.FloatRepr(f16);
410 const repr: Repr = @bitCast(fimm);
411 if (repr.mantissa & std.math.maxInt(Repr.Mantissa) >> 5 != 0 or switch (repr.exponent) {
412 .denormal, .infinite => true,
413 else => std.math.cast(i3, repr.exponent.unbias() - 1) == null,
414 }) {
415 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
416 return null;
417 }
418 }
419 return fimm;
420 },
303421 .extend => |extend_spec| {
304 const Option = Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option;
305422 var buf: [
306423 max_len: {
307424 var max_len = 0;
308 for (@typeInfo(Option).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
425 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
309426 break :max_len max_len;
310427 } + 1
311428 ]u8 = undefined;
312 const extend = std.meta.stringToEnum(Option, std.ascii.lowerString(
429 const extend = std.meta.stringToEnum(Result, std.ascii.lowerString(
313430 &buf,
314431 token[0..@min(token.len, buf.len)],
315432 )) orelse {
......@@ -323,15 +440,14 @@ const SymbolSpec = union(enum) {
323440 return extend;
324441 },
325442 .shift => |shift_spec| {
326 const ShiftOp = Instruction.DataProcessingRegister.Shift.Op;
327443 var buf: [
328444 max_len: {
329445 var max_len = 0;
330 for (@typeInfo(ShiftOp).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
446 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
331447 break :max_len max_len;
332448 } + 1
333449 ]u8 = undefined;
334 const shift = std.meta.stringToEnum(ShiftOp, std.ascii.lowerString(
450 const shift = std.meta.stringToEnum(Result, std.ascii.lowerString(
335451 &buf,
336452 token[0..@min(token.len, buf.len)],
337453 )) orelse {
......@@ -345,15 +461,14 @@ const SymbolSpec = union(enum) {
345461 return shift;
346462 },
347463 .barrier => |barrier_spec| {
348 const Option = Instruction.BranchExceptionGeneratingSystem.Barriers.Option;
349464 var buf: [
350465 max_len: {
351466 var max_len = 0;
352 for (@typeInfo(Option).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
467 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
353468 break :max_len max_len;
354469 } + 1
355470 ]u8 = undefined;
356 const barrier = std.meta.stringToEnum(Option, std.ascii.lowerString(
471 const barrier = std.meta.stringToEnum(Result, std.ascii.lowerString(
357472 &buf,
358473 token[0..@min(token.len, buf.len)],
359474 )) orelse {
......@@ -778,6 +893,76 @@ test "add sub" {
778893
779894 try std.testing.expect(null == try as.nextInstruction());
780895}
896test "bit manipulation" {
897 var as: Assemble = .{
898 .source =
899 \\rbit w0, w1
900 \\rbit w2, wzr
901 \\rbit x3, x4
902 \\rbit xzr, x5
903 \\
904 \\rev16 w0, w1
905 \\rev16 w2, wzr
906 \\rev16 x3, x4
907 \\rev16 xzr, x5
908 \\
909 \\rev32 x3, x4
910 \\rev32 xzr, x5
911 \\
912 \\rev w0, w1
913 \\rev w2, wzr
914 \\rev x3, x4
915 \\rev xzr, x5
916 \\
917 \\rev64 x3, x4
918 \\rev64 xzr, x5
919 \\
920 \\clz w0, w1
921 \\clz w2, wzr
922 \\clz x3, x4
923 \\clz xzr, x5
924 \\
925 \\cls w0, w1
926 \\cls w2, wzr
927 \\cls x3, x4
928 \\cls xzr, x5
929 ,
930 .operands = .empty,
931 };
932
933 try std.testing.expectFmt("rbit w0, w1", "{f}", .{(try as.nextInstruction()).?});
934 try std.testing.expectFmt("rbit w2, wzr", "{f}", .{(try as.nextInstruction()).?});
935 try std.testing.expectFmt("rbit x3, x4", "{f}", .{(try as.nextInstruction()).?});
936 try std.testing.expectFmt("rbit xzr, x5", "{f}", .{(try as.nextInstruction()).?});
937
938 try std.testing.expectFmt("rev16 w0, w1", "{f}", .{(try as.nextInstruction()).?});
939 try std.testing.expectFmt("rev16 w2, wzr", "{f}", .{(try as.nextInstruction()).?});
940 try std.testing.expectFmt("rev16 x3, x4", "{f}", .{(try as.nextInstruction()).?});
941 try std.testing.expectFmt("rev16 xzr, x5", "{f}", .{(try as.nextInstruction()).?});
942
943 try std.testing.expectFmt("rev32 x3, x4", "{f}", .{(try as.nextInstruction()).?});
944 try std.testing.expectFmt("rev32 xzr, x5", "{f}", .{(try as.nextInstruction()).?});
945
946 try std.testing.expectFmt("rev w0, w1", "{f}", .{(try as.nextInstruction()).?});
947 try std.testing.expectFmt("rev w2, wzr", "{f}", .{(try as.nextInstruction()).?});
948 try std.testing.expectFmt("rev x3, x4", "{f}", .{(try as.nextInstruction()).?});
949 try std.testing.expectFmt("rev xzr, x5", "{f}", .{(try as.nextInstruction()).?});
950
951 try std.testing.expectFmt("rev x3, x4", "{f}", .{(try as.nextInstruction()).?});
952 try std.testing.expectFmt("rev xzr, x5", "{f}", .{(try as.nextInstruction()).?});
953
954 try std.testing.expectFmt("clz w0, w1", "{f}", .{(try as.nextInstruction()).?});
955 try std.testing.expectFmt("clz w2, wzr", "{f}", .{(try as.nextInstruction()).?});
956 try std.testing.expectFmt("clz x3, x4", "{f}", .{(try as.nextInstruction()).?});
957 try std.testing.expectFmt("clz xzr, x5", "{f}", .{(try as.nextInstruction()).?});
958
959 try std.testing.expectFmt("cls w0, w1", "{f}", .{(try as.nextInstruction()).?});
960 try std.testing.expectFmt("cls w2, wzr", "{f}", .{(try as.nextInstruction()).?});
961 try std.testing.expectFmt("cls x3, x4", "{f}", .{(try as.nextInstruction()).?});
962 try std.testing.expectFmt("cls xzr, x5", "{f}", .{(try as.nextInstruction()).?});
963
964 try std.testing.expect(null == try as.nextInstruction());
965}
781966test "bitfield" {
782967 var as: Assemble = .{
783968 .source =
......@@ -852,6 +1037,24 @@ test "branch register" {
8521037
8531038 try std.testing.expect(null == try as.nextInstruction());
8541039}
1040test "division" {
1041 var as: Assemble = .{
1042 .source =
1043 \\udiv w0, w1, w2
1044 \\udiv x3, x4, xzr
1045 \\sdiv w5, wzr, w6
1046 \\sdiv x7, x8, x9
1047 ,
1048 .operands = .empty,
1049 };
1050
1051 try std.testing.expectFmt("udiv w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
1052 try std.testing.expectFmt("udiv x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
1053 try std.testing.expectFmt("sdiv w5, wzr, w6", "{f}", .{(try as.nextInstruction()).?});
1054 try std.testing.expectFmt("sdiv x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
1055
1056 try std.testing.expect(null == try as.nextInstruction());
1057}
8551058test "exception generating" {
8561059 var as: Assemble = .{
8571060 .source =
......@@ -1579,6 +1782,91 @@ test "mov" {
15791782 \\MOVZ XZR, #0xffff, lsl #16
15801783 \\MOVZ XZR, #0xffff, lsl #32
15811784 \\MOVZ XZR, #0xffff, lsl #48
1785 \\
1786 \\DUP B0, V1.B[15]
1787 \\DUP H2, V3.H[7]
1788 \\DUP S4, V5.S[3]
1789 \\DUP D6, V7.D[1]
1790 \\
1791 \\DUP V0.8B, V1.B[0]
1792 \\DUP V2.16B, V3.B[15]
1793 \\DUP V4.4H, V5.H[0]
1794 \\DUP V6.8H, V7.H[7]
1795 \\DUP V8.2S, V9.S[0]
1796 \\DUP V10.4S, V11.S[3]
1797 \\DUP V12.2D, V13.D[1]
1798 \\
1799 \\DUP V0.8B, W1
1800 \\DUP V2.16B, W3
1801 \\DUP V4.4H, W5
1802 \\DUP V6.8H, W7
1803 \\DUP V8.2S, W9
1804 \\DUP V10.4S, W11
1805 \\DUP V12.2D, X13
1806 \\
1807 \\FMOV V0.4H, #-31
1808 \\FMOV V1.8H, #-2.625
1809 \\FMOV V2.2S, #-1
1810 \\FMOV V3.4S, #-.2421875
1811 \\FMOV V4.2D, #.2421875
1812 \\FMOV H5, H6
1813 \\FMOV S7, S8
1814 \\FMOV D9, D10
1815 \\FMOV W11, H12
1816 \\FMOV X13, H14
1817 \\FMOV H15, W16
1818 \\FMOV S17, W18
1819 \\FMOV W19, S20
1820 \\FMOV H21, X22
1821 \\FMOV D23, X24
1822 \\FMOV V25.D[0x1], X26
1823 \\FMOV X27, D28
1824 \\FMOV X29, V30 . D [ 0X1 ]
1825 \\FMOV H31, #1
1826 \\FMOV S30, #2.625
1827 \\FMOV D29, #31
1828 \\
1829 \\INS V0.B[0], V1.B[15]
1830 \\INS V2.H[0], V3.H[7]
1831 \\INS V4.S[0], V5.S[3]
1832 \\INS V6.D[0], V7.D[1]
1833 \\
1834 \\INS V0.B[15], W1
1835 \\INS V2.H[7], W3
1836 \\INS V4.S[3], W5
1837 \\INS V6.D[1], X7
1838 \\
1839 \\MOV B0, V1.B [ 0xf]
1840 \\MOV H2, V3.H [ 0x7]
1841 \\MOV S4, V5.S [ 0x3]
1842 \\MOV D6, V7.D [ 0x1]
1843 \\
1844 \\MOV V0.B[0], V1.B[15]
1845 \\MOV V2.H[0], V3.H[7]
1846 \\MOV V4.S[0], V5.S[3]
1847 \\MOV V6.D[0], V7.D[1]
1848 \\
1849 \\MOV V0.B[15], W1
1850 \\MOV V2.H[7], W3
1851 \\MOV V4.S[3], W5
1852 \\MOV V6.D[1], X7
1853 \\
1854 \\MOV V0.8B, V1.8B
1855 \\MOV V2.16B, V3.16B
1856 \\
1857 \\MOV W0, V1.S[0x3]
1858 \\MOV X2, V3.D[0x1]
1859 \\
1860 \\SMOV W0, V1.B[0xF]
1861 \\SMOV W2, V3.H[0x7]
1862 \\SMOV X4, V5.B[0xF]
1863 \\SMOV X6, V7.H[0x7]
1864 \\SMOV X8, V9.S[0x3]
1865 \\
1866 \\UMOV W0, V1.B[0xF]
1867 \\UMOV W2, V3.H[0x7]
1868 \\UMOV W4, V5.S[0x3]
1869 \\UMOV X6, V7.D[0x1]
15821870 ,
15831871 .operands = .empty,
15841872 };
......@@ -1661,6 +1949,171 @@ test "mov" {
16611949 try std.testing.expectFmt("mov xzr, #0xffff00000000", "{f}", .{(try as.nextInstruction()).?});
16621950 try std.testing.expectFmt("mov xzr, #-0x1000000000000", "{f}", .{(try as.nextInstruction()).?});
16631951
1952 try std.testing.expectFmt("mov b0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
1953 try std.testing.expectFmt("mov h2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
1954 try std.testing.expectFmt("mov s4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
1955 try std.testing.expectFmt("mov d6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
1956
1957 try std.testing.expectFmt("dup v0.8b, v1.b[0]", "{f}", .{(try as.nextInstruction()).?});
1958 try std.testing.expectFmt("dup v2.16b, v3.b[15]", "{f}", .{(try as.nextInstruction()).?});
1959 try std.testing.expectFmt("dup v4.4h, v5.h[0]", "{f}", .{(try as.nextInstruction()).?});
1960 try std.testing.expectFmt("dup v6.8h, v7.h[7]", "{f}", .{(try as.nextInstruction()).?});
1961 try std.testing.expectFmt("dup v8.2s, v9.s[0]", "{f}", .{(try as.nextInstruction()).?});
1962 try std.testing.expectFmt("dup v10.4s, v11.s[3]", "{f}", .{(try as.nextInstruction()).?});
1963 try std.testing.expectFmt("dup v12.2d, v13.d[1]", "{f}", .{(try as.nextInstruction()).?});
1964
1965 try std.testing.expectFmt("dup v0.8b, w1", "{f}", .{(try as.nextInstruction()).?});
1966 try std.testing.expectFmt("dup v2.16b, w3", "{f}", .{(try as.nextInstruction()).?});
1967 try std.testing.expectFmt("dup v4.4h, w5", "{f}", .{(try as.nextInstruction()).?});
1968 try std.testing.expectFmt("dup v6.8h, w7", "{f}", .{(try as.nextInstruction()).?});
1969 try std.testing.expectFmt("dup v8.2s, w9", "{f}", .{(try as.nextInstruction()).?});
1970 try std.testing.expectFmt("dup v10.4s, w11", "{f}", .{(try as.nextInstruction()).?});
1971 try std.testing.expectFmt("dup v12.2d, x13", "{f}", .{(try as.nextInstruction()).?});
1972
1973 try std.testing.expectFmt("fmov v0.4h, #-31.0", "{f}", .{(try as.nextInstruction()).?});
1974 try std.testing.expectFmt("fmov v1.8h, #-2.625", "{f}", .{(try as.nextInstruction()).?});
1975 try std.testing.expectFmt("fmov v2.2s, #-1.0", "{f}", .{(try as.nextInstruction()).?});
1976 try std.testing.expectFmt("fmov v3.4s, #-0.2421875", "{f}", .{(try as.nextInstruction()).?});
1977 try std.testing.expectFmt("fmov v4.2d, #0.2421875", "{f}", .{(try as.nextInstruction()).?});
1978 try std.testing.expectFmt("fmov h5, h6", "{f}", .{(try as.nextInstruction()).?});
1979 try std.testing.expectFmt("fmov s7, s8", "{f}", .{(try as.nextInstruction()).?});
1980 try std.testing.expectFmt("fmov d9, d10", "{f}", .{(try as.nextInstruction()).?});
1981 try std.testing.expectFmt("fmov w11, h12", "{f}", .{(try as.nextInstruction()).?});
1982 try std.testing.expectFmt("fmov x13, h14", "{f}", .{(try as.nextInstruction()).?});
1983 try std.testing.expectFmt("fmov h15, w16", "{f}", .{(try as.nextInstruction()).?});
1984 try std.testing.expectFmt("fmov s17, w18", "{f}", .{(try as.nextInstruction()).?});
1985 try std.testing.expectFmt("fmov w19, s20", "{f}", .{(try as.nextInstruction()).?});
1986 try std.testing.expectFmt("fmov h21, x22", "{f}", .{(try as.nextInstruction()).?});
1987 try std.testing.expectFmt("fmov d23, x24", "{f}", .{(try as.nextInstruction()).?});
1988 try std.testing.expectFmt("fmov v25.d[1], x26", "{f}", .{(try as.nextInstruction()).?});
1989 try std.testing.expectFmt("fmov x27, d28", "{f}", .{(try as.nextInstruction()).?});
1990 try std.testing.expectFmt("fmov x29, v30.d[1]", "{f}", .{(try as.nextInstruction()).?});
1991 try std.testing.expectFmt("fmov h31, #1.0", "{f}", .{(try as.nextInstruction()).?});
1992 try std.testing.expectFmt("fmov s30, #2.625", "{f}", .{(try as.nextInstruction()).?});
1993 try std.testing.expectFmt("fmov d29, #31.0", "{f}", .{(try as.nextInstruction()).?});
1994
1995 try std.testing.expectFmt("mov v0.b[0], v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
1996 try std.testing.expectFmt("mov v2.h[0], v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
1997 try std.testing.expectFmt("mov v4.s[0], v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
1998 try std.testing.expectFmt("mov v6.d[0], v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
1999
2000 try std.testing.expectFmt("mov v0.b[15], w1", "{f}", .{(try as.nextInstruction()).?});
2001 try std.testing.expectFmt("mov v2.h[7], w3", "{f}", .{(try as.nextInstruction()).?});
2002 try std.testing.expectFmt("mov v4.s[3], w5", "{f}", .{(try as.nextInstruction()).?});
2003 try std.testing.expectFmt("mov v6.d[1], x7", "{f}", .{(try as.nextInstruction()).?});
2004
2005 try std.testing.expectFmt("mov b0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2006 try std.testing.expectFmt("mov h2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2007 try std.testing.expectFmt("mov s4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2008 try std.testing.expectFmt("mov d6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2009
2010 try std.testing.expectFmt("mov v0.b[0], v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2011 try std.testing.expectFmt("mov v2.h[0], v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2012 try std.testing.expectFmt("mov v4.s[0], v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2013 try std.testing.expectFmt("mov v6.d[0], v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2014
2015 try std.testing.expectFmt("mov v0.b[15], w1", "{f}", .{(try as.nextInstruction()).?});
2016 try std.testing.expectFmt("mov v2.h[7], w3", "{f}", .{(try as.nextInstruction()).?});
2017 try std.testing.expectFmt("mov v4.s[3], w5", "{f}", .{(try as.nextInstruction()).?});
2018 try std.testing.expectFmt("mov v6.d[1], x7", "{f}", .{(try as.nextInstruction()).?});
2019
2020 try std.testing.expectFmt("mov v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2021 try std.testing.expectFmt("mov v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2022
2023 try std.testing.expectFmt("mov w0, v1.s[3]", "{f}", .{(try as.nextInstruction()).?});
2024 try std.testing.expectFmt("mov x2, v3.d[1]", "{f}", .{(try as.nextInstruction()).?});
2025
2026 try std.testing.expectFmt("smov w0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2027 try std.testing.expectFmt("smov w2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2028 try std.testing.expectFmt("smov x4, v5.b[15]", "{f}", .{(try as.nextInstruction()).?});
2029 try std.testing.expectFmt("smov x6, v7.h[7]", "{f}", .{(try as.nextInstruction()).?});
2030 try std.testing.expectFmt("smov x8, v9.s[3]", "{f}", .{(try as.nextInstruction()).?});
2031
2032 try std.testing.expectFmt("umov w0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2033 try std.testing.expectFmt("umov w2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2034 try std.testing.expectFmt("mov w4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2035 try std.testing.expectFmt("mov x6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2036
2037 try std.testing.expect(null == try as.nextInstruction());
2038}
2039test "multiply" {
2040 var as: Assemble = .{
2041 .source =
2042 \\madd w0, w1, w2, w3
2043 \\madd w4, w5, w6, wzr
2044 \\mul w7, w8, w9
2045 \\madd x10, x11, x12, x13
2046 \\madd x14, x15, x16, xzr
2047 \\mul x17, x18, x19
2048 \\
2049 \\msub w0, w1, w2, w3
2050 \\msub w4, w5, w6, wzr
2051 \\mneg w7, w8, w9
2052 \\msub x10, x11, x12, x13
2053 \\msub x14, x15, x16, xzr
2054 \\mneg x17, x18, x19
2055 \\
2056 \\smaddl x0, w1, w2, x3
2057 \\smaddl x4, w5, w6, xzr
2058 \\smull x7, w8, w9
2059 \\
2060 \\smsubl x0, w1, w2, x3
2061 \\smsubl x4, w5, w6, xzr
2062 \\smnegl x7, w8, w9
2063 \\
2064 \\smulh x0, x1, x2
2065 \\smulh x3, x4, xzr
2066 \\
2067 \\umaddl x0, w1, w2, x3
2068 \\umaddl x4, w5, w6, xzr
2069 \\umull x7, w8, w9
2070 \\
2071 \\umsubl x0, w1, w2, x3
2072 \\umsubl x4, w5, w6, xzr
2073 \\umnegl x7, w8, w9
2074 \\
2075 \\umulh x0, x1, x2
2076 \\umulh x3, x4, xzr
2077 ,
2078 .operands = .empty,
2079 };
2080
2081 try std.testing.expectFmt("madd w0, w1, w2, w3", "{f}", .{(try as.nextInstruction()).?});
2082 try std.testing.expectFmt("mul w4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2083 try std.testing.expectFmt("mul w7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2084 try std.testing.expectFmt("madd x10, x11, x12, x13", "{f}", .{(try as.nextInstruction()).?});
2085 try std.testing.expectFmt("mul x14, x15, x16", "{f}", .{(try as.nextInstruction()).?});
2086 try std.testing.expectFmt("mul x17, x18, x19", "{f}", .{(try as.nextInstruction()).?});
2087
2088 try std.testing.expectFmt("msub w0, w1, w2, w3", "{f}", .{(try as.nextInstruction()).?});
2089 try std.testing.expectFmt("mneg w4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2090 try std.testing.expectFmt("mneg w7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2091 try std.testing.expectFmt("msub x10, x11, x12, x13", "{f}", .{(try as.nextInstruction()).?});
2092 try std.testing.expectFmt("mneg x14, x15, x16", "{f}", .{(try as.nextInstruction()).?});
2093 try std.testing.expectFmt("mneg x17, x18, x19", "{f}", .{(try as.nextInstruction()).?});
2094
2095 try std.testing.expectFmt("smaddl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2096 try std.testing.expectFmt("smull x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2097 try std.testing.expectFmt("smull x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2098
2099 try std.testing.expectFmt("smsubl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2100 try std.testing.expectFmt("smnegl x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2101 try std.testing.expectFmt("smnegl x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2102
2103 try std.testing.expectFmt("smulh x0, x1, x2", "{f}", .{(try as.nextInstruction()).?});
2104 try std.testing.expectFmt("smulh x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
2105
2106 try std.testing.expectFmt("umaddl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2107 try std.testing.expectFmt("umull x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2108 try std.testing.expectFmt("umull x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2109
2110 try std.testing.expectFmt("umsubl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2111 try std.testing.expectFmt("umnegl x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2112 try std.testing.expectFmt("umnegl x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2113
2114 try std.testing.expectFmt("umulh x0, x1, x2", "{f}", .{(try as.nextInstruction()).?});
2115 try std.testing.expectFmt("umulh x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
2116
16642117 try std.testing.expect(null == try as.nextInstruction());
16652118}
16662119test "reserved" {
......@@ -1675,6 +2128,808 @@ test "reserved" {
16752128
16762129 try std.testing.expect(null == try as.nextInstruction());
16772130}
2131test "shift" {
2132 var as: Assemble = .{
2133 .source =
2134 \\lsl w0, w1, w2
2135 \\lslv w3, w4, wzr
2136 \\lsl x5, x6, xzr
2137 \\lslv x7, x8, x9
2138 \\
2139 \\lsr w0, w1, w2
2140 \\lsrv w3, w4, wzr
2141 \\lsr x5, x6, xzr
2142 \\lsrv x7, x8, x9
2143 \\
2144 \\asr w0, w1, w2
2145 \\asrv w3, w4, wzr
2146 \\asr x5, x6, xzr
2147 \\asrv x7, x8, x9
2148 \\
2149 \\ror w0, w1, w2
2150 \\rorv w3, w4, wzr
2151 \\ror x5, x6, xzr
2152 \\rorv x7, x8, x9
2153 ,
2154 .operands = .empty,
2155 };
2156
2157 try std.testing.expectFmt("lsl w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2158 try std.testing.expectFmt("lsl w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2159 try std.testing.expectFmt("lsl x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2160 try std.testing.expectFmt("lsl x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2161
2162 try std.testing.expectFmt("lsr w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2163 try std.testing.expectFmt("lsr w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2164 try std.testing.expectFmt("lsr x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2165 try std.testing.expectFmt("lsr x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2166
2167 try std.testing.expectFmt("asr w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2168 try std.testing.expectFmt("asr w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2169 try std.testing.expectFmt("asr x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2170 try std.testing.expectFmt("asr x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2171
2172 try std.testing.expectFmt("ror w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2173 try std.testing.expectFmt("ror w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2174 try std.testing.expectFmt("ror x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2175 try std.testing.expectFmt("ror x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2176
2177 try std.testing.expect(null == try as.nextInstruction());
2178}
2179test "unary vector" {
2180 var as: Assemble = .{
2181 .source =
2182 \\SUQADD B0, B1
2183 \\SUQADD H2, H3
2184 \\SUQADD S4, S5
2185 \\SUQADD D6, D7
2186 \\SUQADD V8.8B, V9.8B
2187 \\SUQADD V10.16B, V11.16B
2188 \\SUQADD V12.4H, V13.4H
2189 \\SUQADD V14.8H, V15.8H
2190 \\SUQADD V16.2S, V17.2S
2191 \\SUQADD V18.4S, V19.4S
2192 \\SUQADD V20.2D, V21.2D
2193 \\
2194 \\CNT V0.8B, V1.8B
2195 \\CNT V2.16B, V3.16B
2196 \\
2197 \\SQABS B0, B1
2198 \\SQABS H2, H3
2199 \\SQABS S4, S5
2200 \\SQABS D6, D7
2201 \\SQABS V8.8B, V9.8B
2202 \\SQABS V10.16B, V11.16B
2203 \\SQABS V12.4H, V13.4H
2204 \\SQABS V14.8H, V15.8H
2205 \\SQABS V16.2S, V17.2S
2206 \\SQABS V18.4S, V19.4S
2207 \\SQABS V20.2D, V21.2D
2208 \\
2209 \\CMGT D0, D1, #00
2210 \\CMGT V2.8B, V3.8B, #0
2211 \\CMGT V4.16B, V5.16B, #0
2212 \\CMGT V6.4H, V7.4H, #0
2213 \\CMGT V8.8H, V9.8H, #0
2214 \\CMGT V10.2S, V11.2S, #0
2215 \\CMGT V12.4S, V13.4S, #0
2216 \\CMGT V14.2D, V15.2D, #0
2217 \\
2218 \\CMEQ D0, D1, #00
2219 \\CMEQ V2.8B, V3.8B, #0
2220 \\CMEQ V4.16B, V5.16B, #0
2221 \\CMEQ V6.4H, V7.4H, #0
2222 \\CMEQ V8.8H, V9.8H, #0
2223 \\CMEQ V10.2S, V11.2S, #0
2224 \\CMEQ V12.4S, V13.4S, #0
2225 \\CMEQ V14.2D, V15.2D, #0
2226 \\
2227 \\CMLT D0, D1, #00
2228 \\CMLT V2.8B, V3.8B, #0
2229 \\CMLT V4.16B, V5.16B, #0
2230 \\CMLT V6.4H, V7.4H, #0
2231 \\CMLT V8.8H, V9.8H, #0
2232 \\CMLT V10.2S, V11.2S, #0
2233 \\CMLT V12.4S, V13.4S, #0
2234 \\CMLT V14.2D, V15.2D, #0
2235 \\
2236 \\ABS D0, D1
2237 \\ABS V2.8B, V3.8B
2238 \\ABS V4.16B, V5.16B
2239 \\ABS V6.4H, V7.4H
2240 \\ABS V8.8H, V9.8H
2241 \\ABS V10.2S, V11.2S
2242 \\ABS V12.4S, V13.4S
2243 \\ABS V14.2D, V15.2D
2244 \\
2245 \\SQXTN B0, H1
2246 \\SQXTN H2, S3
2247 \\SQXTN S4, D5
2248 \\SQXTN V6.8B, V7.8H
2249 \\SQXTN2 V8.16B, V9.8H
2250 \\SQXTN V10.4H, V11.4S
2251 \\SQXTN2 V12.8H, V13.4S
2252 \\SQXTN V14.2S, V15.2D
2253 \\SQXTN2 V16.4S, V17.2D
2254 \\
2255 \\FRINTN V0.4H, V1.4H
2256 \\FRINTN V2.8H, V3.8H
2257 \\FRINTN V4.2S, V5.2S
2258 \\FRINTN V6.4S, V7.4S
2259 \\FRINTN V8.2D, V9.2D
2260 \\FRINTN H10, H11
2261 \\FRINTN S12, S13
2262 \\FRINTN D14, D15
2263 \\
2264 \\FRINTM V0.4H, V1.4H
2265 \\FRINTM V2.8H, V3.8H
2266 \\FRINTM V4.2S, V5.2S
2267 \\FRINTM V6.4S, V7.4S
2268 \\FRINTM V8.2D, V9.2D
2269 \\FRINTM H10, H11
2270 \\FRINTM S12, S13
2271 \\FRINTM D14, D15
2272 \\
2273 \\FCVTNS H0, H1
2274 \\FCVTNS S2, S3
2275 \\FCVTNS D4, D5
2276 \\FCVTNS V6.4H, V7.4H
2277 \\FCVTNS V8.8H, V9.8H
2278 \\FCVTNS V10.2S, V11.2S
2279 \\FCVTNS V12.4S, V13.4S
2280 \\FCVTNS V14.2D, V15.2D
2281 \\FCVTNS W16, H17
2282 \\FCVTNS X18, H19
2283 \\FCVTNS W20, S21
2284 \\FCVTNS X22, S23
2285 \\FCVTNS W24, D25
2286 \\FCVTNS X26, D27
2287 \\
2288 \\FCVTMS H0, H1
2289 \\FCVTMS S2, S3
2290 \\FCVTMS D4, D5
2291 \\FCVTMS V6.4H, V7.4H
2292 \\FCVTMS V8.8H, V9.8H
2293 \\FCVTMS V10.2S, V11.2S
2294 \\FCVTMS V12.4S, V13.4S
2295 \\FCVTMS V14.2D, V15.2D
2296 \\FCVTMS W16, H17
2297 \\FCVTMS X18, H19
2298 \\FCVTMS W20, S21
2299 \\FCVTMS X22, S23
2300 \\FCVTMS W24, D25
2301 \\FCVTMS X26, D27
2302 \\
2303 \\FCVTAS H0, H1
2304 \\FCVTAS S2, S3
2305 \\FCVTAS D4, D5
2306 \\FCVTAS V6.4H, V7.4H
2307 \\FCVTAS V8.8H, V9.8H
2308 \\FCVTAS V10.2S, V11.2S
2309 \\FCVTAS V12.4S, V13.4S
2310 \\FCVTAS V14.2D, V15.2D
2311 \\FCVTAS W16, H17
2312 \\FCVTAS X18, H19
2313 \\FCVTAS W20, S21
2314 \\FCVTAS X22, S23
2315 \\FCVTAS W24, D25
2316 \\FCVTAS X26, D27
2317 \\
2318 \\SCVTF H0, H1
2319 \\SCVTF S2, S3
2320 \\SCVTF D4, D5
2321 \\SCVTF V6.4H, V7.4H
2322 \\SCVTF V8.8H, V9.8H
2323 \\SCVTF V10.2S, V11.2S
2324 \\SCVTF V12.4S, V13.4S
2325 \\SCVTF V14.2D, V15.2D
2326 \\SCVTF H16, W17
2327 \\SCVTF H18, X19
2328 \\SCVTF S20, W21
2329 \\SCVTF S22, X23
2330 \\SCVTF D24, W25
2331 \\SCVTF D26, X27
2332 \\
2333 \\FCMGT H0, H1, #0.0
2334 \\FCMGT S2, S3, # 0.0
2335 \\FCMGT D4, D5, #+0.0
2336 \\FCMGT V6.4H, V7.4H, # +0.0
2337 \\FCMGT V8.8H, V9.8H, #0
2338 \\FCMGT V10.2S, V11.2S, # 0
2339 \\FCMGT V12.4S, V13.4S, #+0
2340 \\FCMGT V14.2D, V15.2D, # +0
2341 \\
2342 \\FCMEQ H0, H1, #0.0
2343 \\FCMEQ S2, S3, # 0.0
2344 \\FCMEQ D4, D5, #+0.0
2345 \\FCMEQ V6.4H, V7.4H, # +0.0
2346 \\FCMEQ V8.8H, V9.8H, #0
2347 \\FCMEQ V10.2S, V11.2S, # 0
2348 \\FCMEQ V12.4S, V13.4S, #+0
2349 \\FCMEQ V14.2D, V15.2D, # +0
2350 \\
2351 \\FCMLT H0, H1, #0.0
2352 \\FCMLT S2, S3, # 0.0
2353 \\FCMLT D4, D5, #+0.0
2354 \\FCMLT V6.4H, V7.4H, # +0.0
2355 \\FCMLT V8.8H, V9.8H, #0
2356 \\FCMLT V10.2S, V11.2S, # 0
2357 \\FCMLT V12.4S, V13.4S, #+0
2358 \\FCMLT V14.2D, V15.2D, # +0
2359 \\
2360 \\FRINTP V0.4H, V1.4H
2361 \\FRINTP V2.8H, V3.8H
2362 \\FRINTP V4.2S, V5.2S
2363 \\FRINTP V6.4S, V7.4S
2364 \\FRINTP V8.2D, V9.2D
2365 \\FRINTP H10, H11
2366 \\FRINTP S12, S13
2367 \\FRINTP D14, D15
2368 \\
2369 \\FRINTZ V0.4H, V1.4H
2370 \\FRINTZ V2.8H, V3.8H
2371 \\FRINTZ V4.2S, V5.2S
2372 \\FRINTZ V6.4S, V7.4S
2373 \\FRINTZ V8.2D, V9.2D
2374 \\FRINTZ H10, H11
2375 \\FRINTZ S12, S13
2376 \\FRINTZ D14, D15
2377 \\
2378 \\FCVTPS H0, H1
2379 \\FCVTPS S2, S3
2380 \\FCVTPS D4, D5
2381 \\FCVTPS V6.4H, V7.4H
2382 \\FCVTPS V8.8H, V9.8H
2383 \\FCVTPS V10.2S, V11.2S
2384 \\FCVTPS V12.4S, V13.4S
2385 \\FCVTPS V14.2D, V15.2D
2386 \\FCVTPS W16, H17
2387 \\FCVTPS X18, H19
2388 \\FCVTPS W20, S21
2389 \\FCVTPS X22, S23
2390 \\FCVTPS W24, D25
2391 \\FCVTPS X26, D27
2392 \\
2393 \\FCVTZS H0, H1
2394 \\FCVTZS S2, S3
2395 \\FCVTZS D4, D5
2396 \\FCVTZS V6.4H, V7.4H
2397 \\FCVTZS V8.8H, V9.8H
2398 \\FCVTZS V10.2S, V11.2S
2399 \\FCVTZS V12.4S, V13.4S
2400 \\FCVTZS V14.2D, V15.2D
2401 \\FCVTZS W16, H17
2402 \\FCVTZS X18, H19
2403 \\FCVTZS W20, S21
2404 \\FCVTZS X22, S23
2405 \\FCVTZS W24, D25
2406 \\FCVTZS X26, D27
2407 \\
2408 \\CMGE D0, D1, #00
2409 \\CMGE V2.8B, V3.8B, #0
2410 \\CMGE V4.16B, V5.16B, #0
2411 \\CMGE V6.4H, V7.4H, #0
2412 \\CMGE V8.8H, V9.8H, #0
2413 \\CMGE V10.2S, V11.2S, #0
2414 \\CMGE V12.4S, V13.4S, #0
2415 \\CMGE V14.2D, V15.2D, #0
2416 \\
2417 \\CMLE D0, D1, #00
2418 \\CMLE V2.8B, V3.8B, #0
2419 \\CMLE V4.16B, V5.16B, #0
2420 \\CMLE V6.4H, V7.4H, #0
2421 \\CMLE V8.8H, V9.8H, #0
2422 \\CMLE V10.2S, V11.2S, #0
2423 \\CMLE V12.4S, V13.4S, #0
2424 \\CMLE V14.2D, V15.2D, #0
2425 \\
2426 \\NEG D0, D1
2427 \\NEG V2.8B, V3.8B
2428 \\NEG V4.16B, V5.16B
2429 \\NEG V6.4H, V7.4H
2430 \\NEG V8.8H, V9.8H
2431 \\NEG V10.2S, V11.2S
2432 \\NEG V12.4S, V13.4S
2433 \\NEG V14.2D, V15.2D
2434 \\
2435 \\FCVTNU H0, H1
2436 \\FCVTNU S2, S3
2437 \\FCVTNU D4, D5
2438 \\FCVTNU V6.4H, V7.4H
2439 \\FCVTNU V8.8H, V9.8H
2440 \\FCVTNU V10.2S, V11.2S
2441 \\FCVTNU V12.4S, V13.4S
2442 \\FCVTNU V14.2D, V15.2D
2443 \\FCVTNU W16, H17
2444 \\FCVTNU X18, H19
2445 \\FCVTNU W20, S21
2446 \\FCVTNU X22, S23
2447 \\FCVTNU W24, D25
2448 \\FCVTNU X26, D27
2449 \\
2450 \\FCVTMU H0, H1
2451 \\FCVTMU S2, S3
2452 \\FCVTMU D4, D5
2453 \\FCVTMU V6.4H, V7.4H
2454 \\FCVTMU V8.8H, V9.8H
2455 \\FCVTMU V10.2S, V11.2S
2456 \\FCVTMU V12.4S, V13.4S
2457 \\FCVTMU V14.2D, V15.2D
2458 \\FCVTMU W16, H17
2459 \\FCVTMU X18, H19
2460 \\FCVTMU W20, S21
2461 \\FCVTMU X22, S23
2462 \\FCVTMU W24, D25
2463 \\FCVTMU X26, D27
2464 \\
2465 \\FCVTAU H0, H1
2466 \\FCVTAU S2, S3
2467 \\FCVTAU D4, D5
2468 \\FCVTAU V6.4H, V7.4H
2469 \\FCVTAU V8.8H, V9.8H
2470 \\FCVTAU V10.2S, V11.2S
2471 \\FCVTAU V12.4S, V13.4S
2472 \\FCVTAU V14.2D, V15.2D
2473 \\FCVTAU W16, H17
2474 \\FCVTAU X18, H19
2475 \\FCVTAU W20, S21
2476 \\FCVTAU X22, S23
2477 \\FCVTAU W24, D25
2478 \\FCVTAU X26, D27
2479 \\
2480 \\UCVTF H0, H1
2481 \\UCVTF S2, S3
2482 \\UCVTF D4, D5
2483 \\UCVTF V6.4H, V7.4H
2484 \\UCVTF V8.8H, V9.8H
2485 \\UCVTF V10.2S, V11.2S
2486 \\UCVTF V12.4S, V13.4S
2487 \\UCVTF V14.2D, V15.2D
2488 \\UCVTF H16, W17
2489 \\UCVTF H18, X19
2490 \\UCVTF S20, W21
2491 \\UCVTF S22, X23
2492 \\UCVTF D24, W25
2493 \\UCVTF D26, X27
2494 \\
2495 \\NOT V0.8B, V1.8B
2496 \\NOT V2.16B, V3.16B
2497 \\
2498 \\FCMGE H0, H1, #0.0
2499 \\FCMGE S2, S3, # 0.0
2500 \\FCMGE D4, D5, #+0.0
2501 \\FCMGE V6.4H, V7.4H, # +0.0
2502 \\FCMGE V8.8H, V9.8H, #0
2503 \\FCMGE V10.2S, V11.2S, # 0
2504 \\FCMGE V12.4S, V13.4S, #+0
2505 \\FCMGE V14.2D, V15.2D, # +0
2506 \\
2507 \\FCMLE H0, H1, #0.0
2508 \\FCMLE S2, S3, # 0.0
2509 \\FCMLE D4, D5, #+0.0
2510 \\FCMLE V6.4H, V7.4H, # +0.0
2511 \\FCMLE V8.8H, V9.8H, #0
2512 \\FCMLE V10.2S, V11.2S, # 0
2513 \\FCMLE V12.4S, V13.4S, #+0
2514 \\FCMLE V14.2D, V15.2D, # +0
2515 \\
2516 \\FRINTI V0.4H, V1.4H
2517 \\FRINTI V2.8H, V3.8H
2518 \\FRINTI V4.2S, V5.2S
2519 \\FRINTI V6.4S, V7.4S
2520 \\FRINTI V8.2D, V9.2D
2521 \\FRINTI H10, H11
2522 \\FRINTI S12, S13
2523 \\FRINTI D14, D15
2524 \\
2525 \\FCVTPU H0, H1
2526 \\FCVTPU S2, S3
2527 \\FCVTPU D4, D5
2528 \\FCVTPU V6.4H, V7.4H
2529 \\FCVTPU V8.8H, V9.8H
2530 \\FCVTPU V10.2S, V11.2S
2531 \\FCVTPU V12.4S, V13.4S
2532 \\FCVTPU V14.2D, V15.2D
2533 \\FCVTPU W16, H17
2534 \\FCVTPU X18, H19
2535 \\FCVTPU W20, S21
2536 \\FCVTPU X22, S23
2537 \\FCVTPU W24, D25
2538 \\FCVTPU X26, D27
2539 \\
2540 \\FCVTZU H0, H1
2541 \\FCVTZU S2, S3
2542 \\FCVTZU D4, D5
2543 \\FCVTZU V6.4H, V7.4H
2544 \\FCVTZU V8.8H, V9.8H
2545 \\FCVTZU V10.2S, V11.2S
2546 \\FCVTZU V12.4S, V13.4S
2547 \\FCVTZU V14.2D, V15.2D
2548 \\FCVTZU W16, H17
2549 \\FCVTZU X18, H19
2550 \\FCVTZU W20, S21
2551 \\FCVTZU X22, S23
2552 \\FCVTZU W24, D25
2553 \\FCVTZU X26, D27
2554 ,
2555 .operands = .empty,
2556 };
2557
2558 try std.testing.expectFmt("suqadd b0, b1", "{f}", .{(try as.nextInstruction()).?});
2559 try std.testing.expectFmt("suqadd h2, h3", "{f}", .{(try as.nextInstruction()).?});
2560 try std.testing.expectFmt("suqadd s4, s5", "{f}", .{(try as.nextInstruction()).?});
2561 try std.testing.expectFmt("suqadd d6, d7", "{f}", .{(try as.nextInstruction()).?});
2562 try std.testing.expectFmt("suqadd v8.8b, v9.8b", "{f}", .{(try as.nextInstruction()).?});
2563 try std.testing.expectFmt("suqadd v10.16b, v11.16b", "{f}", .{(try as.nextInstruction()).?});
2564 try std.testing.expectFmt("suqadd v12.4h, v13.4h", "{f}", .{(try as.nextInstruction()).?});
2565 try std.testing.expectFmt("suqadd v14.8h, v15.8h", "{f}", .{(try as.nextInstruction()).?});
2566 try std.testing.expectFmt("suqadd v16.2s, v17.2s", "{f}", .{(try as.nextInstruction()).?});
2567 try std.testing.expectFmt("suqadd v18.4s, v19.4s", "{f}", .{(try as.nextInstruction()).?});
2568 try std.testing.expectFmt("suqadd v20.2d, v21.2d", "{f}", .{(try as.nextInstruction()).?});
2569
2570 try std.testing.expectFmt("cnt v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2571 try std.testing.expectFmt("cnt v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2572
2573 try std.testing.expectFmt("sqabs b0, b1", "{f}", .{(try as.nextInstruction()).?});
2574 try std.testing.expectFmt("sqabs h2, h3", "{f}", .{(try as.nextInstruction()).?});
2575 try std.testing.expectFmt("sqabs s4, s5", "{f}", .{(try as.nextInstruction()).?});
2576 try std.testing.expectFmt("sqabs d6, d7", "{f}", .{(try as.nextInstruction()).?});
2577 try std.testing.expectFmt("sqabs v8.8b, v9.8b", "{f}", .{(try as.nextInstruction()).?});
2578 try std.testing.expectFmt("sqabs v10.16b, v11.16b", "{f}", .{(try as.nextInstruction()).?});
2579 try std.testing.expectFmt("sqabs v12.4h, v13.4h", "{f}", .{(try as.nextInstruction()).?});
2580 try std.testing.expectFmt("sqabs v14.8h, v15.8h", "{f}", .{(try as.nextInstruction()).?});
2581 try std.testing.expectFmt("sqabs v16.2s, v17.2s", "{f}", .{(try as.nextInstruction()).?});
2582 try std.testing.expectFmt("sqabs v18.4s, v19.4s", "{f}", .{(try as.nextInstruction()).?});
2583 try std.testing.expectFmt("sqabs v20.2d, v21.2d", "{f}", .{(try as.nextInstruction()).?});
2584
2585 try std.testing.expectFmt("cmgt d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2586 try std.testing.expectFmt("cmgt v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2587 try std.testing.expectFmt("cmgt v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2588 try std.testing.expectFmt("cmgt v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2589 try std.testing.expectFmt("cmgt v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2590 try std.testing.expectFmt("cmgt v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2591 try std.testing.expectFmt("cmgt v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2592 try std.testing.expectFmt("cmgt v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2593
2594 try std.testing.expectFmt("cmeq d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2595 try std.testing.expectFmt("cmeq v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2596 try std.testing.expectFmt("cmeq v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2597 try std.testing.expectFmt("cmeq v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2598 try std.testing.expectFmt("cmeq v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2599 try std.testing.expectFmt("cmeq v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2600 try std.testing.expectFmt("cmeq v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2601 try std.testing.expectFmt("cmeq v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2602
2603 try std.testing.expectFmt("cmlt d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2604 try std.testing.expectFmt("cmlt v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2605 try std.testing.expectFmt("cmlt v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2606 try std.testing.expectFmt("cmlt v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2607 try std.testing.expectFmt("cmlt v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2608 try std.testing.expectFmt("cmlt v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2609 try std.testing.expectFmt("cmlt v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2610 try std.testing.expectFmt("cmlt v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2611
2612 try std.testing.expectFmt("abs d0, d1", "{f}", .{(try as.nextInstruction()).?});
2613 try std.testing.expectFmt("abs v2.8b, v3.8b", "{f}", .{(try as.nextInstruction()).?});
2614 try std.testing.expectFmt("abs v4.16b, v5.16b", "{f}", .{(try as.nextInstruction()).?});
2615 try std.testing.expectFmt("abs v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2616 try std.testing.expectFmt("abs v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2617 try std.testing.expectFmt("abs v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2618 try std.testing.expectFmt("abs v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2619 try std.testing.expectFmt("abs v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2620
2621 try std.testing.expectFmt("sqxtn b0, h1", "{f}", .{(try as.nextInstruction()).?});
2622 try std.testing.expectFmt("sqxtn h2, s3", "{f}", .{(try as.nextInstruction()).?});
2623 try std.testing.expectFmt("sqxtn s4, d5", "{f}", .{(try as.nextInstruction()).?});
2624 try std.testing.expectFmt("sqxtn v6.8b, v7.8h", "{f}", .{(try as.nextInstruction()).?});
2625 try std.testing.expectFmt("sqxtn2 v8.16b, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2626 try std.testing.expectFmt("sqxtn v10.4h, v11.4s", "{f}", .{(try as.nextInstruction()).?});
2627 try std.testing.expectFmt("sqxtn2 v12.8h, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2628 try std.testing.expectFmt("sqxtn v14.2s, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2629 try std.testing.expectFmt("sqxtn2 v16.4s, v17.2d", "{f}", .{(try as.nextInstruction()).?});
2630
2631 try std.testing.expectFmt("frintn v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2632 try std.testing.expectFmt("frintn v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2633 try std.testing.expectFmt("frintn v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2634 try std.testing.expectFmt("frintn v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2635 try std.testing.expectFmt("frintn v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2636 try std.testing.expectFmt("frintn h10, h11", "{f}", .{(try as.nextInstruction()).?});
2637 try std.testing.expectFmt("frintn s12, s13", "{f}", .{(try as.nextInstruction()).?});
2638 try std.testing.expectFmt("frintn d14, d15", "{f}", .{(try as.nextInstruction()).?});
2639
2640 try std.testing.expectFmt("frintm v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2641 try std.testing.expectFmt("frintm v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2642 try std.testing.expectFmt("frintm v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2643 try std.testing.expectFmt("frintm v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2644 try std.testing.expectFmt("frintm v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2645 try std.testing.expectFmt("frintm h10, h11", "{f}", .{(try as.nextInstruction()).?});
2646 try std.testing.expectFmt("frintm s12, s13", "{f}", .{(try as.nextInstruction()).?});
2647 try std.testing.expectFmt("frintm d14, d15", "{f}", .{(try as.nextInstruction()).?});
2648
2649 try std.testing.expectFmt("fcvtns h0, h1", "{f}", .{(try as.nextInstruction()).?});
2650 try std.testing.expectFmt("fcvtns s2, s3", "{f}", .{(try as.nextInstruction()).?});
2651 try std.testing.expectFmt("fcvtns d4, d5", "{f}", .{(try as.nextInstruction()).?});
2652 try std.testing.expectFmt("fcvtns v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2653 try std.testing.expectFmt("fcvtns v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2654 try std.testing.expectFmt("fcvtns v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2655 try std.testing.expectFmt("fcvtns v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2656 try std.testing.expectFmt("fcvtns v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2657 try std.testing.expectFmt("fcvtns w16, h17", "{f}", .{(try as.nextInstruction()).?});
2658 try std.testing.expectFmt("fcvtns x18, h19", "{f}", .{(try as.nextInstruction()).?});
2659 try std.testing.expectFmt("fcvtns w20, s21", "{f}", .{(try as.nextInstruction()).?});
2660 try std.testing.expectFmt("fcvtns x22, s23", "{f}", .{(try as.nextInstruction()).?});
2661 try std.testing.expectFmt("fcvtns w24, d25", "{f}", .{(try as.nextInstruction()).?});
2662 try std.testing.expectFmt("fcvtns x26, d27", "{f}", .{(try as.nextInstruction()).?});
2663
2664 try std.testing.expectFmt("fcvtms h0, h1", "{f}", .{(try as.nextInstruction()).?});
2665 try std.testing.expectFmt("fcvtms s2, s3", "{f}", .{(try as.nextInstruction()).?});
2666 try std.testing.expectFmt("fcvtms d4, d5", "{f}", .{(try as.nextInstruction()).?});
2667 try std.testing.expectFmt("fcvtms v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2668 try std.testing.expectFmt("fcvtms v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2669 try std.testing.expectFmt("fcvtms v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2670 try std.testing.expectFmt("fcvtms v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2671 try std.testing.expectFmt("fcvtms v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2672 try std.testing.expectFmt("fcvtms w16, h17", "{f}", .{(try as.nextInstruction()).?});
2673 try std.testing.expectFmt("fcvtms x18, h19", "{f}", .{(try as.nextInstruction()).?});
2674 try std.testing.expectFmt("fcvtms w20, s21", "{f}", .{(try as.nextInstruction()).?});
2675 try std.testing.expectFmt("fcvtms x22, s23", "{f}", .{(try as.nextInstruction()).?});
2676 try std.testing.expectFmt("fcvtms w24, d25", "{f}", .{(try as.nextInstruction()).?});
2677 try std.testing.expectFmt("fcvtms x26, d27", "{f}", .{(try as.nextInstruction()).?});
2678
2679 try std.testing.expectFmt("fcvtas h0, h1", "{f}", .{(try as.nextInstruction()).?});
2680 try std.testing.expectFmt("fcvtas s2, s3", "{f}", .{(try as.nextInstruction()).?});
2681 try std.testing.expectFmt("fcvtas d4, d5", "{f}", .{(try as.nextInstruction()).?});
2682 try std.testing.expectFmt("fcvtas v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2683 try std.testing.expectFmt("fcvtas v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2684 try std.testing.expectFmt("fcvtas v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2685 try std.testing.expectFmt("fcvtas v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2686 try std.testing.expectFmt("fcvtas v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2687 try std.testing.expectFmt("fcvtas w16, h17", "{f}", .{(try as.nextInstruction()).?});
2688 try std.testing.expectFmt("fcvtas x18, h19", "{f}", .{(try as.nextInstruction()).?});
2689 try std.testing.expectFmt("fcvtas w20, s21", "{f}", .{(try as.nextInstruction()).?});
2690 try std.testing.expectFmt("fcvtas x22, s23", "{f}", .{(try as.nextInstruction()).?});
2691 try std.testing.expectFmt("fcvtas w24, d25", "{f}", .{(try as.nextInstruction()).?});
2692 try std.testing.expectFmt("fcvtas x26, d27", "{f}", .{(try as.nextInstruction()).?});
2693
2694 try std.testing.expectFmt("scvtf h0, h1", "{f}", .{(try as.nextInstruction()).?});
2695 try std.testing.expectFmt("scvtf s2, s3", "{f}", .{(try as.nextInstruction()).?});
2696 try std.testing.expectFmt("scvtf d4, d5", "{f}", .{(try as.nextInstruction()).?});
2697 try std.testing.expectFmt("scvtf v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2698 try std.testing.expectFmt("scvtf v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2699 try std.testing.expectFmt("scvtf v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2700 try std.testing.expectFmt("scvtf v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2701 try std.testing.expectFmt("scvtf v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2702 try std.testing.expectFmt("scvtf h16, w17", "{f}", .{(try as.nextInstruction()).?});
2703 try std.testing.expectFmt("scvtf h18, x19", "{f}", .{(try as.nextInstruction()).?});
2704 try std.testing.expectFmt("scvtf s20, w21", "{f}", .{(try as.nextInstruction()).?});
2705 try std.testing.expectFmt("scvtf s22, x23", "{f}", .{(try as.nextInstruction()).?});
2706 try std.testing.expectFmt("scvtf d24, w25", "{f}", .{(try as.nextInstruction()).?});
2707 try std.testing.expectFmt("scvtf d26, x27", "{f}", .{(try as.nextInstruction()).?});
2708
2709 try std.testing.expectFmt("fcmgt h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2710 try std.testing.expectFmt("fcmgt s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2711 try std.testing.expectFmt("fcmgt d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2712 try std.testing.expectFmt("fcmgt v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2713 try std.testing.expectFmt("fcmgt v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2714 try std.testing.expectFmt("fcmgt v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2715 try std.testing.expectFmt("fcmgt v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2716 try std.testing.expectFmt("fcmgt v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2717
2718 try std.testing.expectFmt("fcmeq h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2719 try std.testing.expectFmt("fcmeq s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2720 try std.testing.expectFmt("fcmeq d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2721 try std.testing.expectFmt("fcmeq v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2722 try std.testing.expectFmt("fcmeq v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2723 try std.testing.expectFmt("fcmeq v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2724 try std.testing.expectFmt("fcmeq v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2725 try std.testing.expectFmt("fcmeq v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2726
2727 try std.testing.expectFmt("fcmlt h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2728 try std.testing.expectFmt("fcmlt s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2729 try std.testing.expectFmt("fcmlt d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2730 try std.testing.expectFmt("fcmlt v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2731 try std.testing.expectFmt("fcmlt v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2732 try std.testing.expectFmt("fcmlt v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2733 try std.testing.expectFmt("fcmlt v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2734 try std.testing.expectFmt("fcmlt v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2735
2736 try std.testing.expectFmt("frintp v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2737 try std.testing.expectFmt("frintp v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2738 try std.testing.expectFmt("frintp v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2739 try std.testing.expectFmt("frintp v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2740 try std.testing.expectFmt("frintp v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2741 try std.testing.expectFmt("frintp h10, h11", "{f}", .{(try as.nextInstruction()).?});
2742 try std.testing.expectFmt("frintp s12, s13", "{f}", .{(try as.nextInstruction()).?});
2743 try std.testing.expectFmt("frintp d14, d15", "{f}", .{(try as.nextInstruction()).?});
2744
2745 try std.testing.expectFmt("frintz v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2746 try std.testing.expectFmt("frintz v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2747 try std.testing.expectFmt("frintz v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2748 try std.testing.expectFmt("frintz v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2749 try std.testing.expectFmt("frintz v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2750 try std.testing.expectFmt("frintz h10, h11", "{f}", .{(try as.nextInstruction()).?});
2751 try std.testing.expectFmt("frintz s12, s13", "{f}", .{(try as.nextInstruction()).?});
2752 try std.testing.expectFmt("frintz d14, d15", "{f}", .{(try as.nextInstruction()).?});
2753
2754 try std.testing.expectFmt("fcvtps h0, h1", "{f}", .{(try as.nextInstruction()).?});
2755 try std.testing.expectFmt("fcvtps s2, s3", "{f}", .{(try as.nextInstruction()).?});
2756 try std.testing.expectFmt("fcvtps d4, d5", "{f}", .{(try as.nextInstruction()).?});
2757 try std.testing.expectFmt("fcvtps v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2758 try std.testing.expectFmt("fcvtps v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2759 try std.testing.expectFmt("fcvtps v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2760 try std.testing.expectFmt("fcvtps v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2761 try std.testing.expectFmt("fcvtps v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2762 try std.testing.expectFmt("fcvtps w16, h17", "{f}", .{(try as.nextInstruction()).?});
2763 try std.testing.expectFmt("fcvtps x18, h19", "{f}", .{(try as.nextInstruction()).?});
2764 try std.testing.expectFmt("fcvtps w20, s21", "{f}", .{(try as.nextInstruction()).?});
2765 try std.testing.expectFmt("fcvtps x22, s23", "{f}", .{(try as.nextInstruction()).?});
2766 try std.testing.expectFmt("fcvtps w24, d25", "{f}", .{(try as.nextInstruction()).?});
2767 try std.testing.expectFmt("fcvtps x26, d27", "{f}", .{(try as.nextInstruction()).?});
2768
2769 try std.testing.expectFmt("fcvtzs h0, h1", "{f}", .{(try as.nextInstruction()).?});
2770 try std.testing.expectFmt("fcvtzs s2, s3", "{f}", .{(try as.nextInstruction()).?});
2771 try std.testing.expectFmt("fcvtzs d4, d5", "{f}", .{(try as.nextInstruction()).?});
2772 try std.testing.expectFmt("fcvtzs v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2773 try std.testing.expectFmt("fcvtzs v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2774 try std.testing.expectFmt("fcvtzs v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2775 try std.testing.expectFmt("fcvtzs v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2776 try std.testing.expectFmt("fcvtzs v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2777 try std.testing.expectFmt("fcvtzs w16, h17", "{f}", .{(try as.nextInstruction()).?});
2778 try std.testing.expectFmt("fcvtzs x18, h19", "{f}", .{(try as.nextInstruction()).?});
2779 try std.testing.expectFmt("fcvtzs w20, s21", "{f}", .{(try as.nextInstruction()).?});
2780 try std.testing.expectFmt("fcvtzs x22, s23", "{f}", .{(try as.nextInstruction()).?});
2781 try std.testing.expectFmt("fcvtzs w24, d25", "{f}", .{(try as.nextInstruction()).?});
2782 try std.testing.expectFmt("fcvtzs x26, d27", "{f}", .{(try as.nextInstruction()).?});
2783
2784 try std.testing.expectFmt("cmge d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2785 try std.testing.expectFmt("cmge v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2786 try std.testing.expectFmt("cmge v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2787 try std.testing.expectFmt("cmge v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2788 try std.testing.expectFmt("cmge v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2789 try std.testing.expectFmt("cmge v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2790 try std.testing.expectFmt("cmge v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2791 try std.testing.expectFmt("cmge v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2792
2793 try std.testing.expectFmt("cmle d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2794 try std.testing.expectFmt("cmle v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2795 try std.testing.expectFmt("cmle v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2796 try std.testing.expectFmt("cmle v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2797 try std.testing.expectFmt("cmle v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2798 try std.testing.expectFmt("cmle v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2799 try std.testing.expectFmt("cmle v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2800 try std.testing.expectFmt("cmle v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2801
2802 try std.testing.expectFmt("neg d0, d1", "{f}", .{(try as.nextInstruction()).?});
2803 try std.testing.expectFmt("neg v2.8b, v3.8b", "{f}", .{(try as.nextInstruction()).?});
2804 try std.testing.expectFmt("neg v4.16b, v5.16b", "{f}", .{(try as.nextInstruction()).?});
2805 try std.testing.expectFmt("neg v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2806 try std.testing.expectFmt("neg v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2807 try std.testing.expectFmt("neg v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2808 try std.testing.expectFmt("neg v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2809 try std.testing.expectFmt("neg v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2810
2811 try std.testing.expectFmt("fcvtnu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2812 try std.testing.expectFmt("fcvtnu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2813 try std.testing.expectFmt("fcvtnu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2814 try std.testing.expectFmt("fcvtnu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2815 try std.testing.expectFmt("fcvtnu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2816 try std.testing.expectFmt("fcvtnu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2817 try std.testing.expectFmt("fcvtnu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2818 try std.testing.expectFmt("fcvtnu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2819 try std.testing.expectFmt("fcvtnu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2820 try std.testing.expectFmt("fcvtnu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2821 try std.testing.expectFmt("fcvtnu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2822 try std.testing.expectFmt("fcvtnu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2823 try std.testing.expectFmt("fcvtnu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2824 try std.testing.expectFmt("fcvtnu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2825
2826 try std.testing.expectFmt("fcvtmu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2827 try std.testing.expectFmt("fcvtmu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2828 try std.testing.expectFmt("fcvtmu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2829 try std.testing.expectFmt("fcvtmu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2830 try std.testing.expectFmt("fcvtmu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2831 try std.testing.expectFmt("fcvtmu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2832 try std.testing.expectFmt("fcvtmu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2833 try std.testing.expectFmt("fcvtmu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2834 try std.testing.expectFmt("fcvtmu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2835 try std.testing.expectFmt("fcvtmu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2836 try std.testing.expectFmt("fcvtmu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2837 try std.testing.expectFmt("fcvtmu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2838 try std.testing.expectFmt("fcvtmu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2839 try std.testing.expectFmt("fcvtmu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2840
2841 try std.testing.expectFmt("fcvtau h0, h1", "{f}", .{(try as.nextInstruction()).?});
2842 try std.testing.expectFmt("fcvtau s2, s3", "{f}", .{(try as.nextInstruction()).?});
2843 try std.testing.expectFmt("fcvtau d4, d5", "{f}", .{(try as.nextInstruction()).?});
2844 try std.testing.expectFmt("fcvtau v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2845 try std.testing.expectFmt("fcvtau v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2846 try std.testing.expectFmt("fcvtau v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2847 try std.testing.expectFmt("fcvtau v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2848 try std.testing.expectFmt("fcvtau v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2849 try std.testing.expectFmt("fcvtau w16, h17", "{f}", .{(try as.nextInstruction()).?});
2850 try std.testing.expectFmt("fcvtau x18, h19", "{f}", .{(try as.nextInstruction()).?});
2851 try std.testing.expectFmt("fcvtau w20, s21", "{f}", .{(try as.nextInstruction()).?});
2852 try std.testing.expectFmt("fcvtau x22, s23", "{f}", .{(try as.nextInstruction()).?});
2853 try std.testing.expectFmt("fcvtau w24, d25", "{f}", .{(try as.nextInstruction()).?});
2854 try std.testing.expectFmt("fcvtau x26, d27", "{f}", .{(try as.nextInstruction()).?});
2855
2856 try std.testing.expectFmt("ucvtf h0, h1", "{f}", .{(try as.nextInstruction()).?});
2857 try std.testing.expectFmt("ucvtf s2, s3", "{f}", .{(try as.nextInstruction()).?});
2858 try std.testing.expectFmt("ucvtf d4, d5", "{f}", .{(try as.nextInstruction()).?});
2859 try std.testing.expectFmt("ucvtf v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2860 try std.testing.expectFmt("ucvtf v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2861 try std.testing.expectFmt("ucvtf v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2862 try std.testing.expectFmt("ucvtf v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2863 try std.testing.expectFmt("ucvtf v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2864 try std.testing.expectFmt("ucvtf h16, w17", "{f}", .{(try as.nextInstruction()).?});
2865 try std.testing.expectFmt("ucvtf h18, x19", "{f}", .{(try as.nextInstruction()).?});
2866 try std.testing.expectFmt("ucvtf s20, w21", "{f}", .{(try as.nextInstruction()).?});
2867 try std.testing.expectFmt("ucvtf s22, x23", "{f}", .{(try as.nextInstruction()).?});
2868 try std.testing.expectFmt("ucvtf d24, w25", "{f}", .{(try as.nextInstruction()).?});
2869 try std.testing.expectFmt("ucvtf d26, x27", "{f}", .{(try as.nextInstruction()).?});
2870
2871 try std.testing.expectFmt("not v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2872 try std.testing.expectFmt("not v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2873
2874 try std.testing.expectFmt("fcmge h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2875 try std.testing.expectFmt("fcmge s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2876 try std.testing.expectFmt("fcmge d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2877 try std.testing.expectFmt("fcmge v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2878 try std.testing.expectFmt("fcmge v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2879 try std.testing.expectFmt("fcmge v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2880 try std.testing.expectFmt("fcmge v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2881 try std.testing.expectFmt("fcmge v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2882
2883 try std.testing.expectFmt("fcmle h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2884 try std.testing.expectFmt("fcmle s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2885 try std.testing.expectFmt("fcmle d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2886 try std.testing.expectFmt("fcmle v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2887 try std.testing.expectFmt("fcmle v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2888 try std.testing.expectFmt("fcmle v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2889 try std.testing.expectFmt("fcmle v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2890 try std.testing.expectFmt("fcmle v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2891
2892 try std.testing.expectFmt("frinti v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2893 try std.testing.expectFmt("frinti v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2894 try std.testing.expectFmt("frinti v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2895 try std.testing.expectFmt("frinti v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2896 try std.testing.expectFmt("frinti v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2897 try std.testing.expectFmt("frinti h10, h11", "{f}", .{(try as.nextInstruction()).?});
2898 try std.testing.expectFmt("frinti s12, s13", "{f}", .{(try as.nextInstruction()).?});
2899 try std.testing.expectFmt("frinti d14, d15", "{f}", .{(try as.nextInstruction()).?});
2900
2901 try std.testing.expectFmt("fcvtpu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2902 try std.testing.expectFmt("fcvtpu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2903 try std.testing.expectFmt("fcvtpu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2904 try std.testing.expectFmt("fcvtpu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2905 try std.testing.expectFmt("fcvtpu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2906 try std.testing.expectFmt("fcvtpu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2907 try std.testing.expectFmt("fcvtpu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2908 try std.testing.expectFmt("fcvtpu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2909 try std.testing.expectFmt("fcvtpu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2910 try std.testing.expectFmt("fcvtpu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2911 try std.testing.expectFmt("fcvtpu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2912 try std.testing.expectFmt("fcvtpu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2913 try std.testing.expectFmt("fcvtpu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2914 try std.testing.expectFmt("fcvtpu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2915
2916 try std.testing.expectFmt("fcvtzu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2917 try std.testing.expectFmt("fcvtzu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2918 try std.testing.expectFmt("fcvtzu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2919 try std.testing.expectFmt("fcvtzu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2920 try std.testing.expectFmt("fcvtzu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2921 try std.testing.expectFmt("fcvtzu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2922 try std.testing.expectFmt("fcvtzu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2923 try std.testing.expectFmt("fcvtzu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2924 try std.testing.expectFmt("fcvtzu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2925 try std.testing.expectFmt("fcvtzu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2926 try std.testing.expectFmt("fcvtzu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2927 try std.testing.expectFmt("fcvtzu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2928 try std.testing.expectFmt("fcvtzu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2929 try std.testing.expectFmt("fcvtzu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2930
2931 try std.testing.expect(null == try as.nextInstruction());
2932}
16782933
16792934const aarch64 = @import("../aarch64.zig");
16802935const Assemble = @This();
src/codegen/aarch64/Disassemble.zig+527-96
......@@ -3,9 +3,18 @@ mnemonic_operands_separator: []const u8 = " ",
33operands_separator: []const u8 = ", ",
44enable_aliases: bool = true,
55
6pub const Case = enum { lower, upper };
6pub const Case = enum {
7 lower,
8 upper,
9 pub fn convert(case: Case, c: u8) u8 {
10 return switch (case) {
11 .lower => std.ascii.toLower(c),
12 .upper => std.ascii.toUpper(c),
13 };
14 }
15};
716
8pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void {
17pub fn printInstruction(dis: Disassemble, inst: aarch64.encoding.Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void {
918 unallocated: switch (inst.decode()) {
1019 .unallocated => break :unallocated,
1120 .reserved => |reserved| switch (reserved.decode()) {
......@@ -23,13 +32,13 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
2332 .pc_relative_addressing => |pc_relative_addressing| {
2433 const group = pc_relative_addressing.group;
2534 const imm = (@as(i33, group.immhi) << 2 | @as(i33, group.immlo) << 0) + @as(i33, switch (group.op) {
26 .adr => Instruction.size,
35 .adr => aarch64.encoding.Instruction.size,
2736 .adrp => 0,
2837 });
2938 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{
3039 fmtCase(group.op, dis.case),
3140 dis.mnemonic_operands_separator,
32 group.Rd.decodeInteger(.doubleword, .{}).fmtCase(dis.case),
41 group.Rd.decode(.{}).x().fmtCase(dis.case),
3342 dis.operands_separator,
3443 @as(u8, if (imm < 0) '-' else '+'),
3544 switch (group.op) {
......@@ -45,8 +54,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
4554 const sf = group.sf;
4655 const sh = group.sh;
4756 const imm12 = group.imm12;
48 const Rn = group.Rn.decodeInteger(sf, .{ .sp = true });
49 const Rd = group.Rd.decodeInteger(sf, .{ .sp = !S });
57 const Rn = group.Rn.decode(.{ .sp = true }).general(sf);
58 const Rd = group.Rd.decode(.{ .sp = !S }).general(sf);
5059 const elide_shift = sh == .@"0";
5160 if (dis.enable_aliases and op == .add and S == false and elide_shift and imm12 == 0 and
5261 (Rn.alias == .sp or Rd.alias == .sp)) try writer.print("{f}{s}{f}{s}{f}", .{
......@@ -82,8 +91,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
8291 .word => @as(i32, @bitCast(@as(u32, @intCast(decoded_imm)))),
8392 .doubleword => @as(i64, @bitCast(decoded_imm)),
8493 };
85 const Rn = group.Rn.decodeInteger(sf, .{});
86 const Rd = group.Rd.decodeInteger(sf, .{ .sp = decoded != .ands });
94 const Rn = group.Rn.decode(.{}).general(sf);
95 const Rd = group.Rd.decode(.{ .sp = decoded != .ands }).general(sf);
8796 return if (dis.enable_aliases and decoded == .orr and Rn.alias == .zr and !group.imm.moveWidePreferred(sf)) writer.print("{f}{s}{f}{s}#{s}0x{x}", .{
8897 fmtCase(.mov, dis.case),
8998 dis.mnemonic_operands_separator,
......@@ -115,7 +124,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
115124 const sf = group.sf;
116125 const hw = group.hw;
117126 const imm16 = group.imm16;
118 const Rd = group.Rd.decodeInteger(sf, .{});
127 const Rd = group.Rd.decode(.{}).general(sf);
119128 const elide_shift = hw == .@"0";
120129 if (dis.enable_aliases and switch (decoded) {
121130 .unallocated => unreachable,
......@@ -166,9 +175,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
166175 return writer.print("{f}{s}{f}{s}{f}{s}#{d}{s}#{d}", .{
167176 fmtCase(decoded, dis.case),
168177 dis.mnemonic_operands_separator,
169 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),
178 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
170179 dis.operands_separator,
171 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),
180 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
172181 dis.operands_separator,
173182 group.imm.immr,
174183 dis.operands_separator,
......@@ -183,11 +192,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
183192 return writer.print("{f}{s}{f}{s}{f}{s}{f}{s}#{d}", .{
184193 fmtCase(decoded, dis.case),
185194 dis.mnemonic_operands_separator,
186 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),
195 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
187196 dis.operands_separator,
188 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),
197 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
189198 dis.operands_separator,
190 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),
199 group.Rm.decode(.{}).general(sf).fmtCase(dis.case),
191200 dis.operands_separator,
192201 group.imms,
193202 });
......@@ -248,7 +257,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
248257 const decoded = unconditional_branch_register.decode();
249258 if (decoded == .unallocated) break :unallocated;
250259 const group = unconditional_branch_register.group;
251 const Rn = group.Rn.decodeInteger(.doubleword, .{});
260 const Rn = group.Rn.decode(.{}).x();
252261 try writer.print("{f}", .{fmtCase(decoded, dis.case)});
253262 return if (decoded != .ret or Rn.alias != .r30) try writer.print("{s}{f}", .{
254263 dis.mnemonic_operands_separator,
......@@ -271,7 +280,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
271280 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{
272281 fmtCase(group.op, dis.case),
273282 dis.mnemonic_operands_separator,
274 group.Rt.decodeInteger(group.sf, .{}).fmtCase(dis.case),
283 group.Rt.decode(.{}).general(group.sf).fmtCase(dis.case),
275284 dis.operands_separator,
276285 @as(u8, if (imm < 0) '-' else '+'),
277286 @abs(imm) << 2,
......@@ -283,7 +292,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
283292 return writer.print("{f}{s}{f}{s}#0x{d}{s}.{c}0x{x}", .{
284293 fmtCase(group.op, dis.case),
285294 dis.mnemonic_operands_separator,
286 group.Rt.decodeInteger(@enumFromInt(group.b5), .{}).fmtCase(dis.case),
295 group.Rt.decode(.{}).general(@enumFromInt(group.b5)).fmtCase(dis.case),
287296 dis.operands_separator,
288297 @as(u6, group.b5) << 5 |
289298 @as(u6, group.b40) << 0,
......@@ -303,15 +312,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
303312 const decoded = integer.decode();
304313 if (decoded == .unallocated) break :unallocated;
305314 const group = integer.group;
306 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);
315 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
307316 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
308317 fmtCase(decoded, dis.case),
309318 dis.mnemonic_operands_separator,
310 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
319 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
311320 dis.operands_separator,
312 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),
321 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
313322 dis.operands_separator,
314 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
323 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
315324 dis.operands_separator,
316325 if (group.imm7 < 0) "-" else "",
317326 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),
......@@ -325,11 +334,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
325334 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
326335 fmtCase(decoded, dis.case),
327336 dis.mnemonic_operands_separator,
328 group.Rt.decodeVector(vs).fmtCase(dis.case),
337 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
329338 dis.operands_separator,
330 group.Rt2.decodeVector(vs).fmtCase(dis.case),
339 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
331340 dis.operands_separator,
332 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
341 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
333342 dis.operands_separator,
334343 if (group.imm7 < 0) "-" else "",
335344 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),
......@@ -341,15 +350,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
341350 const decoded = integer.decode();
342351 if (decoded == .unallocated) break :unallocated;
343352 const group = integer.group;
344 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);
353 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
345354 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{
346355 fmtCase(decoded, dis.case),
347356 dis.mnemonic_operands_separator,
348 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
357 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
349358 dis.operands_separator,
350 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),
359 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
351360 dis.operands_separator,
352 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
361 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
353362 });
354363 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{
355364 dis.operands_separator,
......@@ -366,11 +375,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
366375 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{
367376 fmtCase(decoded, dis.case),
368377 dis.mnemonic_operands_separator,
369 group.Rt.decodeVector(vs).fmtCase(dis.case),
378 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
370379 dis.operands_separator,
371 group.Rt2.decodeVector(vs).fmtCase(dis.case),
380 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
372381 dis.operands_separator,
373 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
382 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
374383 });
375384 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{
376385 dis.operands_separator,
......@@ -385,15 +394,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
385394 const decoded = integer.decode();
386395 if (decoded == .unallocated) break :unallocated;
387396 const group = integer.group;
388 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);
397 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
389398 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
390399 fmtCase(decoded, dis.case),
391400 dis.mnemonic_operands_separator,
392 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
401 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
393402 dis.operands_separator,
394 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),
403 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
395404 dis.operands_separator,
396 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
405 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
397406 dis.operands_separator,
398407 if (group.imm7 < 0) "-" else "",
399408 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),
......@@ -407,11 +416,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
407416 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
408417 fmtCase(decoded, dis.case),
409418 dis.mnemonic_operands_separator,
410 group.Rt.decodeVector(vs).fmtCase(dis.case),
419 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
411420 dis.operands_separator,
412 group.Rt2.decodeVector(vs).fmtCase(dis.case),
421 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
413422 dis.operands_separator,
414 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
423 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
415424 dis.operands_separator,
416425 if (group.imm7 < 0) "-" else "",
417426 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),
......@@ -422,7 +431,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
422431 .register_immediate_post_indexed => |register_immediate_post_indexed| switch (register_immediate_post_indexed.decode()) {
423432 .integer => |integer| {
424433 const decoded = integer.decode();
425 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {
434 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
426435 .unallocated => break :unallocated,
427436 .strb, .ldrb, .strh, .ldrh => .word,
428437 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
......@@ -436,9 +445,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
436445 return writer.print("{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
437446 fmtCase(decoded, dis.case),
438447 dis.mnemonic_operands_separator,
439 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
448 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
440449 dis.operands_separator,
441 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
450 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
442451 dis.operands_separator,
443452 if (group.imm9 < 0) "-" else "",
444453 @abs(group.imm9),
......@@ -450,7 +459,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
450459 .register_immediate_pre_indexed => |register_immediate_pre_indexed| switch (register_immediate_pre_indexed.decode()) {
451460 .integer => |integer| {
452461 const decoded = integer.decode();
453 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {
462 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
454463 .unallocated => break :unallocated,
455464 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
456465 0b0 => .doubleword,
......@@ -464,9 +473,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
464473 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
465474 fmtCase(decoded, dis.case),
466475 dis.mnemonic_operands_separator,
467 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
476 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
468477 dis.operands_separator,
469 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
478 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
470479 dis.operands_separator,
471480 if (group.imm9 < 0) "-" else "",
472481 @abs(group.imm9),
......@@ -479,9 +488,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
479488 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
480489 fmtCase(decoded, dis.case),
481490 dis.mnemonic_operands_separator,
482 group.Rt.decodeVector(group.opc1.decode(group.size)).fmtCase(dis.case),
491 group.Rt.decode(.{ .V = true }).scalar(group.opc1.decode(group.size)).fmtCase(dis.case),
483492 dis.operands_separator,
484 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
493 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
485494 dis.operands_separator,
486495 if (group.imm9 < 0) "-" else "",
487496 @abs(group.imm9),
......@@ -491,7 +500,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
491500 .register_register_offset => |register_register_offset| switch (register_register_offset.decode()) {
492501 .integer => |integer| {
493502 const decoded = integer.decode();
494 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {
503 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
495504 .unallocated, .prfm => break :unallocated,
496505 .strb, .ldrb, .strh, .ldrh => .word,
497506 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
......@@ -505,11 +514,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
505514 try writer.print("{f}{s}{f}{s}[{f}{s}{f}", .{
506515 fmtCase(decoded, dis.case),
507516 dis.mnemonic_operands_separator,
508 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
517 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
509518 dis.operands_separator,
510 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
519 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
511520 dis.operands_separator,
512 group.Rm.decodeInteger(group.option.sf(), .{}).fmtCase(dis.case),
521 group.Rm.decode(.{}).general(group.option.sf()).fmtCase(dis.case),
513522 });
514523 if (group.option != .lsl or group.S) {
515524 try writer.print("{s}{f}", .{
......@@ -527,7 +536,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
527536 .register_unsigned_immediate => |register_unsigned_immediate| switch (register_unsigned_immediate.decode()) {
528537 .integer => |integer| {
529538 const decoded = integer.decode();
530 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {
539 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
531540 .unallocated, .prfm => break :unallocated,
532541 .strb, .ldrb, .strh, .ldrh => .word,
533542 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
......@@ -541,9 +550,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
541550 try writer.print("{f}{s}{f}{s}[{f}", .{
542551 fmtCase(decoded, dis.case),
543552 dis.mnemonic_operands_separator,
544 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),
553 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
545554 dis.operands_separator,
546 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),
555 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
547556 });
548557 if (group.imm12 > 0) try writer.print("{s}#0x{x}", .{
549558 dis.operands_separator,
......@@ -562,13 +571,21 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
562571 const group = data_processing_two_source.group;
563572 const sf = group.sf;
564573 return writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
565 fmtCase(decoded, dis.case),
574 if (dis.enable_aliases) fmtCase(@as(enum { udiv, sdiv, lsl, lsr, asr, ror }, switch (decoded) {
575 .unallocated => unreachable,
576 .udiv => .udiv,
577 .sdiv => .sdiv,
578 .lslv => .lsl,
579 .lsrv => .lsr,
580 .asrv => .asr,
581 .rorv => .ror,
582 }), dis.case) else fmtCase(decoded, dis.case),
566583 dis.mnemonic_operands_separator,
567 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),
584 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
568585 dis.operands_separator,
569 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),
586 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
570587 dis.operands_separator,
571 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),
588 group.Rm.decode(.{}).general(sf).fmtCase(dis.case),
572589 });
573590 },
574591 .data_processing_one_source => |data_processing_one_source| {
......@@ -579,9 +596,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
579596 return writer.print("{f}{s}{f}{s}{f}", .{
580597 fmtCase(decoded, dis.case),
581598 dis.mnemonic_operands_separator,
582 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),
599 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
583600 dis.operands_separator,
584 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),
601 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
585602 });
586603 },
587604 .logical_shifted_register => |logical_shifted_register| {
......@@ -590,10 +607,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
590607 const group = logical_shifted_register.group;
591608 const sf = group.sf;
592609 const shift = group.shift;
593 const Rm = group.Rm.decodeInteger(sf, .{});
610 const Rm = group.Rm.decode(.{}).general(sf);
594611 const amount = group.imm6;
595 const Rn = group.Rn.decodeInteger(sf, .{});
596 const Rd = group.Rd.decodeInteger(sf, .{});
612 const Rn = group.Rn.decode(.{}).general(sf);
613 const Rd = group.Rd.decode(.{}).general(sf);
597614 const elide_shift = shift == .lsl and amount == 0;
598615 if (dis.enable_aliases and switch (decoded) {
599616 else => false,
......@@ -636,10 +653,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
636653 const group = add_subtract_shifted_register.group;
637654 const sf = group.sf;
638655 const shift = group.shift;
639 const Rm = group.Rm.decodeInteger(sf, .{});
656 const Rm = group.Rm.decode(.{}).general(sf);
640657 const imm6 = group.imm6;
641 const Rn = group.Rn.decodeInteger(sf, .{});
642 const Rd = group.Rd.decodeInteger(sf, .{});
658 const Rn = group.Rn.decode(.{}).general(sf);
659 const Rd = group.Rd.decode(.{}).general(sf);
643660 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
644661 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {
645662 .add => .cmn,
......@@ -678,9 +695,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
678695 if (decoded == .unallocated) break :unallocated;
679696 const group = add_subtract_extended_register.group;
680697 const sf = group.sf;
681 const Rm = group.Rm.decodeInteger(group.option.sf(), .{});
682 const Rn = group.Rn.decodeInteger(sf, .{ .sp = true });
683 const Rd = group.Rd.decodeInteger(sf, .{ .sp = true });
698 const Rm = group.Rm.decode(.{}).general(group.option.sf());
699 const Rn = group.Rn.decode(.{ .sp = true }).general(sf);
700 const Rd = group.Rd.decode(.{ .sp = true }).general(sf);
684701 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
685702 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {
686703 .add => .cmn,
......@@ -699,7 +716,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
699716 dis.operands_separator,
700717 Rm.fmtCase(dis.case),
701718 });
702 return if (group.option != @as(Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option, switch (sf) {
719 return if (group.option != @as(aarch64.encoding.Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option, switch (sf) {
703720 .word => .uxtw,
704721 .doubleword => .uxtx,
705722 }) or group.imm3 != 0) writer.print("{s}{f} #{d}", .{
......@@ -712,9 +729,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
712729 const decoded = add_subtract_with_carry.decode();
713730 const group = add_subtract_with_carry.group;
714731 const sf = group.sf;
715 const Rm = group.Rm.decodeInteger(sf, .{});
716 const Rn = group.Rn.decodeInteger(sf, .{});
717 const Rd = group.Rd.decodeInteger(sf, .{});
732 const Rm = group.Rm.decode(.{}).general(sf);
733 const Rn = group.Rn.decode(.{}).general(sf);
734 const Rd = group.Rd.decode(.{}).general(sf);
718735 return if (dis.enable_aliases and group.op == .sbc and Rn.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
719736 fmtCase(@as(enum { ngc, ngcs }, switch (group.S) {
720737 false => .ngc,
......@@ -743,10 +760,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
743760 if (decoded == .unallocated) break :unallocated;
744761 const group = conditional_select.group;
745762 const sf = group.sf;
746 const Rm = group.Rm.decodeInteger(sf, .{});
763 const Rm = group.Rm.decode(.{}).general(sf);
747764 const cond = group.cond;
748 const Rn = group.Rn.decodeInteger(sf, .{});
749 const Rd = group.Rd.decodeInteger(sf, .{});
765 const Rn = group.Rn.decode(.{}).general(sf);
766 const Rd = group.Rd.decode(.{}).general(sf);
750767 return if (dis.enable_aliases and group.op != group.op2 and Rm.alias == .zr and cond != .al and cond != .nv and Rn.alias == Rm.alias) writer.print("{f}{s}{f}{s}{f}", .{
751768 fmtCase(@as(enum { cset, csetm }, switch (decoded) {
752769 else => unreachable,
......@@ -784,34 +801,447 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
784801 },
785802 .data_processing_three_source => |data_processing_three_source| {
786803 const decoded = data_processing_three_source.decode();
787 if (decoded == .unallocated) break :unallocated;
788804 const group = data_processing_three_source.group;
789805 const sf = group.sf;
806 const operand_sf = switch (decoded) {
807 .unallocated => break :unallocated,
808 .madd, .msub, .smulh, .umulh => sf,
809 .smaddl, .smsubl, .umaddl, .umsubl => .word,
810 };
811 const Ra = group.Ra.decode(.{}).general(sf);
812 const elide_addend = dis.enable_aliases and Ra.alias == .zr;
790813 try writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
791 fmtCase(decoded, dis.case),
814 if (elide_addend) fmtCase(@as(enum {
815 mul,
816 mneg,
817 smull,
818 smnegl,
819 smulh,
820 umull,
821 umnegl,
822 umulh,
823 }, switch (decoded) {
824 .unallocated => unreachable,
825 .madd => .mul,
826 .msub => .mneg,
827 .smaddl => .smull,
828 .smsubl => .smnegl,
829 .smulh => .smulh,
830 .umaddl => .umull,
831 .umsubl => .umnegl,
832 .umulh => .umulh,
833 }), dis.case) else fmtCase(decoded, dis.case),
792834 dis.mnemonic_operands_separator,
793 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),
835 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
794836 dis.operands_separator,
795 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),
837 group.Rn.decode(.{}).general(operand_sf).fmtCase(dis.case),
796838 dis.operands_separator,
797 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),
839 group.Rm.decode(.{}).general(operand_sf).fmtCase(dis.case),
798840 });
799 return switch (decoded) {
841 return if (!elide_addend) switch (decoded) {
800842 .unallocated => unreachable,
801843 .madd, .msub, .smaddl, .smsubl, .umaddl, .umsubl => writer.print("{s}{f}", .{
802844 dis.operands_separator,
803 group.Ra.decodeInteger(sf, .{}).fmtCase(dis.case),
845 Ra.fmtCase(dis.case),
804846 }),
805847 .smulh, .umulh => {},
806848 };
807849 },
808850 },
809 .data_processing_vector => {},
851 .data_processing_vector => |data_processing_vector| switch (data_processing_vector.decode()) {
852 .unallocated => break :unallocated,
853 .simd_scalar_copy => |simd_scalar_copy| {
854 const decoded = simd_scalar_copy.decode();
855 if (decoded == .unallocated) break :unallocated;
856 const group = simd_scalar_copy.group;
857 const elem_size = @ctz(group.imm5);
858 return writer.print("{f}{s}{f}{s}{f}", .{
859 if (dis.enable_aliases and decoded == .dup)
860 fmtCase(.mov, dis.case)
861 else
862 fmtCase(decoded, dis.case),
863 dis.mnemonic_operands_separator,
864 group.Rd.decode(.{ .V = true }).scalar(@enumFromInt(elem_size)).fmtCase(dis.case),
865 dis.operands_separator,
866 group.Rn.decode(.{ .V = true }).element(
867 @enumFromInt(elem_size),
868 @intCast(group.imm5 >> (elem_size + 1)),
869 ).fmtCase(dis.case),
870 });
871 },
872 .simd_scalar_two_register_miscellaneous_fp16 => |simd_scalar_two_register_miscellaneous_fp16| {
873 const decoded = simd_scalar_two_register_miscellaneous_fp16.decode();
874 if (decoded == .unallocated) break :unallocated;
875 const group = simd_scalar_two_register_miscellaneous_fp16.group;
876 try writer.print("{f}{s}{f}{s}{f}", .{
877 fmtCase(decoded, dis.case),
878 dis.mnemonic_operands_separator,
879 group.Rd.decode(.{ .V = true }).h().fmtCase(dis.case),
880 dis.operands_separator,
881 group.Rn.decode(.{ .V = true }).h().fmtCase(dis.case),
882 });
883 return switch (decoded) {
884 .unallocated => unreachable,
885 else => {},
886 .fcmgt,
887 .fcmeq,
888 .fcmlt,
889 .fcmge,
890 .fcmle,
891 => writer.print("{s}#0.0", .{dis.operands_separator}),
892 };
893 },
894 .simd_scalar_two_register_miscellaneous => |simd_scalar_two_register_miscellaneous| {
895 const decoded = simd_scalar_two_register_miscellaneous.decode();
896 const group = simd_scalar_two_register_miscellaneous.group;
897 const elem_size = switch (decoded) {
898 .unallocated => break :unallocated,
899 inline .fcvtns,
900 .fcvtms,
901 .fcvtas,
902 .scvtf,
903 .fcvtps,
904 .fcvtzs,
905 .fcvtxn,
906 .fcvtnu,
907 .fcvtmu,
908 .fcvtau,
909 .ucvtf,
910 .fcvtpu,
911 .fcvtzu,
912 => |f| f.sz.toScalarSize(),
913 else => group.size.toScalarSize(),
914 };
915 try writer.print("{f}{s}{f}{s}{f}", .{
916 fmtCase(decoded, dis.case),
917 dis.mnemonic_operands_separator,
918 group.Rd.decode(.{ .V = true }).scalar(elem_size).fmtCase(dis.case),
919 dis.operands_separator,
920 group.Rn.decode(.{ .V = true }).scalar(switch (decoded) {
921 .unallocated => unreachable,
922 else => elem_size,
923 .sqxtn => elem_size.w(),
924 }).fmtCase(dis.case),
925 });
926 return switch (decoded) {
927 .unallocated => unreachable,
928 else => {},
929 .cmgt,
930 .cmeq,
931 .cmlt,
932 .cmge,
933 .cmle,
934 => writer.print("{s}#0", .{dis.operands_separator}),
935 .fcmgt,
936 .fcmeq,
937 .fcmlt,
938 .fcmge,
939 .fcmle,
940 => writer.print("{s}#0.0", .{dis.operands_separator}),
941 };
942 },
943 .simd_scalar_pairwise => {},
944 .simd_copy => |simd_copy| {
945 const decoded = simd_copy.decode();
946 if (decoded == .unallocated) break :unallocated;
947 const group = simd_copy.group;
948 const elem_size = @ctz(group.imm5);
949 return writer.print("{f}{s}{f}{s}{f}", .{
950 if (dis.enable_aliases and switch (decoded) {
951 .unallocated => unreachable,
952 .dup, .smov => false,
953 .umov => elem_size >= 2,
954 .ins => true,
955 }) fmtCase(.mov, dis.case) else fmtCase(decoded, dis.case),
956 dis.mnemonic_operands_separator,
957 switch (decoded) {
958 .unallocated => unreachable,
959 .dup => |dup| group.Rd.decode(.{ .V = true }).vector(.wrap(.{
960 .size = dup.Q,
961 .elem_size = @enumFromInt(elem_size),
962 })),
963 inline .smov, .umov => |mov| group.Rd.decode(.{}).general(mov.Q),
964 .ins => group.Rd.decode(.{ .V = true }).element(
965 @enumFromInt(elem_size),
966 @intCast(group.imm5 >> (elem_size + 1)),
967 ),
968 }.fmtCase(dis.case),
969 dis.operands_separator,
970 switch (decoded) {
971 .unallocated => unreachable,
972 .dup => |dup| switch (dup.imm4) {
973 .element => group.Rn.decode(.{ .V = true }).element(
974 @enumFromInt(elem_size),
975 @intCast(group.imm5 >> (elem_size + 1)),
976 ),
977 .general => group.Rn.decode(.{}).general(switch (elem_size) {
978 0...2 => .word,
979 3 => .doubleword,
980 else => unreachable,
981 }),
982 _ => unreachable,
983 },
984 .smov, .umov => group.Rn.decode(.{ .V = true }).element(
985 @enumFromInt(elem_size),
986 @intCast(group.imm5 >> (elem_size + 1)),
987 ),
988 .ins => |ins| switch (ins.op) {
989 .element => group.Rn.decode(.{ .V = true }).element(
990 @enumFromInt(elem_size),
991 @intCast(group.imm4 >> @intCast(elem_size)),
992 ),
993 .general => group.Rn.decode(.{}).general(switch (elem_size) {
994 0...2 => .word,
995 3 => .doubleword,
996 else => unreachable,
997 }),
998 },
999 }.fmtCase(dis.case),
1000 });
1001 },
1002 .simd_two_register_miscellaneous_fp16 => |simd_two_register_miscellaneous_fp16| {
1003 const decoded = simd_two_register_miscellaneous_fp16.decode();
1004 if (decoded == .unallocated) break :unallocated;
1005 const group = simd_two_register_miscellaneous_fp16.group;
1006 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1007 .size = group.Q,
1008 .elem_size = .half,
1009 });
1010 try writer.print("{f}{s}{f}{s}{f}", .{
1011 fmtCase(decoded, dis.case),
1012 dis.mnemonic_operands_separator,
1013 group.Rd.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1014 dis.operands_separator,
1015 group.Rn.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1016 });
1017 return switch (decoded) {
1018 .unallocated => unreachable,
1019 else => {},
1020 .fcmgt,
1021 .fcmeq,
1022 .fcmlt,
1023 .fcmge,
1024 .fcmle,
1025 => writer.print("{s}#0.0", .{dis.operands_separator}),
1026 };
1027 },
1028 .simd_two_register_miscellaneous => |simd_two_register_miscellaneous| {
1029 const decoded = simd_two_register_miscellaneous.decode();
1030 const group = simd_two_register_miscellaneous.group;
1031 const elem_size = switch (decoded) {
1032 .unallocated => break :unallocated,
1033 inline .frintn,
1034 .frintm,
1035 .fcvtns,
1036 .fcvtms,
1037 .fcvtas,
1038 .scvtf,
1039 .frintp,
1040 .frintz,
1041 .fcvtps,
1042 .fcvtzs,
1043 .fcvtxn,
1044 .frinta,
1045 .frintx,
1046 .fcvtnu,
1047 .fcvtmu,
1048 .fcvtau,
1049 .ucvtf,
1050 .frinti,
1051 .fcvtpu,
1052 .fcvtzu,
1053 => |f| f.sz.toSize(),
1054 else => group.size,
1055 };
1056 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1057 .size = group.Q,
1058 .elem_size = elem_size,
1059 });
1060 try writer.print("{f}{s}{s}{f}{s}{f}", .{
1061 fmtCase(decoded, dis.case),
1062 switch (decoded) {
1063 .unallocated => unreachable,
1064 else => "",
1065 .sqxtn => switch (group.Q) {
1066 .double => "",
1067 .quad => "2",
1068 },
1069 },
1070 dis.mnemonic_operands_separator,
1071 group.Rd.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1072 dis.operands_separator,
1073 group.Rn.decode(.{ .V = true }).vector(switch (decoded) {
1074 .unallocated => unreachable,
1075 else => arrangement,
1076 .sqxtn => .wrap(.{
1077 .size = .quad,
1078 .elem_size = elem_size.w(),
1079 }),
1080 }).fmtCase(dis.case),
1081 });
1082 return switch (decoded) {
1083 .unallocated => unreachable,
1084 else => {},
1085 .cmgt,
1086 .cmeq,
1087 .cmlt,
1088 .cmge,
1089 .cmle,
1090 => writer.print("{s}#0", .{dis.operands_separator}),
1091 .fcmgt,
1092 .fcmeq,
1093 .fcmlt,
1094 .fcmge,
1095 .fcmle,
1096 => writer.print("{s}#0.0", .{dis.operands_separator}),
1097 };
1098 },
1099 .simd_across_lanes => |simd_across_lanes| {
1100 const decoded = simd_across_lanes.decode();
1101 if (decoded == .unallocated) break :unallocated;
1102 const group = simd_across_lanes.group;
1103 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1104 .size = group.Q,
1105 .elem_size = group.size,
1106 });
1107 return writer.print("{f}{s}{f}{s}{f}", .{
1108 fmtCase(decoded, dis.case),
1109 dis.mnemonic_operands_separator,
1110 group.Rd.decode(.{ .V = true }).scalar(group.size.toScalarSize()).fmtCase(dis.case),
1111 dis.operands_separator,
1112 group.Rn.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1113 });
1114 },
1115 .simd_three_same => |simd_three_same| {
1116 const decoded = simd_three_same.decode();
1117 if (decoded == .unallocated) break :unallocated;
1118 const group = simd_three_same.group;
1119 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1120 .size = group.Q,
1121 .elem_size = switch (decoded) {
1122 .unallocated => break :unallocated,
1123 .addp => group.size,
1124 .@"and", .bic, .orr, .orn, .eor, .bsl, .bit, .bif => .byte,
1125 },
1126 });
1127 const Rd = group.Rd.decode(.{ .V = true }).vector(arrangement);
1128 const Rn = group.Rn.decode(.{ .V = true }).vector(arrangement);
1129 const Rm = group.Rm.decode(.{ .V = true }).vector(arrangement);
1130 return if (dis.enable_aliases and decoded == .orr and Rm.alias == Rn.alias) try writer.print("{f}{s}{f}{s}{f}", .{
1131 fmtCase(.mov, dis.case),
1132 dis.mnemonic_operands_separator,
1133 Rd.fmtCase(dis.case),
1134 dis.operands_separator,
1135 Rn.fmtCase(dis.case),
1136 }) else try writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
1137 fmtCase(decoded, dis.case),
1138 dis.mnemonic_operands_separator,
1139 Rd.fmtCase(dis.case),
1140 dis.operands_separator,
1141 Rn.fmtCase(dis.case),
1142 dis.operands_separator,
1143 Rm.fmtCase(dis.case),
1144 });
1145 },
1146 .simd_modified_immediate => |simd_modified_immediate| {
1147 const decoded = simd_modified_immediate.decode();
1148 if (decoded == .unallocated) break :unallocated;
1149 const group = simd_modified_immediate.group;
1150 const DataProcessingVector = aarch64.encoding.Instruction.DataProcessingVector;
1151 try writer.print("{f}{s}{f}", .{
1152 fmtCase(decoded, dis.case),
1153 dis.mnemonic_operands_separator,
1154 group.Rd.decode(.{ .V = true }).vector(.wrap(.{
1155 .size = group.Q,
1156 .elem_size = switch (group.o2) {
1157 0b1 => .half,
1158 0b0 => DataProcessingVector.Sz.toSize(@enumFromInt(group.op)),
1159 },
1160 })).fmtCase(dis.case),
1161 });
1162 return switch (decoded) {
1163 .unallocated => unreachable,
1164 .fmov => {
1165 const imm = DataProcessingVector.FloatImmediate.Fmov.Imm8.fromModified(.{
1166 .imm5 = group.imm5,
1167 .imm3 = group.imm3,
1168 }).decode();
1169 try writer.print("{s}#{d}{s}", .{
1170 dis.operands_separator,
1171 @as(f32, imm),
1172 if (imm == @trunc(imm)) ".0" else "",
1173 });
1174 },
1175 };
1176 },
1177 .convert_float_fixed => {},
1178 .convert_float_integer => |convert_float_integer| {
1179 const decoded = convert_float_integer.decode();
1180 if (decoded == .unallocated) break :unallocated;
1181 const group = convert_float_integer.group;
1182 const direction: enum { float_to_integer, integer_to_float } = switch (group.opcode) {
1183 0b000, 0b001, 0b100, 0b101, 0b110 => .float_to_integer,
1184 0b010, 0b011, 0b111 => .integer_to_float,
1185 };
1186 return writer.print("{f}{s}{f}{s}{f}", .{
1187 fmtCase(decoded, dis.case),
1188 dis.mnemonic_operands_separator,
1189 @as(aarch64.encoding.Register, switch (direction) {
1190 .float_to_integer => group.Rd.decode(.{}).general(group.sf),
1191 .integer_to_float => switch (group.ptype) {
1192 .single, .double, .half => group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()),
1193 .quad => group.Rd.decode(.{ .V = true }).@"d[]"(@intCast(group.rmode)),
1194 },
1195 }).fmtCase(dis.case),
1196 dis.operands_separator,
1197 @as(aarch64.encoding.Register, switch (direction) {
1198 .float_to_integer => switch (group.ptype) {
1199 .single, .double, .half => group.Rn.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()),
1200 .quad => group.Rn.decode(.{ .V = true }).@"d[]"(@intCast(group.rmode)),
1201 },
1202 .integer_to_float => group.Rn.decode(.{}).general(group.sf),
1203 }).fmtCase(dis.case),
1204 });
1205 },
1206 .float_data_processing_one_source => |float_data_processing_one_source| {
1207 const decoded = float_data_processing_one_source.decode();
1208 if (decoded == .unallocated) break :unallocated;
1209 const group = float_data_processing_one_source.group;
1210 return writer.print("{f}{s}{f}{s}{f}", .{
1211 fmtCase(decoded, dis.case),
1212 dis.mnemonic_operands_separator,
1213 group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1214 dis.operands_separator,
1215 group.Rn.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1216 });
1217 },
1218 .float_compare => {},
1219 .float_immediate => |float_immediate| {
1220 const decoded = float_immediate.decode();
1221 const group = float_immediate.group;
1222 const imm = switch (decoded) {
1223 .unallocated => break :unallocated,
1224 .fmov => |fmov| fmov.imm8.decode(),
1225 };
1226 return writer.print("{f}{s}{f}{s}#{d}{s}", .{
1227 fmtCase(decoded, dis.case),
1228 dis.mnemonic_operands_separator,
1229 group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1230 dis.operands_separator,
1231 @as(f32, imm),
1232 if (imm == @trunc(imm)) ".0" else "",
1233 });
1234 },
1235 .float_conditional_compare => {},
1236 .float_data_processing_two_source => {},
1237 .float_conditional_select => {},
1238 .float_data_processing_three_source => {},
1239 },
8101240 }
8111241 return writer.print(".{f}{s}0x{x:0>8}", .{
8121242 fmtCase(.word, dis.case),
8131243 dis.mnemonic_operands_separator,
814 @as(Instruction.Backing, @bitCast(inst)),
1244 @as(aarch64.encoding.Instruction.Backing, @bitCast(inst)),
8151245 });
8161246}
8171247
......@@ -819,10 +1249,7 @@ fn fmtCase(tag: anytype, case: Case) struct {
8191249 tag: []const u8,
8201250 case: Case,
8211251 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {
822 for (data.tag) |c| try writer.writeByte(switch (data.case) {
823 .lower => std.ascii.toLower(c),
824 .upper => std.ascii.toUpper(c),
825 });
1252 for (data.tag) |c| try writer.writeByte(data.case.convert(c));
8261253 }
8271254} {
8281255 return .{ .tag = @tagName(tag), .case = case };
......@@ -834,7 +1261,8 @@ pub const RegisterFormatter = struct {
8341261 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {
8351262 switch (data.reg.format) {
8361263 .alias => try writer.print("{f}", .{fmtCase(data.reg.alias, data.case)}),
837 .integer => |size| switch (data.reg.alias) {
1264 .general => |size| switch (data.reg.alias) {
1265 else => unreachable,
8381266 .r0,
8391267 .r1,
8401268 .r2,
......@@ -867,23 +1295,23 @@ pub const RegisterFormatter = struct {
8671295 .r29,
8681296 .r30,
8691297 => |alias| try writer.print("{c}{d}", .{
870 size.prefix(),
1298 data.case.convert(size.prefix()),
8711299 @intFromEnum(alias.encode(.{})),
8721300 }),
8731301 .zr => try writer.print("{c}{f}", .{
874 size.prefix(),
1302 data.case.convert(size.prefix()),
8751303 fmtCase(data.reg.alias, data.case),
8761304 }),
877 else => try writer.print("{s}{f}", .{
1305 .sp => try writer.print("{s}{f}", .{
8781306 switch (size) {
879 .word => "w",
1307 .word => &.{data.case.convert('w')},
8801308 .doubleword => "",
8811309 },
8821310 fmtCase(data.reg.alias, data.case),
8831311 }),
8841312 },
8851313 .scalar => |size| try writer.print("{c}{d}", .{
886 size.prefix(),
1314 data.case.convert(size.prefix()),
8871315 @intFromEnum(data.reg.alias.encode(.{ .V = true })),
8881316 }),
8891317 .vector => |arrangement| try writer.print("{f}.{f}", .{
......@@ -892,14 +1320,17 @@ pub const RegisterFormatter = struct {
8921320 }),
8931321 .element => |element| try writer.print("{f}.{c}[{d}]", .{
8941322 fmtCase(data.reg.alias, data.case),
895 element.size.prefix(),
1323 data.case.convert(element.size.prefix()),
8961324 element.index,
8971325 }),
1326 .scalable => try writer.print("{c}{d}", .{
1327 data.case.convert('z'),
1328 @intFromEnum(data.reg.alias.encode(.{ .V = true })),
1329 }),
8981330 }
8991331 }
9001332};
9011333
9021334const aarch64 = @import("../aarch64.zig");
9031335const Disassemble = @This();
904const Instruction = aarch64.encoding.Instruction;
9051336const std = @import("std");
src/codegen/aarch64/Mir.zig-1
......@@ -307,7 +307,6 @@ fn emitReloc(
307307 .single => .LDST32_ABS_LO12_NC,
308308 .double => .LDST64_ABS_LO12_NC,
309309 .quad => .LDST128_ABS_LO12_NC,
310 .scalable, .predicate => unreachable,
311310 },
312311 };
313312 try atom.addReloc(gpa, .{
src/codegen/aarch64/Select.zig+1-1
......@@ -8186,7 +8186,7 @@ fn fail(isel: *Select, comptime format: []const u8, args: anytype) error{ OutOfM
81868186
81878187/// dst = src
81888188fn movImmediate(isel: *Select, dst_reg: Register, src_imm: u64) !void {
8189 const sf = dst_reg.format.integer;
8189 const sf = dst_reg.format.general;
81908190 if (src_imm == 0) {
81918191 const zr: Register = switch (sf) {
81928192 .word => .wzr,
src/codegen/aarch64/encoding.zig+2109-1289
......@@ -4,57 +4,75 @@ pub const Register = struct {
44 format: Format,
55
66 pub const Format = union(enum) {
7 alias,
8 integer: IntegerSize,
9 scalar: VectorSize,
7 alias: Format.Alias,
8 general: GeneralSize,
9 scalar: ScalarSize,
1010 vector: Arrangement,
11 element: struct { size: VectorSize, index: u4 },
11 element: struct { size: ScalarSize, index: u4 },
12 scalable,
13
14 pub const Alias = enum { general, other, vector, predicate };
1215 };
1316
14 pub const IntegerSize = enum(u1) {
17 pub const GeneralSize = enum(u1) {
1518 word = 0b0,
1619 doubleword = 0b1,
1720
18 pub fn prefix(is: IntegerSize) u8 {
19 return (comptime std.enums.EnumArray(IntegerSize, u8).init(.{
21 pub fn prefix(gs: GeneralSize) u8 {
22 return (comptime std.enums.EnumArray(GeneralSize, u8).init(.{
2023 .word = 'w',
2124 .doubleword = 'x',
22 })).get(is);
25 })).get(gs);
2326 }
2427 };
2528
26 pub const VectorSize = enum(u3) {
29 pub const ScalarSize = enum(u3) {
2730 byte = 0,
2831 half = 1,
2932 single = 2,
3033 double = 3,
3134 quad = 4,
32 scalable,
33 predicate,
3435
35 pub fn prefix(vs: VectorSize) u8 {
36 return (comptime std.enums.EnumArray(VectorSize, u8).init(.{
36 pub fn n(ss: ScalarSize) ScalarSize {
37 return @enumFromInt(@intFromEnum(ss) - 1);
38 }
39
40 pub fn w(ss: ScalarSize) ScalarSize {
41 return @enumFromInt(@intFromEnum(ss) + 1);
42 }
43
44 pub fn prefix(ss: ScalarSize) u8 {
45 return (comptime std.enums.EnumArray(ScalarSize, u8).init(.{
3746 .byte = 'b',
3847 .half = 'h',
3948 .single = 's',
4049 .double = 'd',
4150 .quad = 'q',
42 .scalable = 'z',
43 .predicate = 'p',
44 })).get(vs);
51 })).get(ss);
4552 }
4653 };
4754
48 pub const Arrangement = enum {
49 @"2d",
50 @"4s",
51 @"8h",
52 @"16b",
55 pub const Arrangement = enum(u3) {
56 @"2d" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .double }),
57 @"4s" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .single }),
58 @"8h" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .half }),
59 @"16b" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .byte }),
60
61 @"1d" = @bitCast(Unwrapped{ .size = .double, .elem_size = .double }),
62 @"2s" = @bitCast(Unwrapped{ .size = .double, .elem_size = .single }),
63 @"4h" = @bitCast(Unwrapped{ .size = .double, .elem_size = .half }),
64 @"8b" = @bitCast(Unwrapped{ .size = .double, .elem_size = .byte }),
5365
54 @"1d",
55 @"2s",
56 @"4h",
57 @"8b",
66 pub const Unwrapped = packed struct {
67 size: Instruction.DataProcessingVector.Q,
68 elem_size: Instruction.DataProcessingVector.Size,
69 };
70 pub fn wrap(unwrapped: Unwrapped) Arrangement {
71 return @enumFromInt(@as(@typeInfo(Arrangement).@"enum".tag_type, @bitCast(unwrapped)));
72 }
73 pub fn unwrap(arrangement: Arrangement) Unwrapped {
74 return @bitCast(@intFromEnum(arrangement));
75 }
5876
5977 pub fn len(arrangement: Arrangement) u5 {
6078 return switch (arrangement) {
......@@ -67,625 +85,319 @@ pub const Register = struct {
6785 }
6886
6987 pub fn size(arrangement: Arrangement) Instruction.DataProcessingVector.Q {
70 return switch (arrangement) {
71 .@"2d", .@"4s", .@"8h", .@"16b" => .quad,
72 .@"1d", .@"2s", .@"4h", .@"8b" => .double,
73 };
88 return arrangement.unwrap().size;
7489 }
75
7690 pub fn elemSize(arrangement: Arrangement) Instruction.DataProcessingVector.Size {
77 return switch (arrangement) {
78 .@"2d", .@"1d" => .double,
79 .@"4s", .@"2s" => .single,
80 .@"8h", .@"4h" => .half,
81 .@"16b", .@"8b" => .byte,
82 };
91 return arrangement.unwrap().elem_size;
8392 }
84
8593 pub fn elemSz(arrangement: Arrangement) Instruction.DataProcessingVector.Sz {
86 return switch (arrangement) {
87 else => unreachable,
88 .@"2d", .@"1d" => .double,
89 .@"4s", .@"2s" => .single,
90 };
94 return arrangement.elemSize().toSz();
9195 }
9296 };
9397
94 pub const x0: Register = .{ .alias = .r0, .format = .{ .integer = .doubleword } };
95 pub const x1: Register = .{ .alias = .r1, .format = .{ .integer = .doubleword } };
96 pub const x2: Register = .{ .alias = .r2, .format = .{ .integer = .doubleword } };
97 pub const x3: Register = .{ .alias = .r3, .format = .{ .integer = .doubleword } };
98 pub const x4: Register = .{ .alias = .r4, .format = .{ .integer = .doubleword } };
99 pub const x5: Register = .{ .alias = .r5, .format = .{ .integer = .doubleword } };
100 pub const x6: Register = .{ .alias = .r6, .format = .{ .integer = .doubleword } };
101 pub const x7: Register = .{ .alias = .r7, .format = .{ .integer = .doubleword } };
102 pub const x8: Register = .{ .alias = .r8, .format = .{ .integer = .doubleword } };
103 pub const x9: Register = .{ .alias = .r9, .format = .{ .integer = .doubleword } };
104 pub const x10: Register = .{ .alias = .r10, .format = .{ .integer = .doubleword } };
105 pub const x11: Register = .{ .alias = .r11, .format = .{ .integer = .doubleword } };
106 pub const x12: Register = .{ .alias = .r12, .format = .{ .integer = .doubleword } };
107 pub const x13: Register = .{ .alias = .r13, .format = .{ .integer = .doubleword } };
108 pub const x14: Register = .{ .alias = .r14, .format = .{ .integer = .doubleword } };
109 pub const x15: Register = .{ .alias = .r15, .format = .{ .integer = .doubleword } };
110 pub const x16: Register = .{ .alias = .r16, .format = .{ .integer = .doubleword } };
111 pub const x17: Register = .{ .alias = .r17, .format = .{ .integer = .doubleword } };
112 pub const x18: Register = .{ .alias = .r18, .format = .{ .integer = .doubleword } };
113 pub const x19: Register = .{ .alias = .r19, .format = .{ .integer = .doubleword } };
114 pub const x20: Register = .{ .alias = .r20, .format = .{ .integer = .doubleword } };
115 pub const x21: Register = .{ .alias = .r21, .format = .{ .integer = .doubleword } };
116 pub const x22: Register = .{ .alias = .r22, .format = .{ .integer = .doubleword } };
117 pub const x23: Register = .{ .alias = .r23, .format = .{ .integer = .doubleword } };
118 pub const x24: Register = .{ .alias = .r24, .format = .{ .integer = .doubleword } };
119 pub const x25: Register = .{ .alias = .r25, .format = .{ .integer = .doubleword } };
120 pub const x26: Register = .{ .alias = .r26, .format = .{ .integer = .doubleword } };
121 pub const x27: Register = .{ .alias = .r27, .format = .{ .integer = .doubleword } };
122 pub const x28: Register = .{ .alias = .r28, .format = .{ .integer = .doubleword } };
123 pub const x29: Register = .{ .alias = .r29, .format = .{ .integer = .doubleword } };
124 pub const x30: Register = .{ .alias = .r30, .format = .{ .integer = .doubleword } };
125 pub const xzr: Register = .{ .alias = .zr, .format = .{ .integer = .doubleword } };
126 pub const sp: Register = .{ .alias = .sp, .format = .{ .integer = .doubleword } };
127
128 pub const w0: Register = .{ .alias = .r0, .format = .{ .integer = .word } };
129 pub const w1: Register = .{ .alias = .r1, .format = .{ .integer = .word } };
130 pub const w2: Register = .{ .alias = .r2, .format = .{ .integer = .word } };
131 pub const w3: Register = .{ .alias = .r3, .format = .{ .integer = .word } };
132 pub const w4: Register = .{ .alias = .r4, .format = .{ .integer = .word } };
133 pub const w5: Register = .{ .alias = .r5, .format = .{ .integer = .word } };
134 pub const w6: Register = .{ .alias = .r6, .format = .{ .integer = .word } };
135 pub const w7: Register = .{ .alias = .r7, .format = .{ .integer = .word } };
136 pub const w8: Register = .{ .alias = .r8, .format = .{ .integer = .word } };
137 pub const w9: Register = .{ .alias = .r9, .format = .{ .integer = .word } };
138 pub const w10: Register = .{ .alias = .r10, .format = .{ .integer = .word } };
139 pub const w11: Register = .{ .alias = .r11, .format = .{ .integer = .word } };
140 pub const w12: Register = .{ .alias = .r12, .format = .{ .integer = .word } };
141 pub const w13: Register = .{ .alias = .r13, .format = .{ .integer = .word } };
142 pub const w14: Register = .{ .alias = .r14, .format = .{ .integer = .word } };
143 pub const w15: Register = .{ .alias = .r15, .format = .{ .integer = .word } };
144 pub const w16: Register = .{ .alias = .r16, .format = .{ .integer = .word } };
145 pub const w17: Register = .{ .alias = .r17, .format = .{ .integer = .word } };
146 pub const w18: Register = .{ .alias = .r18, .format = .{ .integer = .word } };
147 pub const w19: Register = .{ .alias = .r19, .format = .{ .integer = .word } };
148 pub const w20: Register = .{ .alias = .r20, .format = .{ .integer = .word } };
149 pub const w21: Register = .{ .alias = .r21, .format = .{ .integer = .word } };
150 pub const w22: Register = .{ .alias = .r22, .format = .{ .integer = .word } };
151 pub const w23: Register = .{ .alias = .r23, .format = .{ .integer = .word } };
152 pub const w24: Register = .{ .alias = .r24, .format = .{ .integer = .word } };
153 pub const w25: Register = .{ .alias = .r25, .format = .{ .integer = .word } };
154 pub const w26: Register = .{ .alias = .r26, .format = .{ .integer = .word } };
155 pub const w27: Register = .{ .alias = .r27, .format = .{ .integer = .word } };
156 pub const w28: Register = .{ .alias = .r28, .format = .{ .integer = .word } };
157 pub const w29: Register = .{ .alias = .r29, .format = .{ .integer = .word } };
158 pub const w30: Register = .{ .alias = .r30, .format = .{ .integer = .word } };
159 pub const wzr: Register = .{ .alias = .zr, .format = .{ .integer = .word } };
160 pub const wsp: Register = .{ .alias = .sp, .format = .{ .integer = .word } };
98 pub const x0 = Alias.r0.x();
99 pub const x1 = Alias.r1.x();
100 pub const x2 = Alias.r2.x();
101 pub const x3 = Alias.r3.x();
102 pub const x4 = Alias.r4.x();
103 pub const x5 = Alias.r5.x();
104 pub const x6 = Alias.r6.x();
105 pub const x7 = Alias.r7.x();
106 pub const x8 = Alias.r8.x();
107 pub const x9 = Alias.r9.x();
108 pub const x10 = Alias.r10.x();
109 pub const x11 = Alias.r11.x();
110 pub const x12 = Alias.r12.x();
111 pub const x13 = Alias.r13.x();
112 pub const x14 = Alias.r14.x();
113 pub const x15 = Alias.r15.x();
114 pub const x16 = Alias.r16.x();
115 pub const x17 = Alias.r17.x();
116 pub const x18 = Alias.r18.x();
117 pub const x19 = Alias.r19.x();
118 pub const x20 = Alias.r20.x();
119 pub const x21 = Alias.r21.x();
120 pub const x22 = Alias.r22.x();
121 pub const x23 = Alias.r23.x();
122 pub const x24 = Alias.r24.x();
123 pub const x25 = Alias.r25.x();
124 pub const x26 = Alias.r26.x();
125 pub const x27 = Alias.r27.x();
126 pub const x28 = Alias.r28.x();
127 pub const x29 = Alias.r29.x();
128 pub const x30 = Alias.r30.x();
129 pub const xzr = Alias.zr.x();
130 pub const sp = Alias.sp.x();
131
132 pub const w0 = Alias.r0.w();
133 pub const w1 = Alias.r1.w();
134 pub const w2 = Alias.r2.w();
135 pub const w3 = Alias.r3.w();
136 pub const w4 = Alias.r4.w();
137 pub const w5 = Alias.r5.w();
138 pub const w6 = Alias.r6.w();
139 pub const w7 = Alias.r7.w();
140 pub const w8 = Alias.r8.w();
141 pub const w9 = Alias.r9.w();
142 pub const w10 = Alias.r10.w();
143 pub const w11 = Alias.r11.w();
144 pub const w12 = Alias.r12.w();
145 pub const w13 = Alias.r13.w();
146 pub const w14 = Alias.r14.w();
147 pub const w15 = Alias.r15.w();
148 pub const w16 = Alias.r16.w();
149 pub const w17 = Alias.r17.w();
150 pub const w18 = Alias.r18.w();
151 pub const w19 = Alias.r19.w();
152 pub const w20 = Alias.r20.w();
153 pub const w21 = Alias.r21.w();
154 pub const w22 = Alias.r22.w();
155 pub const w23 = Alias.r23.w();
156 pub const w24 = Alias.r24.w();
157 pub const w25 = Alias.r25.w();
158 pub const w26 = Alias.r26.w();
159 pub const w27 = Alias.r27.w();
160 pub const w28 = Alias.r28.w();
161 pub const w29 = Alias.r29.w();
162 pub const w30 = Alias.r30.w();
163 pub const wzr = Alias.zr.w();
164 pub const wsp = Alias.sp.w();
161165
162166 pub const ip = x16;
163167 pub const ip0 = x16;
164168 pub const ip1 = x17;
165169 pub const fp = x29;
166170 pub const lr = x30;
167 pub const pc: Register = .{ .alias = .pc, .format = .{ .integer = .doubleword } };
168
169 pub const q0: Register = .{ .alias = .v0, .format = .{ .scalar = .quad } };
170 pub const q1: Register = .{ .alias = .v1, .format = .{ .scalar = .quad } };
171 pub const q2: Register = .{ .alias = .v2, .format = .{ .scalar = .quad } };
172 pub const q3: Register = .{ .alias = .v3, .format = .{ .scalar = .quad } };
173 pub const q4: Register = .{ .alias = .v4, .format = .{ .scalar = .quad } };
174 pub const q5: Register = .{ .alias = .v5, .format = .{ .scalar = .quad } };
175 pub const q6: Register = .{ .alias = .v6, .format = .{ .scalar = .quad } };
176 pub const q7: Register = .{ .alias = .v7, .format = .{ .scalar = .quad } };
177 pub const q8: Register = .{ .alias = .v8, .format = .{ .scalar = .quad } };
178 pub const q9: Register = .{ .alias = .v9, .format = .{ .scalar = .quad } };
179 pub const q10: Register = .{ .alias = .v10, .format = .{ .scalar = .quad } };
180 pub const q11: Register = .{ .alias = .v11, .format = .{ .scalar = .quad } };
181 pub const q12: Register = .{ .alias = .v12, .format = .{ .scalar = .quad } };
182 pub const q13: Register = .{ .alias = .v13, .format = .{ .scalar = .quad } };
183 pub const q14: Register = .{ .alias = .v14, .format = .{ .scalar = .quad } };
184 pub const q15: Register = .{ .alias = .v15, .format = .{ .scalar = .quad } };
185 pub const q16: Register = .{ .alias = .v16, .format = .{ .scalar = .quad } };
186 pub const q17: Register = .{ .alias = .v17, .format = .{ .scalar = .quad } };
187 pub const q18: Register = .{ .alias = .v18, .format = .{ .scalar = .quad } };
188 pub const q19: Register = .{ .alias = .v19, .format = .{ .scalar = .quad } };
189 pub const q20: Register = .{ .alias = .v20, .format = .{ .scalar = .quad } };
190 pub const q21: Register = .{ .alias = .v21, .format = .{ .scalar = .quad } };
191 pub const q22: Register = .{ .alias = .v22, .format = .{ .scalar = .quad } };
192 pub const q23: Register = .{ .alias = .v23, .format = .{ .scalar = .quad } };
193 pub const q24: Register = .{ .alias = .v24, .format = .{ .scalar = .quad } };
194 pub const q25: Register = .{ .alias = .v25, .format = .{ .scalar = .quad } };
195 pub const q26: Register = .{ .alias = .v26, .format = .{ .scalar = .quad } };
196 pub const q27: Register = .{ .alias = .v27, .format = .{ .scalar = .quad } };
197 pub const q28: Register = .{ .alias = .v28, .format = .{ .scalar = .quad } };
198 pub const q29: Register = .{ .alias = .v29, .format = .{ .scalar = .quad } };
199 pub const q30: Register = .{ .alias = .v30, .format = .{ .scalar = .quad } };
200 pub const q31: Register = .{ .alias = .v31, .format = .{ .scalar = .quad } };
201
202 pub const d0: Register = .{ .alias = .v0, .format = .{ .scalar = .double } };
203 pub const d1: Register = .{ .alias = .v1, .format = .{ .scalar = .double } };
204 pub const d2: Register = .{ .alias = .v2, .format = .{ .scalar = .double } };
205 pub const d3: Register = .{ .alias = .v3, .format = .{ .scalar = .double } };
206 pub const d4: Register = .{ .alias = .v4, .format = .{ .scalar = .double } };
207 pub const d5: Register = .{ .alias = .v5, .format = .{ .scalar = .double } };
208 pub const d6: Register = .{ .alias = .v6, .format = .{ .scalar = .double } };
209 pub const d7: Register = .{ .alias = .v7, .format = .{ .scalar = .double } };
210 pub const d8: Register = .{ .alias = .v8, .format = .{ .scalar = .double } };
211 pub const d9: Register = .{ .alias = .v9, .format = .{ .scalar = .double } };
212 pub const d10: Register = .{ .alias = .v10, .format = .{ .scalar = .double } };
213 pub const d11: Register = .{ .alias = .v11, .format = .{ .scalar = .double } };
214 pub const d12: Register = .{ .alias = .v12, .format = .{ .scalar = .double } };
215 pub const d13: Register = .{ .alias = .v13, .format = .{ .scalar = .double } };
216 pub const d14: Register = .{ .alias = .v14, .format = .{ .scalar = .double } };
217 pub const d15: Register = .{ .alias = .v15, .format = .{ .scalar = .double } };
218 pub const d16: Register = .{ .alias = .v16, .format = .{ .scalar = .double } };
219 pub const d17: Register = .{ .alias = .v17, .format = .{ .scalar = .double } };
220 pub const d18: Register = .{ .alias = .v18, .format = .{ .scalar = .double } };
221 pub const d19: Register = .{ .alias = .v19, .format = .{ .scalar = .double } };
222 pub const d20: Register = .{ .alias = .v20, .format = .{ .scalar = .double } };
223 pub const d21: Register = .{ .alias = .v21, .format = .{ .scalar = .double } };
224 pub const d22: Register = .{ .alias = .v22, .format = .{ .scalar = .double } };
225 pub const d23: Register = .{ .alias = .v23, .format = .{ .scalar = .double } };
226 pub const d24: Register = .{ .alias = .v24, .format = .{ .scalar = .double } };
227 pub const d25: Register = .{ .alias = .v25, .format = .{ .scalar = .double } };
228 pub const d26: Register = .{ .alias = .v26, .format = .{ .scalar = .double } };
229 pub const d27: Register = .{ .alias = .v27, .format = .{ .scalar = .double } };
230 pub const d28: Register = .{ .alias = .v28, .format = .{ .scalar = .double } };
231 pub const d29: Register = .{ .alias = .v29, .format = .{ .scalar = .double } };
232 pub const d30: Register = .{ .alias = .v30, .format = .{ .scalar = .double } };
233 pub const d31: Register = .{ .alias = .v31, .format = .{ .scalar = .double } };
234
235 pub const s0: Register = .{ .alias = .v0, .format = .{ .scalar = .single } };
236 pub const s1: Register = .{ .alias = .v1, .format = .{ .scalar = .single } };
237 pub const s2: Register = .{ .alias = .v2, .format = .{ .scalar = .single } };
238 pub const s3: Register = .{ .alias = .v3, .format = .{ .scalar = .single } };
239 pub const s4: Register = .{ .alias = .v4, .format = .{ .scalar = .single } };
240 pub const s5: Register = .{ .alias = .v5, .format = .{ .scalar = .single } };
241 pub const s6: Register = .{ .alias = .v6, .format = .{ .scalar = .single } };
242 pub const s7: Register = .{ .alias = .v7, .format = .{ .scalar = .single } };
243 pub const s8: Register = .{ .alias = .v8, .format = .{ .scalar = .single } };
244 pub const s9: Register = .{ .alias = .v9, .format = .{ .scalar = .single } };
245 pub const s10: Register = .{ .alias = .v10, .format = .{ .scalar = .single } };
246 pub const s11: Register = .{ .alias = .v11, .format = .{ .scalar = .single } };
247 pub const s12: Register = .{ .alias = .v12, .format = .{ .scalar = .single } };
248 pub const s13: Register = .{ .alias = .v13, .format = .{ .scalar = .single } };
249 pub const s14: Register = .{ .alias = .v14, .format = .{ .scalar = .single } };
250 pub const s15: Register = .{ .alias = .v15, .format = .{ .scalar = .single } };
251 pub const s16: Register = .{ .alias = .v16, .format = .{ .scalar = .single } };
252 pub const s17: Register = .{ .alias = .v17, .format = .{ .scalar = .single } };
253 pub const s18: Register = .{ .alias = .v18, .format = .{ .scalar = .single } };
254 pub const s19: Register = .{ .alias = .v19, .format = .{ .scalar = .single } };
255 pub const s20: Register = .{ .alias = .v20, .format = .{ .scalar = .single } };
256 pub const s21: Register = .{ .alias = .v21, .format = .{ .scalar = .single } };
257 pub const s22: Register = .{ .alias = .v22, .format = .{ .scalar = .single } };
258 pub const s23: Register = .{ .alias = .v23, .format = .{ .scalar = .single } };
259 pub const s24: Register = .{ .alias = .v24, .format = .{ .scalar = .single } };
260 pub const s25: Register = .{ .alias = .v25, .format = .{ .scalar = .single } };
261 pub const s26: Register = .{ .alias = .v26, .format = .{ .scalar = .single } };
262 pub const s27: Register = .{ .alias = .v27, .format = .{ .scalar = .single } };
263 pub const s28: Register = .{ .alias = .v28, .format = .{ .scalar = .single } };
264 pub const s29: Register = .{ .alias = .v29, .format = .{ .scalar = .single } };
265 pub const s30: Register = .{ .alias = .v30, .format = .{ .scalar = .single } };
266 pub const s31: Register = .{ .alias = .v31, .format = .{ .scalar = .single } };
267
268 pub const h0: Register = .{ .alias = .v0, .format = .{ .scalar = .half } };
269 pub const h1: Register = .{ .alias = .v1, .format = .{ .scalar = .half } };
270 pub const h2: Register = .{ .alias = .v2, .format = .{ .scalar = .half } };
271 pub const h3: Register = .{ .alias = .v3, .format = .{ .scalar = .half } };
272 pub const h4: Register = .{ .alias = .v4, .format = .{ .scalar = .half } };
273 pub const h5: Register = .{ .alias = .v5, .format = .{ .scalar = .half } };
274 pub const h6: Register = .{ .alias = .v6, .format = .{ .scalar = .half } };
275 pub const h7: Register = .{ .alias = .v7, .format = .{ .scalar = .half } };
276 pub const h8: Register = .{ .alias = .v8, .format = .{ .scalar = .half } };
277 pub const h9: Register = .{ .alias = .v9, .format = .{ .scalar = .half } };
278 pub const h10: Register = .{ .alias = .v10, .format = .{ .scalar = .half } };
279 pub const h11: Register = .{ .alias = .v11, .format = .{ .scalar = .half } };
280 pub const h12: Register = .{ .alias = .v12, .format = .{ .scalar = .half } };
281 pub const h13: Register = .{ .alias = .v13, .format = .{ .scalar = .half } };
282 pub const h14: Register = .{ .alias = .v14, .format = .{ .scalar = .half } };
283 pub const h15: Register = .{ .alias = .v15, .format = .{ .scalar = .half } };
284 pub const h16: Register = .{ .alias = .v16, .format = .{ .scalar = .half } };
285 pub const h17: Register = .{ .alias = .v17, .format = .{ .scalar = .half } };
286 pub const h18: Register = .{ .alias = .v18, .format = .{ .scalar = .half } };
287 pub const h19: Register = .{ .alias = .v19, .format = .{ .scalar = .half } };
288 pub const h20: Register = .{ .alias = .v20, .format = .{ .scalar = .half } };
289 pub const h21: Register = .{ .alias = .v21, .format = .{ .scalar = .half } };
290 pub const h22: Register = .{ .alias = .v22, .format = .{ .scalar = .half } };
291 pub const h23: Register = .{ .alias = .v23, .format = .{ .scalar = .half } };
292 pub const h24: Register = .{ .alias = .v24, .format = .{ .scalar = .half } };
293 pub const h25: Register = .{ .alias = .v25, .format = .{ .scalar = .half } };
294 pub const h26: Register = .{ .alias = .v26, .format = .{ .scalar = .half } };
295 pub const h27: Register = .{ .alias = .v27, .format = .{ .scalar = .half } };
296 pub const h28: Register = .{ .alias = .v28, .format = .{ .scalar = .half } };
297 pub const h29: Register = .{ .alias = .v29, .format = .{ .scalar = .half } };
298 pub const h30: Register = .{ .alias = .v30, .format = .{ .scalar = .half } };
299 pub const h31: Register = .{ .alias = .v31, .format = .{ .scalar = .half } };
300
301 pub const b0: Register = .{ .alias = .v0, .format = .{ .scalar = .byte } };
302 pub const b1: Register = .{ .alias = .v1, .format = .{ .scalar = .byte } };
303 pub const b2: Register = .{ .alias = .v2, .format = .{ .scalar = .byte } };
304 pub const b3: Register = .{ .alias = .v3, .format = .{ .scalar = .byte } };
305 pub const b4: Register = .{ .alias = .v4, .format = .{ .scalar = .byte } };
306 pub const b5: Register = .{ .alias = .v5, .format = .{ .scalar = .byte } };
307 pub const b6: Register = .{ .alias = .v6, .format = .{ .scalar = .byte } };
308 pub const b7: Register = .{ .alias = .v7, .format = .{ .scalar = .byte } };
309 pub const b8: Register = .{ .alias = .v8, .format = .{ .scalar = .byte } };
310 pub const b9: Register = .{ .alias = .v9, .format = .{ .scalar = .byte } };
311 pub const b10: Register = .{ .alias = .v10, .format = .{ .scalar = .byte } };
312 pub const b11: Register = .{ .alias = .v11, .format = .{ .scalar = .byte } };
313 pub const b12: Register = .{ .alias = .v12, .format = .{ .scalar = .byte } };
314 pub const b13: Register = .{ .alias = .v13, .format = .{ .scalar = .byte } };
315 pub const b14: Register = .{ .alias = .v14, .format = .{ .scalar = .byte } };
316 pub const b15: Register = .{ .alias = .v15, .format = .{ .scalar = .byte } };
317 pub const b16: Register = .{ .alias = .v16, .format = .{ .scalar = .byte } };
318 pub const b17: Register = .{ .alias = .v17, .format = .{ .scalar = .byte } };
319 pub const b18: Register = .{ .alias = .v18, .format = .{ .scalar = .byte } };
320 pub const b19: Register = .{ .alias = .v19, .format = .{ .scalar = .byte } };
321 pub const b20: Register = .{ .alias = .v20, .format = .{ .scalar = .byte } };
322 pub const b21: Register = .{ .alias = .v21, .format = .{ .scalar = .byte } };
323 pub const b22: Register = .{ .alias = .v22, .format = .{ .scalar = .byte } };
324 pub const b23: Register = .{ .alias = .v23, .format = .{ .scalar = .byte } };
325 pub const b24: Register = .{ .alias = .v24, .format = .{ .scalar = .byte } };
326 pub const b25: Register = .{ .alias = .v25, .format = .{ .scalar = .byte } };
327 pub const b26: Register = .{ .alias = .v26, .format = .{ .scalar = .byte } };
328 pub const b27: Register = .{ .alias = .v27, .format = .{ .scalar = .byte } };
329 pub const b28: Register = .{ .alias = .v28, .format = .{ .scalar = .byte } };
330 pub const b29: Register = .{ .alias = .v29, .format = .{ .scalar = .byte } };
331 pub const b30: Register = .{ .alias = .v30, .format = .{ .scalar = .byte } };
332 pub const b31: Register = .{ .alias = .v31, .format = .{ .scalar = .byte } };
333
334 pub const fpcr: Register = .{ .alias = .fpcr, .format = .{ .integer = .doubleword } };
335 pub const fpsr: Register = .{ .alias = .fpsr, .format = .{ .integer = .doubleword } };
336
337 pub const z0: Register = .{ .alias = .v0, .format = .{ .scalar = .scalable } };
338 pub const z1: Register = .{ .alias = .v1, .format = .{ .scalar = .scalable } };
339 pub const z2: Register = .{ .alias = .v2, .format = .{ .scalar = .scalable } };
340 pub const z3: Register = .{ .alias = .v3, .format = .{ .scalar = .scalable } };
341 pub const z4: Register = .{ .alias = .v4, .format = .{ .scalar = .scalable } };
342 pub const z5: Register = .{ .alias = .v5, .format = .{ .scalar = .scalable } };
343 pub const z6: Register = .{ .alias = .v6, .format = .{ .scalar = .scalable } };
344 pub const z7: Register = .{ .alias = .v7, .format = .{ .scalar = .scalable } };
345 pub const z8: Register = .{ .alias = .v8, .format = .{ .scalar = .scalable } };
346 pub const z9: Register = .{ .alias = .v9, .format = .{ .scalar = .scalable } };
347 pub const z10: Register = .{ .alias = .v10, .format = .{ .scalar = .scalable } };
348 pub const z11: Register = .{ .alias = .v11, .format = .{ .scalar = .scalable } };
349 pub const z12: Register = .{ .alias = .v12, .format = .{ .scalar = .scalable } };
350 pub const z13: Register = .{ .alias = .v13, .format = .{ .scalar = .scalable } };
351 pub const z14: Register = .{ .alias = .v14, .format = .{ .scalar = .scalable } };
352 pub const z15: Register = .{ .alias = .v15, .format = .{ .scalar = .scalable } };
353 pub const z16: Register = .{ .alias = .v16, .format = .{ .scalar = .scalable } };
354 pub const z17: Register = .{ .alias = .v17, .format = .{ .scalar = .scalable } };
355 pub const z18: Register = .{ .alias = .v18, .format = .{ .scalar = .scalable } };
356 pub const z19: Register = .{ .alias = .v19, .format = .{ .scalar = .scalable } };
357 pub const z20: Register = .{ .alias = .v20, .format = .{ .scalar = .scalable } };
358 pub const z21: Register = .{ .alias = .v21, .format = .{ .scalar = .scalable } };
359 pub const z22: Register = .{ .alias = .v22, .format = .{ .scalar = .scalable } };
360 pub const z23: Register = .{ .alias = .v23, .format = .{ .scalar = .scalable } };
361 pub const z24: Register = .{ .alias = .v24, .format = .{ .scalar = .scalable } };
362 pub const z25: Register = .{ .alias = .v25, .format = .{ .scalar = .scalable } };
363 pub const z26: Register = .{ .alias = .v26, .format = .{ .scalar = .scalable } };
364 pub const z27: Register = .{ .alias = .v27, .format = .{ .scalar = .scalable } };
365 pub const z28: Register = .{ .alias = .v28, .format = .{ .scalar = .scalable } };
366 pub const z29: Register = .{ .alias = .v29, .format = .{ .scalar = .scalable } };
367 pub const z30: Register = .{ .alias = .v30, .format = .{ .scalar = .scalable } };
368 pub const z31: Register = .{ .alias = .v31, .format = .{ .scalar = .scalable } };
369
370 pub const p0: Register = .{ .alias = .v0, .format = .{ .scalar = .predicate } };
371 pub const p1: Register = .{ .alias = .v1, .format = .{ .scalar = .predicate } };
372 pub const p2: Register = .{ .alias = .v2, .format = .{ .scalar = .predicate } };
373 pub const p3: Register = .{ .alias = .v3, .format = .{ .scalar = .predicate } };
374 pub const p4: Register = .{ .alias = .v4, .format = .{ .scalar = .predicate } };
375 pub const p5: Register = .{ .alias = .v5, .format = .{ .scalar = .predicate } };
376 pub const p6: Register = .{ .alias = .v6, .format = .{ .scalar = .predicate } };
377 pub const p7: Register = .{ .alias = .v7, .format = .{ .scalar = .predicate } };
378 pub const p8: Register = .{ .alias = .v8, .format = .{ .scalar = .predicate } };
379 pub const p9: Register = .{ .alias = .v9, .format = .{ .scalar = .predicate } };
380 pub const p10: Register = .{ .alias = .v10, .format = .{ .scalar = .predicate } };
381 pub const p11: Register = .{ .alias = .v11, .format = .{ .scalar = .predicate } };
382 pub const p12: Register = .{ .alias = .v12, .format = .{ .scalar = .predicate } };
383 pub const p13: Register = .{ .alias = .v13, .format = .{ .scalar = .predicate } };
384 pub const p14: Register = .{ .alias = .v14, .format = .{ .scalar = .predicate } };
385 pub const p15: Register = .{ .alias = .v15, .format = .{ .scalar = .predicate } };
386
387 pub const ffr: Register = .{ .alias = .ffr, .format = .{ .integer = .doubleword } };
171 pub const pc = Alias.pc.alias(.other);
172
173 pub const q0 = Alias.v0.q();
174 pub const q1 = Alias.v1.q();
175 pub const q2 = Alias.v2.q();
176 pub const q3 = Alias.v3.q();
177 pub const q4 = Alias.v4.q();
178 pub const q5 = Alias.v5.q();
179 pub const q6 = Alias.v6.q();
180 pub const q7 = Alias.v7.q();
181 pub const q8 = Alias.v8.q();
182 pub const q9 = Alias.v9.q();
183 pub const q10 = Alias.v10.q();
184 pub const q11 = Alias.v11.q();
185 pub const q12 = Alias.v12.q();
186 pub const q13 = Alias.v13.q();
187 pub const q14 = Alias.v14.q();
188 pub const q15 = Alias.v15.q();
189 pub const q16 = Alias.v16.q();
190 pub const q17 = Alias.v17.q();
191 pub const q18 = Alias.v18.q();
192 pub const q19 = Alias.v19.q();
193 pub const q20 = Alias.v20.q();
194 pub const q21 = Alias.v21.q();
195 pub const q22 = Alias.v22.q();
196 pub const q23 = Alias.v23.q();
197 pub const q24 = Alias.v24.q();
198 pub const q25 = Alias.v25.q();
199 pub const q26 = Alias.v26.q();
200 pub const q27 = Alias.v27.q();
201 pub const q28 = Alias.v28.q();
202 pub const q29 = Alias.v29.q();
203 pub const q30 = Alias.v30.q();
204 pub const q31 = Alias.v31.q();
205
206 pub const d0 = Alias.v0.d();
207 pub const d1 = Alias.v1.d();
208 pub const d2 = Alias.v2.d();
209 pub const d3 = Alias.v3.d();
210 pub const d4 = Alias.v4.d();
211 pub const d5 = Alias.v5.d();
212 pub const d6 = Alias.v6.d();
213 pub const d7 = Alias.v7.d();
214 pub const d8 = Alias.v8.d();
215 pub const d9 = Alias.v9.d();
216 pub const d10 = Alias.v10.d();
217 pub const d11 = Alias.v11.d();
218 pub const d12 = Alias.v12.d();
219 pub const d13 = Alias.v13.d();
220 pub const d14 = Alias.v14.d();
221 pub const d15 = Alias.v15.d();
222 pub const d16 = Alias.v16.d();
223 pub const d17 = Alias.v17.d();
224 pub const d18 = Alias.v18.d();
225 pub const d19 = Alias.v19.d();
226 pub const d20 = Alias.v20.d();
227 pub const d21 = Alias.v21.d();
228 pub const d22 = Alias.v22.d();
229 pub const d23 = Alias.v23.d();
230 pub const d24 = Alias.v24.d();
231 pub const d25 = Alias.v25.d();
232 pub const d26 = Alias.v26.d();
233 pub const d27 = Alias.v27.d();
234 pub const d28 = Alias.v28.d();
235 pub const d29 = Alias.v29.d();
236 pub const d30 = Alias.v30.d();
237 pub const d31 = Alias.v31.d();
238
239 pub const s0 = Alias.v0.s();
240 pub const s1 = Alias.v1.s();
241 pub const s2 = Alias.v2.s();
242 pub const s3 = Alias.v3.s();
243 pub const s4 = Alias.v4.s();
244 pub const s5 = Alias.v5.s();
245 pub const s6 = Alias.v6.s();
246 pub const s7 = Alias.v7.s();
247 pub const s8 = Alias.v8.s();
248 pub const s9 = Alias.v9.s();
249 pub const s10 = Alias.v10.s();
250 pub const s11 = Alias.v11.s();
251 pub const s12 = Alias.v12.s();
252 pub const s13 = Alias.v13.s();
253 pub const s14 = Alias.v14.s();
254 pub const s15 = Alias.v15.s();
255 pub const s16 = Alias.v16.s();
256 pub const s17 = Alias.v17.s();
257 pub const s18 = Alias.v18.s();
258 pub const s19 = Alias.v19.s();
259 pub const s20 = Alias.v20.s();
260 pub const s21 = Alias.v21.s();
261 pub const s22 = Alias.v22.s();
262 pub const s23 = Alias.v23.s();
263 pub const s24 = Alias.v24.s();
264 pub const s25 = Alias.v25.s();
265 pub const s26 = Alias.v26.s();
266 pub const s27 = Alias.v27.s();
267 pub const s28 = Alias.v28.s();
268 pub const s29 = Alias.v29.s();
269 pub const s30 = Alias.v30.s();
270 pub const s31 = Alias.v31.s();
271
272 pub const h0 = Alias.v0.h();
273 pub const h1 = Alias.v1.h();
274 pub const h2 = Alias.v2.h();
275 pub const h3 = Alias.v3.h();
276 pub const h4 = Alias.v4.h();
277 pub const h5 = Alias.v5.h();
278 pub const h6 = Alias.v6.h();
279 pub const h7 = Alias.v7.h();
280 pub const h8 = Alias.v8.h();
281 pub const h9 = Alias.v9.h();
282 pub const h10 = Alias.v10.h();
283 pub const h11 = Alias.v11.h();
284 pub const h12 = Alias.v12.h();
285 pub const h13 = Alias.v13.h();
286 pub const h14 = Alias.v14.h();
287 pub const h15 = Alias.v15.h();
288 pub const h16 = Alias.v16.h();
289 pub const h17 = Alias.v17.h();
290 pub const h18 = Alias.v18.h();
291 pub const h19 = Alias.v19.h();
292 pub const h20 = Alias.v20.h();
293 pub const h21 = Alias.v21.h();
294 pub const h22 = Alias.v22.h();
295 pub const h23 = Alias.v23.h();
296 pub const h24 = Alias.v24.h();
297 pub const h25 = Alias.v25.h();
298 pub const h26 = Alias.v26.h();
299 pub const h27 = Alias.v27.h();
300 pub const h28 = Alias.v28.h();
301 pub const h29 = Alias.v29.h();
302 pub const h30 = Alias.v30.h();
303 pub const h31 = Alias.v31.h();
304
305 pub const b0 = Alias.v0.b();
306 pub const b1 = Alias.v1.b();
307 pub const b2 = Alias.v2.b();
308 pub const b3 = Alias.v3.b();
309 pub const b4 = Alias.v4.b();
310 pub const b5 = Alias.v5.b();
311 pub const b6 = Alias.v6.b();
312 pub const b7 = Alias.v7.b();
313 pub const b8 = Alias.v8.b();
314 pub const b9 = Alias.v9.b();
315 pub const b10 = Alias.v10.b();
316 pub const b11 = Alias.v11.b();
317 pub const b12 = Alias.v12.b();
318 pub const b13 = Alias.v13.b();
319 pub const b14 = Alias.v14.b();
320 pub const b15 = Alias.v15.b();
321 pub const b16 = Alias.v16.b();
322 pub const b17 = Alias.v17.b();
323 pub const b18 = Alias.v18.b();
324 pub const b19 = Alias.v19.b();
325 pub const b20 = Alias.v20.b();
326 pub const b21 = Alias.v21.b();
327 pub const b22 = Alias.v22.b();
328 pub const b23 = Alias.v23.b();
329 pub const b24 = Alias.v24.b();
330 pub const b25 = Alias.v25.b();
331 pub const b26 = Alias.v26.b();
332 pub const b27 = Alias.v27.b();
333 pub const b28 = Alias.v28.b();
334 pub const b29 = Alias.v29.b();
335 pub const b30 = Alias.v30.b();
336 pub const b31 = Alias.v31.b();
337
338 pub const fpcr = Alias.fpcr.alias(.other);
339 pub const fpsr = Alias.fpsr.alias(.other);
340
341 pub const z0 = Alias.v0.z();
342 pub const z1 = Alias.v1.z();
343 pub const z2 = Alias.v2.z();
344 pub const z3 = Alias.v3.z();
345 pub const z4 = Alias.v4.z();
346 pub const z5 = Alias.v5.z();
347 pub const z6 = Alias.v6.z();
348 pub const z7 = Alias.v7.z();
349 pub const z8 = Alias.v8.z();
350 pub const z9 = Alias.v9.z();
351 pub const z10 = Alias.v10.z();
352 pub const z11 = Alias.v11.z();
353 pub const z12 = Alias.v12.z();
354 pub const z13 = Alias.v13.z();
355 pub const z14 = Alias.v14.z();
356 pub const z15 = Alias.v15.z();
357 pub const z16 = Alias.v16.z();
358 pub const z17 = Alias.v17.z();
359 pub const z18 = Alias.v18.z();
360 pub const z19 = Alias.v19.z();
361 pub const z20 = Alias.v20.z();
362 pub const z21 = Alias.v21.z();
363 pub const z22 = Alias.v22.z();
364 pub const z23 = Alias.v23.z();
365 pub const z24 = Alias.v24.z();
366 pub const z25 = Alias.v25.z();
367 pub const z26 = Alias.v26.z();
368 pub const z27 = Alias.v27.z();
369 pub const z28 = Alias.v28.z();
370 pub const z29 = Alias.v29.z();
371 pub const z30 = Alias.v30.z();
372 pub const z31 = Alias.v31.z();
373
374 pub const p0 = Alias.p0.p();
375 pub const p1 = Alias.p1.p();
376 pub const p2 = Alias.p2.p();
377 pub const p3 = Alias.p3.p();
378 pub const p4 = Alias.p4.p();
379 pub const p5 = Alias.p5.p();
380 pub const p6 = Alias.p6.p();
381 pub const p7 = Alias.p7.p();
382 pub const p8 = Alias.p8.p();
383 pub const p9 = Alias.p9.p();
384 pub const p10 = Alias.p10.p();
385 pub const p11 = Alias.p11.p();
386 pub const p12 = Alias.p12.p();
387 pub const p13 = Alias.p13.p();
388 pub const p14 = Alias.p14.p();
389 pub const p15 = Alias.p15.p();
390
391 pub const ffr = Alias.ffr.alias(.other);
388392
389393 pub const Encoded = enum(u5) {
390394 _,
391395
392 pub fn decodeInteger(enc: Encoded, sf_enc: IntegerSize, opts: struct { sp: bool = false }) Register {
393 return switch (sf_enc) {
394 .word => switch (@intFromEnum(enc)) {
395 0 => .w0,
396 1 => .w1,
397 2 => .w2,
398 3 => .w3,
399 4 => .w4,
400 5 => .w5,
401 6 => .w6,
402 7 => .w7,
403 8 => .w8,
404 9 => .w9,
405 10 => .w10,
406 11 => .w11,
407 12 => .w12,
408 13 => .w13,
409 14 => .w14,
410 15 => .w15,
411 16 => .w16,
412 17 => .w17,
413 18 => .w18,
414 19 => .w19,
415 20 => .w20,
416 21 => .w21,
417 22 => .w22,
418 23 => .w23,
419 24 => .w24,
420 25 => .w25,
421 26 => .w26,
422 27 => .w27,
423 28 => .w28,
424 29 => .w29,
425 30 => .w30,
426 31 => if (opts.sp) .wsp else .wzr,
427 },
428 .doubleword => switch (@intFromEnum(enc)) {
429 0 => .x0,
430 1 => .x1,
431 2 => .x2,
432 3 => .x3,
433 4 => .x4,
434 5 => .x5,
435 6 => .x6,
436 7 => .x7,
437 8 => .x8,
438 9 => .x9,
439 10 => .x10,
440 11 => .x11,
441 12 => .x12,
442 13 => .x13,
443 14 => .x14,
444 15 => .x15,
445 16 => .x16,
446 17 => .x17,
447 18 => .x18,
448 19 => .x19,
449 20 => .x20,
450 21 => .x21,
451 22 => .x22,
452 23 => .x23,
453 24 => .x24,
454 25 => .x25,
455 26 => .x26,
456 27 => .x27,
457 28 => .x28,
458 29 => .x29,
459 30 => .x30,
460 31 => if (opts.sp) .sp else .xzr,
461 },
462 };
463 }
464
465 pub fn decodeVector(enc: Encoded, vs_enc: VectorSize) Register {
466 return switch (vs_enc) {
467 .byte => switch (@intFromEnum(enc)) {
468 0 => .b0,
469 1 => .b1,
470 2 => .b2,
471 3 => .b3,
472 4 => .b4,
473 5 => .b5,
474 6 => .b6,
475 7 => .b7,
476 8 => .b8,
477 9 => .b9,
478 10 => .b10,
479 11 => .b11,
480 12 => .b12,
481 13 => .b13,
482 14 => .b14,
483 15 => .b15,
484 16 => .b16,
485 17 => .b17,
486 18 => .b18,
487 19 => .b19,
488 20 => .b20,
489 21 => .b21,
490 22 => .b22,
491 23 => .b23,
492 24 => .b24,
493 25 => .b25,
494 26 => .b26,
495 27 => .b27,
496 28 => .b28,
497 29 => .b29,
498 30 => .b30,
499 31 => .b31,
500 },
501 .half => switch (@intFromEnum(enc)) {
502 0 => .h0,
503 1 => .h1,
504 2 => .h2,
505 3 => .h3,
506 4 => .h4,
507 5 => .h5,
508 6 => .h6,
509 7 => .h7,
510 8 => .h8,
511 9 => .h9,
512 10 => .h10,
513 11 => .h11,
514 12 => .h12,
515 13 => .h13,
516 14 => .h14,
517 15 => .h15,
518 16 => .h16,
519 17 => .h17,
520 18 => .h18,
521 19 => .h19,
522 20 => .h20,
523 21 => .h21,
524 22 => .h22,
525 23 => .h23,
526 24 => .h24,
527 25 => .h25,
528 26 => .h26,
529 27 => .h27,
530 28 => .h28,
531 29 => .h29,
532 30 => .h30,
533 31 => .h31,
534 },
535 .single => switch (@intFromEnum(enc)) {
536 0 => .s0,
537 1 => .s1,
538 2 => .s2,
539 3 => .s3,
540 4 => .s4,
541 5 => .s5,
542 6 => .s6,
543 7 => .s7,
544 8 => .s8,
545 9 => .s9,
546 10 => .s10,
547 11 => .s11,
548 12 => .s12,
549 13 => .s13,
550 14 => .s14,
551 15 => .s15,
552 16 => .s16,
553 17 => .s17,
554 18 => .s18,
555 19 => .s19,
556 20 => .s20,
557 21 => .s21,
558 22 => .s22,
559 23 => .s23,
560 24 => .s24,
561 25 => .s25,
562 26 => .s26,
563 27 => .s27,
564 28 => .s28,
565 29 => .s29,
566 30 => .s30,
567 31 => .s31,
568 },
569 .double => switch (@intFromEnum(enc)) {
570 0 => .d0,
571 1 => .d1,
572 2 => .d2,
573 3 => .d3,
574 4 => .d4,
575 5 => .d5,
576 6 => .d6,
577 7 => .d7,
578 8 => .d8,
579 9 => .d9,
580 10 => .d10,
581 11 => .d11,
582 12 => .d12,
583 13 => .d13,
584 14 => .d14,
585 15 => .d15,
586 16 => .d16,
587 17 => .d17,
588 18 => .d18,
589 19 => .d19,
590 20 => .d20,
591 21 => .d21,
592 22 => .d22,
593 23 => .d23,
594 24 => .d24,
595 25 => .d25,
596 26 => .d26,
597 27 => .d27,
598 28 => .d28,
599 29 => .d29,
600 30 => .d30,
601 31 => .d31,
602 },
603 .quad => switch (@intFromEnum(enc)) {
604 0 => .q0,
605 1 => .q1,
606 2 => .q2,
607 3 => .q3,
608 4 => .q4,
609 5 => .q5,
610 6 => .q6,
611 7 => .q7,
612 8 => .q8,
613 9 => .q9,
614 10 => .q10,
615 11 => .q11,
616 12 => .q12,
617 13 => .q13,
618 14 => .q14,
619 15 => .q15,
620 16 => .q16,
621 17 => .q17,
622 18 => .q18,
623 19 => .q19,
624 20 => .q20,
625 21 => .q21,
626 22 => .q22,
627 23 => .q23,
628 24 => .q24,
629 25 => .q25,
630 26 => .q26,
631 27 => .q27,
632 28 => .q28,
633 29 => .q29,
634 30 => .q30,
635 31 => .q31,
636 },
637 .scalable => switch (@intFromEnum(enc)) {
638 0 => .z0,
639 1 => .z1,
640 2 => .z2,
641 3 => .z3,
642 4 => .z4,
643 5 => .z5,
644 6 => .z6,
645 7 => .z7,
646 8 => .z8,
647 9 => .z9,
648 10 => .z10,
649 11 => .z11,
650 12 => .z12,
651 13 => .z13,
652 14 => .z14,
653 15 => .z15,
654 16 => .z16,
655 17 => .z17,
656 18 => .z18,
657 19 => .z19,
658 20 => .z20,
659 21 => .z21,
660 22 => .z22,
661 23 => .z23,
662 24 => .z24,
663 25 => .z25,
664 26 => .z26,
665 27 => .z27,
666 28 => .z28,
667 29 => .z29,
668 30 => .z30,
669 31 => .z31,
670 },
671 .predicate => switch (@as(u4, @intCast(@intFromEnum(enc)))) {
672 0 => .p0,
673 1 => .p1,
674 2 => .p2,
675 3 => .p3,
676 4 => .p4,
677 5 => .p5,
678 6 => .p6,
679 7 => .p7,
680 8 => .p8,
681 9 => .p9,
682 10 => .p10,
683 11 => .p11,
684 12 => .p12,
685 13 => .p13,
686 14 => .p14,
687 15 => .p15,
688 },
396 pub fn decode(enc: Encoded, opts: struct { sp: bool = false, V: bool = false }) Alias {
397 return switch (opts.V) {
398 false => @enumFromInt(@intFromEnum(Alias.r0) + @intFromEnum(enc) +
399 @intFromBool(opts.sp and enc == comptime Alias.sp.encode(.{ .sp = true }))),
400 true => @enumFromInt(@intFromEnum(Alias.v0) + @intFromEnum(enc)),
689401 };
690402 }
691403 };
......@@ -789,97 +501,105 @@ pub const Register = struct {
789501 pub const fp: Alias = .r29;
790502 pub const lr: Alias = .r30;
791503
504 pub fn alias(ra: Alias, fa: Format.Alias) Register {
505 switch (fa) {
506 .general => assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp)),
507 .other => switch (ra) {
508 else => unreachable,
509 .pc, .fpcr, .fpsr, .ffr => {},
510 },
511 .vector => assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31)),
512 .predicate => assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15)),
513 }
514 return .{ .alias = ra, .format = .{ .alias = fa } };
515 }
516 pub fn general(ra: Alias, gs: GeneralSize) Register {
517 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));
518 return .{ .alias = ra, .format = .{ .general = gs } };
519 }
520 pub fn scalar(ra: Alias, ss: ScalarSize) Register {
521 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
522 return .{ .alias = ra, .format = .{ .scalar = ss } };
523 }
524 pub fn vector(ra: Alias, arrangement: Arrangement) Register {
525 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
526 return .{ .alias = ra, .format = .{ .vector = arrangement } };
527 }
528 pub fn element(ra: Alias, ss: ScalarSize, index: u4) Register {
529 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
530 return .{ .alias = ra, .format = .{ .element = .{ .size = ss, .index = index } } };
531 }
532 pub fn z(ra: Alias) Register {
533 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
534 return .{ .alias = ra, .format = .scalable };
535 }
536 pub fn p(ra: Alias) Register {
537 assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15));
538 return .{ .alias = ra, .format = .{ .scalar = .predicate } };
539 }
540
792541 pub fn r(ra: Alias) Register {
793 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.pc));
794 return .{ .alias = ra, .format = .alias };
542 return ra.alias(.general);
795543 }
796544 pub fn x(ra: Alias) Register {
797 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));
798 return .{ .alias = ra, .format = .{ .integer = .doubleword } };
545 return ra.general(.doubleword);
799546 }
800547 pub fn w(ra: Alias) Register {
801 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));
802 return .{ .alias = ra, .format = .{ .integer = .word } };
548 return ra.general(.word);
803549 }
804550 pub fn v(ra: Alias) Register {
805 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
806 return .{ .alias = ra, .format = .alias };
551 return ra.alias(.vector);
807552 }
808553 pub fn q(ra: Alias) Register {
809 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
810 return .{ .alias = ra, .format = .{ .scalar = .quad } };
554 return ra.scalar(.quad);
811555 }
812556 pub fn d(ra: Alias) Register {
813 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
814 return .{ .alias = ra, .format = .{ .scalar = .double } };
557 return ra.scalar(.double);
815558 }
816559 pub fn s(ra: Alias) Register {
817 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
818 return .{ .alias = ra, .format = .{ .scalar = .single } };
560 return ra.scalar(.single);
819561 }
820562 pub fn h(ra: Alias) Register {
821 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
822 return .{ .alias = ra, .format = .{ .scalar = .half } };
563 return ra.scalar(.half);
823564 }
824565 pub fn b(ra: Alias) Register {
825 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
826 return .{ .alias = ra, .format = .{ .scalar = .byte } };
827 }
828 pub fn z(ra: Alias) Register {
829 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
830 return .{ .alias = ra, .format = .{ .scalar = .scalable } };
831 }
832 pub fn p(ra: Alias) Register {
833 assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15));
834 return .{ .alias = ra, .format = .{ .scalar = .predicate } };
566 return ra.scalar(.byte);
835567 }
836568 pub fn @"2d"(ra: Alias) Register {
837 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
838 return .{ .alias = ra, .format = .{ .vector = .@"2d" } };
569 return ra.vector(.@"2d");
839570 }
840571 pub fn @"4s"(ra: Alias) Register {
841 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
842 return .{ .alias = ra, .format = .{ .vector = .@"4s" } };
572 return ra.vector(.@"4s");
843573 }
844574 pub fn @"8h"(ra: Alias) Register {
845 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
846 return .{ .alias = ra, .format = .{ .vector = .@"8h" } };
575 return ra.vector(.@"8h");
847576 }
848577 pub fn @"16b"(ra: Alias) Register {
849 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
850 return .{ .alias = ra, .format = .{ .vector = .@"16b" } };
578 return ra.vector(.@"16b");
851579 }
852580 pub fn @"1d"(ra: Alias) Register {
853 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
854 return .{ .alias = ra, .format = .{ .vector = .@"1d" } };
581 return ra.vector(.@"1d");
855582 }
856583 pub fn @"2s"(ra: Alias) Register {
857 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
858 return .{ .alias = ra, .format = .{ .vector = .@"2s" } };
584 return ra.vector(.@"2s");
859585 }
860586 pub fn @"4h"(ra: Alias) Register {
861 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
862 return .{ .alias = ra, .format = .{ .vector = .@"4h" } };
587 return ra.vector(.@"4h");
863588 }
864589 pub fn @"8b"(ra: Alias) Register {
865 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
866 return .{ .alias = ra, .format = .{ .vector = .@"8b" } };
590 return ra.vector(.@"8b");
867591 }
868592 pub fn @"d[]"(ra: Alias, index: u1) Register {
869 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
870 return .{ .alias = ra, .format = .{ .element = .{ .size = .double, .index = index } } };
593 return ra.element(.double, index);
871594 }
872595 pub fn @"s[]"(ra: Alias, index: u2) Register {
873 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
874 return .{ .alias = ra, .format = .{ .element = .{ .size = .single, .index = index } } };
596 return ra.element(.single, index);
875597 }
876598 pub fn @"h[]"(ra: Alias, index: u3) Register {
877 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
878 return .{ .alias = ra, .format = .{ .element = .{ .size = .half, .index = index } } };
599 return ra.element(.half, index);
879600 }
880601 pub fn @"b[]"(ra: Alias, index: u4) Register {
881 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
882 return .{ .alias = ra, .format = .{ .element = .{ .size = .byte, .index = index } } };
602 return ra.element(.byte, index);
883603 }
884604
885605 pub fn isVector(ra: Alias) bool {
......@@ -1061,23 +781,23 @@ pub const Register = struct {
1061781 pub fn size(reg: Register) ?u5 {
1062782 return format: switch (reg.format) {
1063783 .alias => unreachable,
1064 .integer => |sf| switch (sf) {
784 .general => |sf| switch (sf) {
1065785 .word => 4,
1066786 .doubleword => 8,
1067787 },
1068 .vector => |vs| switch (vs) {
788 .scalar => |elem_size| switch (elem_size) {
1069789 .byte => 1,
1070 .word => 2,
790 .half => 2,
1071791 .single => 4,
1072792 .double => 8,
1073793 .quad => 16,
1074 .scalable, .predicate => null,
1075794 },
1076 .arrangement => |arrangement| switch (arrangement) {
795 .vector => |arrangement| switch (arrangement) {
1077796 .@"2d", .@"4s", .@"8h", .@"16b" => 16,
1078797 .@"1d", .@"2s", .@"4h", .@"8b" => 8,
1079798 },
1080 .element => |element| continue :format .{ .vector = element.size },
799 .element => |element| continue :format .{ .scalar = element.size },
800 .scalable => null,
1081801 };
1082802 }
1083803
......@@ -1087,21 +807,21 @@ pub const Register = struct {
1087807 'r' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1088808 0...30 => .{
1089809 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1090 .format = .alias,
810 .format = .{ .alias = .general },
1091811 },
1092812 31 => null,
1093813 } else |_| null,
1094814 'x' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1095815 0...30 => .{
1096816 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1097 .format = .{ .integer = .doubleword },
817 .format = .{ .general = .doubleword },
1098818 },
1099819 31 => null,
1100820 } else |_| if (toLowerEqlAssertLower(reg, "xzr")) .xzr else null,
1101821 'w' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1102822 0...30 => .{
1103823 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1104 .format = .{ .integer = .word },
824 .format = .{ .general = .word },
1105825 },
1106826 31 => null,
1107827 } else |_| if (toLowerEqlAssertLower(reg, "wzr"))
......@@ -1120,7 +840,7 @@ pub const Register = struct {
1120840 'p' => return if (toLowerEqlAssertLower(reg, "pc")) .pc else null,
1121841 'v' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{
1122842 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),
1123 .format = .alias,
843 .format = .{ .alias = .vector },
1124844 } else |_| null,
1125845 'q' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{
1126846 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),
......@@ -1788,6 +1508,17 @@ pub const Instruction = packed union {
17881508 adr = 0b0,
17891509 adrp = 0b1,
17901510 };
1511
1512 pub const Decoded = union(enum) {
1513 adr: Adr,
1514 adrp: Adrp,
1515 };
1516 pub fn decode(inst: @This()) @This().Decoded {
1517 return switch (inst.group.op) {
1518 .adr => .{ .adr = inst.adr },
1519 .adrp => .{ .adrp = inst.adrp },
1520 };
1521 }
17911522 };
17921523
17931524 /// Add/subtract (immediate)
......@@ -1806,7 +1537,7 @@ pub const Instruction = packed union {
18061537 decoded23: u6 = 0b100010,
18071538 S: bool,
18081539 op: AddSubtractOp,
1809 sf: Register.IntegerSize,
1540 sf: Register.GeneralSize,
18101541 };
18111542
18121543 /// C6.2.4 ADD (immediate)
......@@ -1818,7 +1549,7 @@ pub const Instruction = packed union {
18181549 decoded23: u6 = 0b100010,
18191550 S: bool = false,
18201551 op: AddSubtractOp = .add,
1821 sf: Register.IntegerSize,
1552 sf: Register.GeneralSize,
18221553 };
18231554
18241555 /// C6.2.8 ADDS (immediate)
......@@ -1830,7 +1561,7 @@ pub const Instruction = packed union {
18301561 decoded23: u6 = 0b100010,
18311562 S: bool = true,
18321563 op: AddSubtractOp = .add,
1833 sf: Register.IntegerSize,
1564 sf: Register.GeneralSize,
18341565 };
18351566
18361567 /// C6.2.357 SUB (immediate)
......@@ -1842,7 +1573,7 @@ pub const Instruction = packed union {
18421573 decoded23: u6 = 0b100010,
18431574 S: bool = false,
18441575 op: AddSubtractOp = .sub,
1845 sf: Register.IntegerSize,
1576 sf: Register.GeneralSize,
18461577 };
18471578
18481579 /// C6.2.363 SUBS (immediate)
......@@ -1854,18 +1585,39 @@ pub const Instruction = packed union {
18541585 decoded23: u6 = 0b100010,
18551586 S: bool = true,
18561587 op: AddSubtractOp = .sub,
1857 sf: Register.IntegerSize,
1588 sf: Register.GeneralSize,
18581589 };
18591590
18601591 pub const Shift = enum(u1) {
18611592 @"0" = 0b0,
18621593 @"12" = 0b1,
18631594 };
1595
1596 pub const Decoded = union(enum) {
1597 add: Add,
1598 adds: Adds,
1599 sub: Sub,
1600 subs: Subs,
1601 };
1602 pub fn decode(inst: @This()) @This().Decaded {
1603 return switch (inst.group.op) {
1604 .add => switch (inst.group.S) {
1605 false => .{ .add = inst.add },
1606 true => .{ .addc = inst.addc },
1607 },
1608 .sub => switch (inst.group.S) {
1609 false => .{ .sub = inst.sub },
1610 true => .{ .subc = inst.subc },
1611 },
1612 };
1613 }
18641614 };
18651615
18661616 /// Add/subtract (immediate, with tags)
18671617 pub const AddSubtractImmediateWithTags = packed union {
18681618 group: @This().Group,
1619 addg: Addg,
1620 subg: Subg,
18691621
18701622 pub const Group = packed struct {
18711623 Rd: Register.Encoded,
......@@ -1877,8 +1629,57 @@ pub const Instruction = packed union {
18771629 decoded23: u6 = 0b100011,
18781630 S: bool,
18791631 op: AddSubtractOp,
1880 sf: Register.IntegerSize,
1632 sf: Register.GeneralSize,
1633 };
1634
1635 /// C6.2.6 ADDG
1636 pub const Addg = packed struct {
1637 Xd: Register.Encoded,
1638 Xn: Register.Encoded,
1639 uimm4: u4,
1640 op3: u2 = 0b00,
1641 uimm6: u6,
1642 o2: u1 = 0b0,
1643 decoded23: u6 = 0b100011,
1644 S: bool = false,
1645 op: AddSubtractOp = .add,
1646 sf: Register.GeneralSize = .doubleword,
1647 };
1648
1649 /// C6.2.359 SUBG
1650 pub const Subg = packed struct {
1651 Xd: Register.Encoded,
1652 Xn: Register.Encoded,
1653 uimm4: u4,
1654 op3: u2 = 0b00,
1655 uimm6: u6,
1656 o2: u1 = 0b0,
1657 decoded23: u6 = 0b100011,
1658 S: bool = false,
1659 op: AddSubtractOp = .sub,
1660 sf: Register.GeneralSize = .doubleword,
1661 };
1662
1663 pub const Decoded = union(enum) {
1664 unallocated,
1665 addg: Addg,
1666 subg: Subg,
18811667 };
1668 pub fn decode(inst: @This()) @This().Decoded {
1669 return switch (inst.group.o2) {
1670 0b1 => .unallocated,
1671 0b0 => switch (inst.group.sf) {
1672 .word => .unallocated,
1673 .doubleword => switch (inst.group.S) {
1674 true => .unallocated,
1675 false => switch (inst.group.op) {
1676 .add => .{ .addg = inst.addg },
1677 .sub => .{ .subg = inst.subg },
1678 },
1679 },
1680 },
1681 };
1682 }
18821683 };
18831684
18841685 /// Logical (immediate)
......@@ -1895,7 +1696,7 @@ pub const Instruction = packed union {
18951696 imm: Bitmask,
18961697 decoded23: u6 = 0b100100,
18971698 opc: LogicalOpc,
1898 sf: Register.IntegerSize,
1699 sf: Register.GeneralSize,
18991700 };
19001701
19011702 /// C6.2.12 AND (immediate)
......@@ -1905,7 +1706,7 @@ pub const Instruction = packed union {
19051706 imm: Bitmask,
19061707 decoded23: u6 = 0b100100,
19071708 opc: LogicalOpc = .@"and",
1908 sf: Register.IntegerSize,
1709 sf: Register.GeneralSize,
19091710 };
19101711
19111712 /// C6.2.240 ORR (immediate)
......@@ -1915,7 +1716,7 @@ pub const Instruction = packed union {
19151716 imm: Bitmask,
19161717 decoded23: u6 = 0b100100,
19171718 opc: LogicalOpc = .orr,
1918 sf: Register.IntegerSize,
1719 sf: Register.GeneralSize,
19191720 };
19201721
19211722 /// C6.2.119 EOR (immediate)
......@@ -1925,7 +1726,7 @@ pub const Instruction = packed union {
19251726 imm: Bitmask,
19261727 decoded23: u6 = 0b100100,
19271728 opc: LogicalOpc = .eor,
1928 sf: Register.IntegerSize,
1729 sf: Register.GeneralSize,
19291730 };
19301731
19311732 /// C6.2.14 ANDS (immediate)
......@@ -1935,7 +1736,7 @@ pub const Instruction = packed union {
19351736 imm: Bitmask,
19361737 decoded23: u6 = 0b100100,
19371738 opc: LogicalOpc = .ands,
1938 sf: Register.IntegerSize,
1739 sf: Register.GeneralSize,
19391740 };
19401741
19411742 pub const Decoded = union(enum) {
......@@ -1970,7 +1771,7 @@ pub const Instruction = packed union {
19701771 hw: Hw,
19711772 decoded23: u6 = 0b100101,
19721773 opc: Opc,
1973 sf: Register.IntegerSize,
1774 sf: Register.GeneralSize,
19741775 };
19751776
19761777 /// C6.2.226 MOVN
......@@ -1980,7 +1781,7 @@ pub const Instruction = packed union {
19801781 hw: Hw,
19811782 decoded23: u6 = 0b100101,
19821783 opc: Opc = .movn,
1983 sf: Register.IntegerSize,
1784 sf: Register.GeneralSize,
19841785 };
19851786
19861787 /// C6.2.227 MOVZ
......@@ -1990,7 +1791,7 @@ pub const Instruction = packed union {
19901791 hw: Hw,
19911792 decoded23: u6 = 0b100101,
19921793 opc: Opc = .movz,
1993 sf: Register.IntegerSize,
1794 sf: Register.GeneralSize,
19941795 };
19951796
19961797 /// C6.2.225 MOVK
......@@ -2000,7 +1801,7 @@ pub const Instruction = packed union {
20001801 hw: Hw,
20011802 decoded23: u6 = 0b100101,
20021803 opc: Opc = .movk,
2003 sf: Register.IntegerSize,
1804 sf: Register.GeneralSize,
20041805 };
20051806
20061807 pub const Hw = enum(u2) {
......@@ -2018,7 +1819,7 @@ pub const Instruction = packed union {
20181819 };
20191820 }
20201821
2021 pub fn sf(hw: Hw) Register.IntegerSize {
1822 pub fn sf(hw: Hw) Register.GeneralSize {
20221823 return switch (hw) {
20231824 .@"0", .@"16" => .word,
20241825 .@"32", .@"48" => .doubleword,
......@@ -2064,7 +1865,7 @@ pub const Instruction = packed union {
20641865 imm: Bitmask,
20651866 decoded23: u6 = 0b100110,
20661867 opc: Opc,
2067 sf: Register.IntegerSize,
1868 sf: Register.GeneralSize,
20681869 };
20691870
20701871 pub const Sbfm = packed struct {
......@@ -2073,7 +1874,7 @@ pub const Instruction = packed union {
20731874 imm: Bitmask,
20741875 decoded23: u6 = 0b100110,
20751876 opc: Opc = .sbfm,
2076 sf: Register.IntegerSize,
1877 sf: Register.GeneralSize,
20771878 };
20781879
20791880 pub const Bfm = packed struct {
......@@ -2082,7 +1883,7 @@ pub const Instruction = packed union {
20821883 imm: Bitmask,
20831884 decoded23: u6 = 0b100110,
20841885 opc: Opc = .bfm,
2085 sf: Register.IntegerSize,
1886 sf: Register.GeneralSize,
20861887 };
20871888
20881889 pub const Ubfm = packed struct {
......@@ -2091,7 +1892,7 @@ pub const Instruction = packed union {
20911892 imm: Bitmask,
20921893 decoded23: u6 = 0b100110,
20931894 opc: Opc = .ubfm,
2094 sf: Register.IntegerSize,
1895 sf: Register.GeneralSize,
20951896 };
20961897
20971898 pub const Opc = enum(u2) {
......@@ -2130,10 +1931,10 @@ pub const Instruction = packed union {
21301931 imms: u6,
21311932 Rm: Register.Encoded,
21321933 o0: u1,
2133 N: Register.IntegerSize,
1934 N: Register.GeneralSize,
21341935 decoded23: u6 = 0b100111,
21351936 op21: u2,
2136 sf: Register.IntegerSize,
1937 sf: Register.GeneralSize,
21371938 };
21381939
21391940 pub const Extr = packed struct {
......@@ -2142,10 +1943,10 @@ pub const Instruction = packed union {
21421943 imms: u6,
21431944 Rm: Register.Encoded,
21441945 o0: u1 = 0b0,
2145 N: Register.IntegerSize,
1946 N: Register.GeneralSize,
21461947 decoded23: u6 = 0b100111,
21471948 op21: u2 = 0b00,
2148 sf: Register.IntegerSize,
1949 sf: Register.GeneralSize,
21491950 };
21501951
21511952 pub const Decoded = union(enum) {
......@@ -2170,22 +1971,22 @@ pub const Instruction = packed union {
21701971 pub const Bitmask = packed struct {
21711972 imms: u6,
21721973 immr: u6,
2173 N: Register.IntegerSize,
1974 N: Register.GeneralSize,
21741975
21751976 fn lenHsb(bitmask: Bitmask) u7 {
21761977 return @bitCast(packed struct {
21771978 not_imms: u6,
2178 N: Register.IntegerSize,
1979 N: Register.GeneralSize,
21791980 }{ .not_imms = ~bitmask.imms, .N = bitmask.N });
21801981 }
21811982
2182 fn validImmediate(bitmask: Bitmask, sf: Register.IntegerSize) bool {
1983 fn validImmediate(bitmask: Bitmask, sf: Register.GeneralSize) bool {
21831984 if (sf == .word and bitmask.N == .doubleword) return false;
21841985 const len_hsb = bitmask.lenHsb();
21851986 return (len_hsb -% 1) & len_hsb != 0b0_000000;
21861987 }
21871988
2188 fn validBitfield(bitmask: Bitmask, sf: Register.IntegerSize) bool {
1989 fn validBitfield(bitmask: Bitmask, sf: Register.GeneralSize) bool {
21891990 if (sf != bitmask.N) return false;
21901991 if (sf == .word and (@as(u1, @truncate(bitmask.immr >> 5)) != 0b0 or
21911992 @as(u1, @truncate(bitmask.imms >> 5)) != 0b0)) return false;
......@@ -2193,7 +1994,7 @@ pub const Instruction = packed union {
21931994 return len_hsb >= 0b0_000010;
21941995 }
21951996
2196 fn decode(bitmask: Bitmask, sf: Register.IntegerSize) struct { u64, u64 } {
1997 fn decode(bitmask: Bitmask, sf: Register.GeneralSize) struct { u64, u64 } {
21971998 const esize = @as(u7, 1 << 6) >> @clz(bitmask.lenHsb());
21981999 const levels: u6 = @intCast(esize - 1);
21992000 const s = bitmask.imms & levels;
......@@ -2211,18 +2012,18 @@ pub const Instruction = packed union {
22112012 };
22122013 }
22132014
2214 pub fn decodeImmediate(bitmask: Bitmask, sf: Register.IntegerSize) u64 {
2015 pub fn decodeImmediate(bitmask: Bitmask, sf: Register.GeneralSize) u64 {
22152016 assert(bitmask.validImmediate(sf));
22162017 const imm, _ = bitmask.decode(sf);
22172018 return imm;
22182019 }
22192020
2220 pub fn decodeBitfield(bitmask: Bitmask, sf: Register.IntegerSize) struct { u64, u64 } {
2021 pub fn decodeBitfield(bitmask: Bitmask, sf: Register.GeneralSize) struct { u64, u64 } {
22212022 assert(bitmask.validBitfield(sf));
22222023 return bitmask.decode(sf);
22232024 }
22242025
2225 pub fn moveWidePreferred(bitmask: Bitmask, sf: Register.IntegerSize) bool {
2026 pub fn moveWidePreferred(bitmask: Bitmask, sf: Register.GeneralSize) bool {
22262027 const s = bitmask.imms;
22272028 const r = bitmask.immr;
22282029 const width: u7 = switch (sf) {
......@@ -2646,7 +2447,7 @@ pub const Instruction = packed union {
26462447
26472448 /// C6.2.56 CLREX
26482449 pub const Clrex = packed struct {
2649 Rt: Register.Encoded = @enumFromInt(0b11111),
2450 Rt: Register.Encoded = no_reg,
26502451 op2: u3 = 0b010,
26512452 CRm: u4,
26522453 decoded12: u4 = 0b0011,
......@@ -2658,7 +2459,7 @@ pub const Instruction = packed union {
26582459
26592460 /// C6.2.116 DSB
26602461 pub const Dsb = packed struct {
2661 Rt: Register.Encoded = @enumFromInt(0b11111),
2462 Rt: Register.Encoded = no_reg,
26622463 opc: u2 = 0b00,
26632464 decoded7: u1 = 0b1,
26642465 CRm: Option,
......@@ -2671,7 +2472,7 @@ pub const Instruction = packed union {
26712472
26722473 /// C6.2.114 DMB
26732474 pub const Dmb = packed struct {
2674 Rt: Register.Encoded = @enumFromInt(0b11111),
2475 Rt: Register.Encoded = no_reg,
26752476 opc: u2 = 0b01,
26762477 decoded7: u1 = 0b1,
26772478 CRm: Option,
......@@ -2684,7 +2485,7 @@ pub const Instruction = packed union {
26842485
26852486 /// C6.2.131 ISB
26862487 pub const Isb = packed struct {
2687 Rt: Register.Encoded = @enumFromInt(0b11111),
2488 Rt: Register.Encoded = no_reg,
26882489 opc: u2 = 0b10,
26892490 decoded7: u1 = 0b1,
26902491 CRm: Option,
......@@ -2697,7 +2498,7 @@ pub const Instruction = packed union {
26972498
26982499 /// C6.2.264 SB
26992500 pub const Sb = packed struct {
2700 Rt: Register.Encoded = @enumFromInt(0b11111),
2501 Rt: Register.Encoded = no_reg,
27012502 opc: u2 = 0b11,
27022503 decoded7: u1 = 0b1,
27032504 CRm: u4 = 0b0000,
......@@ -2723,16 +2524,115 @@ pub const Instruction = packed union {
27232524 sy = 0b1111,
27242525 _,
27252526 };
2527
2528 pub const Decoded = union(enum) {
2529 unallocated,
2530 clrex: Clrex,
2531 dsb: Dsb,
2532 dmb: Dmb,
2533 isb: Isb,
2534 sb: Sb,
2535 };
2536 pub fn decode(inst: @This()) @This().Decoded {
2537 return switch (inst.group.op2) {
2538 0b000, 0b001 => .unallocated,
2539 0b010 => switch (inst.group.Rt) {
2540 no_reg => .{ .clrex = inst.clrex },
2541 else => .unallocated,
2542 },
2543 0b100 => switch (inst.group.Rt) {
2544 no_reg => .{ .dsb = inst.dsb },
2545 else => .unallocated,
2546 },
2547 0b101 => switch (inst.group.Rt) {
2548 no_reg => .{ .dmb = inst.dmb },
2549 else => .unallocated,
2550 },
2551 0b110 => switch (inst.group.Rt) {
2552 no_reg => .{ .isb = inst.isb },
2553 else => .unallocated,
2554 },
2555 0b111 => switch (inst.group.Rt) {
2556 no_reg => .{ .sb = inst.sb },
2557 else => .unallocated,
2558 },
2559 };
2560 }
27262561 };
27272562
27282563 /// PSTATE
2729 pub const Pstate = packed struct {
2730 Rt: Register.Encoded,
2731 op2: u3,
2732 CRm: u4,
2733 decoded12: u4 = 0b0100,
2734 op1: u3,
2735 decoded19: u13 = 0b1101010100000,
2564 pub const Pstate = packed union {
2565 group: @This().Group,
2566
2567 pub const Group = packed struct {
2568 Rt: Register.Encoded,
2569 op2: u3,
2570 CRm: u4,
2571 decoded12: u4 = 0b0100,
2572 op1: u3,
2573 decoded19: u13 = 0b1101010100000,
2574 };
2575
2576 /// C6.2.229 MSR (immediate)
2577 pub const Msr = packed struct {
2578 Rt: Register.Encoded = no_reg,
2579 op2: u3,
2580 CRm: u4,
2581 decoded12: u4 = 0b0100,
2582 op1: u3,
2583 decoded19: u13 = 0b1101010100000,
2584 };
2585
2586 /// C6.2.52 CFINV
2587 pub const Cfinv = packed struct {
2588 Rt: Register.Encoded = no_reg,
2589 op2: u3 = 0b000,
2590 CRm: u4 = 0b0000,
2591 decoded12: u4 = 0b0100,
2592 op1: u3 = 0b000,
2593 decoded19: u13 = 0b1101010100000,
2594 };
2595
2596 /// C6.2.400 XAFLAG
2597 pub const Xaflag = packed struct {
2598 Rt: Register.Encoded = no_reg,
2599 op2: u3 = 0b001,
2600 CRm: u4 = 0b0000,
2601 decoded12: u4 = 0b0100,
2602 op1: u3 = 0b000,
2603 decoded19: u13 = 0b1101010100000,
2604 };
2605
2606 /// C6.2.24 AXFLAG
2607 pub const Axflag = packed struct {
2608 Rt: Register.Encoded = no_reg,
2609 op2: u3 = 0b010,
2610 CRm: u4 = 0b0000,
2611 decoded12: u4 = 0b0100,
2612 op1: u3 = 0b000,
2613 decoded19: u13 = 0b1101010100000,
2614 };
2615
2616 pub const Decoded = union(enum) {
2617 unallocated,
2618 cfinv: Cfinv,
2619 xaflag: Xaflag,
2620 axflag: Axflag,
2621 };
2622 pub fn decode(inst: @This()) @This().Decoded {
2623 return switch (inst.group.Rt) {
2624 else => .unallocated,
2625 no_reg => switch (inst.group.op1) {
2626 else => .{ .msr = inst.msr },
2627 0b000 => switch (inst.group.op2) {
2628 else => .{ .msr = inst.msr },
2629 0b000 => .{ .cfinv = inst.cfinv },
2630 0b001 => .{ .xaflag = inst.xaflag },
2631 0b010 => .{ .axflag = inst.axflag },
2632 },
2633 },
2634 };
2635 }
27362636 };
27372637
27382638 /// System with result
......@@ -2965,6 +2865,17 @@ pub const Instruction = packed union {
29652865 b = 0b0,
29662866 bl = 0b1,
29672867 };
2868
2869 pub const Decoded = union(enum) {
2870 b: B,
2871 bl: Bl,
2872 };
2873 pub fn decode(inst: @This()) @This().Decoded {
2874 return switch (inst.group.op) {
2875 .b => .{ .b = inst.b },
2876 .bl => .{ .bl = inst.bl },
2877 };
2878 }
29682879 };
29692880
29702881 /// Compare and branch (immediate)
......@@ -2978,7 +2889,7 @@ pub const Instruction = packed union {
29782889 imm19: i19,
29792890 op: Op,
29802891 decoded25: u6 = 0b011010,
2981 sf: Register.IntegerSize,
2892 sf: Register.GeneralSize,
29822893 };
29832894
29842895 /// C6.2.47 CBZ
......@@ -2987,7 +2898,7 @@ pub const Instruction = packed union {
29872898 imm19: i19,
29882899 op: Op = .cbz,
29892900 decoded25: u6 = 0b011010,
2990 sf: Register.IntegerSize,
2901 sf: Register.GeneralSize,
29912902 };
29922903
29932904 /// C6.2.46 CBNZ
......@@ -2996,13 +2907,24 @@ pub const Instruction = packed union {
29962907 imm19: i19,
29972908 op: Op = .cbnz,
29982909 decoded25: u6 = 0b011010,
2999 sf: Register.IntegerSize,
2910 sf: Register.GeneralSize,
30002911 };
30012912
30022913 pub const Op = enum(u1) {
30032914 cbz = 0b0,
30042915 cbnz = 0b1,
30052916 };
2917
2918 pub const Decoded = union(enum) {
2919 cbz: Cbz,
2920 cbnz: Cbnz,
2921 };
2922 pub fn decode(inst: @This()) @This().Decoded {
2923 return switch (inst.group.op) {
2924 .cbz => .{ .cbz = inst.cbz },
2925 .cbnz => .{ .cbnz = inst.cbnz },
2926 };
2927 }
30062928 };
30072929
30082930 /// Test and branch (immediate)
......@@ -3044,8 +2966,21 @@ pub const Instruction = packed union {
30442966 tbz = 0b0,
30452967 tbnz = 0b1,
30462968 };
2969
2970 pub const Decoded = union(enum) {
2971 tbz: Tbz,
2972 tbnz: Tbnz,
2973 };
2974 pub fn decode(inst: @This()) @This().Decoded {
2975 return switch (inst.group.op) {
2976 .tbz => .{ .tbz = inst.tbz },
2977 .tbnz => .{ .tbnz = inst.tbnz },
2978 };
2979 }
30472980 };
30482981
2982 pub const no_reg: Register.Encoded = Register.Alias.zr.encode(.{});
2983
30492984 pub const Decoded = union(enum) {
30502985 unallocated,
30512986 conditional_branch_immediate: ConditionalBranchImmediate,
......@@ -3168,7 +3103,7 @@ pub const Instruction = packed union {
31683103 decoded24: u2 = 0b00,
31693104 V: bool = false,
31703105 decoded27: u3 = 0b011,
3171 sf: Register.IntegerSize,
3106 sf: Register.GeneralSize,
31723107 opc1: u1 = 0b0,
31733108 };
31743109
......@@ -3241,7 +3176,7 @@ pub const Instruction = packed union {
32413176 decoded24: u2 = 0b01,
32423177 o0: u1,
32433178 decoded27: u3 = 0b011,
3244 size: IntegerSize,
3179 size: Size,
32453180 };
32463181
32473182 /// Load/store no-allocate pair (offset)
......@@ -3304,7 +3239,7 @@ pub const Instruction = packed union {
33043239 V: bool = false,
33053240 decoded27: u3 = 0b101,
33063241 opc0: u1 = 0b0,
3307 sf: Register.IntegerSize,
3242 sf: Register.GeneralSize,
33083243 };
33093244
33103245 /// C6.2.164 LDP
......@@ -3318,7 +3253,7 @@ pub const Instruction = packed union {
33183253 V: bool = false,
33193254 decoded27: u3 = 0b101,
33203255 opc0: u1 = 0b0,
3321 sf: Register.IntegerSize,
3256 sf: Register.GeneralSize,
33223257 };
33233258
33243259 /// C6.2.165 LDPSW
......@@ -3473,7 +3408,7 @@ pub const Instruction = packed union {
34733408 V: bool = false,
34743409 decoded27: u3 = 0b101,
34753410 opc0: u1 = 0b0,
3476 sf: Register.IntegerSize,
3411 sf: Register.GeneralSize,
34773412 };
34783413
34793414 /// C6.2.164 LDP
......@@ -3487,7 +3422,7 @@ pub const Instruction = packed union {
34873422 V: bool = false,
34883423 decoded27: u3 = 0b101,
34893424 opc0: u1 = 0b0,
3490 sf: Register.IntegerSize,
3425 sf: Register.GeneralSize,
34913426 };
34923427
34933428 /// C6.2.165 LDPSW
......@@ -3642,7 +3577,7 @@ pub const Instruction = packed union {
36423577 V: bool = false,
36433578 decoded27: u3 = 0b101,
36443579 opc0: u1 = 0b0,
3645 sf: Register.IntegerSize,
3580 sf: Register.GeneralSize,
36463581 };
36473582
36483583 /// C6.2.164 LDP
......@@ -3656,7 +3591,7 @@ pub const Instruction = packed union {
36563591 V: bool = false,
36573592 decoded27: u3 = 0b101,
36583593 opc0: u1 = 0b0,
3659 sf: Register.IntegerSize,
3594 sf: Register.GeneralSize,
36603595 };
36613596
36623597 /// C6.2.165 LDPSW
......@@ -3806,7 +3741,7 @@ pub const Instruction = packed union {
38063741 decoded24: u2 = 0b00,
38073742 V: bool = false,
38083743 decoded27: u3 = 0b111,
3809 size: IntegerSize,
3744 size: Size,
38103745 };
38113746
38123747 /// C6.2.347 STURB
......@@ -3820,7 +3755,7 @@ pub const Instruction = packed union {
38203755 decoded24: u2 = 0b00,
38213756 V: bool = false,
38223757 decoded27: u3 = 0b111,
3823 size: IntegerSize = .byte,
3758 size: Size = .byte,
38243759 };
38253760
38263761 /// C6.2.203 LDURB
......@@ -3834,7 +3769,7 @@ pub const Instruction = packed union {
38343769 decoded24: u2 = 0b00,
38353770 V: bool = false,
38363771 decoded27: u3 = 0b111,
3837 size: IntegerSize = .byte,
3772 size: Size = .byte,
38383773 };
38393774
38403775 /// C6.2.205 LDURSB
......@@ -3849,7 +3784,7 @@ pub const Instruction = packed union {
38493784 decoded24: u2 = 0b00,
38503785 V: bool = false,
38513786 decoded27: u3 = 0b111,
3852 size: IntegerSize = .byte,
3787 size: Size = .byte,
38533788 };
38543789
38553790 /// C6.2.348 STURH
......@@ -3863,7 +3798,7 @@ pub const Instruction = packed union {
38633798 decoded24: u2 = 0b00,
38643799 V: bool = false,
38653800 decoded27: u3 = 0b111,
3866 size: IntegerSize = .halfword,
3801 size: Size = .halfword,
38673802 };
38683803
38693804 /// C6.2.204 LDURH
......@@ -3877,7 +3812,7 @@ pub const Instruction = packed union {
38773812 decoded24: u2 = 0b00,
38783813 V: bool = false,
38793814 decoded27: u3 = 0b111,
3880 size: IntegerSize = .halfword,
3815 size: Size = .halfword,
38813816 };
38823817
38833818 /// C6.2.206 LDURSH
......@@ -3892,7 +3827,7 @@ pub const Instruction = packed union {
38923827 decoded24: u2 = 0b00,
38933828 V: bool = false,
38943829 decoded27: u3 = 0b111,
3895 size: IntegerSize = .halfword,
3830 size: Size = .halfword,
38963831 };
38973832
38983833 /// C6.2.346 STUR
......@@ -3906,7 +3841,7 @@ pub const Instruction = packed union {
39063841 decoded24: u2 = 0b00,
39073842 V: bool = false,
39083843 decoded27: u3 = 0b111,
3909 sf: Register.IntegerSize,
3844 sf: Register.GeneralSize,
39103845 size1: u1 = 0b1,
39113846 };
39123847
......@@ -3921,7 +3856,7 @@ pub const Instruction = packed union {
39213856 decoded24: u2 = 0b00,
39223857 V: bool = false,
39233858 decoded27: u3 = 0b111,
3924 sf: Register.IntegerSize,
3859 sf: Register.GeneralSize,
39253860 size1: u1 = 0b1,
39263861 };
39273862
......@@ -3936,7 +3871,7 @@ pub const Instruction = packed union {
39363871 decoded24: u2 = 0b00,
39373872 V: bool = false,
39383873 decoded27: u3 = 0b111,
3939 size: IntegerSize = .word,
3874 size: Size = .word,
39403875 };
39413876
39423877 /// C6.2.250 PRFUM
......@@ -3950,7 +3885,7 @@ pub const Instruction = packed union {
39503885 decoded24: u2 = 0b00,
39513886 V: bool = false,
39523887 decoded27: u3 = 0b111,
3953 size: IntegerSize = .doubleword,
3888 size: Size = .doubleword,
39543889 };
39553890
39563891 pub const Decoded = union(enum) {
......@@ -4022,7 +3957,7 @@ pub const Instruction = packed union {
40223957 decoded24: u2 = 0b00,
40233958 V: bool = true,
40243959 decoded27: u3 = 0b111,
4025 size: Size,
3960 size: Vector.Size,
40263961 };
40273962
40283963 /// C7.2.333 STUR (SIMD&FP)
......@@ -4037,7 +3972,7 @@ pub const Instruction = packed union {
40373972 decoded24: u2 = 0b00,
40383973 V: bool = true,
40393974 decoded27: u3 = 0b111,
4040 size: Size,
3975 size: Vector.Size,
40413976 };
40423977
40433978 /// C7.2.194 LDUR (SIMD&FP)
......@@ -4052,21 +3987,20 @@ pub const Instruction = packed union {
40523987 decoded24: u2 = 0b00,
40533988 V: bool = true,
40543989 decoded27: u3 = 0b111,
4055 size: Size,
3990 size: Vector.Size,
40563991 };
40573992
40583993 pub const Opc1 = packed struct {
40593994 encoded: u1,
40603995
4061 pub fn encode(vs: Register.VectorSize) Opc1 {
4062 return .{ .encoded = switch (vs) {
3996 pub fn encode(ss: Register.ScalarSize) Opc1 {
3997 return .{ .encoded = switch (ss) {
40633998 .byte, .half, .single, .double => 0b0,
40643999 .quad => 0b1,
4065 else => unreachable,
40664000 } };
40674001 }
40684002
4069 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {
4003 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
40704004 return switch (enc_size.encoded) {
40714005 0b00 => switch (enc_opc1.encoded) {
40724006 0b0 => .byte,
......@@ -4091,13 +4025,12 @@ pub const Instruction = packed union {
40914025 pub const Size = packed struct {
40924026 encoded: u2,
40934027
4094 pub fn encode(vs: Register.VectorSize) Size {
4095 return .{ .encoded = switch (vs) {
4028 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4029 return .{ .encoded = switch (ss) {
40964030 .byte, .quad => 0b00,
40974031 .half => 0b01,
40984032 .single => 0b10,
40994033 .double => 0b11,
4100 else => unreachable,
41014034 } };
41024035 }
41034036 };
......@@ -4177,7 +4110,7 @@ pub const Instruction = packed union {
41774110 decoded24: u2 = 0b00,
41784111 V: bool = false,
41794112 decoded27: u3 = 0b111,
4180 size: IntegerSize,
4113 size: Size,
41814114 };
41824115
41834116 /// C6.2.324 STRB (immediate)
......@@ -4191,7 +4124,7 @@ pub const Instruction = packed union {
41914124 decoded24: u2 = 0b00,
41924125 V: bool = false,
41934126 decoded27: u3 = 0b111,
4194 size: IntegerSize = .byte,
4127 size: Size = .byte,
41954128 };
41964129
41974130 /// C6.2.170 LDRB (immediate)
......@@ -4205,7 +4138,7 @@ pub const Instruction = packed union {
42054138 decoded24: u2 = 0b00,
42064139 V: bool = false,
42074140 decoded27: u3 = 0b111,
4208 size: IntegerSize = .byte,
4141 size: Size = .byte,
42094142 };
42104143
42114144 /// C6.2.174 LDRSB (immediate)
......@@ -4220,7 +4153,7 @@ pub const Instruction = packed union {
42204153 decoded24: u2 = 0b00,
42214154 V: bool = false,
42224155 decoded27: u3 = 0b111,
4223 size: IntegerSize = .byte,
4156 size: Size = .byte,
42244157 };
42254158
42264159 /// C6.2.326 STRH (immediate)
......@@ -4234,7 +4167,7 @@ pub const Instruction = packed union {
42344167 decoded24: u2 = 0b00,
42354168 V: bool = false,
42364169 decoded27: u3 = 0b111,
4237 size: IntegerSize = .halfword,
4170 size: Size = .halfword,
42384171 };
42394172
42404173 /// C6.2.172 LDRH (immediate)
......@@ -4248,7 +4181,7 @@ pub const Instruction = packed union {
42484181 decoded24: u2 = 0b00,
42494182 V: bool = false,
42504183 decoded27: u3 = 0b111,
4251 size: IntegerSize = .halfword,
4184 size: Size = .halfword,
42524185 };
42534186
42544187 /// C6.2.176 LDRSH (immediate)
......@@ -4263,7 +4196,7 @@ pub const Instruction = packed union {
42634196 decoded24: u2 = 0b00,
42644197 V: bool = false,
42654198 decoded27: u3 = 0b111,
4266 size: IntegerSize = .halfword,
4199 size: Size = .halfword,
42674200 };
42684201
42694202 /// C6.2.322 STR (immediate)
......@@ -4277,7 +4210,7 @@ pub const Instruction = packed union {
42774210 decoded24: u2 = 0b00,
42784211 V: bool = false,
42794212 decoded27: u3 = 0b111,
4280 sf: Register.IntegerSize,
4213 sf: Register.GeneralSize,
42814214 size1: u1 = 0b1,
42824215 };
42834216
......@@ -4292,7 +4225,7 @@ pub const Instruction = packed union {
42924225 decoded24: u2 = 0b00,
42934226 V: bool = false,
42944227 decoded27: u3 = 0b111,
4295 sf: Register.IntegerSize,
4228 sf: Register.GeneralSize,
42964229 size1: u1 = 0b1,
42974230 };
42984231
......@@ -4307,7 +4240,7 @@ pub const Instruction = packed union {
43074240 decoded24: u2 = 0b00,
43084241 V: bool = false,
43094242 decoded27: u3 = 0b111,
4310 size: IntegerSize = .word,
4243 size: Size = .word,
43114244 };
43124245
43134246 pub const Decoded = union(enum) {
......@@ -4377,7 +4310,7 @@ pub const Instruction = packed union {
43774310 decoded24: u2 = 0b00,
43784311 V: bool = true,
43794312 decoded27: u3 = 0b111,
4380 size: Size,
4313 size: Vector.Size,
43814314 };
43824315
43834316 /// C7.2.331 STR (immediate, SIMD&FP)
......@@ -4392,7 +4325,7 @@ pub const Instruction = packed union {
43924325 decoded24: u2 = 0b00,
43934326 V: bool = true,
43944327 decoded27: u3 = 0b111,
4395 size: Size,
4328 size: Vector.Size,
43964329 };
43974330
43984331 /// C7.2.191 LDR (immediate, SIMD&FP)
......@@ -4407,21 +4340,20 @@ pub const Instruction = packed union {
44074340 decoded24: u2 = 0b00,
44084341 V: bool = true,
44094342 decoded27: u3 = 0b111,
4410 size: Size,
4343 size: Vector.Size,
44114344 };
44124345
44134346 pub const Opc1 = packed struct {
44144347 encoded: u1,
44154348
4416 pub fn encode(vs: Register.VectorSize) Opc1 {
4417 return .{ .encoded = switch (vs) {
4349 pub fn encode(ss: Register.ScalarSize) Opc1 {
4350 return .{ .encoded = switch (ss) {
44184351 .byte, .half, .single, .double => 0b0,
44194352 .quad => 0b1,
4420 else => unreachable,
44214353 } };
44224354 }
44234355
4424 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {
4356 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
44254357 return switch (enc_size.encoded) {
44264358 0b00 => switch (enc_opc1.encoded) {
44274359 0b0 => .byte,
......@@ -4446,13 +4378,12 @@ pub const Instruction = packed union {
44464378 pub const Size = packed struct {
44474379 encoded: u2,
44484380
4449 pub fn encode(vs: Register.VectorSize) Size {
4450 return .{ .encoded = switch (vs) {
4381 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4382 return .{ .encoded = switch (ss) {
44514383 .byte, .quad => 0b00,
44524384 .half => 0b01,
44534385 .single => 0b10,
44544386 .double => 0b11,
4455 else => unreachable,
44564387 } };
44574388 }
44584389 };
......@@ -4502,7 +4433,7 @@ pub const Instruction = packed union {
45024433 decoded24: u2 = 0b00,
45034434 V: bool,
45044435 decoded27: u3 = 0b111,
4505 size: IntegerSize,
4436 size: Size,
45064437 };
45074438
45084439 /// Load/store register (immediate pre-indexed)
......@@ -4546,7 +4477,7 @@ pub const Instruction = packed union {
45464477 decoded24: u2 = 0b00,
45474478 V: bool = false,
45484479 decoded27: u3 = 0b111,
4549 size: IntegerSize,
4480 size: Size,
45504481 };
45514482
45524483 /// C6.2.324 STRB (immediate)
......@@ -4560,7 +4491,7 @@ pub const Instruction = packed union {
45604491 decoded24: u2 = 0b00,
45614492 V: bool = false,
45624493 decoded27: u3 = 0b111,
4563 size: IntegerSize = .byte,
4494 size: Size = .byte,
45644495 };
45654496
45664497 /// C6.2.170 LDRB (immediate)
......@@ -4574,7 +4505,7 @@ pub const Instruction = packed union {
45744505 decoded24: u2 = 0b00,
45754506 V: bool = false,
45764507 decoded27: u3 = 0b111,
4577 size: IntegerSize = .byte,
4508 size: Size = .byte,
45784509 };
45794510
45804511 /// C6.2.174 LDRSB (immediate)
......@@ -4589,7 +4520,7 @@ pub const Instruction = packed union {
45894520 decoded24: u2 = 0b00,
45904521 V: bool = false,
45914522 decoded27: u3 = 0b111,
4592 size: IntegerSize = .byte,
4523 size: Size = .byte,
45934524 };
45944525
45954526 /// C6.2.326 STRH (immediate)
......@@ -4603,7 +4534,7 @@ pub const Instruction = packed union {
46034534 decoded24: u2 = 0b00,
46044535 V: bool = false,
46054536 decoded27: u3 = 0b111,
4606 size: IntegerSize = .halfword,
4537 size: Size = .halfword,
46074538 };
46084539
46094540 /// C6.2.172 LDRH (immediate)
......@@ -4617,7 +4548,7 @@ pub const Instruction = packed union {
46174548 decoded24: u2 = 0b00,
46184549 V: bool = false,
46194550 decoded27: u3 = 0b111,
4620 size: IntegerSize = .halfword,
4551 size: Size = .halfword,
46214552 };
46224553
46234554 /// C6.2.176 LDRSH (immediate)
......@@ -4632,7 +4563,7 @@ pub const Instruction = packed union {
46324563 decoded24: u2 = 0b00,
46334564 V: bool = false,
46344565 decoded27: u3 = 0b111,
4635 size: IntegerSize = .halfword,
4566 size: Size = .halfword,
46364567 };
46374568
46384569 /// C6.2.322 STR (immediate)
......@@ -4646,7 +4577,7 @@ pub const Instruction = packed union {
46464577 decoded24: u2 = 0b00,
46474578 V: bool = false,
46484579 decoded27: u3 = 0b111,
4649 sf: Register.IntegerSize,
4580 sf: Register.GeneralSize,
46504581 size1: u1 = 0b1,
46514582 };
46524583
......@@ -4661,7 +4592,7 @@ pub const Instruction = packed union {
46614592 decoded24: u2 = 0b00,
46624593 V: bool = false,
46634594 decoded27: u3 = 0b111,
4664 sf: Register.IntegerSize,
4595 sf: Register.GeneralSize,
46654596 size1: u1 = 0b1,
46664597 };
46674598
......@@ -4676,7 +4607,7 @@ pub const Instruction = packed union {
46764607 decoded24: u2 = 0b00,
46774608 V: bool = false,
46784609 decoded27: u3 = 0b111,
4679 size: IntegerSize = .word,
4610 size: Size = .word,
46804611 };
46814612
46824613 pub const Decoded = union(enum) {
......@@ -4734,7 +4665,7 @@ pub const Instruction = packed union {
47344665 decoded24: u2 = 0b00,
47354666 V: bool = true,
47364667 decoded27: u3 = 0b111,
4737 size: Size,
4668 size: Vector.Size,
47384669 };
47394670
47404671 /// C7.2.331 STR (immediate, SIMD&FP)
......@@ -4749,7 +4680,7 @@ pub const Instruction = packed union {
47494680 decoded24: u2 = 0b00,
47504681 V: bool = true,
47514682 decoded27: u3 = 0b111,
4752 size: Size,
4683 size: Vector.Size,
47534684 };
47544685
47554686 /// C7.2.191 LDR (immediate, SIMD&FP)
......@@ -4764,21 +4695,20 @@ pub const Instruction = packed union {
47644695 decoded24: u2 = 0b00,
47654696 V: bool = true,
47664697 decoded27: u3 = 0b111,
4767 size: Size,
4698 size: Vector.Size,
47684699 };
47694700
47704701 pub const Opc1 = packed struct {
47714702 encoded: u1,
47724703
4773 pub fn encode(vs: Register.VectorSize) Opc1 {
4774 return .{ .encoded = switch (vs) {
4704 pub fn encode(ss: Register.ScalarSize) Opc1 {
4705 return .{ .encoded = switch (ss) {
47754706 .byte, .half, .single, .double => 0b0,
47764707 .quad => 0b1,
4777 else => unreachable,
47784708 } };
47794709 }
47804710
4781 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {
4711 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
47824712 return switch (enc_size.encoded) {
47834713 0b00 => switch (enc_opc1.encoded) {
47844714 0b0 => .byte,
......@@ -4803,13 +4733,12 @@ pub const Instruction = packed union {
48034733 pub const Size = packed struct {
48044734 encoded: u2,
48054735
4806 pub fn encode(vs: Register.VectorSize) Size {
4807 return .{ .encoded = switch (vs) {
4736 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4737 return .{ .encoded = switch (ss) {
48084738 .byte, .quad => 0b00,
48094739 .half => 0b01,
48104740 .single => 0b10,
48114741 .double => 0b11,
4812 else => unreachable,
48134742 } };
48144743 }
48154744 };
......@@ -4894,7 +4823,7 @@ pub const Instruction = packed union {
48944823 decoded24: u2 = 0b00,
48954824 V: bool = false,
48964825 decoded27: u3 = 0b111,
4897 size: IntegerSize,
4826 size: Size,
48984827 };
48994828
49004829 /// C6.2.325 STRB (register)
......@@ -4910,7 +4839,7 @@ pub const Instruction = packed union {
49104839 decoded24: u2 = 0b00,
49114840 V: bool = false,
49124841 decoded27: u3 = 0b111,
4913 size: IntegerSize = .byte,
4842 size: Size = .byte,
49144843 };
49154844
49164845 /// C6.2.171 LDRB (register)
......@@ -4926,7 +4855,7 @@ pub const Instruction = packed union {
49264855 decoded24: u2 = 0b00,
49274856 V: bool = false,
49284857 decoded27: u3 = 0b111,
4929 size: IntegerSize = .byte,
4858 size: Size = .byte,
49304859 };
49314860
49324861 /// C6.2.175 LDRSB (register)
......@@ -4943,7 +4872,7 @@ pub const Instruction = packed union {
49434872 decoded24: u2 = 0b00,
49444873 V: bool = false,
49454874 decoded27: u3 = 0b111,
4946 size: IntegerSize = .byte,
4875 size: Size = .byte,
49474876 };
49484877
49494878 /// C6.2.327 STRH (register)
......@@ -4959,7 +4888,7 @@ pub const Instruction = packed union {
49594888 decoded24: u2 = 0b00,
49604889 V: bool = false,
49614890 decoded27: u3 = 0b111,
4962 size: IntegerSize = .halfword,
4891 size: Size = .halfword,
49634892 };
49644893
49654894 /// C6.2.173 LDRH (register)
......@@ -4975,7 +4904,7 @@ pub const Instruction = packed union {
49754904 decoded24: u2 = 0b00,
49764905 V: bool = false,
49774906 decoded27: u3 = 0b111,
4978 size: IntegerSize = .halfword,
4907 size: Size = .halfword,
49794908 };
49804909
49814910 /// C6.2.177 LDRSH (register)
......@@ -4992,7 +4921,7 @@ pub const Instruction = packed union {
49924921 decoded24: u2 = 0b00,
49934922 V: bool = false,
49944923 decoded27: u3 = 0b111,
4995 size: IntegerSize = .halfword,
4924 size: Size = .halfword,
49964925 };
49974926
49984927 /// C6.2.323 STR (register)
......@@ -5008,7 +4937,7 @@ pub const Instruction = packed union {
50084937 decoded24: u2 = 0b00,
50094938 V: bool = false,
50104939 decoded27: u3 = 0b111,
5011 sf: Register.IntegerSize,
4940 sf: Register.GeneralSize,
50124941 size1: u1 = 0b1,
50134942 };
50144943
......@@ -5025,7 +4954,7 @@ pub const Instruction = packed union {
50254954 decoded24: u2 = 0b00,
50264955 V: bool = false,
50274956 decoded27: u3 = 0b111,
5028 sf: Register.IntegerSize,
4957 sf: Register.GeneralSize,
50294958 size1: u1 = 0b1,
50304959 };
50314960
......@@ -5042,7 +4971,7 @@ pub const Instruction = packed union {
50424971 decoded24: u2 = 0b00,
50434972 V: bool = false,
50444973 decoded27: u3 = 0b111,
5045 size: IntegerSize = .word,
4974 size: Size = .word,
50464975 };
50474976
50484977 /// C6.2.249 PRFM (register)
......@@ -5058,7 +4987,7 @@ pub const Instruction = packed union {
50584987 decoded24: u2 = 0b00,
50594988 V: bool = false,
50604989 decoded27: u3 = 0b111,
5061 size: IntegerSize = .doubleword,
4990 size: Size = .doubleword,
50624991 };
50634992
50644993 pub const Decoded = union(enum) {
......@@ -5131,7 +5060,7 @@ pub const Instruction = packed union {
51315060 decoded24: u2 = 0b00,
51325061 V: bool = true,
51335062 decoded27: u3 = 0b111,
5134 size: Size,
5063 size: Vector.Size,
51355064 };
51365065
51375066 /// C7.2.332 STR (register, SIMD&FP)
......@@ -5148,7 +5077,7 @@ pub const Instruction = packed union {
51485077 decoded24: u2 = 0b00,
51495078 V: bool = true,
51505079 decoded27: u3 = 0b111,
5151 size: Size,
5080 size: Vector.Size,
51525081 };
51535082
51545083 /// C7.2.193 LDR (register, SIMD&FP)
......@@ -5165,21 +5094,20 @@ pub const Instruction = packed union {
51655094 decoded24: u2 = 0b00,
51665095 V: bool = true,
51675096 decoded27: u3 = 0b111,
5168 size: Size,
5097 size: Vector.Size,
51695098 };
51705099
51715100 pub const Opc1 = packed struct {
51725101 encoded: u1,
51735102
5174 pub fn encode(vs: Register.VectorSize) Opc1 {
5175 return .{ .encoded = switch (vs) {
5103 pub fn encode(ss: Register.ScalarSize) Opc1 {
5104 return .{ .encoded = switch (ss) {
51765105 .byte, .half, .single, .double => 0b0,
51775106 .quad => 0b1,
5178 else => unreachable,
51795107 } };
51805108 }
51815109
5182 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {
5110 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
51835111 return switch (enc_size.encoded) {
51845112 0b00 => switch (enc_opc1.encoded) {
51855113 0b0 => .byte,
......@@ -5204,13 +5132,12 @@ pub const Instruction = packed union {
52045132 pub const Size = packed struct {
52055133 encoded: u2,
52065134
5207 pub fn encode(vs: Register.VectorSize) Size {
5208 return .{ .encoded = switch (vs) {
5135 pub fn encode(ss: Register.ScalarSize) Vector.Size {
5136 return .{ .encoded = switch (ss) {
52095137 .byte, .quad => 0b00,
52105138 .half => 0b01,
52115139 .single => 0b10,
52125140 .double => 0b11,
5213 else => unreachable,
52145141 } };
52155142 }
52165143 };
......@@ -5223,7 +5150,7 @@ pub const Instruction = packed union {
52235150 sxtx = 0b111,
52245151 _,
52255152
5226 pub fn sf(option: Option) Register.IntegerSize {
5153 pub fn sf(option: Option) Register.GeneralSize {
52275154 return switch (option) {
52285155 .uxtw, .sxtw => .word,
52295156 .lsl, .sxtx => .doubleword,
......@@ -5291,7 +5218,7 @@ pub const Instruction = packed union {
52915218 decoded24: u2 = 0b01,
52925219 V: bool = false,
52935220 decoded27: u3 = 0b111,
5294 size: IntegerSize,
5221 size: Size,
52955222 };
52965223
52975224 /// C6.2.324 STRB (immediate)
......@@ -5303,7 +5230,7 @@ pub const Instruction = packed union {
53035230 decoded24: u2 = 0b01,
53045231 V: bool = false,
53055232 decoded27: u3 = 0b111,
5306 size: IntegerSize = .byte,
5233 size: Size = .byte,
53075234 };
53085235
53095236 /// C6.2.170 LDRB (immediate)
......@@ -5315,7 +5242,7 @@ pub const Instruction = packed union {
53155242 decoded24: u2 = 0b01,
53165243 V: bool = false,
53175244 decoded27: u3 = 0b111,
5318 size: IntegerSize = .byte,
5245 size: Size = .byte,
53195246 };
53205247
53215248 /// C6.2.174 LDRSB (immediate)
......@@ -5328,7 +5255,7 @@ pub const Instruction = packed union {
53285255 decoded24: u2 = 0b01,
53295256 V: bool = false,
53305257 decoded27: u3 = 0b111,
5331 size: IntegerSize = .byte,
5258 size: Size = .byte,
53325259 };
53335260
53345261 /// C6.2.326 STRH (immediate)
......@@ -5340,7 +5267,7 @@ pub const Instruction = packed union {
53405267 decoded24: u2 = 0b01,
53415268 V: bool = false,
53425269 decoded27: u3 = 0b111,
5343 size: IntegerSize = .halfword,
5270 size: Size = .halfword,
53445271 };
53455272
53465273 /// C6.2.172 LDRH (immediate)
......@@ -5352,7 +5279,7 @@ pub const Instruction = packed union {
53525279 decoded24: u2 = 0b01,
53535280 V: bool = false,
53545281 decoded27: u3 = 0b111,
5355 size: IntegerSize = .halfword,
5282 size: Size = .halfword,
53565283 };
53575284
53585285 /// C6.2.176 LDRSH (immediate)
......@@ -5365,7 +5292,7 @@ pub const Instruction = packed union {
53655292 decoded24: u2 = 0b01,
53665293 V: bool = false,
53675294 decoded27: u3 = 0b111,
5368 size: IntegerSize = .halfword,
5295 size: Size = .halfword,
53695296 };
53705297
53715298 /// C6.2.322 STR (immediate)
......@@ -5377,7 +5304,7 @@ pub const Instruction = packed union {
53775304 decoded24: u2 = 0b01,
53785305 V: bool = false,
53795306 decoded27: u3 = 0b111,
5380 sf: Register.IntegerSize,
5307 sf: Register.GeneralSize,
53815308 size1: u1 = 0b1,
53825309 };
53835310
......@@ -5390,7 +5317,7 @@ pub const Instruction = packed union {
53905317 decoded24: u2 = 0b01,
53915318 V: bool = false,
53925319 decoded27: u3 = 0b111,
5393 sf: Register.IntegerSize,
5320 sf: Register.GeneralSize,
53945321 size1: u1 = 0b1,
53955322 };
53965323
......@@ -5403,7 +5330,7 @@ pub const Instruction = packed union {
54035330 decoded24: u2 = 0b01,
54045331 V: bool = false,
54055332 decoded27: u3 = 0b111,
5406 size: IntegerSize = .word,
5333 size: Size = .word,
54075334 };
54085335
54095336 /// C6.2.247 PRFM (immediate)
......@@ -5415,7 +5342,7 @@ pub const Instruction = packed union {
54155342 decoded24: u2 = 0b01,
54165343 V: bool = false,
54175344 decoded27: u3 = 0b111,
5418 size: IntegerSize = .doubleword,
5345 size: Size = .doubleword,
54195346 };
54205347
54215348 pub const Decoded = union(enum) {
......@@ -5485,7 +5412,7 @@ pub const Instruction = packed union {
54855412 decoded24: u2 = 0b01,
54865413 V: bool = true,
54875414 decoded27: u3 = 0b111,
5488 size: Size,
5415 size: Vector.Size,
54895416 };
54905417
54915418 /// C7.2.331 STR (immediate, SIMD&FP)
......@@ -5498,7 +5425,7 @@ pub const Instruction = packed union {
54985425 decoded24: u2 = 0b01,
54995426 V: bool = true,
55005427 decoded27: u3 = 0b111,
5501 size: Size,
5428 size: Vector.Size,
55025429 };
55035430
55045431 /// C7.2.191 LDR (immediate, SIMD&FP)
......@@ -5511,21 +5438,20 @@ pub const Instruction = packed union {
55115438 decoded24: u2 = 0b01,
55125439 V: bool = true,
55135440 decoded27: u3 = 0b111,
5514 size: Size,
5441 size: Vector.Size,
55155442 };
55165443
55175444 pub const Opc1 = packed struct {
55185445 encoded: u1,
55195446
5520 pub fn encode(vs: Register.VectorSize) Opc1 {
5521 return .{ .encoded = switch (vs) {
5447 pub fn encode(ss: Register.ScalarSize) Opc1 {
5448 return .{ .encoded = switch (ss) {
55225449 .byte, .half, .single, .double => 0b0,
55235450 .quad => 0b1,
5524 else => unreachable,
55255451 } };
55265452 }
55275453
5528 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {
5454 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
55295455 return switch (enc_size.encoded) {
55305456 0b00 => switch (enc_opc1.encoded) {
55315457 0b0 => .byte,
......@@ -5550,13 +5476,12 @@ pub const Instruction = packed union {
55505476 pub const Size = packed struct {
55515477 encoded: u2,
55525478
5553 pub fn encode(vs: Register.VectorSize) Size {
5554 return .{ .encoded = switch (vs) {
5479 pub fn encode(ss: Register.ScalarSize) Vector.Size {
5480 return .{ .encoded = switch (ss) {
55555481 .byte, .quad => 0b00,
55565482 .half => 0b01,
55575483 .single => 0b10,
55585484 .double => 0b11,
5559 else => unreachable,
55605485 } };
55615486 }
55625487 };
......@@ -5600,7 +5525,7 @@ pub const Instruction = packed union {
56005525 load = 0b1,
56015526 };
56025527
5603 pub const IntegerSize = enum(u2) {
5528 pub const Size = enum(u2) {
56045529 byte = 0b00,
56055530 halfword = 0b01,
56065531 word = 0b10,
......@@ -5613,7 +5538,7 @@ pub const Instruction = packed union {
56135538 quad = 0b10,
56145539 _,
56155540
5616 pub fn decode(vs: VectorSize) Register.VectorSize {
5541 pub fn decode(vs: VectorSize) Register.ScalarSize {
56175542 return switch (vs) {
56185543 .single => .single,
56195544 .double => .double,
......@@ -5622,8 +5547,8 @@ pub const Instruction = packed union {
56225547 };
56235548 }
56245549
5625 pub fn encode(vs: Register.VectorSize) VectorSize {
5626 return switch (vs) {
5550 pub fn encode(ss: Register.ScalarSize) VectorSize {
5551 return switch (ss) {
56275552 else => unreachable,
56285553 .single => .single,
56295554 .double => .double,
......@@ -5767,7 +5692,7 @@ pub const Instruction = packed union {
57675692 decoded21: u8 = 0b11010110,
57685693 S: bool,
57695694 decoded30: u1 = 0b0,
5770 sf: Register.IntegerSize,
5695 sf: Register.GeneralSize,
57715696 };
57725697
57735698 /// C6.2.388 UDIV
......@@ -5780,7 +5705,7 @@ pub const Instruction = packed union {
57805705 decoded21: u8 = 0b11010110,
57815706 S: bool = false,
57825707 decoded30: u1 = 0b0,
5783 sf: Register.IntegerSize,
5708 sf: Register.GeneralSize,
57845709 };
57855710
57865711 /// C6.2.270 SDIV
......@@ -5793,7 +5718,7 @@ pub const Instruction = packed union {
57935718 decoded21: u8 = 0b11010110,
57945719 S: bool = false,
57955720 decoded30: u1 = 0b0,
5796 sf: Register.IntegerSize,
5721 sf: Register.GeneralSize,
57975722 };
57985723
57995724 /// C6.2.214 LSLV
......@@ -5806,7 +5731,7 @@ pub const Instruction = packed union {
58065731 decoded21: u8 = 0b11010110,
58075732 S: bool = false,
58085733 decoded30: u1 = 0b0,
5809 sf: Register.IntegerSize,
5734 sf: Register.GeneralSize,
58105735 };
58115736
58125737 /// C6.2.217 LSRV
......@@ -5819,7 +5744,7 @@ pub const Instruction = packed union {
58195744 decoded21: u8 = 0b11010110,
58205745 S: bool = false,
58215746 decoded30: u1 = 0b0,
5822 sf: Register.IntegerSize,
5747 sf: Register.GeneralSize,
58235748 };
58245749
58255750 /// C6.2.18 ASRV
......@@ -5832,7 +5757,7 @@ pub const Instruction = packed union {
58325757 decoded21: u8 = 0b11010110,
58335758 S: bool = false,
58345759 decoded30: u1 = 0b0,
5835 sf: Register.IntegerSize,
5760 sf: Register.GeneralSize,
58365761 };
58375762
58385763 /// C6.2.263 RORV
......@@ -5845,7 +5770,7 @@ pub const Instruction = packed union {
58455770 decoded21: u8 = 0b11010110,
58465771 S: bool = false,
58475772 decoded30: u1 = 0b0,
5848 sf: Register.IntegerSize,
5773 sf: Register.GeneralSize,
58495774 };
58505775
58515776 pub const DivOp = enum(u1) {
......@@ -5903,7 +5828,7 @@ pub const Instruction = packed union {
59035828 decoded21: u8 = 0b11010110,
59045829 S: bool,
59055830 decoded30: u1 = 0b1,
5906 sf: Register.IntegerSize,
5831 sf: Register.GeneralSize,
59075832 };
59085833
59095834 /// C6.2.253 RBIT
......@@ -5916,7 +5841,7 @@ pub const Instruction = packed union {
59165841 decoded21: u8 = 0b11010110,
59175842 S: bool = false,
59185843 decoded30: u1 = 0b1,
5919 sf: Register.IntegerSize,
5844 sf: Register.GeneralSize,
59205845 };
59215846
59225847 /// C6.2.257 REV16
......@@ -5929,7 +5854,7 @@ pub const Instruction = packed union {
59295854 decoded21: u8 = 0b11010110,
59305855 S: bool = false,
59315856 decoded30: u1 = 0b1,
5932 sf: Register.IntegerSize,
5857 sf: Register.GeneralSize,
59335858 };
59345859
59355860 /// C6.2.258 REV32
......@@ -5942,21 +5867,21 @@ pub const Instruction = packed union {
59425867 decoded21: u8 = 0b11010110,
59435868 S: bool = false,
59445869 decoded30: u1 = 0b1,
5945 sf: Register.IntegerSize = .doubleword,
5870 sf: Register.GeneralSize = .doubleword,
59465871 };
59475872
59485873 /// C6.2.256 REV
59495874 pub const Rev = packed struct {
59505875 Rd: Register.Encoded,
59515876 Rn: Register.Encoded,
5952 opc0: Register.IntegerSize,
5877 opc0: Register.GeneralSize,
59535878 opc1: u1 = 0b1,
59545879 decoded12: u4 = 0b0000,
59555880 decoded16: u5 = 0b00000,
59565881 decoded21: u8 = 0b11010110,
59575882 S: bool = false,
59585883 decoded30: u1 = 0b1,
5959 sf: Register.IntegerSize,
5884 sf: Register.GeneralSize,
59605885 };
59615886
59625887 /// C6.2.58 CLZ
......@@ -5969,7 +5894,7 @@ pub const Instruction = packed union {
59695894 decoded21: u8 = 0b11010110,
59705895 S: bool = false,
59715896 decoded30: u1 = 0b1,
5972 sf: Register.IntegerSize,
5897 sf: Register.GeneralSize,
59735898 };
59745899
59755900 /// C6.2.57 CLS
......@@ -5982,7 +5907,7 @@ pub const Instruction = packed union {
59825907 decoded21: u8 = 0b11010110,
59835908 S: bool = false,
59845909 decoded30: u1 = 0b1,
5985 sf: Register.IntegerSize,
5910 sf: Register.GeneralSize,
59865911 };
59875912
59885913 pub const Decoded = union(enum) {
......@@ -6040,7 +5965,7 @@ pub const Instruction = packed union {
60405965 shift: Shift.Op,
60415966 decoded24: u5 = 0b01010,
60425967 opc: LogicalOpc,
6043 sf: Register.IntegerSize,
5968 sf: Register.GeneralSize,
60445969 };
60455970
60465971 /// C6.2.13 AND (shifted register)
......@@ -6053,7 +5978,7 @@ pub const Instruction = packed union {
60535978 shift: Shift.Op,
60545979 decoded24: u5 = 0b01010,
60555980 opc: LogicalOpc = .@"and",
6056 sf: Register.IntegerSize,
5981 sf: Register.GeneralSize,
60575982 };
60585983
60595984 /// C6.2.32 BIC (shifted register)
......@@ -6066,7 +5991,7 @@ pub const Instruction = packed union {
60665991 shift: Shift.Op,
60675992 decoded24: u5 = 0b01010,
60685993 opc: LogicalOpc = .@"and",
6069 sf: Register.IntegerSize,
5994 sf: Register.GeneralSize,
60705995 };
60715996
60725997 /// C6.2.241 ORR (shifted register)
......@@ -6079,7 +6004,7 @@ pub const Instruction = packed union {
60796004 shift: Shift.Op,
60806005 decoded24: u5 = 0b01010,
60816006 opc: LogicalOpc = .orr,
6082 sf: Register.IntegerSize,
6007 sf: Register.GeneralSize,
60836008 };
60846009
60856010 /// C6.2.239 ORN (shifted register)
......@@ -6092,7 +6017,7 @@ pub const Instruction = packed union {
60926017 shift: Shift.Op,
60936018 decoded24: u5 = 0b01010,
60946019 opc: LogicalOpc = .orr,
6095 sf: Register.IntegerSize,
6020 sf: Register.GeneralSize,
60966021 };
60976022
60986023 /// C6.2.120 EOR (shifted register)
......@@ -6105,7 +6030,7 @@ pub const Instruction = packed union {
61056030 shift: Shift.Op,
61066031 decoded24: u5 = 0b01010,
61076032 opc: LogicalOpc = .eor,
6108 sf: Register.IntegerSize,
6033 sf: Register.GeneralSize,
61096034 };
61106035
61116036 /// C6.2.118 EON (shifted register)
......@@ -6118,7 +6043,7 @@ pub const Instruction = packed union {
61186043 shift: Shift.Op,
61196044 decoded24: u5 = 0b01010,
61206045 opc: LogicalOpc = .eor,
6121 sf: Register.IntegerSize,
6046 sf: Register.GeneralSize,
61226047 };
61236048
61246049 /// C6.2.15 ANDS (shifted register)
......@@ -6131,7 +6056,7 @@ pub const Instruction = packed union {
61316056 shift: Shift.Op,
61326057 decoded24: u5 = 0b01010,
61336058 opc: LogicalOpc = .ands,
6134 sf: Register.IntegerSize,
6059 sf: Register.GeneralSize,
61356060 };
61366061
61376062 /// C6.2.33 BICS (shifted register)
......@@ -6144,7 +6069,7 @@ pub const Instruction = packed union {
61446069 shift: Shift.Op,
61456070 decoded24: u5 = 0b01010,
61466071 opc: LogicalOpc = .ands,
6147 sf: Register.IntegerSize,
6072 sf: Register.GeneralSize,
61486073 };
61496074
61506075 pub const Decoded = union(enum) {
......@@ -6200,7 +6125,7 @@ pub const Instruction = packed union {
62006125 decoded24: u5 = 0b01011,
62016126 S: bool,
62026127 op: AddSubtractOp,
6203 sf: Register.IntegerSize,
6128 sf: Register.GeneralSize,
62046129 };
62056130
62066131 /// C6.2.5 ADD (shifted register)
......@@ -6214,7 +6139,7 @@ pub const Instruction = packed union {
62146139 decoded24: u5 = 0b01011,
62156140 S: bool = false,
62166141 op: AddSubtractOp = .add,
6217 sf: Register.IntegerSize,
6142 sf: Register.GeneralSize,
62186143 };
62196144
62206145 /// C6.2.9 ADDS (shifted register)
......@@ -6228,7 +6153,7 @@ pub const Instruction = packed union {
62286153 decoded24: u5 = 0b01011,
62296154 S: bool = true,
62306155 op: AddSubtractOp = .add,
6231 sf: Register.IntegerSize,
6156 sf: Register.GeneralSize,
62326157 };
62336158
62346159 /// C6.2.5 SUB (shifted register)
......@@ -6242,7 +6167,7 @@ pub const Instruction = packed union {
62426167 decoded24: u5 = 0b01011,
62436168 S: bool = false,
62446169 op: AddSubtractOp = .sub,
6245 sf: Register.IntegerSize,
6170 sf: Register.GeneralSize,
62466171 };
62476172
62486173 /// C6.2.9 SUBS (shifted register)
......@@ -6256,7 +6181,7 @@ pub const Instruction = packed union {
62566181 decoded24: u5 = 0b01011,
62576182 S: bool = true,
62586183 op: AddSubtractOp = .sub,
6259 sf: Register.IntegerSize,
6184 sf: Register.GeneralSize,
62606185 };
62616186
62626187 pub const Decoded = union(enum) {
......@@ -6304,7 +6229,7 @@ pub const Instruction = packed union {
63046229 decoded24: u5 = 0b01011,
63056230 S: bool,
63066231 op: AddSubtractOp,
6307 sf: Register.IntegerSize,
6232 sf: Register.GeneralSize,
63086233 };
63096234
63106235 /// C6.2.3 ADD (extended register)
......@@ -6319,7 +6244,7 @@ pub const Instruction = packed union {
63196244 decoded24: u5 = 0b01011,
63206245 S: bool = false,
63216246 op: AddSubtractOp = .add,
6322 sf: Register.IntegerSize,
6247 sf: Register.GeneralSize,
63236248 };
63246249
63256250 /// C6.2.7 ADDS (extended register)
......@@ -6334,7 +6259,7 @@ pub const Instruction = packed union {
63346259 decoded24: u5 = 0b01011,
63356260 S: bool = true,
63366261 op: AddSubtractOp = .add,
6337 sf: Register.IntegerSize,
6262 sf: Register.GeneralSize,
63386263 };
63396264
63406265 /// C6.2.356 SUB (extended register)
......@@ -6349,7 +6274,7 @@ pub const Instruction = packed union {
63496274 decoded24: u5 = 0b01011,
63506275 S: bool = false,
63516276 op: AddSubtractOp = .sub,
6352 sf: Register.IntegerSize,
6277 sf: Register.GeneralSize,
63536278 };
63546279
63556280 /// C6.2.362 SUBS (extended register)
......@@ -6364,7 +6289,7 @@ pub const Instruction = packed union {
63646289 decoded24: u5 = 0b01011,
63656290 S: bool = true,
63666291 op: AddSubtractOp = .sub,
6367 sf: Register.IntegerSize,
6292 sf: Register.GeneralSize,
63686293 };
63696294
63706295 pub const Option = enum(u3) {
......@@ -6377,7 +6302,7 @@ pub const Instruction = packed union {
63776302 sxtw = 0b110,
63786303 sxtx = 0b111,
63796304
6380 pub fn sf(option: Option) Register.IntegerSize {
6305 pub fn sf(option: Option) Register.GeneralSize {
63816306 return switch (option) {
63826307 .uxtb, .uxth, .uxtw, .sxtb, .sxth, .sxtw => .word,
63836308 .uxtx, .sxtx => .doubleword,
......@@ -6443,7 +6368,7 @@ pub const Instruction = packed union {
64436368 decoded21: u8 = 0b11010000,
64446369 S: bool,
64456370 op: Op,
6446 sf: Register.IntegerSize,
6371 sf: Register.GeneralSize,
64476372 };
64486373
64496374 /// C6.2.1 ADC
......@@ -6455,7 +6380,7 @@ pub const Instruction = packed union {
64556380 decoded21: u8 = 0b11010000,
64566381 S: bool = false,
64576382 op: Op = .adc,
6458 sf: Register.IntegerSize,
6383 sf: Register.GeneralSize,
64596384 };
64606385
64616386 /// C6.2.2 ADCS
......@@ -6467,7 +6392,7 @@ pub const Instruction = packed union {
64676392 decoded21: u8 = 0b11010000,
64686393 S: bool = true,
64696394 op: Op = .adc,
6470 sf: Register.IntegerSize,
6395 sf: Register.GeneralSize,
64716396 };
64726397
64736398 /// C6.2.265 SBC
......@@ -6479,7 +6404,7 @@ pub const Instruction = packed union {
64796404 decoded21: u8 = 0b11010000,
64806405 S: bool = false,
64816406 op: Op = .sbc,
6482 sf: Register.IntegerSize,
6407 sf: Register.GeneralSize,
64836408 };
64846409
64856410 /// C6.2.266 SBCS
......@@ -6491,7 +6416,7 @@ pub const Instruction = packed union {
64916416 decoded21: u8 = 0b11010000,
64926417 S: bool = true,
64936418 op: Op = .sbc,
6494 sf: Register.IntegerSize,
6419 sf: Register.GeneralSize,
64956420 };
64966421
64976422 pub const Op = enum(u1) {
......@@ -6532,7 +6457,7 @@ pub const Instruction = packed union {
65326457 decoded21: u8 = 0b11010000,
65336458 S: bool,
65346459 op: u1,
6535 sf: Register.IntegerSize,
6460 sf: Register.GeneralSize,
65366461 };
65376462 };
65386463
......@@ -6553,7 +6478,7 @@ pub const Instruction = packed union {
65536478 decoded21: u8 = 0b11010000,
65546479 S: bool,
65556480 op: u1,
6556 sf: Register.IntegerSize,
6481 sf: Register.GeneralSize,
65576482 };
65586483 };
65596484
......@@ -6574,7 +6499,7 @@ pub const Instruction = packed union {
65746499 decoded21: u8 = 0b11010010,
65756500 S: bool,
65766501 op: Op,
6577 sf: Register.IntegerSize,
6502 sf: Register.GeneralSize,
65786503 };
65796504
65806505 /// C6.2.49 CCMN (register)
......@@ -6589,7 +6514,7 @@ pub const Instruction = packed union {
65896514 decoded21: u8 = 0b11010010,
65906515 S: bool = true,
65916516 op: Op = .ccmn,
6592 sf: Register.IntegerSize,
6517 sf: Register.GeneralSize,
65936518 };
65946519
65956520 /// C6.2.51 CCMP (register)
......@@ -6604,7 +6529,7 @@ pub const Instruction = packed union {
66046529 decoded21: u8 = 0b11010010,
66056530 S: bool = true,
66066531 op: Op = .ccmp,
6607 sf: Register.IntegerSize,
6532 sf: Register.GeneralSize,
66086533 };
66096534
66106535 pub const Op = enum(u1) {
......@@ -6630,7 +6555,7 @@ pub const Instruction = packed union {
66306555 decoded21: u8 = 0b11010010,
66316556 S: bool,
66326557 op: Op,
6633 sf: Register.IntegerSize,
6558 sf: Register.GeneralSize,
66346559 };
66356560
66366561 /// C6.2.48 CCMN (immediate)
......@@ -6645,7 +6570,7 @@ pub const Instruction = packed union {
66456570 decoded21: u8 = 0b11010010,
66466571 S: bool = true,
66476572 op: Op = .ccmn,
6648 sf: Register.IntegerSize,
6573 sf: Register.GeneralSize,
66496574 };
66506575
66516576 /// C6.2.50 CCMP (immediate)
......@@ -6660,7 +6585,7 @@ pub const Instruction = packed union {
66606585 decoded21: u8 = 0b11010010,
66616586 S: bool = true,
66626587 op: Op = .ccmp,
6663 sf: Register.IntegerSize,
6588 sf: Register.GeneralSize,
66646589 };
66656590
66666591 pub const Op = enum(u1) {
......@@ -6686,7 +6611,7 @@ pub const Instruction = packed union {
66866611 decoded21: u8 = 0b11010100,
66876612 S: bool,
66886613 op: u1,
6689 sf: Register.IntegerSize,
6614 sf: Register.GeneralSize,
66906615 };
66916616
66926617 /// C6.2.103 CSEL
......@@ -6699,7 +6624,7 @@ pub const Instruction = packed union {
66996624 decoded21: u8 = 0b11010100,
67006625 S: bool = false,
67016626 op: u1 = 0b0,
6702 sf: Register.IntegerSize,
6627 sf: Register.GeneralSize,
67036628 };
67046629
67056630 /// C6.2.106 CSINC
......@@ -6712,7 +6637,7 @@ pub const Instruction = packed union {
67126637 decoded21: u8 = 0b11010100,
67136638 S: bool = false,
67146639 op: u1 = 0b0,
6715 sf: Register.IntegerSize,
6640 sf: Register.GeneralSize,
67166641 };
67176642
67186643 /// C6.2.107 CSINV
......@@ -6725,7 +6650,7 @@ pub const Instruction = packed union {
67256650 decoded21: u8 = 0b11010100,
67266651 S: bool = false,
67276652 op: u1 = 0b1,
6728 sf: Register.IntegerSize,
6653 sf: Register.GeneralSize,
67296654 };
67306655
67316656 /// C6.2.108 CSNEG
......@@ -6738,7 +6663,7 @@ pub const Instruction = packed union {
67386663 decoded21: u8 = 0b11010100,
67396664 S: bool = false,
67406665 op: u1 = 0b1,
6741 sf: Register.IntegerSize,
6666 sf: Register.GeneralSize,
67426667 };
67436668
67446669 pub const Decoded = union(enum) {
......@@ -6788,7 +6713,7 @@ pub const Instruction = packed union {
67886713 op31: u3,
67896714 decoded24: u5 = 0b11011,
67906715 op54: u2,
6791 sf: Register.IntegerSize,
6716 sf: Register.GeneralSize,
67926717 };
67936718
67946719 /// C6.2.218 MADD
......@@ -6801,7 +6726,7 @@ pub const Instruction = packed union {
68016726 op31: u3 = 0b000,
68026727 decoded24: u5 = 0b11011,
68036728 op54: u2 = 0b00,
6804 sf: Register.IntegerSize,
6729 sf: Register.GeneralSize,
68056730 };
68066731
68076732 /// C6.2.231 MSUB
......@@ -6814,7 +6739,7 @@ pub const Instruction = packed union {
68146739 op31: u3 = 0b000,
68156740 decoded24: u5 = 0b11011,
68166741 op54: u2 = 0b00,
6817 sf: Register.IntegerSize,
6742 sf: Register.GeneralSize,
68186743 };
68196744
68206745 /// C6.2.282 SMADDL
......@@ -6828,7 +6753,7 @@ pub const Instruction = packed union {
68286753 U: std.builtin.Signedness = .signed,
68296754 decoded24: u5 = 0b11011,
68306755 op54: u2 = 0b00,
6831 sf: Register.IntegerSize = .doubleword,
6756 sf: Register.GeneralSize = .doubleword,
68326757 };
68336758
68346759 /// C6.2.287 SMSUBL
......@@ -6842,21 +6767,21 @@ pub const Instruction = packed union {
68426767 U: std.builtin.Signedness = .signed,
68436768 decoded24: u5 = 0b11011,
68446769 op54: u2 = 0b00,
6845 sf: Register.IntegerSize = .doubleword,
6770 sf: Register.GeneralSize = .doubleword,
68466771 };
68476772
68486773 /// C6.2.288 SMULH
68496774 pub const Smulh = packed struct {
68506775 Rd: Register.Encoded,
68516776 Rn: Register.Encoded,
6852 Ra: Register.Encoded = @enumFromInt(0b11111),
6777 Ra: Register.Encoded = Register.Alias.zr.encode(.{}),
68536778 o0: AddSubtractOp = .add,
68546779 Rm: Register.Encoded,
68556780 op21: u2 = 0b10,
68566781 U: std.builtin.Signedness = .signed,
68576782 decoded24: u5 = 0b11011,
68586783 op54: u2 = 0b00,
6859 sf: Register.IntegerSize = .doubleword,
6784 sf: Register.GeneralSize = .doubleword,
68606785 };
68616786
68626787 /// C6.2.389 UMADDL
......@@ -6870,7 +6795,7 @@ pub const Instruction = packed union {
68706795 U: std.builtin.Signedness = .unsigned,
68716796 decoded24: u5 = 0b11011,
68726797 op54: u2 = 0b00,
6873 sf: Register.IntegerSize = .doubleword,
6798 sf: Register.GeneralSize = .doubleword,
68746799 };
68756800
68766801 /// C6.2.391 UMSUBL
......@@ -6884,21 +6809,21 @@ pub const Instruction = packed union {
68846809 U: std.builtin.Signedness = .unsigned,
68856810 decoded24: u5 = 0b11011,
68866811 op54: u2 = 0b00,
6887 sf: Register.IntegerSize = .doubleword,
6812 sf: Register.GeneralSize = .doubleword,
68886813 };
68896814
68906815 /// C6.2.392 UMULH
68916816 pub const Umulh = packed struct {
68926817 Rd: Register.Encoded,
68936818 Rn: Register.Encoded,
6894 Ra: Register.Encoded = @enumFromInt(0b11111),
6819 Ra: Register.Encoded = Register.Alias.zr.encode(.{}),
68956820 o0: AddSubtractOp = .add,
68966821 Rm: Register.Encoded,
68976822 op21: u2 = 0b10,
68986823 U: std.builtin.Signedness = .unsigned,
68996824 decoded24: u5 = 0b11011,
69006825 op54: u2 = 0b00,
6901 sf: Register.IntegerSize = .doubleword,
6826 sf: Register.GeneralSize = .doubleword,
69026827 };
69036828
69046829 pub const Decoded = union(enum) {
......@@ -6965,8 +6890,6 @@ pub const Instruction = packed union {
69656890 pub const none: Shift = .{ .lsl = 0 };
69666891 };
69676892
6968 pub const Nzcv = packed struct { v: bool, c: bool, z: bool, n: bool };
6969
69706893 pub const Decoded = union(enum) {
69716894 unallocated,
69726895 data_processing_two_source: DataProcessingTwoSource,
......@@ -7027,10 +6950,12 @@ pub const Instruction = packed union {
70276950 simd_across_lanes: SimdAcrossLanes,
70286951 simd_three_same: SimdThreeSame,
70296952 simd_modified_immediate: SimdModifiedImmediate,
6953 convert_float_fixed: ConvertFloatFixed,
70306954 convert_float_integer: ConvertFloatInteger,
70316955 float_data_processing_one_source: FloatDataProcessingOneSource,
70326956 float_compare: FloatCompare,
70336957 float_immediate: FloatImmediate,
6958 float_conditional_compare: FloatConditionalCompare,
70346959 float_data_processing_two_source: FloatDataProcessingTwoSource,
70356960 float_conditional_select: FloatConditionalSelect,
70366961 float_data_processing_three_source: FloatDataProcessingThreeSource,
......@@ -7385,22 +7310,86 @@ pub const Instruction = packed union {
73857310 U: std.builtin.Signedness = .unsigned,
73867311 decoded30: u2 = 0b01,
73877312 };
7388 };
73897313
7390 /// Advanced SIMD scalar two-register miscellaneous
7391 pub const SimdScalarTwoRegisterMiscellaneous = packed union {
7392 group: @This().Group,
7393 suqadd: Suqadd,
7394 sqabs: Sqabs,
7395 cmgt: Cmgt,
7396 cmeq: Cmeq,
7397 cmlt: Cmlt,
7398 abs: Abs,
7399 sqxtn: Sqxtn,
7400 fcvtns: Fcvtns,
7401 fcvtms: Fcvtms,
7402 fcvtas: Fcvtas,
7403 scvtf: Scvtf,
7314 pub const Decoded = union(enum) {
7315 unallocated,
7316 fcvtns: Fcvtns,
7317 fcvtms: Fcvtms,
7318 fcvtas: Fcvtas,
7319 scvtf: Scvtf,
7320 fcmgt: Fcmgt,
7321 fcmeq: Fcmeq,
7322 fcmlt: Fcmlt,
7323 fcvtps: Fcvtps,
7324 fcvtzs: Fcvtzs,
7325 frecpe: Frecpe,
7326 frecpx: Frecpx,
7327 fcvtnu: Fcvtnu,
7328 fcvtmu: Fcvtmu,
7329 fcvtau: Fcvtau,
7330 ucvtf: Ucvtf,
7331 fcmge: Fcmge,
7332 fcmle: Fcmle,
7333 fcvtpu: Fcvtpu,
7334 fcvtzu: Fcvtzu,
7335 frsqrte: Frsqrte,
7336 };
7337 pub fn decode(inst: @This()) @This().Decoded {
7338 return switch (inst.group.U) {
7339 .signed => switch (inst.group.a) {
7340 0b0 => switch (inst.group.opcode) {
7341 else => .unallocated,
7342 0b11010 => .{ .fcvtns = inst.fcvtns },
7343 0b11011 => .{ .fcvtms = inst.fcvtms },
7344 0b11100 => .{ .fcvtas = inst.fcvtas },
7345 0b11101 => .{ .scvtf = inst.scvtf },
7346 },
7347 0b1 => switch (inst.group.opcode) {
7348 else => .unallocated,
7349 0b01100 => .{ .fcmgt = inst.fcmgt },
7350 0b01101 => .{ .fcmeq = inst.fcmeq },
7351 0b01110 => .{ .fcmlt = inst.fcmlt },
7352 0b11010 => .{ .fcvtps = inst.fcvtps },
7353 0b11011 => .{ .fcvtzs = inst.fcvtzs },
7354 0b11101 => .{ .frecpe = inst.frecpe },
7355 0b11111 => .{ .frecpx = inst.frecpx },
7356 },
7357 },
7358 .unsigned => switch (inst.group.a) {
7359 0b0 => switch (inst.group.opcode) {
7360 else => .unallocated,
7361 0b11010 => .{ .fcvtnu = inst.fcvtnu },
7362 0b11011 => .{ .fcvtmu = inst.fcvtmu },
7363 0b11100 => .{ .fcvtau = inst.fcvtau },
7364 0b11101 => .{ .ucvtf = inst.ucvtf },
7365 },
7366 0b1 => switch (inst.group.opcode) {
7367 else => .unallocated,
7368 0b01100 => .{ .fcmge = inst.fcmge },
7369 0b01101 => .{ .fcmle = inst.fcmle },
7370 0b11010 => .{ .fcvtpu = inst.fcvtpu },
7371 0b11011 => .{ .fcvtzu = inst.fcvtzu },
7372 0b11101 => .{ .frsqrte = inst.frsqrte },
7373 },
7374 },
7375 };
7376 }
7377 };
7378
7379 /// Advanced SIMD scalar two-register miscellaneous
7380 pub const SimdScalarTwoRegisterMiscellaneous = packed union {
7381 group: @This().Group,
7382 suqadd: Suqadd,
7383 sqabs: Sqabs,
7384 cmgt: Cmgt,
7385 cmeq: Cmeq,
7386 cmlt: Cmlt,
7387 abs: Abs,
7388 sqxtn: Sqxtn,
7389 fcvtns: Fcvtns,
7390 fcvtms: Fcvtms,
7391 fcvtas: Fcvtas,
7392 scvtf: Scvtf,
74047393 fcmgt: Fcmgt,
74057394 fcmeq: Fcmeq,
74067395 fcmlt: Fcmlt,
......@@ -7913,6 +7902,129 @@ pub const Instruction = packed union {
79137902 U: std.builtin.Signedness = .unsigned,
79147903 decoded30: u2 = 0b01,
79157904 };
7905
7906 pub const Decoded = union(enum) {
7907 unallocated,
7908 suqadd: Suqadd,
7909 sqabs: Sqabs,
7910 cmgt: Cmgt,
7911 cmeq: Cmeq,
7912 cmlt: Cmlt,
7913 abs: Abs,
7914 sqxtn: Sqxtn,
7915 fcvtns: Fcvtns,
7916 fcvtms: Fcvtms,
7917 fcvtas: Fcvtas,
7918 scvtf: Scvtf,
7919 fcmgt: Fcmgt,
7920 fcmeq: Fcmeq,
7921 fcmlt: Fcmlt,
7922 fcvtps: Fcvtps,
7923 fcvtzs: Fcvtzs,
7924 frecpe: Frecpe,
7925 frecpx: Frecpx,
7926 usqadd: Usqadd,
7927 sqneg: Sqneg,
7928 cmge: Cmge,
7929 cmle: Cmle,
7930 neg: Neg,
7931 sqxtun: Sqxtun,
7932 uqxtn: Uqxtn,
7933 fcvtxn: Fcvtxn,
7934 fcvtnu: Fcvtnu,
7935 fcvtmu: Fcvtmu,
7936 fcvtau: Fcvtau,
7937 ucvtf: Ucvtf,
7938 fcmge: Fcmge,
7939 fcmle: Fcmle,
7940 fcvtpu: Fcvtpu,
7941 fcvtzu: Fcvtzu,
7942 frsqrte: Frsqrte,
7943 };
7944 pub fn decode(inst: @This()) @This().Decoded {
7945 return switch (inst.group.U) {
7946 .signed => switch (inst.group.opcode) {
7947 else => .unallocated,
7948 0b00011 => .{ .suqadd = inst.suqadd },
7949 0b00111 => .{ .sqabs = inst.sqabs },
7950 0b01000 => .{ .cmgt = inst.cmgt },
7951 0b01001 => .{ .cmeq = inst.cmeq },
7952 0b01010 => .{ .cmlt = inst.cmlt },
7953 0b01011 => .{ .abs = inst.abs },
7954 0b10100 => .{ .sqxtn = inst.sqxtn },
7955 0b11010 => switch (inst.group.size) {
7956 .byte, .half => .{ .fcvtns = inst.fcvtns },
7957 .single, .double => .{ .fcvtps = inst.fcvtps },
7958 },
7959 0b11011 => switch (inst.group.size) {
7960 .byte, .half => .{ .fcvtms = inst.fcvtms },
7961 .single, .double => .{ .fcvtzs = inst.fcvtzs },
7962 },
7963 0b11100 => switch (inst.group.size) {
7964 .byte, .half => .{ .fcvtas = inst.fcvtas },
7965 .single, .double => .unallocated,
7966 },
7967 0b11101 => switch (inst.group.size) {
7968 .byte, .half => .{ .scvtf = inst.scvtf },
7969 .single, .double => .{ .frecpe = inst.frecpe },
7970 },
7971 0b01100 => switch (inst.group.size) {
7972 .byte, .half => .unallocated,
7973 .single, .double => .{ .fcmgt = inst.fcmgt },
7974 },
7975 0b01101 => switch (inst.group.size) {
7976 .byte, .half => .unallocated,
7977 .single, .double => .{ .fcmeq = inst.fcmeq },
7978 },
7979 0b01110 => switch (inst.group.size) {
7980 .byte, .half => .unallocated,
7981 .single, .double => .{ .fcmlt = inst.fcmlt },
7982 },
7983 0b11111 => switch (inst.group.size) {
7984 .byte, .half => .unallocated,
7985 .single, .double => .{ .frecpx = inst.frecpx },
7986 },
7987 },
7988 .unsigned => switch (inst.group.opcode) {
7989 else => .unallocated,
7990 0b00011 => .{ .usqadd = inst.usqadd },
7991 0b00111 => .{ .sqneg = inst.sqneg },
7992 0b01000 => .{ .cmge = inst.cmge },
7993 0b01001 => .{ .cmle = inst.cmle },
7994 0b01011 => .{ .neg = inst.neg },
7995 0b10010 => .{ .sqxtun = inst.sqxtun },
7996 0b10100 => .{ .uqxtn = inst.uqxtn },
7997 0b10110 => switch (inst.group.size) {
7998 .byte, .half => .{ .fcvtxn = inst.fcvtxn },
7999 .single, .double => .unallocated,
8000 },
8001 0b11010 => switch (inst.group.size) {
8002 .byte, .half => .{ .fcvtnu = inst.fcvtnu },
8003 .single, .double => .{ .fcvtpu = inst.fcvtpu },
8004 },
8005 0b11011 => switch (inst.group.size) {
8006 .byte, .half => .{ .fcvtmu = inst.fcvtmu },
8007 .single, .double => .{ .fcvtzu = inst.fcvtzu },
8008 },
8009 0b11100 => switch (inst.group.size) {
8010 .byte, .half => .{ .fcvtau = inst.fcvtau },
8011 .single, .double => .unallocated,
8012 },
8013 0b11101 => switch (inst.group.size) {
8014 .byte, .half => .{ .ucvtf = inst.ucvtf },
8015 .single, .double => .{ .frsqrte = inst.frsqrte },
8016 },
8017 0b01100 => switch (inst.group.size) {
8018 .byte, .half => .unallocated,
8019 .single, .double => .{ .fcmge = inst.fcmge },
8020 },
8021 0b01101 => switch (inst.group.size) {
8022 .byte, .half => .unallocated,
8023 .single, .double => .{ .fcmle = inst.fcmle },
8024 },
8025 },
8026 };
8027 }
79168028 };
79178029
79188030 /// Advanced SIMD scalar pairwise
......@@ -7944,6 +8056,20 @@ pub const Instruction = packed union {
79448056 U: std.builtin.Signedness = .signed,
79458057 decoded30: u2 = 0b01,
79468058 };
8059
8060 pub const Decoded = union(enum) {
8061 unallocated,
8062 addp: Addp,
8063 };
8064 pub fn decode(inst: @This()) @This().Decoded {
8065 return switch (inst.group.U) {
8066 .signed => switch (inst.group.opcode) {
8067 else => .unallocated,
8068 0b11011 => .{ .addp = inst.addp },
8069 },
8070 .unsigned => .unallocated,
8071 };
8072 }
79478073 };
79488074
79498075 /// Advanced SIMD copy
......@@ -7998,7 +8124,7 @@ pub const Instruction = packed union {
79988124 imm5: u5,
79998125 decoded21: u8 = 0b01110000,
80008126 op: u1 = 0b0,
8001 Q: Register.IntegerSize,
8127 Q: Register.GeneralSize,
80028128 decoded31: u1 = 0b0,
80038129 };
80048130
......@@ -8012,7 +8138,7 @@ pub const Instruction = packed union {
80128138 imm5: u5,
80138139 decoded21: u8 = 0b01110000,
80148140 op: u1 = 0b0,
8015 Q: Register.IntegerSize,
8141 Q: Register.GeneralSize,
80168142 decoded31: u1 = 0b0,
80178143 };
80188144
......@@ -8031,8 +8157,8 @@ pub const Instruction = packed union {
80318157 decoded31: u1 = 0b0,
80328158
80338159 pub const Imm4 = packed union {
8034 general: General,
80358160 element: u4,
8161 general: General,
80368162
80378163 pub const General = enum(u4) {
80388164 general = 0b0011,
......@@ -8077,6 +8203,10 @@ pub const Instruction = packed union {
80778203 },
80788204 else => .unallocated,
80798205 },
8206 0b0011 => switch (inst.group.Q) {
8207 0b0 => .unallocated,
8208 0b1 => .{ .ins = inst.ins },
8209 },
80808210 },
80818211 0b1 => switch (inst.group.Q) {
80828212 0b0 => .unallocated,
......@@ -8537,6 +8667,88 @@ pub const Instruction = packed union {
85378667 Q: Q,
85388668 decoded31: u1 = 0b0,
85398669 };
8670
8671 pub const Decoded = union(enum) {
8672 unallocated,
8673 frintn: Frintn,
8674 frintm: Frintm,
8675 fcvtns: Fcvtns,
8676 fcvtms: Fcvtms,
8677 fcvtas: Fcvtas,
8678 scvtf: Scvtf,
8679 fcmgt: Fcmgt,
8680 fcmeq: Fcmeq,
8681 fcmlt: Fcmlt,
8682 fabs: Fabs,
8683 frintp: Frintp,
8684 frintz: Frintz,
8685 fcvtps: Fcvtps,
8686 fcvtzs: Fcvtzs,
8687 frecpe: Frecpe,
8688 frinta: Frinta,
8689 frintx: Frintx,
8690 fcvtnu: Fcvtnu,
8691 fcvtmu: Fcvtmu,
8692 fcvtau: Fcvtau,
8693 ucvtf: Ucvtf,
8694 fcmge: Fcmge,
8695 fcmle: Fcmle,
8696 fneg: Fneg,
8697 frinti: Frinti,
8698 fcvtpu: Fcvtpu,
8699 fcvtzu: Fcvtzu,
8700 frsqrte: Frsqrte,
8701 fsqrt: Fsqrt,
8702 };
8703 pub fn decode(inst: @This()) @This().Decoded {
8704 return switch (inst.group.U) {
8705 .signed => switch (inst.group.a) {
8706 0b0 => switch (inst.group.opcode) {
8707 else => .unallocated,
8708 0b11000 => .{ .frintn = inst.frintn },
8709 0b11001 => .{ .frintm = inst.frintm },
8710 0b11010 => .{ .fcvtns = inst.fcvtns },
8711 0b11011 => .{ .fcvtms = inst.fcvtms },
8712 0b11100 => .{ .fcvtas = inst.fcvtas },
8713 0b11101 => .{ .scvtf = inst.scvtf },
8714 },
8715 0b1 => switch (inst.group.opcode) {
8716 else => .unallocated,
8717 0b01100 => .{ .fcmgt = inst.fcmgt },
8718 0b01101 => .{ .fcmeq = inst.fcmeq },
8719 0b01110 => .{ .fcmlt = inst.fcmlt },
8720 0b01111 => .{ .fabs = inst.fabs },
8721 0b11000 => .{ .frintp = inst.frintp },
8722 0b11001 => .{ .frintz = inst.frintz },
8723 0b11010 => .{ .fcvtps = inst.fcvtps },
8724 0b11011 => .{ .fcvtzs = inst.fcvtzs },
8725 0b11101 => .{ .frecpe = inst.frecpe },
8726 },
8727 },
8728 .unsigned => switch (inst.group.a) {
8729 0b0 => switch (inst.group.opcode) {
8730 else => .unallocated,
8731 0b11000 => .{ .frinta = inst.frinta },
8732 0b11001 => .{ .frintx = inst.frintx },
8733 0b11010 => .{ .fcvtnu = inst.fcvtnu },
8734 0b11011 => .{ .fcvtmu = inst.fcvtmu },
8735 0b11100 => .{ .fcvtau = inst.fcvtau },
8736 0b11101 => .{ .ucvtf = inst.ucvtf },
8737 },
8738 0b1 => switch (inst.group.opcode) {
8739 else => .unallocated,
8740 0b01100 => .{ .fcmge = inst.fcmge },
8741 0b01101 => .{ .fcmle = inst.fcmle },
8742 0b01111 => .{ .fneg = inst.fneg },
8743 0b11001 => .{ .frinti = inst.frinti },
8744 0b11010 => .{ .fcvtpu = inst.fcvtpu },
8745 0b11011 => .{ .fcvtzu = inst.fcvtzu },
8746 0b11101 => .{ .frsqrte = inst.frsqrte },
8747 0b11111 => .{ .fsqrt = inst.fsqrt },
8748 },
8749 },
8750 };
8751 }
85408752 };
85418753
85428754 /// Advanced SIMD two-register miscellaneous
......@@ -8700,7 +8912,7 @@ pub const Instruction = packed union {
87008912 decoded31: u1 = 0b0,
87018913 };
87028914
8703 /// C7.2.308 SQXTN
8915 /// C7.2.308 SQXTN, SQXTN2
87048916 pub const Sqxtn = packed struct {
87058917 Rd: Register.Encoded,
87068918 Rn: Register.Encoded,
......@@ -9275,6 +9487,169 @@ pub const Instruction = packed union {
92759487 Q: Q,
92769488 decoded31: u1 = 0b0,
92779489 };
9490
9491 pub const Decoded = union(enum) {
9492 unallocated,
9493 suqadd: Suqadd,
9494 cnt: Cnt,
9495 sqabs: Sqabs,
9496 cmgt: Cmgt,
9497 cmeq: Cmeq,
9498 cmlt: Cmlt,
9499 abs: Abs,
9500 sqxtn: Sqxtn,
9501 frintn: Frintn,
9502 frintm: Frintm,
9503 fcvtns: Fcvtns,
9504 fcvtms: Fcvtms,
9505 fcvtas: Fcvtas,
9506 scvtf: Scvtf,
9507 fcmgt: Fcmgt,
9508 fcmeq: Fcmeq,
9509 fcmlt: Fcmlt,
9510 fabs: Fabs,
9511 frintp: Frintp,
9512 frintz: Frintz,
9513 fcvtps: Fcvtps,
9514 fcvtzs: Fcvtzs,
9515 frecpe: Frecpe,
9516 usqadd: Usqadd,
9517 sqneg: Sqneg,
9518 cmge: Cmge,
9519 cmle: Cmle,
9520 neg: Neg,
9521 sqxtun: Sqxtun,
9522 uqxtn: Uqxtn,
9523 fcvtxn: Fcvtxn,
9524 frinta: Frinta,
9525 frintx: Frintx,
9526 fcvtnu: Fcvtnu,
9527 fcvtmu: Fcvtmu,
9528 fcvtau: Fcvtau,
9529 ucvtf: Ucvtf,
9530 not: Not,
9531 fcmge: Fcmge,
9532 fcmle: Fcmle,
9533 fneg: Fneg,
9534 frinti: Frinti,
9535 fcvtpu: Fcvtpu,
9536 fcvtzu: Fcvtzu,
9537 frsqrte: Frsqrte,
9538 fsqrt: Fsqrt,
9539 };
9540 pub fn decode(inst: @This()) @This().Decoded {
9541 return switch (inst.group.U) {
9542 .signed => switch (inst.group.opcode) {
9543 else => .unallocated,
9544 0b00011 => .{ .suqadd = inst.suqadd },
9545 0b00101 => .{ .cnt = inst.cnt },
9546 0b00111 => .{ .sqabs = inst.sqabs },
9547 0b01000 => .{ .cmgt = inst.cmgt },
9548 0b01001 => .{ .cmeq = inst.cmeq },
9549 0b01010 => .{ .cmlt = inst.cmlt },
9550 0b01011 => .{ .abs = inst.abs },
9551 0b10100 => .{ .sqxtn = inst.sqxtn },
9552 0b11000 => switch (inst.group.size) {
9553 .byte, .half => .{ .frintn = inst.frintn },
9554 .single, .double => .{ .frintp = inst.frintp },
9555 },
9556 0b11001 => switch (inst.group.size) {
9557 .byte, .half => .{ .frintm = inst.frintm },
9558 .single, .double => .{ .frintz = inst.frintz },
9559 },
9560 0b11010 => switch (inst.group.size) {
9561 .byte, .half => .{ .fcvtns = inst.fcvtns },
9562 .single, .double => .{ .fcvtps = inst.fcvtps },
9563 },
9564 0b11011 => switch (inst.group.size) {
9565 .byte, .half => .{ .fcvtms = inst.fcvtms },
9566 .single, .double => .{ .fcvtzs = inst.fcvtzs },
9567 },
9568 0b11100 => switch (inst.group.size) {
9569 .byte, .half => .{ .fcvtas = inst.fcvtas },
9570 .single, .double => .unallocated,
9571 },
9572 0b11101 => switch (inst.group.size) {
9573 .byte, .half => .{ .scvtf = inst.scvtf },
9574 .single, .double => .{ .frecpe = inst.frecpe },
9575 },
9576 0b01100 => switch (inst.group.size) {
9577 .byte, .half => .unallocated,
9578 .single, .double => .{ .fcmgt = inst.fcmgt },
9579 },
9580 0b01101 => switch (inst.group.size) {
9581 .byte, .half => .unallocated,
9582 .single, .double => .{ .fcmeq = inst.fcmeq },
9583 },
9584 0b01110 => switch (inst.group.size) {
9585 .byte, .half => .unallocated,
9586 .single, .double => .{ .fcmlt = inst.fcmlt },
9587 },
9588 0b01111 => switch (inst.group.size) {
9589 .byte, .half => .unallocated,
9590 .single, .double => .{ .fabs = inst.fabs },
9591 },
9592 },
9593 .unsigned => switch (inst.group.opcode) {
9594 else => .unallocated,
9595 0b00011 => .{ .usqadd = inst.usqadd },
9596 0b00111 => .{ .sqneg = inst.sqneg },
9597 0b01000 => .{ .cmge = inst.cmge },
9598 0b01001 => .{ .cmle = inst.cmle },
9599 0b01011 => .{ .neg = inst.neg },
9600 0b10010 => .{ .sqxtun = inst.sqxtun },
9601 0b10100 => .{ .uqxtn = inst.uqxtn },
9602 0b10110 => switch (inst.group.size) {
9603 .byte, .half => .{ .fcvtxn = inst.fcvtxn },
9604 .single, .double => .unallocated,
9605 },
9606 0b11000 => switch (inst.group.size) {
9607 .byte, .half => .{ .frinta = inst.frinta },
9608 .single, .double => .unallocated,
9609 },
9610 0b11001 => switch (inst.group.size) {
9611 .byte, .half => .{ .frintx = inst.frintx },
9612 .single, .double => .{ .frinti = inst.frinti },
9613 },
9614 0b11010 => switch (inst.group.size) {
9615 .byte, .half => .{ .fcvtnu = inst.fcvtnu },
9616 .single, .double => .{ .fcvtpu = inst.fcvtpu },
9617 },
9618 0b11011 => switch (inst.group.size) {
9619 .byte, .half => .{ .fcvtmu = inst.fcvtmu },
9620 .single, .double => .{ .fcvtzu = inst.fcvtzu },
9621 },
9622 0b11100 => switch (inst.group.size) {
9623 .byte, .half => .{ .fcvtau = inst.fcvtau },
9624 .single, .double => .unallocated,
9625 },
9626 0b11101 => switch (inst.group.size) {
9627 .byte, .half => .{ .ucvtf = inst.ucvtf },
9628 .single, .double => .{ .frsqrte = inst.frsqrte },
9629 },
9630 0b00101 => switch (inst.group.size) {
9631 .byte => .{ .not = inst.not },
9632 .half, .single, .double => .unallocated,
9633 },
9634 0b01100 => switch (inst.group.size) {
9635 .byte, .half => .unallocated,
9636 .single, .double => .{ .fcmge = inst.fcmge },
9637 },
9638 0b01101 => switch (inst.group.size) {
9639 .byte, .half => .unallocated,
9640 .single, .double => .{ .fcmle = inst.fcmle },
9641 },
9642 0b01111 => switch (inst.group.size) {
9643 .byte, .half => .unallocated,
9644 .single, .double => .{ .fneg = inst.fneg },
9645 },
9646 0b11111 => switch (inst.group.size) {
9647 .byte, .half => .unallocated,
9648 .single, .double => .{ .fsqrt = inst.fsqrt },
9649 },
9650 },
9651 };
9652 }
92789653 };
92799654
92809655 /// Advanced SIMD across lanes
......@@ -9308,6 +9683,20 @@ pub const Instruction = packed union {
93089683 Q: Q,
93099684 decoded31: u1 = 0b0,
93109685 };
9686
9687 pub const Decoded = union(enum) {
9688 unallocated,
9689 addv: Addv,
9690 };
9691 pub fn decode(inst: @This()) @This().Decoded {
9692 return switch (inst.group.U) {
9693 .signed => switch (inst.group.opcode) {
9694 else => .unallocated,
9695 0b11011 => .{ .addv = inst.addv },
9696 },
9697 .unsigned => .unallocated,
9698 };
9699 }
93119700 };
93129701
93139702 /// Advanced SIMD three same
......@@ -9471,6 +9860,42 @@ pub const Instruction = packed union {
94719860 Q: Q,
94729861 decoded31: u1 = 0b0,
94739862 };
9863
9864 pub const Decoded = union(enum) {
9865 unallocated,
9866 addp: Addp,
9867 @"and": And,
9868 bic: Bic,
9869 orr: Orr,
9870 orn: Orn,
9871 eor: Eor,
9872 bsl: Bsl,
9873 bit: Bit,
9874 bif: Bif,
9875 };
9876 pub fn decode(inst: @This()) @This().Decoded {
9877 return switch (inst.group.U) {
9878 .signed => switch (inst.group.opcode) {
9879 else => .unallocated,
9880 0b10111 => .{ .addp = inst.addp },
9881 0b00011 => switch (inst.group.size) {
9882 .byte => .{ .@"and" = inst.@"and" },
9883 .half => .{ .bic = inst.bic },
9884 .single => .{ .orr = inst.orr },
9885 .double => .{ .orn = inst.orn },
9886 },
9887 },
9888 .unsigned => switch (inst.group.opcode) {
9889 else => .unallocated,
9890 0b00011 => switch (inst.group.size) {
9891 .byte => .{ .eor = inst.eor },
9892 .half => .{ .bsl = inst.bsl },
9893 .single => .{ .bit = inst.bit },
9894 .double => .{ .bif = inst.bif },
9895 },
9896 },
9897 };
9898 }
94749899 };
94759900
94769901 /// Advanced SIMD modified immediate
......@@ -9529,11 +9954,11 @@ pub const Instruction = packed union {
95299954 Rd: Register.Encoded,
95309955 imm5: u5,
95319956 decoded10: u1 = 0b1,
9532 o2: u1 = 0b1,
9957 o2: u1,
95339958 cmode: u4 = 0b1111,
95349959 imm3: u3,
95359960 decoded19: u10 = 0b0111100000,
9536 op: u1 = 0b0,
9961 op: u1,
95379962 Q: Q,
95389963 decoded31: u1 = 0b0,
95399964 };
......@@ -9566,6 +9991,45 @@ pub const Instruction = packed union {
95669991 Q: Q,
95679992 decoded31: u1 = 0b0,
95689993 };
9994
9995 pub const Decoded = union(enum) {
9996 unallocated,
9997 fmov: Fmov,
9998 };
9999 pub fn decode(inst: @This()) @This().Decoded {
10000 return switch (inst.group.cmode) {
10001 else => .unallocated,
10002 0b1111 => switch (inst.group.op) {
10003 0b0 => .{ .fmov = inst.fmov },
10004 0b1 => switch (inst.group.Q) {
10005 .double => .unallocated,
10006 .quad => switch (inst.group.o2) {
10007 0b1 => .unallocated,
10008 0b0 => .{ .fmov = inst.fmov },
10009 },
10010 },
10011 },
10012 };
10013 }
10014 };
10015
10016 /// Conversion between floating-point and fixed-point
10017 pub const ConvertFloatFixed = packed union {
10018 group: @This().Group,
10019
10020 pub const Group = packed struct {
10021 Rd: Register.Encoded,
10022 Rn: Register.Encoded,
10023 scale: u6,
10024 opcode: u3,
10025 rmode: u2,
10026 decoded21: u1 = 0b0,
10027 ptype: Ftype,
10028 decoded24: u5 = 0b11110,
10029 S: bool,
10030 decoded30: u1 = 0b0,
10031 sf: Register.GeneralSize,
10032 };
956910033 };
957010034
957110035 /// Conversion between floating-point and integer
......@@ -9597,7 +10061,7 @@ pub const Instruction = packed union {
959710061 decoded24: u5 = 0b11110,
959810062 S: bool,
959910063 decoded30: u1 = 0b0,
9600 sf: Register.IntegerSize,
10064 sf: Register.GeneralSize,
960110065 };
960210066
960310067 /// C7.2.81 FCVTNS (scalar)
......@@ -9612,7 +10076,7 @@ pub const Instruction = packed union {
961210076 decoded24: u5 = 0b11110,
961310077 S: bool = false,
961410078 decoded30: u1 = 0b0,
9615 sf: Register.IntegerSize,
10079 sf: Register.GeneralSize,
961610080 };
961710081
961810082 /// C7.2.83 FCVTNU (scalar)
......@@ -9627,7 +10091,7 @@ pub const Instruction = packed union {
962710091 decoded24: u5 = 0b11110,
962810092 S: bool = false,
962910093 decoded30: u1 = 0b0,
9630 sf: Register.IntegerSize,
10094 sf: Register.GeneralSize,
963110095 };
963210096
963310097 /// C7.2.236 SCVTF (scalar, integer)
......@@ -9642,7 +10106,7 @@ pub const Instruction = packed union {
964210106 decoded24: u5 = 0b11110,
964310107 S: bool = false,
964410108 decoded30: u1 = 0b0,
9645 sf: Register.IntegerSize,
10109 sf: Register.GeneralSize,
964610110 };
964710111
964810112 /// C7.2.355 UCVTF (scalar, integer)
......@@ -9657,7 +10121,7 @@ pub const Instruction = packed union {
965710121 decoded24: u5 = 0b11110,
965810122 S: bool = false,
965910123 decoded30: u1 = 0b0,
9660 sf: Register.IntegerSize,
10124 sf: Register.GeneralSize,
966110125 };
966210126
966310127 /// C7.2.71 FCVTAS (scalar)
......@@ -9672,7 +10136,7 @@ pub const Instruction = packed union {
967210136 decoded24: u5 = 0b11110,
967310137 S: bool = false,
967410138 decoded30: u1 = 0b0,
9675 sf: Register.IntegerSize,
10139 sf: Register.GeneralSize,
967610140 };
967710141
967810142 /// C7.2.73 FCVTAU (scalar)
......@@ -9687,7 +10151,7 @@ pub const Instruction = packed union {
968710151 decoded24: u5 = 0b11110,
968810152 S: bool = false,
968910153 decoded30: u1 = 0b0,
9690 sf: Register.IntegerSize,
10154 sf: Register.GeneralSize,
969110155 };
969210156
969310157 /// C7.2.131 FMOV (general)
......@@ -9702,7 +10166,7 @@ pub const Instruction = packed union {
970210166 decoded24: u5 = 0b11110,
970310167 S: bool = false,
970410168 decoded30: u1 = 0b0,
9705 sf: Register.IntegerSize,
10169 sf: Register.GeneralSize,
970610170
970710171 pub const Opcode = enum(u3) {
970810172 float_to_integer = 0b110,
......@@ -9729,7 +10193,7 @@ pub const Instruction = packed union {
972910193 decoded24: u5 = 0b11110,
973010194 S: bool = false,
973110195 decoded30: u1 = 0b0,
9732 sf: Register.IntegerSize,
10196 sf: Register.GeneralSize,
973310197 };
973410198
973510199 /// C7.2.87 FCVTPU (scalar)
......@@ -9744,7 +10208,7 @@ pub const Instruction = packed union {
974410208 decoded24: u5 = 0b11110,
974510209 S: bool = false,
974610210 decoded30: u1 = 0b0,
9747 sf: Register.IntegerSize,
10211 sf: Register.GeneralSize,
974810212 };
974910213
975010214 /// C7.2.76 FCVTMS (scalar)
......@@ -9759,7 +10223,7 @@ pub const Instruction = packed union {
975910223 decoded24: u5 = 0b11110,
976010224 S: bool = false,
976110225 decoded30: u1 = 0b0,
9762 sf: Register.IntegerSize,
10226 sf: Register.GeneralSize,
976310227 };
976410228
976510229 /// C7.2.78 FCVTMU (scalar)
......@@ -9774,7 +10238,7 @@ pub const Instruction = packed union {
977410238 decoded24: u5 = 0b11110,
977510239 S: bool = false,
977610240 decoded30: u1 = 0b0,
9777 sf: Register.IntegerSize,
10241 sf: Register.GeneralSize,
977810242 };
977910243
978010244 /// C7.2.92 FCVTZS (scalar, integer)
......@@ -9789,7 +10253,7 @@ pub const Instruction = packed union {
978910253 decoded24: u5 = 0b11110,
979010254 S: bool = false,
979110255 decoded30: u1 = 0b0,
9792 sf: Register.IntegerSize,
10256 sf: Register.GeneralSize,
979310257 };
979410258
979510259 /// C7.2.96 FCVTZU (scalar, integer)
......@@ -9804,7 +10268,7 @@ pub const Instruction = packed union {
980410268 decoded24: u5 = 0b11110,
980510269 S: bool = false,
980610270 decoded30: u1 = 0b0,
9807 sf: Register.IntegerSize,
10271 sf: Register.GeneralSize,
980810272 };
980910273
981010274 /// C7.2.99 FJCVTZS
......@@ -9819,7 +10283,7 @@ pub const Instruction = packed union {
981910283 decoded24: u5 = 0b11110,
982010284 S: bool = false,
982110285 decoded30: u1 = 0b0,
9822 sf: Register.IntegerSize = .word,
10286 sf: Register.GeneralSize = .word,
982310287 };
982410288
982510289 pub const Rmode = enum(u2) {
......@@ -9832,6 +10296,84 @@ pub const Instruction = packed union {
983210296 /// toward zero
983310297 z = 0b11,
983410298 };
10299
10300 pub const Decoded = union(enum) {
10301 unallocated,
10302 fcvtns: Fcvtns,
10303 fcvtnu: Fcvtnu,
10304 scvtf: Scvtf,
10305 ucvtf: Ucvtf,
10306 fcvtas: Fcvtas,
10307 fcvtau: Fcvtau,
10308 fmov: Fmov,
10309 fcvtps: Fcvtps,
10310 fcvtpu: Fcvtpu,
10311 fcvtms: Fcvtms,
10312 fcvtmu: Fcvtmu,
10313 fcvtzs: Fcvtzs,
10314 fcvtzu: Fcvtzu,
10315 fjcvtzs: Fjcvtzs,
10316 };
10317 pub fn decode(inst: @This()) @This().Decoded {
10318 return switch (inst.group.S) {
10319 true => .unallocated,
10320 false => switch (inst.group.ptype) {
10321 .single, .double, .half => switch (inst.group.opcode) {
10322 0b000 => switch (inst.group.rmode) {
10323 0b00 => .{ .fcvtns = inst.fcvtns },
10324 0b01 => .{ .fcvtps = inst.fcvtps },
10325 0b10 => .{ .fcvtms = inst.fcvtms },
10326 0b11 => .{ .fcvtzs = inst.fcvtzs },
10327 },
10328 0b001 => switch (inst.group.rmode) {
10329 0b00 => .{ .fcvtnu = inst.fcvtnu },
10330 0b01 => .{ .fcvtpu = inst.fcvtpu },
10331 0b10 => .{ .fcvtmu = inst.fcvtmu },
10332 0b11 => .{ .fcvtzu = inst.fcvtzu },
10333 },
10334 0b010 => switch (inst.group.rmode) {
10335 else => .unallocated,
10336 0b00 => .{ .scvtf = inst.scvtf },
10337 },
10338 0b011 => switch (inst.group.rmode) {
10339 else => .unallocated,
10340 0b00 => .{ .ucvtf = inst.ucvtf },
10341 },
10342 0b100 => switch (inst.group.rmode) {
10343 else => .unallocated,
10344 0b00 => .{ .fcvtas = inst.fcvtas },
10345 },
10346 0b101 => switch (inst.group.rmode) {
10347 else => .unallocated,
10348 0b00 => .{ .fcvtau = inst.fcvtau },
10349 },
10350 0b110 => switch (inst.group.rmode) {
10351 else => .unallocated,
10352 0b00 => .{ .fmov = inst.fmov },
10353 0b11 => switch (inst.group.ptype) {
10354 .single, .double => .unallocated,
10355 .quad => unreachable,
10356 .half => .{ .fjcvtzs = inst.fjcvtzs },
10357 },
10358 },
10359 0b111 => switch (inst.group.rmode) {
10360 else => .unallocated,
10361 0b00 => .{ .fmov = inst.fmov },
10362 },
10363 },
10364 .quad => switch (inst.group.opcode) {
10365 else => .unallocated,
10366 0b110, 0b111 => switch (inst.group.rmode) {
10367 else => .unallocated,
10368 0b01 => switch (inst.group.sf) {
10369 .word => .unallocated,
10370 .doubleword => .{ .fmov = inst.fmov },
10371 },
10372 },
10373 },
10374 },
10375 };
10376 }
983510377 };
983610378
983710379 /// Floating-point data-processing (1 source)
......@@ -10060,6 +10602,48 @@ pub const Instruction = packed union {
1006010602 i = 0b111,
1006110603 _,
1006210604 };
10605
10606 pub const Decoded = union(enum) {
10607 unallocated,
10608 fmov: Fmov,
10609 fabs: Fabs,
10610 fneg: Fneg,
10611 fsqrt: Fsqrt,
10612 fcvt: Fcvt,
10613 frintn: Frintn,
10614 frintp: Frintp,
10615 frintm: Frintm,
10616 frintz: Frintz,
10617 frinta: Frinta,
10618 frintx: Frintx,
10619 frinti: Frinti,
10620 };
10621 pub fn decode(inst: @This()) @This().Decoded {
10622 return switch (inst.group.M) {
10623 0b0 => switch (inst.group.S) {
10624 true => .unallocated,
10625 false => switch (inst.group.ptype) {
10626 .single, .double, .half => switch (inst.group.opcode) {
10627 else => .unallocated,
10628 0b000000 => .{ .fmov = inst.fmov },
10629 0b000001 => .{ .fabs = inst.fabs },
10630 0b000010 => .{ .fneg = inst.fneg },
10631 0b000011 => .{ .fsqrt = inst.fsqrt },
10632 0b000101, 0b000111 => .{ .fcvt = inst.fcvt },
10633 0b001000 => .{ .frintn = inst.frintn },
10634 0b001001 => .{ .frintp = inst.frintp },
10635 0b001010 => .{ .frintm = inst.frintm },
10636 0b001011 => .{ .frintz = inst.frintz },
10637 0b001100 => .{ .frinta = inst.frinta },
10638 0b001110 => .{ .frintx = inst.frintx },
10639 0b001111 => .{ .frinti = inst.frinti },
10640 },
10641 .quad => .unallocated,
10642 },
10643 },
10644 0b1 => .unallocated,
10645 };
10646 }
1006310647 };
1006410648
1006510649 /// Floating-point compare
......@@ -10145,13 +10729,77 @@ pub const Instruction = packed union {
1014510729 Rd: Register.Encoded,
1014610730 imm5: u5 = 0b00000,
1014710731 decoded10: u3 = 0b100,
10148 imm8: u8,
10732 imm8: Imm8,
1014910733 decoded21: u1 = 0b1,
1015010734 ftype: Ftype,
1015110735 decoded24: u5 = 0b11110,
1015210736 S: bool = false,
1015310737 decoded30: u1 = 0b0,
1015410738 M: u1 = 0b0,
10739
10740 pub const Imm8 = packed struct(u8) {
10741 mantissa: u4,
10742 exponent: i3,
10743 sign: std.math.Sign,
10744
10745 pub const Modified = packed struct(u8) { imm5: u5, imm3: u3 };
10746
10747 pub fn fromModified(mod: Modified) Imm8 {
10748 return @bitCast(mod);
10749 }
10750
10751 pub fn toModified(imm8: Imm8) Modified {
10752 return @bitCast(imm8);
10753 }
10754
10755 pub fn decode(imm8: Imm8) f16 {
10756 const Normalized = std.math.FloatRepr(f16).Normalized;
10757 return Normalized.reconstruct(.{
10758 .fraction = @as(Normalized.Fraction, imm8.mantissa) << 6,
10759 .exponent = @as(Normalized.Exponent, imm8.exponent) + 1,
10760 }, imm8.sign);
10761 }
10762 };
10763 };
10764
10765 pub const Decoded = union(enum) {
10766 unallocated,
10767 fmov: Fmov,
10768 };
10769 pub fn decode(inst: @This()) @This().Decoded {
10770 return switch (inst.group.M) {
10771 0b0 => switch (inst.group.S) {
10772 true => .unallocated,
10773 false => switch (inst.group.imm5) {
10774 else => .unallocated,
10775 0b00000 => switch (inst.group.ptype) {
10776 .quad => .unallocated,
10777 .single, .double, .half => .{ .fmov = inst.fmov },
10778 },
10779 },
10780 },
10781 0b1 => .unallocated,
10782 };
10783 }
10784 };
10785
10786 /// Floating-point conditional compare
10787 pub const FloatConditionalCompare = packed union {
10788 group: @This().Group,
10789
10790 pub const Group = packed struct {
10791 nzcv: Nzcv,
10792 op: u1,
10793 Rn: Register.Encoded,
10794 decoded10: u2 = 0b01,
10795 cond: ConditionCode,
10796 Rm: Register.Encoded,
10797 decoded21: u1 = 0b1,
10798 ptype: Ftype,
10799 decoded24: u5 = 0b11110,
10800 S: bool,
10801 decoded30: u1 = 0b0,
10802 M: u1,
1015510803 };
1015610804 };
1015710805
......@@ -10477,7 +11125,15 @@ pub const Instruction = packed union {
1047711125 single = 0b10,
1047811126 double = 0b11,
1047911127
10480 pub fn toVectorSize(s: Size) Register.VectorSize {
11128 pub fn n(s: Size) Size {
11129 return @enumFromInt(@intFromEnum(s) - 1);
11130 }
11131
11132 pub fn w(s: Size) Size {
11133 return @enumFromInt(@intFromEnum(s) + 1);
11134 }
11135
11136 pub fn toScalarSize(s: Size) Register.ScalarSize {
1048111137 return switch (s) {
1048211138 .byte => .byte,
1048311139 .half => .half,
......@@ -10486,8 +11142,8 @@ pub const Instruction = packed union {
1048611142 };
1048711143 }
1048811144
10489 pub fn fromVectorSize(vs: Register.VectorSize) Size {
10490 return switch (vs) {
11145 pub fn fromScalarSize(ss: Register.ScalarSize) Size {
11146 return switch (ss) {
1049111147 else => unreachable,
1049211148 .byte => .byte,
1049311149 .half => .half,
......@@ -10495,26 +11151,41 @@ pub const Instruction = packed union {
1049511151 .double => .double,
1049611152 };
1049711153 }
11154
11155 pub fn toSz(s: Size) Sz {
11156 return switch (s) {
11157 else => unreachable,
11158 .single => .single,
11159 .double => .double,
11160 };
11161 }
1049811162 };
1049911163
1050011164 pub const Sz = enum(u1) {
1050111165 single = 0b0,
1050211166 double = 0b1,
1050311167
10504 pub fn toVectorSize(sz: Sz) Register.VectorSize {
11168 pub fn toScalarSize(sz: Sz) Register.ScalarSize {
1050511169 return switch (sz) {
1050611170 .single => .single,
1050711171 .double => .double,
1050811172 };
1050911173 }
1051011174
10511 pub fn fromVectorSize(vs: Register.VectorSize) Sz {
10512 return switch (vs) {
11175 pub fn fromScalarSize(ss: Register.ScalarSize) Sz {
11176 return switch (ss) {
1051311177 else => unreachable,
1051411178 .single => .single,
1051511179 .double => .double,
1051611180 };
1051711181 }
11182
11183 pub fn toSize(sz: Sz) Size {
11184 return switch (sz) {
11185 .single => .single,
11186 .double => .double,
11187 };
11188 }
1051811189 };
1051911190
1052011191 pub const Q = enum(u1) {
......@@ -10528,24 +11199,104 @@ pub const Instruction = packed union {
1052811199 quad = 0b10,
1052911200 half = 0b11,
1053011201
10531 pub fn toVectorSize(ftype: Ftype) Register.VectorSize {
11202 pub fn toScalarSize(ftype: Ftype) Register.ScalarSize {
1053211203 return switch (ftype) {
10533 _ => unreachable,
1053411204 .single => .single,
1053511205 .double => .double,
11206 .quad => .quad,
1053611207 .half => .half,
1053711208 };
1053811209 }
1053911210
10540 pub fn fromVectorSize(vs: Register.VectorSize) Ftype {
10541 return switch (vs) {
11211 pub fn fromScalarSize(ss: Register.ScalarSize) Ftype {
11212 return switch (ss) {
1054211213 else => unreachable,
1054311214 .single => .single,
1054411215 .double => .double,
11216 .quad => .quad,
1054511217 .half => .half,
1054611218 };
1054711219 }
1054811220 };
11221
11222 pub const Decoded = union(enum) {
11223 unallocated,
11224 simd_scalar_copy: SimdScalarCopy,
11225 simd_scalar_two_register_miscellaneous_fp16: SimdScalarTwoRegisterMiscellaneousFp16,
11226 simd_scalar_two_register_miscellaneous: SimdScalarTwoRegisterMiscellaneous,
11227 simd_scalar_pairwise: SimdScalarPairwise,
11228 simd_copy: SimdCopy,
11229 simd_two_register_miscellaneous_fp16: SimdTwoRegisterMiscellaneousFp16,
11230 simd_two_register_miscellaneous: SimdTwoRegisterMiscellaneous,
11231 simd_across_lanes: SimdAcrossLanes,
11232 simd_three_same: SimdThreeSame,
11233 simd_modified_immediate: SimdModifiedImmediate,
11234 convert_float_fixed: ConvertFloatFixed,
11235 convert_float_integer: ConvertFloatInteger,
11236 float_data_processing_one_source: FloatDataProcessingOneSource,
11237 float_compare: FloatCompare,
11238 float_immediate: FloatImmediate,
11239 float_conditional_compare: FloatConditionalCompare,
11240 float_data_processing_two_source: FloatDataProcessingTwoSource,
11241 float_conditional_select: FloatConditionalSelect,
11242 float_data_processing_three_source: FloatDataProcessingThreeSource,
11243 };
11244 pub fn decode(inst: @This()) @This().Decoded {
11245 return switch (inst.group.op0) {
11246 else => .unallocated,
11247 0b0101, 0b0111 => switch (inst.group.op1) {
11248 0b00...0b01 => if (inst.group.op3 & 0b000100001 == 0b000000001)
11249 if (inst.group.op1 == 0b00 and inst.group.op2 & 0b1100 == 0b0000)
11250 .{ .simd_scalar_copy = inst.simd_scalar_copy }
11251 else
11252 .unallocated
11253 else if (inst.group.op3 & 0b110000011 == 0b000000010) switch (inst.group.op2) {
11254 else => .unallocated,
11255 0b1111 => .{ .simd_scalar_two_register_miscellaneous_fp16 = inst.simd_scalar_two_register_miscellaneous_fp16 },
11256 0b0100, 0b1100 => .{ .simd_scalar_two_register_miscellaneous = inst.simd_scalar_two_register_miscellaneous },
11257 0b0110, 0b1110 => .{ .simd_scalar_pairwise = inst.simd_scalar_pairwise },
11258 } else .unallocated,
11259 0b10, 0b11 => switch (@as(u1, @truncate(inst.group.op3 >> 0))) {
11260 0b1 => switch (inst.group.op1) {
11261 0b10 => .unallocated,
11262 else => .unallocated,
11263 },
11264 0b0 => .unallocated,
11265 },
11266 },
11267 0b0000, 0b0010, 0b0100, 0b0110 => if (inst.group.op1 == 0b00 and inst.group.op2 & 0b1100 == 0b0000 and inst.group.op3 & 0b000100001 == 0b0000000001)
11268 .{ .simd_copy = inst.simd_copy }
11269 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 == 0b1111 and inst.group.op3 & 0b110000011 == 0b000000010)
11270 .{ .simd_two_register_miscellaneous_fp16 = inst.simd_two_register_miscellaneous_fp16 }
11271 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0111 == 0b0100 and inst.group.op3 & 0b110000011 == 0b000000010)
11272 .{ .simd_two_register_miscellaneous = inst.simd_two_register_miscellaneous }
11273 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0111 == 0b0110 and inst.group.op3 & 0b110000011 == 0b000000010)
11274 .{ .simd_across_lanes = inst.simd_across_lanes }
11275 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0100 == 0b0100 and inst.group.op3 & 0b000000001 == 0b000000001)
11276 .{ .simd_three_same = inst.simd_three_same }
11277 else if (inst.group.op1 == 0b10 and inst.group.op2 == 0b0000 and inst.group.op3 & 0b000000001 == 0b000000001)
11278 .{ .simd_modified_immediate = inst.simd_modified_immediate }
11279 else
11280 .unallocated,
11281 0b0001, 0b0011, 0b1001, 0b1011 => switch (@as(u1, @truncate(inst.group.op1 >> 1))) {
11282 0b0 => switch (@as(u1, @truncate(inst.group.op2 >> 2))) {
11283 0b0 => .{ .convert_float_fixed = inst.convert_float_fixed },
11284 0b1 => switch (@ctz(inst.group.op3)) {
11285 else => .{ .convert_float_integer = inst.convert_float_integer },
11286 4 => .{ .float_data_processing_one_source = inst.float_data_processing_one_source },
11287 3 => .{ .float_compare = inst.float_compare },
11288 2 => .{ .float_immediate = inst.float_immediate },
11289 1 => .{ .float_data_processing_two_source = inst.float_data_processing_two_source },
11290 0 => switch (@as(u1, @truncate(inst.group.op3 >> 1))) {
11291 0b0 => .unallocated,
11292 0b1 => .{ .float_conditional_select = inst.float_conditional_select },
11293 },
11294 },
11295 },
11296 0b1 => .unallocated,
11297 },
11298 };
11299 }
1054911300 };
1055011301
1055111302 pub const AddSubtractOp = enum(u1) {
......@@ -10560,6 +11311,8 @@ pub const Instruction = packed union {
1056011311 ands = 0b11,
1056111312 };
1056211313
11314 pub const Nzcv = packed struct { v: bool, c: bool, z: bool, n: bool };
11315
1056311316 pub const Decoded = union(enum) {
1056411317 unallocated,
1056511318 reserved: Reserved,
......@@ -10588,7 +11341,7 @@ pub const Instruction = packed union {
1058811341 };
1058911342 }
1059011343
10591 /// C7.2.1 ABS (zero)
11344 /// C7.2.1 ABS
1059211345 pub fn abs(d: Register, n: Register) Instruction {
1059311346 switch (d.format) {
1059411347 else => unreachable,
......@@ -10598,7 +11351,7 @@ pub const Instruction = packed union {
1059811351 .abs = .{
1059911352 .Rd = d.alias.encode(.{ .V = true }),
1060011353 .Rn = n.alias.encode(.{ .V = true }),
10601 .size = .fromVectorSize(elem_size),
11354 .size = .fromScalarSize(elem_size),
1060211355 },
1060311356 } } };
1060411357 },
......@@ -10617,8 +11370,8 @@ pub const Instruction = packed union {
1061711370 }
1061811371 /// C6.2.1 ADC
1061911372 pub fn adc(d: Register, n: Register, m: Register) Instruction {
10620 const sf = d.format.integer;
10621 assert(n.format.integer == sf and m.format.integer == sf);
11373 const sf = d.format.general;
11374 assert(n.format.general == sf and m.format.general == sf);
1062211375 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
1062311376 .adc = .{
1062411377 .Rd = d.alias.encode(.{}),
......@@ -10630,8 +11383,8 @@ pub const Instruction = packed union {
1063011383 }
1063111384 /// C6.2.2 ADCS
1063211385 pub fn adcs(d: Register, n: Register, m: Register) Instruction {
10633 const sf = d.format.integer;
10634 assert(n.format.integer == sf and m.format.integer == sf);
11386 const sf = d.format.general;
11387 assert(n.format.general == sf and m.format.general == sf);
1063511388 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
1063611389 .adcs = .{
1063711390 .Rd = d.alias.encode(.{}),
......@@ -10657,11 +11410,11 @@ pub const Instruction = packed union {
1065711410 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1065811411 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1065911412 }) Instruction {
10660 const sf = d.format.integer;
10661 assert(n.format.integer == sf);
11413 const sf = d.format.general;
11414 assert(n.format.general == sf);
1066211415 form: switch (form) {
1066311416 .extended_register_explicit => |extended_register_explicit| {
10664 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());
11417 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
1066511418 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
1066611419 .add = .{
1066711420 .Rd = d.alias.encode(.{ .sp = true }),
......@@ -10703,7 +11456,7 @@ pub const Instruction = packed union {
1070311456 else
1070411457 .{ .shifted_register = .{ .register = register } },
1070511458 .shifted_register_explicit => |shifted_register_explicit| {
10706 assert(shifted_register_explicit.register.format.integer == sf);
11459 assert(shifted_register_explicit.register.format.general == sf);
1070711460 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
1070811461 .add = .{
1070911462 .Rd = d.alias.encode(.{}),
......@@ -10779,11 +11532,11 @@ pub const Instruction = packed union {
1077911532 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1078011533 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1078111534 }) Instruction {
10782 const sf = d.format.integer;
10783 assert(n.format.integer == sf);
11535 const sf = d.format.general;
11536 assert(n.format.general == sf);
1078411537 form: switch (form) {
1078511538 .extended_register_explicit => |extended_register_explicit| {
10786 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());
11539 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
1078711540 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
1078811541 .adds = .{
1078911542 .Rd = d.alias.encode(.{}),
......@@ -10825,7 +11578,7 @@ pub const Instruction = packed union {
1082511578 else
1082611579 .{ .shifted_register = .{ .register = register } },
1082711580 .shifted_register_explicit => |shifted_register_explicit| {
10828 assert(shifted_register_explicit.register.format.integer == sf);
11581 assert(shifted_register_explicit.register.format.general == sf);
1082911582 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
1083011583 .adds = .{
1083111584 .Rd = d.alias.encode(.{}),
......@@ -10856,7 +11609,7 @@ pub const Instruction = packed union {
1085611609 /// C7.2.6 ADDV
1085711610 pub fn addv(d: Register, n: Register) Instruction {
1085811611 const arrangement = n.format.vector;
10859 assert(arrangement.len() > 2 and d.format.scalar == arrangement.elemSize().toVectorSize());
11612 assert(arrangement.len() > 2 and d.format.scalar == arrangement.elemSize().toScalarSize());
1086011613 return .{ .data_processing_vector = .{ .simd_across_lanes = .{
1086111614 .addv = .{
1086211615 .Rd = d.alias.encode(.{ .V = true }),
......@@ -10868,7 +11621,7 @@ pub const Instruction = packed union {
1086811621 }
1086911622 /// C6.2.10 ADR
1087011623 pub fn adr(d: Register, label: i21) Instruction {
10871 assert(d.format.integer == .doubleword);
11624 assert(d.format.general == .doubleword);
1087211625 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{
1087311626 .adr = .{
1087411627 .Rd = d.alias.encode(.{}),
......@@ -10879,7 +11632,7 @@ pub const Instruction = packed union {
1087911632 }
1088011633 /// C6.2.11 ADRP
1088111634 pub fn adrp(d: Register, label: i33) Instruction {
10882 assert(d.format.integer == .doubleword);
11635 assert(d.format.general == .doubleword);
1088311636 const imm: i21 = @intCast(@shrExact(label, 12));
1088411637 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{
1088511638 .adrp = .{
......@@ -10900,8 +11653,8 @@ pub const Instruction = packed union {
1090011653 }) Instruction {
1090111654 switch (d.format) {
1090211655 else => unreachable,
10903 .integer => |sf| {
10904 assert(n.format.integer == sf);
11656 .general => |sf| {
11657 assert(n.format.general == sf);
1090511658 form: switch (form) {
1090611659 .immediate => |bitmask| {
1090711660 assert(bitmask.validImmediate(sf));
......@@ -10916,7 +11669,7 @@ pub const Instruction = packed union {
1091611669 },
1091711670 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1091811671 .shifted_register_explicit => |shifted_register_explicit| {
10919 assert(shifted_register_explicit.register.format.integer == sf);
11672 assert(shifted_register_explicit.register.format.general == sf);
1092011673 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1092111674 .@"and" = .{
1092211675 .Rd = d.alias.encode(.{}),
......@@ -10962,8 +11715,8 @@ pub const Instruction = packed union {
1096211715 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1096311716 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1096411717 }) Instruction {
10965 const sf = d.format.integer;
10966 assert(n.format.integer == sf);
11718 const sf = d.format.general;
11719 assert(n.format.general == sf);
1096711720 form: switch (form) {
1096811721 .immediate => |bitmask| {
1096911722 assert(bitmask.validImmediate(sf));
......@@ -10978,7 +11731,7 @@ pub const Instruction = packed union {
1097811731 },
1097911732 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1098011733 .shifted_register_explicit => |shifted_register_explicit| {
10981 assert(shifted_register_explicit.register.format.integer == sf);
11734 assert(shifted_register_explicit.register.format.general == sf);
1098211735 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1098311736 .ands = .{
1098411737 .Rd = d.alias.encode(.{}),
......@@ -11004,8 +11757,8 @@ pub const Instruction = packed union {
1100411757 }
1100511758 /// C6.2.18 ASRV
1100611759 pub fn asrv(d: Register, n: Register, m: Register) Instruction {
11007 const sf = d.format.integer;
11008 assert(n.format.integer == sf and m.format.integer == sf);
11760 const sf = d.format.general;
11761 assert(n.format.general == sf and m.format.general == sf);
1100911762 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1101011763 .asrv = .{
1101111764 .Rd = d.alias.encode(.{}),
......@@ -11041,8 +11794,8 @@ pub const Instruction = packed union {
1104111794 }
1104211795 /// C6.2.30 BFM
1104311796 pub fn bfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
11044 const sf = d.format.integer;
11045 assert(n.format.integer == sf and bitmask.validBitfield(sf));
11797 const sf = d.format.general;
11798 assert(n.format.general == sf and bitmask.validBitfield(sf));
1104611799 return .{ .data_processing_immediate = .{ .bitfield = .{
1104711800 .bfm = .{
1104811801 .Rd = d.alias.encode(.{}),
......@@ -11063,13 +11816,13 @@ pub const Instruction = packed union {
1106311816 }) Instruction {
1106411817 switch (d.format) {
1106511818 else => unreachable,
11066 .integer => |sf| {
11067 assert(n.format.integer == sf);
11819 .general => |sf| {
11820 assert(n.format.general == sf);
1106811821 form: switch (form) {
1106911822 else => unreachable,
1107011823 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1107111824 .shifted_register_explicit => |shifted_register_explicit| {
11072 assert(shifted_register_explicit.register.format.integer == sf);
11825 assert(shifted_register_explicit.register.format.general == sf);
1107311826 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1107411827 .bic = .{
1107511828 .Rd = d.alias.encode(.{}),
......@@ -11133,12 +11886,12 @@ pub const Instruction = packed union {
1113311886 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1113411887 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1113511888 }) Instruction {
11136 const sf = d.format.integer;
11137 assert(n.format.integer == sf);
11889 const sf = d.format.general;
11890 assert(n.format.general == sf);
1113811891 form: switch (form) {
1113911892 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1114011893 .shifted_register_explicit => |shifted_register_explicit| {
11141 assert(shifted_register_explicit.register.format.integer == sf);
11894 assert(shifted_register_explicit.register.format.general == sf);
1114211895 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1114311896 .bics = .{
1114411897 .Rd = d.alias.encode(.{}),
......@@ -11209,14 +11962,14 @@ pub const Instruction = packed union {
1120911962 }
1121011963 /// C6.2.35 BLR
1121111964 pub fn blr(n: Register) Instruction {
11212 assert(n.format.integer == .doubleword);
11965 assert(n.format.general == .doubleword);
1121311966 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
1121411967 .blr = .{ .Rn = n.alias.encode(.{}) },
1121511968 } } };
1121611969 }
1121711970 /// C6.2.37 BR
1121811971 pub fn br(n: Register) Instruction {
11219 assert(n.format.integer == .doubleword);
11972 assert(n.format.general == .doubleword);
1122011973 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
1122111974 .br = .{ .Rn = n.alias.encode(.{}) },
1122211975 } } };
......@@ -11233,7 +11986,7 @@ pub const Instruction = packed union {
1123311986 .cbnz = .{
1123411987 .Rt = t.alias.encode(.{}),
1123511988 .imm19 = @intCast(@shrExact(label, 2)),
11236 .sf = t.format.integer,
11989 .sf = t.format.general,
1123711990 },
1123811991 } } };
1123911992 }
......@@ -11243,7 +11996,7 @@ pub const Instruction = packed union {
1124311996 .cbz = .{
1124411997 .Rt = t.alias.encode(.{}),
1124511998 .imm19 = @intCast(@shrExact(label, 2)),
11246 .sf = t.format.integer,
11999 .sf = t.format.general,
1124712000 },
1124812001 } } };
1124912002 }
......@@ -11252,13 +12005,13 @@ pub const Instruction = packed union {
1125212005 pub fn ccmn(
1125312006 n: Register,
1125412007 form: union(enum) { register: Register, immediate: u5 },
11255 nzcv: DataProcessingRegister.Nzcv,
12008 nzcv: Nzcv,
1125612009 cond: ConditionCode,
1125712010 ) Instruction {
11258 const sf = n.format.integer;
12011 const sf = n.format.general;
1125912012 switch (form) {
1126012013 .register => |m| {
11261 assert(m.format.integer == sf);
12014 assert(m.format.general == sf);
1126212015 return .{ .data_processing_register = .{ .conditional_compare_register = .{
1126312016 .ccmn = .{
1126412017 .nzcv = nzcv,
......@@ -11285,13 +12038,13 @@ pub const Instruction = packed union {
1128512038 pub fn ccmp(
1128612039 n: Register,
1128712040 form: union(enum) { register: Register, immediate: u5 },
11288 nzcv: DataProcessingRegister.Nzcv,
12041 nzcv: Nzcv,
1128912042 cond: ConditionCode,
1129012043 ) Instruction {
11291 const sf = n.format.integer;
12044 const sf = n.format.general;
1129212045 switch (form) {
1129312046 .register => |m| {
11294 assert(m.format.integer == sf);
12047 assert(m.format.general == sf);
1129512048 return .{ .data_processing_register = .{ .conditional_compare_register = .{
1129612049 .ccmp = .{
1129712050 .nzcv = nzcv,
......@@ -11321,10 +12074,22 @@ pub const Instruction = packed union {
1132112074 },
1132212075 } } };
1132312076 }
12077 /// C6.2.57 CLS
12078 pub fn cls(d: Register, n: Register) Instruction {
12079 const sf = d.format.general;
12080 assert(n.format.general == sf);
12081 return .{ .data_processing_register = .{ .data_processing_one_source = .{
12082 .cls = .{
12083 .Rd = d.alias.encode(.{}),
12084 .Rn = n.alias.encode(.{}),
12085 .sf = sf,
12086 },
12087 } } };
12088 }
1132412089 /// C6.2.58 CLZ
1132512090 pub fn clz(d: Register, n: Register) Instruction {
11326 const sf = d.format.integer;
11327 assert(n.format.integer == sf);
12091 const sf = d.format.general;
12092 assert(n.format.general == sf);
1132812093 return .{ .data_processing_register = .{ .data_processing_one_source = .{
1132912094 .clz = .{
1133012095 .Rd = d.alias.encode(.{}),
......@@ -11344,7 +12109,7 @@ pub const Instruction = packed union {
1134412109 .cmeq = .{
1134512110 .Rd = d.alias.encode(.{ .V = true }),
1134612111 .Rn = n.alias.encode(.{ .V = true }),
11347 .size = .fromVectorSize(elem_size),
12112 .size = .fromScalarSize(elem_size),
1134812113 },
1134912114 } } };
1135012115 },
......@@ -11373,7 +12138,7 @@ pub const Instruction = packed union {
1137312138 .cmge = .{
1137412139 .Rd = d.alias.encode(.{ .V = true }),
1137512140 .Rn = n.alias.encode(.{ .V = true }),
11376 .size = .fromVectorSize(elem_size),
12141 .size = .fromScalarSize(elem_size),
1137712142 },
1137812143 } } };
1137912144 },
......@@ -11402,7 +12167,7 @@ pub const Instruction = packed union {
1140212167 .cmgt = .{
1140312168 .Rd = d.alias.encode(.{ .V = true }),
1140412169 .Rn = n.alias.encode(.{ .V = true }),
11405 .size = .fromVectorSize(elem_size),
12170 .size = .fromScalarSize(elem_size),
1140612171 },
1140712172 } } };
1140812173 },
......@@ -11431,7 +12196,7 @@ pub const Instruction = packed union {
1143112196 .cmle = .{
1143212197 .Rd = d.alias.encode(.{ .V = true }),
1143312198 .Rn = n.alias.encode(.{ .V = true }),
11434 .size = .fromVectorSize(elem_size),
12199 .size = .fromScalarSize(elem_size),
1143512200 },
1143612201 } } };
1143712202 },
......@@ -11460,7 +12225,7 @@ pub const Instruction = packed union {
1146012225 .cmlt = .{
1146112226 .Rd = d.alias.encode(.{ .V = true }),
1146212227 .Rn = n.alias.encode(.{ .V = true }),
11463 .size = .fromVectorSize(elem_size),
12228 .size = .fromScalarSize(elem_size),
1146412229 },
1146512230 } } };
1146612231 },
......@@ -11493,8 +12258,8 @@ pub const Instruction = packed union {
1149312258 }
1149412259 /// C6.2.103 CSEL
1149512260 pub fn csel(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11496 const sf = d.format.integer;
11497 assert(n.format.integer == sf and m.format.integer == sf);
12261 const sf = d.format.general;
12262 assert(n.format.general == sf and m.format.general == sf);
1149812263 return .{ .data_processing_register = .{ .conditional_select = .{
1149912264 .csel = .{
1150012265 .Rd = d.alias.encode(.{}),
......@@ -11507,8 +12272,8 @@ pub const Instruction = packed union {
1150712272 }
1150812273 /// C6.2.106 CSINC
1150912274 pub fn csinc(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11510 const sf = d.format.integer;
11511 assert(n.format.integer == sf and m.format.integer == sf);
12275 const sf = d.format.general;
12276 assert(n.format.general == sf and m.format.general == sf);
1151212277 return .{ .data_processing_register = .{ .conditional_select = .{
1151312278 .csinc = .{
1151412279 .Rd = d.alias.encode(.{}),
......@@ -11521,8 +12286,8 @@ pub const Instruction = packed union {
1152112286 }
1152212287 /// C6.2.107 CSINV
1152312288 pub fn csinv(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11524 const sf = d.format.integer;
11525 assert(n.format.integer == sf and m.format.integer == sf);
12289 const sf = d.format.general;
12290 assert(n.format.general == sf and m.format.general == sf);
1152612291 return .{ .data_processing_register = .{ .conditional_select = .{
1152712292 .csinv = .{
1152812293 .Rd = d.alias.encode(.{}),
......@@ -11535,8 +12300,8 @@ pub const Instruction = packed union {
1153512300 }
1153612301 /// C6.2.108 CSNEG
1153712302 pub fn csneg(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11538 const sf = d.format.integer;
11539 assert(n.format.integer == sf and m.format.integer == sf);
12303 const sf = d.format.general;
12304 assert(n.format.general == sf and m.format.general == sf);
1154012305 return .{ .data_processing_register = .{ .conditional_select = .{
1154112306 .csneg = .{
1154212307 .Rd = d.alias.encode(.{}),
......@@ -11579,7 +12344,7 @@ pub const Instruction = packed union {
1157912344 switch (d.format) {
1158012345 else => unreachable,
1158112346 .scalar => |elem_size| {
11582 assert(@intFromEnum(elem_size) <= @intFromEnum(Register.VectorSize.double) and elem_size == n.format.element.size);
12347 assert(@intFromEnum(elem_size) <= @intFromEnum(Register.ScalarSize.double) and elem_size == n.format.element.size);
1158312348 return .{ .data_processing_vector = .{ .simd_scalar_copy = .{
1158412349 .dup = .{
1158512350 .Rd = d.alias.encode(.{ .V = true }),
......@@ -11594,7 +12359,7 @@ pub const Instruction = packed union {
1159412359 switch (n.format) {
1159512360 else => unreachable,
1159612361 .element => |element| {
11597 assert(elem_size.toVectorSize() == element.size);
12362 assert(elem_size.toScalarSize() == element.size);
1159812363 return .{ .data_processing_vector = .{ .simd_copy = .{
1159912364 .dup = .{
1160012365 .Rd = d.alias.encode(.{ .V = true }),
......@@ -11605,8 +12370,8 @@ pub const Instruction = packed union {
1160512370 },
1160612371 } } };
1160712372 },
11608 .integer => |sf| {
11609 assert(sf == @as(Register.IntegerSize, switch (elem_size) {
12373 .general => |sf| {
12374 assert(sf == @as(Register.GeneralSize, switch (elem_size) {
1161012375 .byte, .half, .single => .word,
1161112376 .double => .doubleword,
1161212377 }));
......@@ -11630,12 +12395,12 @@ pub const Instruction = packed union {
1163012395 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1163112396 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1163212397 }) Instruction {
11633 const sf = d.format.integer;
11634 assert(n.format.integer == sf);
12398 const sf = d.format.general;
12399 assert(n.format.general == sf);
1163512400 form: switch (form) {
1163612401 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1163712402 .shifted_register_explicit => |shifted_register_explicit| {
11638 assert(shifted_register_explicit.register.format.integer == sf);
12403 assert(shifted_register_explicit.register.format.general == sf);
1163912404 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1164012405 .eon = .{
1164112406 .Rd = d.alias.encode(.{}),
......@@ -11670,8 +12435,8 @@ pub const Instruction = packed union {
1167012435 }) Instruction {
1167112436 switch (d.format) {
1167212437 else => unreachable,
11673 .integer => |sf| {
11674 assert(n.format.integer == sf);
12438 .general => |sf| {
12439 assert(n.format.general == sf);
1167512440 form: switch (form) {
1167612441 .immediate => |bitmask| {
1167712442 assert(bitmask.validImmediate(sf));
......@@ -11686,7 +12451,7 @@ pub const Instruction = packed union {
1168612451 },
1168712452 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1168812453 .shifted_register_explicit => |shifted_register_explicit| {
11689 assert(shifted_register_explicit.register.format.integer == sf);
12454 assert(shifted_register_explicit.register.format.general == sf);
1169012455 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1169112456 .eor = .{
1169212457 .Rd = d.alias.encode(.{}),
......@@ -11726,8 +12491,8 @@ pub const Instruction = packed union {
1172612491 }
1172712492 /// C6.2.124 EXTR
1172812493 pub fn extr(d: Register, n: Register, m: Register, lsb: u6) Instruction {
11729 const sf = d.format.integer;
11730 assert(n.format.integer == sf and m.format.integer == sf);
12494 const sf = d.format.general;
12495 assert(n.format.general == sf and m.format.general == sf);
1173112496 return .{ .data_processing_immediate = .{ .extract = .{
1173212497 .extr = .{
1173312498 .Rd = d.alias.encode(.{}),
......@@ -11774,7 +12539,7 @@ pub const Instruction = packed union {
1177412539 .fabs = .{
1177512540 .Rd = d.alias.encode(.{ .V = true }),
1177612541 .Rn = n.alias.encode(.{ .V = true }),
11777 .ftype = .fromVectorSize(ftype),
12542 .ftype = .fromScalarSize(ftype),
1177812543 },
1177912544 } } };
1178012545 },
......@@ -11789,7 +12554,7 @@ pub const Instruction = packed union {
1178912554 .Rd = d.alias.encode(.{ .V = true }),
1179012555 .Rn = n.alias.encode(.{ .V = true }),
1179112556 .Rm = m.alias.encode(.{ .V = true }),
11792 .ftype = .fromVectorSize(ftype),
12557 .ftype = .fromScalarSize(ftype),
1179312558 },
1179412559 } } };
1179512560 }
......@@ -11814,7 +12579,7 @@ pub const Instruction = packed union {
1181412579 .fcmeq = .{
1181512580 .Rd = d.alias.encode(.{ .V = true }),
1181612581 .Rn = n.alias.encode(.{ .V = true }),
11817 .sz = .fromVectorSize(ftype),
12582 .sz = .fromScalarSize(ftype),
1181812583 },
1181912584 } } },
1182012585 }
......@@ -11865,7 +12630,7 @@ pub const Instruction = packed union {
1186512630 .fcmge = .{
1186612631 .Rd = d.alias.encode(.{ .V = true }),
1186712632 .Rn = n.alias.encode(.{ .V = true }),
11868 .sz = .fromVectorSize(ftype),
12633 .sz = .fromScalarSize(ftype),
1186912634 },
1187012635 } } },
1187112636 }
......@@ -11916,7 +12681,7 @@ pub const Instruction = packed union {
1191612681 .fcmgt = .{
1191712682 .Rd = d.alias.encode(.{ .V = true }),
1191812683 .Rn = n.alias.encode(.{ .V = true }),
11919 .sz = .fromVectorSize(ftype),
12684 .sz = .fromScalarSize(ftype),
1192012685 },
1192112686 } } },
1192212687 }
......@@ -11967,7 +12732,7 @@ pub const Instruction = packed union {
1196712732 .fcmle = .{
1196812733 .Rd = d.alias.encode(.{ .V = true }),
1196912734 .Rn = n.alias.encode(.{ .V = true }),
11970 .sz = .fromVectorSize(ftype),
12735 .sz = .fromScalarSize(ftype),
1197112736 },
1197212737 } } },
1197312738 }
......@@ -12018,7 +12783,7 @@ pub const Instruction = packed union {
1201812783 .fcmlt = .{
1201912784 .Rd = d.alias.encode(.{ .V = true }),
1202012785 .Rn = n.alias.encode(.{ .V = true }),
12021 .sz = .fromVectorSize(ftype),
12786 .sz = .fromScalarSize(ftype),
1202212787 },
1202312788 } } },
1202412789 }
......@@ -12059,7 +12824,7 @@ pub const Instruction = packed union {
1205912824 .opc0 = .register,
1206012825 .Rn = n.alias.encode(.{ .V = true }),
1206112826 .Rm = m.alias.encode(.{ .V = true }),
12062 .ftype = .fromVectorSize(ftype),
12827 .ftype = .fromScalarSize(ftype),
1206312828 },
1206412829 } } };
1206512830 },
......@@ -12068,7 +12833,7 @@ pub const Instruction = packed union {
1206812833 .opc0 = .register,
1206912834 .Rn = n.alias.encode(.{ .V = true }),
1207012835 .Rm = @enumFromInt(0b00000),
12071 .ftype = .fromVectorSize(ftype),
12836 .ftype = .fromScalarSize(ftype),
1207212837 },
1207312838 } } },
1207412839 }
......@@ -12084,7 +12849,7 @@ pub const Instruction = packed union {
1208412849 .opc0 = .zero,
1208512850 .Rn = n.alias.encode(.{ .V = true }),
1208612851 .Rm = m.alias.encode(.{ .V = true }),
12087 .ftype = .fromVectorSize(ftype),
12852 .ftype = .fromScalarSize(ftype),
1208812853 },
1208912854 } } };
1209012855 },
......@@ -12093,7 +12858,7 @@ pub const Instruction = packed union {
1209312858 .opc0 = .zero,
1209412859 .Rn = n.alias.encode(.{ .V = true }),
1209512860 .Rm = @enumFromInt(0b00000),
12096 .ftype = .fromVectorSize(ftype),
12861 .ftype = .fromScalarSize(ftype),
1209712862 },
1209812863 } } },
1209912864 }
......@@ -12108,7 +12873,7 @@ pub const Instruction = packed union {
1210812873 .Rn = n.alias.encode(.{ .V = true }),
1210912874 .cond = cond,
1211012875 .Rm = m.alias.encode(.{ .V = true }),
12111 .ftype = .fromVectorSize(ftype),
12876 .ftype = .fromScalarSize(ftype),
1211212877 },
1211312878 } } };
1211412879 }
......@@ -12125,7 +12890,7 @@ pub const Instruction = packed union {
1212512890 .double => .double,
1212612891 .half => .half,
1212712892 },
12128 .ftype = .fromVectorSize(n.format.scalar),
12893 .ftype = .fromScalarSize(n.format.scalar),
1212912894 },
1213012895 } } };
1213112896 }
......@@ -12134,11 +12899,11 @@ pub const Instruction = packed union {
1213412899 pub fn fcvtas(d: Register, n: Register) Instruction {
1213512900 switch (d.format) {
1213612901 else => unreachable,
12137 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12902 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1213812903 .fcvtas = .{
1213912904 .Rd = d.alias.encode(.{}),
1214012905 .Rn = n.alias.encode(.{ .V = true }),
12141 .ftype = .fromVectorSize(n.format.scalar),
12906 .ftype = .fromScalarSize(n.format.scalar),
1214212907 .sf = sf,
1214312908 },
1214412909 } } },
......@@ -12158,7 +12923,7 @@ pub const Instruction = packed union {
1215812923 .fcvtas = .{
1215912924 .Rd = d.alias.encode(.{ .V = true }),
1216012925 .Rn = n.alias.encode(.{ .V = true }),
12161 .sz = .fromVectorSize(elem_size),
12926 .sz = .fromScalarSize(elem_size),
1216212927 },
1216312928 } } },
1216412929 }
......@@ -12192,11 +12957,11 @@ pub const Instruction = packed union {
1219212957 pub fn fcvtau(d: Register, n: Register) Instruction {
1219312958 switch (d.format) {
1219412959 else => unreachable,
12195 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12960 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1219612961 .fcvtau = .{
1219712962 .Rd = d.alias.encode(.{}),
1219812963 .Rn = n.alias.encode(.{ .V = true }),
12199 .ftype = .fromVectorSize(n.format.scalar),
12964 .ftype = .fromScalarSize(n.format.scalar),
1220012965 .sf = sf,
1220112966 },
1220212967 } } },
......@@ -12216,7 +12981,7 @@ pub const Instruction = packed union {
1221612981 .fcvtau = .{
1221712982 .Rd = d.alias.encode(.{ .V = true }),
1221812983 .Rn = n.alias.encode(.{ .V = true }),
12219 .sz = .fromVectorSize(elem_size),
12984 .sz = .fromScalarSize(elem_size),
1222012985 },
1222112986 } } },
1222212987 }
......@@ -12250,11 +13015,11 @@ pub const Instruction = packed union {
1225013015 pub fn fcvtms(d: Register, n: Register) Instruction {
1225113016 switch (d.format) {
1225213017 else => unreachable,
12253 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13018 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1225413019 .fcvtms = .{
1225513020 .Rd = d.alias.encode(.{}),
1225613021 .Rn = n.alias.encode(.{ .V = true }),
12257 .ftype = .fromVectorSize(n.format.scalar),
13022 .ftype = .fromScalarSize(n.format.scalar),
1225813023 .sf = sf,
1225913024 },
1226013025 } } },
......@@ -12274,7 +13039,7 @@ pub const Instruction = packed union {
1227413039 .fcvtms = .{
1227513040 .Rd = d.alias.encode(.{ .V = true }),
1227613041 .Rn = n.alias.encode(.{ .V = true }),
12277 .sz = .fromVectorSize(elem_size),
13042 .sz = .fromScalarSize(elem_size),
1227813043 },
1227913044 } } },
1228013045 }
......@@ -12308,11 +13073,11 @@ pub const Instruction = packed union {
1230813073 pub fn fcvtmu(d: Register, n: Register) Instruction {
1230913074 switch (d.format) {
1231013075 else => unreachable,
12311 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13076 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1231213077 .fcvtmu = .{
1231313078 .Rd = d.alias.encode(.{}),
1231413079 .Rn = n.alias.encode(.{ .V = true }),
12315 .ftype = .fromVectorSize(n.format.scalar),
13080 .ftype = .fromScalarSize(n.format.scalar),
1231613081 .sf = sf,
1231713082 },
1231813083 } } },
......@@ -12332,7 +13097,7 @@ pub const Instruction = packed union {
1233213097 .fcvtmu = .{
1233313098 .Rd = d.alias.encode(.{ .V = true }),
1233413099 .Rn = n.alias.encode(.{ .V = true }),
12335 .sz = .fromVectorSize(elem_size),
13100 .sz = .fromScalarSize(elem_size),
1233613101 },
1233713102 } } },
1233813103 }
......@@ -12366,11 +13131,11 @@ pub const Instruction = packed union {
1236613131 pub fn fcvtns(d: Register, n: Register) Instruction {
1236713132 switch (d.format) {
1236813133 else => unreachable,
12369 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13134 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1237013135 .fcvtns = .{
1237113136 .Rd = d.alias.encode(.{}),
1237213137 .Rn = n.alias.encode(.{ .V = true }),
12373 .ftype = .fromVectorSize(n.format.scalar),
13138 .ftype = .fromScalarSize(n.format.scalar),
1237413139 .sf = sf,
1237513140 },
1237613141 } } },
......@@ -12390,7 +13155,7 @@ pub const Instruction = packed union {
1239013155 .fcvtns = .{
1239113156 .Rd = d.alias.encode(.{ .V = true }),
1239213157 .Rn = n.alias.encode(.{ .V = true }),
12393 .sz = .fromVectorSize(elem_size),
13158 .sz = .fromScalarSize(elem_size),
1239413159 },
1239513160 } } },
1239613161 }
......@@ -12424,11 +13189,11 @@ pub const Instruction = packed union {
1242413189 pub fn fcvtnu(d: Register, n: Register) Instruction {
1242513190 switch (d.format) {
1242613191 else => unreachable,
12427 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13192 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1242813193 .fcvtnu = .{
1242913194 .Rd = d.alias.encode(.{}),
1243013195 .Rn = n.alias.encode(.{ .V = true }),
12431 .ftype = .fromVectorSize(n.format.scalar),
13196 .ftype = .fromScalarSize(n.format.scalar),
1243213197 .sf = sf,
1243313198 },
1243413199 } } },
......@@ -12448,7 +13213,7 @@ pub const Instruction = packed union {
1244813213 .fcvtnu = .{
1244913214 .Rd = d.alias.encode(.{ .V = true }),
1245013215 .Rn = n.alias.encode(.{ .V = true }),
12451 .sz = .fromVectorSize(elem_size),
13216 .sz = .fromScalarSize(elem_size),
1245213217 },
1245313218 } } },
1245413219 }
......@@ -12482,11 +13247,11 @@ pub const Instruction = packed union {
1248213247 pub fn fcvtps(d: Register, n: Register) Instruction {
1248313248 switch (d.format) {
1248413249 else => unreachable,
12485 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13250 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1248613251 .fcvtps = .{
1248713252 .Rd = d.alias.encode(.{}),
1248813253 .Rn = n.alias.encode(.{ .V = true }),
12489 .ftype = .fromVectorSize(n.format.scalar),
13254 .ftype = .fromScalarSize(n.format.scalar),
1249013255 .sf = sf,
1249113256 },
1249213257 } } },
......@@ -12506,7 +13271,7 @@ pub const Instruction = packed union {
1250613271 .fcvtps = .{
1250713272 .Rd = d.alias.encode(.{ .V = true }),
1250813273 .Rn = n.alias.encode(.{ .V = true }),
12509 .sz = .fromVectorSize(elem_size),
13274 .sz = .fromScalarSize(elem_size),
1251013275 },
1251113276 } } },
1251213277 }
......@@ -12540,11 +13305,11 @@ pub const Instruction = packed union {
1254013305 pub fn fcvtpu(d: Register, n: Register) Instruction {
1254113306 switch (d.format) {
1254213307 else => unreachable,
12543 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13308 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1254413309 .fcvtpu = .{
1254513310 .Rd = d.alias.encode(.{}),
1254613311 .Rn = n.alias.encode(.{ .V = true }),
12547 .ftype = .fromVectorSize(n.format.scalar),
13312 .ftype = .fromScalarSize(n.format.scalar),
1254813313 .sf = sf,
1254913314 },
1255013315 } } },
......@@ -12564,7 +13329,7 @@ pub const Instruction = packed union {
1256413329 .fcvtpu = .{
1256513330 .Rd = d.alias.encode(.{ .V = true }),
1256613331 .Rn = n.alias.encode(.{ .V = true }),
12567 .sz = .fromVectorSize(elem_size),
13332 .sz = .fromScalarSize(elem_size),
1256813333 },
1256913334 } } },
1257013335 }
......@@ -12598,11 +13363,11 @@ pub const Instruction = packed union {
1259813363 pub fn fcvtzs(d: Register, n: Register) Instruction {
1259913364 switch (d.format) {
1260013365 else => unreachable,
12601 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13366 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1260213367 .fcvtzs = .{
1260313368 .Rd = d.alias.encode(.{}),
1260413369 .Rn = n.alias.encode(.{ .V = true }),
12605 .ftype = .fromVectorSize(n.format.scalar),
13370 .ftype = .fromScalarSize(n.format.scalar),
1260613371 .sf = sf,
1260713372 },
1260813373 } } },
......@@ -12622,7 +13387,7 @@ pub const Instruction = packed union {
1262213387 .fcvtzs = .{
1262313388 .Rd = d.alias.encode(.{ .V = true }),
1262413389 .Rn = n.alias.encode(.{ .V = true }),
12625 .sz = .fromVectorSize(elem_size),
13390 .sz = .fromScalarSize(elem_size),
1262613391 },
1262713392 } } },
1262813393 }
......@@ -12656,11 +13421,11 @@ pub const Instruction = packed union {
1265613421 pub fn fcvtzu(d: Register, n: Register) Instruction {
1265713422 switch (d.format) {
1265813423 else => unreachable,
12659 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13424 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1266013425 .fcvtzu = .{
1266113426 .Rd = d.alias.encode(.{}),
1266213427 .Rn = n.alias.encode(.{ .V = true }),
12663 .ftype = .fromVectorSize(n.format.scalar),
13428 .ftype = .fromScalarSize(n.format.scalar),
1266413429 .sf = sf,
1266513430 },
1266613431 } } },
......@@ -12680,7 +13445,7 @@ pub const Instruction = packed union {
1268013445 .fcvtzu = .{
1268113446 .Rd = d.alias.encode(.{ .V = true }),
1268213447 .Rn = n.alias.encode(.{ .V = true }),
12683 .sz = .fromVectorSize(elem_size),
13448 .sz = .fromScalarSize(elem_size),
1268413449 },
1268513450 } } },
1268613451 }
......@@ -12718,13 +13483,13 @@ pub const Instruction = packed union {
1271813483 .Rd = d.alias.encode(.{ .V = true }),
1271913484 .Rn = n.alias.encode(.{ .V = true }),
1272013485 .Rm = m.alias.encode(.{ .V = true }),
12721 .ftype = .fromVectorSize(ftype),
13486 .ftype = .fromScalarSize(ftype),
1272213487 },
1272313488 } } };
1272413489 }
1272513490 /// C7.2.99 FJCVTZS
1272613491 pub fn fjcvtzs(d: Register, n: Register) Instruction {
12727 assert(d.format.integer == .word);
13492 assert(d.format.general == .word);
1272813493 assert(n.format.scalar == .double);
1272913494 return .{ .data_processing_vector = .{ .convert_float_integer = .{
1273013495 .fjcvtzs = .{
......@@ -12743,7 +13508,7 @@ pub const Instruction = packed union {
1274313508 .Rn = n.alias.encode(.{ .V = true }),
1274413509 .Rm = m.alias.encode(.{ .V = true }),
1274513510 .Ra = a.alias.encode(.{ .V = true }),
12746 .ftype = .fromVectorSize(ftype),
13511 .ftype = .fromScalarSize(ftype),
1274713512 },
1274813513 } } };
1274913514 }
......@@ -12756,7 +13521,7 @@ pub const Instruction = packed union {
1275613521 .Rd = d.alias.encode(.{ .V = true }),
1275713522 .Rn = n.alias.encode(.{ .V = true }),
1275813523 .Rm = m.alias.encode(.{ .V = true }),
12759 .ftype = .fromVectorSize(ftype),
13524 .ftype = .fromScalarSize(ftype),
1276013525 },
1276113526 } } };
1276213527 }
......@@ -12769,7 +13534,7 @@ pub const Instruction = packed union {
1276913534 .Rd = d.alias.encode(.{ .V = true }),
1277013535 .Rn = n.alias.encode(.{ .V = true }),
1277113536 .Rm = m.alias.encode(.{ .V = true }),
12772 .ftype = .fromVectorSize(ftype),
13537 .ftype = .fromScalarSize(ftype),
1277313538 },
1277413539 } } };
1277513540 }
......@@ -12782,7 +13547,7 @@ pub const Instruction = packed union {
1278213547 .Rd = d.alias.encode(.{ .V = true }),
1278313548 .Rn = n.alias.encode(.{ .V = true }),
1278413549 .Rm = m.alias.encode(.{ .V = true }),
12785 .ftype = .fromVectorSize(ftype),
13550 .ftype = .fromScalarSize(ftype),
1278613551 },
1278713552 } } };
1278813553 }
......@@ -12795,7 +13560,7 @@ pub const Instruction = packed union {
1279513560 .Rd = d.alias.encode(.{ .V = true }),
1279613561 .Rn = n.alias.encode(.{ .V = true }),
1279713562 .Rm = m.alias.encode(.{ .V = true }),
12798 .ftype = .fromVectorSize(ftype),
13563 .ftype = .fromScalarSize(ftype),
1279913564 },
1280013565 } } };
1280113566 }
......@@ -12807,31 +13572,39 @@ pub const Instruction = packed union {
1280713572 switch (form) {
1280813573 .immediate => |immediate| {
1280913574 const repr: std.math.FloatRepr(f16) = @bitCast(immediate);
12810 const imm: u8 = @bitCast(@as(packed struct(u8) {
12811 mantissa: u4,
12812 exponent: i3,
12813 sign: std.math.Sign,
12814 }, .{
13575 const imm: DataProcessingVector.FloatImmediate.Fmov.Imm8 = .{
1281513576 .mantissa = @intCast(@shrExact(repr.mantissa, 6)),
1281613577 .exponent = @intCast(repr.exponent.unbias() - 1),
1281713578 .sign = repr.sign,
12818 }));
13579 };
1281913580 switch (d.format) {
1282013581 else => unreachable,
1282113582 .scalar => |ftype| return .{ .data_processing_vector = .{ .float_immediate = .{
1282213583 .fmov = .{
1282313584 .Rd = d.alias.encode(.{ .V = true }),
1282413585 .imm8 = imm,
12825 .ftype = .fromVectorSize(ftype),
13586 .ftype = .fromScalarSize(ftype),
1282613587 },
1282713588 } } },
1282813589 .vector => |arrangement| {
12829 assert(arrangement.len() > 1 and arrangement.elemSize() != .byte);
13590 const elem_size = arrangement.elemSize();
13591 assert(arrangement.len() > 1);
13592 const mod_imm = imm.toModified();
1283013593 return .{ .data_processing_vector = .{ .simd_modified_immediate = .{
1283113594 .fmov = .{
1283213595 .Rd = d.alias.encode(.{ .V = true }),
12833 .imm5 = @truncate(imm >> 0),
12834 .imm3 = @intCast(imm >> 5),
13596 .imm5 = mod_imm.imm5,
13597 .o2 = switch (elem_size) {
13598 .byte => unreachable,
13599 .half => 0b1,
13600 .single, .double => 0b0,
13601 },
13602 .imm3 = mod_imm.imm3,
13603 .op = switch (elem_size) {
13604 .byte => unreachable,
13605 .half, .single => 0b0,
13606 .double => 0b1,
13607 },
1283513608 .Q = arrangement.size(),
1283613609 },
1283713610 } } };
......@@ -12840,7 +13613,7 @@ pub const Instruction = packed union {
1284013613 },
1284113614 .register => |n| switch (d.format) {
1284213615 else => unreachable,
12843 .integer => |sf| switch (n.format) {
13616 .general => |sf| switch (n.format) {
1284413617 else => unreachable,
1284513618 .scalar => |ftype| {
1284613619 switch (ftype) {
......@@ -12855,7 +13628,7 @@ pub const Instruction = packed union {
1285513628 .Rn = n.alias.encode(.{ .V = true }),
1285613629 .opcode = .float_to_integer,
1285713630 .rmode = .@"0",
12858 .ftype = .fromVectorSize(ftype),
13631 .ftype = .fromScalarSize(ftype),
1285913632 .sf = sf,
1286013633 },
1286113634 } } };
......@@ -12879,8 +13652,7 @@ pub const Instruction = packed union {
1287913652 },
1288013653 .scalar => |ftype| switch (n.format) {
1288113654 else => unreachable,
12882 .integer => {
12883 const sf = n.format.integer;
13655 .general => |sf| {
1288413656 switch (ftype) {
1288513657 else => unreachable,
1288613658 .half => {},
......@@ -12893,7 +13665,7 @@ pub const Instruction = packed union {
1289313665 .Rn = n.alias.encode(.{}),
1289413666 .opcode = .integer_to_float,
1289513667 .rmode = .@"0",
12896 .ftype = .fromVectorSize(ftype),
13668 .ftype = .fromScalarSize(ftype),
1289713669 .sf = sf,
1289813670 },
1289913671 } } };
......@@ -12904,14 +13676,14 @@ pub const Instruction = packed union {
1290413676 .fmov = .{
1290513677 .Rd = d.alias.encode(.{ .V = true }),
1290613678 .Rn = n.alias.encode(.{ .V = true }),
12907 .ftype = .fromVectorSize(ftype),
13679 .ftype = .fromScalarSize(ftype),
1290813680 },
1290913681 } } };
1291013682 },
1291113683 },
1291213684 .element => |element| switch (n.format) {
1291313685 else => unreachable,
12914 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
13686 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1291513687 .fmov = .{
1291613688 .Rd = d.alias.encode(.{ .V = true }),
1291713689 .Rn = n.alias.encode(.{}),
......@@ -12941,7 +13713,7 @@ pub const Instruction = packed union {
1294113713 .Rn = n.alias.encode(.{ .V = true }),
1294213714 .Rm = m.alias.encode(.{ .V = true }),
1294313715 .Ra = a.alias.encode(.{ .V = true }),
12944 .ftype = .fromVectorSize(ftype),
13716 .ftype = .fromScalarSize(ftype),
1294513717 },
1294613718 } } };
1294713719 }
......@@ -12954,7 +13726,7 @@ pub const Instruction = packed union {
1295413726 .Rd = d.alias.encode(.{ .V = true }),
1295513727 .Rn = n.alias.encode(.{ .V = true }),
1295613728 .Rm = m.alias.encode(.{ .V = true }),
12957 .ftype = .fromVectorSize(ftype),
13729 .ftype = .fromScalarSize(ftype),
1295813730 },
1295913731 } } };
1296013732 }
......@@ -12990,7 +13762,7 @@ pub const Instruction = packed union {
1299013762 .fneg = .{
1299113763 .Rd = d.alias.encode(.{ .V = true }),
1299213764 .Rn = n.alias.encode(.{ .V = true }),
12993 .ftype = .fromVectorSize(ftype),
13765 .ftype = .fromScalarSize(ftype),
1299413766 },
1299513767 } } };
1299613768 },
......@@ -13006,7 +13778,7 @@ pub const Instruction = packed union {
1300613778 .Rn = n.alias.encode(.{ .V = true }),
1300713779 .Rm = m.alias.encode(.{ .V = true }),
1300813780 .Ra = a.alias.encode(.{ .V = true }),
13009 .ftype = .fromVectorSize(ftype),
13781 .ftype = .fromScalarSize(ftype),
1301013782 },
1301113783 } } };
1301213784 }
......@@ -13020,7 +13792,7 @@ pub const Instruction = packed union {
1302013792 .Rn = n.alias.encode(.{ .V = true }),
1302113793 .Rm = m.alias.encode(.{ .V = true }),
1302213794 .Ra = a.alias.encode(.{ .V = true }),
13023 .ftype = .fromVectorSize(ftype),
13795 .ftype = .fromScalarSize(ftype),
1302413796 },
1302513797 } } };
1302613798 }
......@@ -13033,7 +13805,7 @@ pub const Instruction = packed union {
1303313805 .Rd = d.alias.encode(.{ .V = true }),
1303413806 .Rn = n.alias.encode(.{ .V = true }),
1303513807 .Rm = m.alias.encode(.{ .V = true }),
13036 .ftype = .fromVectorSize(ftype),
13808 .ftype = .fromScalarSize(ftype),
1303713809 },
1303813810 } } };
1303913811 }
......@@ -13069,7 +13841,7 @@ pub const Instruction = packed union {
1306913841 .frinta = .{
1307013842 .Rd = d.alias.encode(.{ .V = true }),
1307113843 .Rn = n.alias.encode(.{ .V = true }),
13072 .ftype = .fromVectorSize(ftype),
13844 .ftype = .fromScalarSize(ftype),
1307313845 },
1307413846 } } };
1307513847 },
......@@ -13107,7 +13879,7 @@ pub const Instruction = packed union {
1310713879 .frinti = .{
1310813880 .Rd = d.alias.encode(.{ .V = true }),
1310913881 .Rn = n.alias.encode(.{ .V = true }),
13110 .ftype = .fromVectorSize(ftype),
13882 .ftype = .fromScalarSize(ftype),
1311113883 },
1311213884 } } };
1311313885 },
......@@ -13145,7 +13917,7 @@ pub const Instruction = packed union {
1314513917 .frintm = .{
1314613918 .Rd = d.alias.encode(.{ .V = true }),
1314713919 .Rn = n.alias.encode(.{ .V = true }),
13148 .ftype = .fromVectorSize(ftype),
13920 .ftype = .fromScalarSize(ftype),
1314913921 },
1315013922 } } };
1315113923 },
......@@ -13183,7 +13955,7 @@ pub const Instruction = packed union {
1318313955 .frintn = .{
1318413956 .Rd = d.alias.encode(.{ .V = true }),
1318513957 .Rn = n.alias.encode(.{ .V = true }),
13186 .ftype = .fromVectorSize(ftype),
13958 .ftype = .fromScalarSize(ftype),
1318713959 },
1318813960 } } };
1318913961 },
......@@ -13221,7 +13993,7 @@ pub const Instruction = packed union {
1322113993 .frintp = .{
1322213994 .Rd = d.alias.encode(.{ .V = true }),
1322313995 .Rn = n.alias.encode(.{ .V = true }),
13224 .ftype = .fromVectorSize(ftype),
13996 .ftype = .fromScalarSize(ftype),
1322513997 },
1322613998 } } };
1322713999 },
......@@ -13259,7 +14031,7 @@ pub const Instruction = packed union {
1325914031 .frintx = .{
1326014032 .Rd = d.alias.encode(.{ .V = true }),
1326114033 .Rn = n.alias.encode(.{ .V = true }),
13262 .ftype = .fromVectorSize(ftype),
14034 .ftype = .fromScalarSize(ftype),
1326314035 },
1326414036 } } };
1326514037 },
......@@ -13297,7 +14069,7 @@ pub const Instruction = packed union {
1329714069 .frintz = .{
1329814070 .Rd = d.alias.encode(.{ .V = true }),
1329914071 .Rn = n.alias.encode(.{ .V = true }),
13300 .ftype = .fromVectorSize(ftype),
14072 .ftype = .fromScalarSize(ftype),
1330114073 },
1330214074 } } };
1330314075 },
......@@ -13335,7 +14107,7 @@ pub const Instruction = packed union {
1333514107 .fsqrt = .{
1333614108 .Rd = d.alias.encode(.{ .V = true }),
1333714109 .Rn = n.alias.encode(.{ .V = true }),
13338 .ftype = .fromVectorSize(ftype),
14110 .ftype = .fromScalarSize(ftype),
1333914111 },
1334014112 } } };
1334114113 },
......@@ -13350,7 +14122,7 @@ pub const Instruction = packed union {
1335014122 .Rd = d.alias.encode(.{ .V = true }),
1335114123 .Rn = n.alias.encode(.{ .V = true }),
1335214124 .Rm = m.alias.encode(.{ .V = true }),
13353 .ftype = .fromVectorSize(ftype),
14125 .ftype = .fromScalarSize(ftype),
1335414126 },
1335514127 } } };
1335614128 }
......@@ -13375,6 +14147,42 @@ pub const Instruction = packed union {
1337514147 .hvc = .{ .imm16 = imm },
1337614148 } } };
1337714149 }
14150 /// C7.2.175 INS (element)
14151 /// C7.2.176 INS (general)
14152 pub fn ins(d: Register, n: Register) Instruction {
14153 const elem_size = d.format.element.size;
14154 switch (n.format) {
14155 else => unreachable,
14156 .element => |element| {
14157 assert(elem_size == element.size);
14158 return .{ .data_processing_vector = .{ .simd_copy = .{
14159 .ins = .{
14160 .Rd = d.alias.encode(.{ .V = true }),
14161 .Rn = n.alias.encode(.{ .V = true }),
14162 .imm4 = .{ .element = element.index << @intCast(@intFromEnum(elem_size)) },
14163 .imm5 = (@as(u5, d.format.element.index) << 1 | @as(u5, 0b1) << 0) << @intFromEnum(elem_size),
14164 .op = .element,
14165 },
14166 } } };
14167 },
14168 .general => |general| {
14169 assert(general == @as(Register.GeneralSize, switch (elem_size) {
14170 else => unreachable,
14171 .byte, .half, .single => .word,
14172 .double => .doubleword,
14173 }));
14174 return .{ .data_processing_vector = .{ .simd_copy = .{
14175 .ins = .{
14176 .Rd = d.alias.encode(.{ .V = true }),
14177 .Rn = n.alias.encode(.{}),
14178 .imm4 = .{ .general = .general },
14179 .imm5 = (@as(u5, d.format.element.index) << 1 | @as(u5, 0b1) << 0) << @intFromEnum(elem_size),
14180 .op = .general,
14181 },
14182 } } };
14183 },
14184 }
14185 }
1337814186 /// C6.2.131 ISB
1337914187 pub fn isb(option: BranchExceptionGeneratingSystem.Barriers.Option) Instruction {
1338014188 return .{ .branch_exception_generating_system = .{ .barriers = .{
......@@ -13393,11 +14201,11 @@ pub const Instruction = packed union {
1339314201 }) Instruction {
1339414202 switch (t1.format) {
1339514203 else => unreachable,
13396 .integer => |sf| {
13397 assert(t2.format.integer == sf);
14204 .general => |sf| {
14205 assert(t2.format.general == sf);
1339814206 form: switch (form) {
1339914207 .post_index => |post_index| {
13400 assert(post_index.base.format.integer == .doubleword);
14208 assert(post_index.base.format.general == .doubleword);
1340114209 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{
1340214210 .ldp = .{
1340314211 .Rt = t1.alias.encode(.{}),
......@@ -13409,7 +14217,7 @@ pub const Instruction = packed union {
1340914217 } } } };
1341014218 },
1341114219 .pre_index => |pre_index| {
13412 assert(pre_index.base.format.integer == .doubleword);
14220 assert(pre_index.base.format.general == .doubleword);
1341314221 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{
1341414222 .ldp = .{
1341514223 .Rt = t1.alias.encode(.{}),
......@@ -13421,7 +14229,7 @@ pub const Instruction = packed union {
1342114229 } } } };
1342214230 },
1342314231 .signed_offset => |signed_offset| {
13424 assert(signed_offset.base.format.integer == .doubleword);
14232 assert(signed_offset.base.format.general == .doubleword);
1342514233 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{
1342614234 .ldp = .{
1342714235 .Rt = t1.alias.encode(.{}),
......@@ -13439,7 +14247,7 @@ pub const Instruction = packed union {
1343914247 assert(t2.format.scalar == vs);
1344014248 form: switch (form) {
1344114249 .post_index => |post_index| {
13442 assert(post_index.base.format.integer == .doubleword);
14250 assert(post_index.base.format.general == .doubleword);
1344314251 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{
1344414252 .ldp = .{
1344514253 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -13451,7 +14259,7 @@ pub const Instruction = packed union {
1345114259 } } } };
1345214260 },
1345314261 .signed_offset => |signed_offset| {
13454 assert(signed_offset.base.format.integer == .doubleword);
14262 assert(signed_offset.base.format.general == .doubleword);
1345514263 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{
1345614264 .ldp = .{
1345714265 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -13463,7 +14271,7 @@ pub const Instruction = packed union {
1346314271 } } } };
1346414272 },
1346514273 .pre_index => |pre_index| {
13466 assert(pre_index.base.format.integer == .doubleword);
14274 assert(pre_index.base.format.general == .doubleword);
1346714275 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{
1346814276 .ldp = .{
1346914277 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -13505,9 +14313,9 @@ pub const Instruction = packed union {
1350514313 }) Instruction {
1350614314 switch (t.format) {
1350714315 else => unreachable,
13508 .integer => |sf| form: switch (form) {
14316 .general => |sf| form: switch (form) {
1350914317 .post_index => |post_index| {
13510 assert(post_index.base.format.integer == .doubleword);
14318 assert(post_index.base.format.general == .doubleword);
1351114319 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1351214320 .ldr = .{
1351314321 .Rt = t.alias.encode(.{}),
......@@ -13518,7 +14326,7 @@ pub const Instruction = packed union {
1351814326 } } } };
1351914327 },
1352014328 .pre_index => |pre_index| {
13521 assert(pre_index.base.format.integer == .doubleword);
14329 assert(pre_index.base.format.general == .doubleword);
1352214330 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1352314331 .ldr = .{
1352414332 .Rt = t.alias.encode(.{}),
......@@ -13529,7 +14337,7 @@ pub const Instruction = packed union {
1352914337 } } } };
1353014338 },
1353114339 .unsigned_offset => |unsigned_offset| {
13532 assert(unsigned_offset.base.format.integer == .doubleword);
14340 assert(unsigned_offset.base.format.general == .doubleword);
1353314341 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1353414342 .ldr = .{
1353514343 .Rt = t.alias.encode(.{}),
......@@ -13548,8 +14356,8 @@ pub const Instruction = packed union {
1354814356 },
1354914357 } } } },
1355014358 .extended_register_explicit => |extended_register_explicit| {
13551 assert(extended_register_explicit.base.format.integer == .doubleword and
13552 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14359 assert(extended_register_explicit.base.format.general == .doubleword and
14360 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1355314361 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1355414362 .ldr = .{
1355514363 .Rt = t.alias.encode(.{}),
......@@ -13583,7 +14391,7 @@ pub const Instruction = packed union {
1358314391 },
1358414392 .scalar => |vs| form: switch (form) {
1358514393 .post_index => |post_index| {
13586 assert(post_index.base.format.integer == .doubleword);
14394 assert(post_index.base.format.general == .doubleword);
1358714395 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{
1358814396 .ldr = .{
1358914397 .Rt = t.alias.encode(.{ .V = true }),
......@@ -13595,7 +14403,7 @@ pub const Instruction = packed union {
1359514403 } } } };
1359614404 },
1359714405 .pre_index => |pre_index| {
13598 assert(pre_index.base.format.integer == .doubleword);
14406 assert(pre_index.base.format.general == .doubleword);
1359914407 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{
1360014408 .ldr = .{
1360114409 .Rt = t.alias.encode(.{ .V = true }),
......@@ -13607,7 +14415,7 @@ pub const Instruction = packed union {
1360714415 } } } };
1360814416 },
1360914417 .unsigned_offset => |unsigned_offset| {
13610 assert(unsigned_offset.base.format.integer == .doubleword);
14418 assert(unsigned_offset.base.format.general == .doubleword);
1361114419 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{
1361214420 .ldr = .{
1361314421 .Rt = t.alias.encode(.{ .V = true }),
......@@ -13627,14 +14435,13 @@ pub const Instruction = packed union {
1362714435 },
1362814436 } } } },
1362914437 .extended_register_explicit => |extended_register_explicit| {
13630 assert(extended_register_explicit.base.format.integer == .doubleword and
13631 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14438 assert(extended_register_explicit.base.format.general == .doubleword and
14439 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1363214440 return .{ .load_store = .{ .register_register_offset = .{ .vector = .{
1363314441 .ldr = .{
1363414442 .Rt = t.alias.encode(.{ .V = true }),
1363514443 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),
1363614444 .S = switch (vs) {
13637 else => unreachable,
1363814445 .byte => switch (extended_register_explicit.amount) {
1363914446 0 => false,
1364014447 else => unreachable,
......@@ -13697,10 +14504,10 @@ pub const Instruction = packed union {
1369714504 extend: LoadStore.RegisterRegisterOffset.Extend,
1369814505 },
1369914506 }) Instruction {
13700 assert(t.format.integer == .word);
14507 assert(t.format.general == .word);
1370114508 form: switch (form) {
1370214509 .post_index => |post_index| {
13703 assert(post_index.base.format.integer == .doubleword);
14510 assert(post_index.base.format.general == .doubleword);
1370414511 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1370514512 .ldrb = .{
1370614513 .Rt = t.alias.encode(.{}),
......@@ -13710,7 +14517,7 @@ pub const Instruction = packed union {
1371014517 } } } };
1371114518 },
1371214519 .pre_index => |pre_index| {
13713 assert(pre_index.base.format.integer == .doubleword);
14520 assert(pre_index.base.format.general == .doubleword);
1371414521 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1371514522 .ldrb = .{
1371614523 .Rt = t.alias.encode(.{}),
......@@ -13720,7 +14527,7 @@ pub const Instruction = packed union {
1372014527 } } } };
1372114528 },
1372214529 .unsigned_offset => |unsigned_offset| {
13723 assert(unsigned_offset.base.format.integer == .doubleword);
14530 assert(unsigned_offset.base.format.general == .doubleword);
1372414531 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1372514532 .ldrb = .{
1372614533 .Rt = t.alias.encode(.{}),
......@@ -13731,8 +14538,8 @@ pub const Instruction = packed union {
1373114538 },
1373214539 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
1373314540 .extended_register_explicit => |extended_register_explicit| {
13734 assert(extended_register_explicit.base.format.integer == .doubleword and
13735 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14541 assert(extended_register_explicit.base.format.general == .doubleword and
14542 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1373614543 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1373714544 .ldrb = .{
1373814545 .Rt = t.alias.encode(.{}),
......@@ -13775,10 +14582,10 @@ pub const Instruction = packed union {
1377514582 extend: LoadStore.RegisterRegisterOffset.Extend,
1377614583 },
1377714584 }) Instruction {
13778 assert(t.format.integer == .word);
14585 assert(t.format.general == .word);
1377914586 form: switch (form) {
1378014587 .post_index => |post_index| {
13781 assert(post_index.base.format.integer == .doubleword);
14588 assert(post_index.base.format.general == .doubleword);
1378214589 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1378314590 .ldrh = .{
1378414591 .Rt = t.alias.encode(.{}),
......@@ -13788,7 +14595,7 @@ pub const Instruction = packed union {
1378814595 } } } };
1378914596 },
1379014597 .pre_index => |pre_index| {
13791 assert(pre_index.base.format.integer == .doubleword);
14598 assert(pre_index.base.format.general == .doubleword);
1379214599 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1379314600 .ldrh = .{
1379414601 .Rt = t.alias.encode(.{}),
......@@ -13798,7 +14605,7 @@ pub const Instruction = packed union {
1379814605 } } } };
1379914606 },
1380014607 .unsigned_offset => |unsigned_offset| {
13801 assert(unsigned_offset.base.format.integer == .doubleword);
14608 assert(unsigned_offset.base.format.general == .doubleword);
1380214609 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1380314610 .ldrh = .{
1380414611 .Rt = t.alias.encode(.{}),
......@@ -13809,8 +14616,8 @@ pub const Instruction = packed union {
1380914616 },
1381014617 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
1381114618 .extended_register_explicit => |extended_register_explicit| {
13812 assert(extended_register_explicit.base.format.integer == .doubleword and
13813 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14619 assert(extended_register_explicit.base.format.general == .doubleword and
14620 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1381414621 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1381514622 .ldrh = .{
1381614623 .Rt = t.alias.encode(.{}),
......@@ -13854,10 +14661,10 @@ pub const Instruction = packed union {
1385414661 extend: LoadStore.RegisterRegisterOffset.Extend,
1385514662 },
1385614663 }) Instruction {
13857 const sf = t.format.integer;
14664 const sf = t.format.general;
1385814665 form: switch (form) {
1385914666 .post_index => |post_index| {
13860 assert(post_index.base.format.integer == .doubleword);
14667 assert(post_index.base.format.general == .doubleword);
1386114668 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1386214669 .ldrsb = .{
1386314670 .Rt = t.alias.encode(.{}),
......@@ -13868,7 +14675,7 @@ pub const Instruction = packed union {
1386814675 } } } };
1386914676 },
1387014677 .pre_index => |pre_index| {
13871 assert(pre_index.base.format.integer == .doubleword);
14678 assert(pre_index.base.format.general == .doubleword);
1387214679 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1387314680 .ldrsb = .{
1387414681 .Rt = t.alias.encode(.{}),
......@@ -13879,7 +14686,7 @@ pub const Instruction = packed union {
1387914686 } } } };
1388014687 },
1388114688 .unsigned_offset => |unsigned_offset| {
13882 assert(unsigned_offset.base.format.integer == .doubleword);
14689 assert(unsigned_offset.base.format.general == .doubleword);
1388314690 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1388414691 .ldrsb = .{
1388514692 .Rt = t.alias.encode(.{}),
......@@ -13891,8 +14698,8 @@ pub const Instruction = packed union {
1389114698 },
1389214699 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
1389314700 .extended_register_explicit => |extended_register_explicit| {
13894 assert(extended_register_explicit.base.format.integer == .doubleword and
13895 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14701 assert(extended_register_explicit.base.format.general == .doubleword and
14702 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1389614703 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1389714704 .ldrsb = .{
1389814705 .Rt = t.alias.encode(.{}),
......@@ -13936,10 +14743,10 @@ pub const Instruction = packed union {
1393614743 extend: LoadStore.RegisterRegisterOffset.Extend,
1393714744 },
1393814745 }) Instruction {
13939 const sf = t.format.integer;
14746 const sf = t.format.general;
1394014747 form: switch (form) {
1394114748 .post_index => |post_index| {
13942 assert(post_index.base.format.integer == .doubleword);
14749 assert(post_index.base.format.general == .doubleword);
1394314750 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1394414751 .ldrsh = .{
1394514752 .Rt = t.alias.encode(.{}),
......@@ -13950,7 +14757,7 @@ pub const Instruction = packed union {
1395014757 } } } };
1395114758 },
1395214759 .pre_index => |pre_index| {
13953 assert(pre_index.base.format.integer == .doubleword);
14760 assert(pre_index.base.format.general == .doubleword);
1395414761 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1395514762 .ldrsh = .{
1395614763 .Rt = t.alias.encode(.{}),
......@@ -13961,7 +14768,7 @@ pub const Instruction = packed union {
1396114768 } } } };
1396214769 },
1396314770 .unsigned_offset => |unsigned_offset| {
13964 assert(unsigned_offset.base.format.integer == .doubleword);
14771 assert(unsigned_offset.base.format.general == .doubleword);
1396514772 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1396614773 .ldrsh = .{
1396714774 .Rt = t.alias.encode(.{}),
......@@ -13973,8 +14780,8 @@ pub const Instruction = packed union {
1397314780 },
1397414781 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
1397514782 .extended_register_explicit => |extended_register_explicit| {
13976 assert(extended_register_explicit.base.format.integer == .doubleword and
13977 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14783 assert(extended_register_explicit.base.format.general == .doubleword and
14784 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1397814785 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1397914786 .ldrsh = .{
1398014787 .Rt = t.alias.encode(.{}),
......@@ -14012,29 +14819,29 @@ pub const Instruction = packed union {
1401214819 extended_register_explicit: struct {
1401314820 base: Register,
1401414821 index: Register,
14015 option: LoadStore.RegisterRegisterOffset.Integer.Option,
14016 amount: LoadStore.RegisterRegisterOffset.Integer.Extend.Amount,
14822 option: LoadStore.RegisterRegisterOffset.Option,
14823 amount: LoadStore.RegisterRegisterOffset.Extend.Amount,
1401714824 },
1401814825 extended_register: struct {
1401914826 base: Register,
1402014827 index: Register,
14021 extend: LoadStore.RegisterRegisterOffset.Integer.Extend,
14828 extend: LoadStore.RegisterRegisterOffset.Extend,
1402214829 },
1402314830 }) Instruction {
14024 assert(t.format.integer == .doubleword);
14831 assert(t.format.general == .doubleword);
1402514832 form: switch (form) {
1402614833 .post_index => |post_index| {
14027 assert(post_index.base.format.integer == .doubleword);
14028 return .{ .load_store = .{ .register_immediate_post_indexed = .{
14834 assert(post_index.base.format.general == .doubleword);
14835 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1402914836 .ldrsw = .{
1403014837 .Rt = t.alias.encode(.{}),
1403114838 .Rn = post_index.base.alias.encode(.{ .sp = true }),
1403214839 .imm9 = post_index.index,
1403314840 },
14034 } } };
14841 } } } };
1403514842 },
1403614843 .pre_index => |pre_index| {
14037 assert(pre_index.base.format.integer == .doubleword);
14844 assert(pre_index.base.format.general == .doubleword);
1403814845 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1403914846 .ldrsw = .{
1404014847 .Rt = t.alias.encode(.{}),
......@@ -14044,32 +14851,32 @@ pub const Instruction = packed union {
1404414851 } } } };
1404514852 },
1404614853 .unsigned_offset => |unsigned_offset| {
14047 assert(unsigned_offset.base.format.integer == .doubleword);
14048 return .{ .load_store = .{ .register_unsigned_immediate = .{
14854 assert(unsigned_offset.base.format.general == .doubleword);
14855 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1404914856 .ldrsw = .{
1405014857 .Rt = t.alias.encode(.{}),
1405114858 .Rn = unsigned_offset.base.alias.encode(.{ .sp = true }),
1405214859 .imm12 = @intCast(@shrExact(unsigned_offset.offset, 2)),
1405314860 },
14054 } } };
14861 } } } };
1405514862 },
1405614863 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
14057 .literal => |offset| return .{ .load_store = .{ .register_literal = .{
14864 .literal => |offset| return .{ .load_store = .{ .register_literal = .{ .integer = .{
1405814865 .ldrsw = .{
1405914866 .Rt = t.alias.encode(.{}),
1406014867 .imm19 = @intCast(@shrExact(offset, 2)),
1406114868 },
14062 } } },
14869 } } } },
1406314870 .extended_register_explicit => |extended_register_explicit| {
14064 assert(extended_register_explicit.base.format.integer == .doubleword and
14065 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
14871 assert(extended_register_explicit.base.format.general == .doubleword and
14872 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1406614873 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1406714874 .ldrsw = .{
1406814875 .Rt = t.alias.encode(.{}),
1406914876 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),
1407014877 .S = switch (extended_register_explicit.amount) {
14071 0 => 0b0,
14072 2 => 0b1,
14878 0 => false,
14879 2 => true,
1407314880 else => unreachable,
1407414881 },
1407514882 .option = extended_register_explicit.option,
......@@ -14090,10 +14897,10 @@ pub const Instruction = packed union {
1409014897 /// C6.2.202 LDUR
1409114898 /// C7.2.194 LDUR (SIMD&FP)
1409214899 pub fn ldur(t: Register, n: Register, simm: i9) Instruction {
14093 assert(n.format.integer == .doubleword);
14900 assert(n.format.general == .doubleword);
1409414901 switch (t.format) {
1409514902 else => unreachable,
14096 .integer => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14903 .general => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1409714904 .ldur = .{
1409814905 .Rt = t.alias.encode(.{}),
1409914906 .Rn = n.alias.encode(.{ .sp = true }),
......@@ -14114,7 +14921,7 @@ pub const Instruction = packed union {
1411414921 }
1411514922 /// C6.2.203 LDURB
1411614923 pub fn ldurb(t: Register, n: Register, simm: i9) Instruction {
14117 assert(t.format.integer == .word and n.format.integer == .doubleword);
14924 assert(t.format.general == .word and n.format.general == .doubleword);
1411814925 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1411914926 .ldurb = .{
1412014927 .Rt = t.alias.encode(.{}),
......@@ -14125,7 +14932,7 @@ pub const Instruction = packed union {
1412514932 }
1412614933 /// C6.2.204 LDURH
1412714934 pub fn ldurh(t: Register, n: Register, simm: i9) Instruction {
14128 assert(t.format.integer == .word and n.format.integer == .doubleword);
14935 assert(t.format.general == .word and n.format.general == .doubleword);
1412914936 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1413014937 .ldurh = .{
1413114938 .Rt = t.alias.encode(.{}),
......@@ -14136,31 +14943,31 @@ pub const Instruction = packed union {
1413614943 }
1413714944 /// C6.2.205 LDURSB
1413814945 pub fn ldursb(t: Register, n: Register, simm: i9) Instruction {
14139 assert(n.format.integer == .doubleword);
14946 assert(n.format.general == .doubleword);
1414014947 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1414114948 .ldursb = .{
1414214949 .Rt = t.alias.encode(.{}),
1414314950 .Rn = n.alias.encode(.{ .sp = true }),
1414414951 .imm9 = simm,
14145 .opc0 = ~@intFromEnum(t.format.integer),
14952 .opc0 = ~@intFromEnum(t.format.general),
1414614953 },
1414714954 } } } };
1414814955 }
1414914956 /// C6.2.206 LDURSH
1415014957 pub fn ldursh(t: Register, n: Register, simm: i9) Instruction {
14151 assert(n.format.integer == .doubleword);
14958 assert(n.format.general == .doubleword);
1415214959 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1415314960 .ldursh = .{
1415414961 .Rt = t.alias.encode(.{}),
1415514962 .Rn = n.alias.encode(.{ .sp = true }),
1415614963 .imm9 = simm,
14157 .opc0 = ~@intFromEnum(t.format.integer),
14964 .opc0 = ~@intFromEnum(t.format.general),
1415814965 },
1415914966 } } } };
1416014967 }
1416114968 /// C6.2.207 LDURSW
1416214969 pub fn ldursw(t: Register, n: Register, simm: i9) Instruction {
14163 assert(t.format.integer == .doubleword and n.format.integer == .doubleword);
14970 assert(t.format.general == .doubleword and n.format.general == .doubleword);
1416414971 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1416514972 .ldursw = .{
1416614973 .Rt = t.alias.encode(.{}),
......@@ -14171,8 +14978,8 @@ pub const Instruction = packed union {
1417114978 }
1417214979 /// C6.2.214 LSLV
1417314980 pub fn lslv(d: Register, n: Register, m: Register) Instruction {
14174 const sf = d.format.integer;
14175 assert(n.format.integer == sf and m.format.integer == sf);
14981 const sf = d.format.general;
14982 assert(n.format.general == sf and m.format.general == sf);
1417614983 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1417714984 .lslv = .{
1417814985 .Rd = d.alias.encode(.{}),
......@@ -14184,8 +14991,8 @@ pub const Instruction = packed union {
1418414991 }
1418514992 /// C6.2.217 LSRV
1418614993 pub fn lsrv(d: Register, n: Register, m: Register) Instruction {
14187 const sf = d.format.integer;
14188 assert(n.format.integer == sf and m.format.integer == sf);
14994 const sf = d.format.general;
14995 assert(n.format.general == sf and m.format.general == sf);
1418914996 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1419014997 .lsrv = .{
1419114998 .Rd = d.alias.encode(.{}),
......@@ -14197,8 +15004,8 @@ pub const Instruction = packed union {
1419715004 }
1419815005 /// C6.2.218 MADD
1419915006 pub fn madd(d: Register, n: Register, m: Register, a: Register) Instruction {
14200 const sf = d.format.integer;
14201 assert(n.format.integer == sf and m.format.integer == sf and a.format.integer == sf);
15007 const sf = d.format.general;
15008 assert(n.format.general == sf and m.format.general == sf and a.format.general == sf);
1420215009 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1420315010 .madd = .{
1420415011 .Rd = d.alias.encode(.{}),
......@@ -14261,7 +15068,7 @@ pub const Instruction = packed union {
1426115068 imm: u16,
1426215069 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
1426315070 ) Instruction {
14264 const sf = d.format.integer;
15071 const sf = d.format.general;
1426515072 assert(sf == .doubleword or shift.lsl.sf() == .word);
1426615073 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
1426715074 .movk = .{
......@@ -14278,7 +15085,7 @@ pub const Instruction = packed union {
1427815085 imm: u16,
1427915086 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
1428015087 ) Instruction {
14281 const sf = d.format.integer;
15088 const sf = d.format.general;
1428215089 assert(sf == .doubleword or shift.lsl.sf() == .word);
1428315090 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
1428415091 .movn = .{
......@@ -14295,7 +15102,7 @@ pub const Instruction = packed union {
1429515102 imm: u16,
1429615103 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
1429715104 ) Instruction {
14298 const sf = d.format.integer;
15105 const sf = d.format.general;
1429915106 assert(sf == .doubleword or shift.lsl.sf() == .word);
1430015107 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
1430115108 .movz = .{
......@@ -14308,7 +15115,7 @@ pub const Instruction = packed union {
1430815115 }
1430915116 /// C6.2.228 MRS
1431015117 pub fn mrs(t: Register, systemreg: Register.System) Instruction {
14311 assert(t.format.integer == .doubleword and systemreg.op0 >= 0b10);
15118 assert(t.format.general == .doubleword and systemreg.op0 >= 0b10);
1431215119 return .{ .branch_exception_generating_system = .{ .system_register_move = .{
1431315120 .mrs = .{
1431415121 .Rt = t.alias.encode(.{}),
......@@ -14318,7 +15125,7 @@ pub const Instruction = packed union {
1431815125 }
1431915126 /// C6.2.230 MSR (register)
1432015127 pub fn msr(systemreg: Register.System, t: Register) Instruction {
14321 assert(systemreg.op0 >= 0b10 and t.format.integer == .doubleword);
15128 assert(systemreg.op0 >= 0b10 and t.format.general == .doubleword);
1432215129 return .{ .branch_exception_generating_system = .{ .system_register_move = .{
1432315130 .msr = .{
1432415131 .Rt = t.alias.encode(.{}),
......@@ -14328,8 +15135,8 @@ pub const Instruction = packed union {
1432815135 }
1432915136 /// C6.2.231 MSUB
1433015137 pub fn msub(d: Register, n: Register, m: Register, a: Register) Instruction {
14331 const sf = d.format.integer;
14332 assert(n.format.integer == sf and m.format.integer == sf and a.format.integer == sf);
15138 const sf = d.format.general;
15139 assert(n.format.general == sf and m.format.general == sf and a.format.general == sf);
1433315140 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1433415141 .msub = .{
1433515142 .Rd = d.alias.encode(.{}),
......@@ -14350,7 +15157,7 @@ pub const Instruction = packed union {
1435015157 .neg = .{
1435115158 .Rd = d.alias.encode(.{ .V = true }),
1435215159 .Rn = n.alias.encode(.{ .V = true }),
14353 .size = .fromVectorSize(elem_size),
15160 .size = .fromScalarSize(elem_size),
1435415161 },
1435515162 } } };
1435615163 },
......@@ -14395,12 +15202,12 @@ pub const Instruction = packed union {
1439515202 }) Instruction {
1439615203 switch (d.format) {
1439715204 else => unreachable,
14398 .integer => |sf| {
14399 assert(n.format.integer == sf);
15205 .general => |sf| {
15206 assert(n.format.general == sf);
1440015207 form: switch (form) {
1440115208 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1440215209 .shifted_register_explicit => |shifted_register_explicit| {
14403 assert(shifted_register_explicit.register.format.integer == sf);
15210 assert(shifted_register_explicit.register.format.general == sf);
1440415211 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1440515212 .orn = .{
1440615213 .Rd = d.alias.encode(.{}),
......@@ -14451,8 +15258,8 @@ pub const Instruction = packed union {
1445115258 }) Instruction {
1445215259 switch (d.format) {
1445315260 else => unreachable,
14454 .integer => |sf| {
14455 assert(n.format.integer == sf);
15261 .general => |sf| {
15262 assert(n.format.general == sf);
1445615263 form: switch (form) {
1445715264 .immediate => |bitmask| {
1445815265 assert(bitmask.validImmediate(sf));
......@@ -14468,7 +15275,7 @@ pub const Instruction = packed union {
1446815275 .shifted_immediate => unreachable,
1446915276 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
1447015277 .shifted_register_explicit => |shifted_register_explicit| {
14471 assert(shifted_register_explicit.register.format.integer == sf);
15278 assert(shifted_register_explicit.register.format.general == sf);
1447215279 return .{ .data_processing_register = .{ .logical_shifted_register = .{
1447315280 .orr = .{
1447415281 .Rd = d.alias.encode(.{}),
......@@ -14547,7 +15354,7 @@ pub const Instruction = packed union {
1454715354 }) Instruction {
1454815355 form: switch (form) {
1454915356 .unsigned_offset => |unsigned_offset| {
14550 assert(unsigned_offset.base.format.integer == .doubleword);
15357 assert(unsigned_offset.base.format.general == .doubleword);
1455115358 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1455215359 .prfm = .{
1455315360 .prfop = prfop,
......@@ -14564,8 +15371,8 @@ pub const Instruction = packed union {
1456415371 },
1456515372 } } } },
1456615373 .extended_register_explicit => |extended_register_explicit| {
14567 assert(extended_register_explicit.base.format.integer == .doubleword and
14568 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());
15374 assert(extended_register_explicit.base.format.general == .doubleword and
15375 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
1456915376 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
1457015377 .prfm = .{
1457115378 .prfop = prfop,
......@@ -14592,8 +15399,8 @@ pub const Instruction = packed union {
1459215399 }
1459315400 /// C6.2.253 RBIT
1459415401 pub fn rbit(d: Register, n: Register) Instruction {
14595 const sf = d.format.integer;
14596 assert(n.format.integer == sf);
15402 const sf = d.format.general;
15403 assert(n.format.general == sf);
1459715404 return .{ .data_processing_register = .{ .data_processing_one_source = .{
1459815405 .rbit = .{
1459915406 .Rd = d.alias.encode(.{}),
......@@ -14604,15 +15411,15 @@ pub const Instruction = packed union {
1460415411 }
1460515412 /// C6.2.254 RET
1460615413 pub fn ret(n: Register) Instruction {
14607 assert(n.format.integer == .doubleword);
15414 assert(n.format.general == .doubleword);
1460815415 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
1460915416 .ret = .{ .Rn = n.alias.encode(.{}) },
1461015417 } } };
1461115418 }
1461215419 /// C6.2.256 REV
1461315420 pub fn rev(d: Register, n: Register) Instruction {
14614 const sf = d.format.integer;
14615 assert(n.format.integer == sf);
15421 const sf = d.format.general;
15422 assert(n.format.general == sf);
1461615423 return .{ .data_processing_register = .{ .data_processing_one_source = .{
1461715424 .rev = .{
1461815425 .Rd = d.alias.encode(.{}),
......@@ -14624,8 +15431,8 @@ pub const Instruction = packed union {
1462415431 }
1462515432 /// C6.2.257 REV16
1462615433 pub fn rev16(d: Register, n: Register) Instruction {
14627 const sf = d.format.integer;
14628 assert(n.format.integer == sf);
15434 const sf = d.format.general;
15435 assert(n.format.general == sf);
1462915436 return .{ .data_processing_register = .{ .data_processing_one_source = .{
1463015437 .rev16 = .{
1463115438 .Rd = d.alias.encode(.{}),
......@@ -14636,7 +15443,7 @@ pub const Instruction = packed union {
1463615443 }
1463715444 /// C6.2.258 REV32
1463815445 pub fn rev32(d: Register, n: Register) Instruction {
14639 assert(d.format.integer == .doubleword and n.format.integer == .doubleword);
15446 assert(d.format.general == .doubleword and n.format.general == .doubleword);
1464015447 return .{ .data_processing_register = .{ .data_processing_one_source = .{
1464115448 .rev32 = .{
1464215449 .Rd = d.alias.encode(.{}),
......@@ -14646,8 +15453,8 @@ pub const Instruction = packed union {
1464615453 }
1464715454 /// C6.2.263 RORV
1464815455 pub fn rorv(d: Register, n: Register, m: Register) Instruction {
14649 const sf = d.format.integer;
14650 assert(n.format.integer == sf and m.format.integer == sf);
15456 const sf = d.format.general;
15457 assert(n.format.general == sf and m.format.general == sf);
1465115458 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1465215459 .rorv = .{
1465315460 .Rd = d.alias.encode(.{}),
......@@ -14665,8 +15472,8 @@ pub const Instruction = packed union {
1466515472 }
1466615473 /// C6.2.265 SBC
1466715474 pub fn sbc(d: Register, n: Register, m: Register) Instruction {
14668 const sf = d.format.integer;
14669 assert(n.format.integer == sf and m.format.integer == sf);
15475 const sf = d.format.general;
15476 assert(n.format.general == sf and m.format.general == sf);
1467015477 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
1467115478 .sbc = .{
1467215479 .Rd = d.alias.encode(.{}),
......@@ -14678,8 +15485,8 @@ pub const Instruction = packed union {
1467815485 }
1467915486 /// C6.2.266 SBCS
1468015487 pub fn sbcs(d: Register, n: Register, m: Register) Instruction {
14681 const sf = d.format.integer;
14682 assert(n.format.integer == sf and m.format.integer == sf);
15488 const sf = d.format.general;
15489 assert(n.format.general == sf and m.format.general == sf);
1468315490 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
1468415491 .sbcs = .{
1468515492 .Rd = d.alias.encode(.{}),
......@@ -14691,8 +15498,8 @@ pub const Instruction = packed union {
1469115498 }
1469215499 /// C6.2.268 SBFM
1469315500 pub fn sbfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
14694 const sf = d.format.integer;
14695 assert(n.format.integer == sf and bitmask.validBitfield(sf));
15501 const sf = d.format.general;
15502 assert(n.format.general == sf and bitmask.validBitfield(sf));
1469615503 return .{ .data_processing_immediate = .{ .bitfield = .{
1469715504 .sbfm = .{
1469815505 .Rd = d.alias.encode(.{}),
......@@ -14723,16 +15530,16 @@ pub const Instruction = packed union {
1472315530 .scvtf = .{
1472415531 .Rd = d.alias.encode(.{ .V = true }),
1472515532 .Rn = n.alias.encode(.{ .V = true }),
14726 .sz = .fromVectorSize(ftype),
15533 .sz = .fromScalarSize(ftype),
1472715534 },
1472815535 } } },
1472915536 }
1473015537 },
14731 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
15538 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1473215539 .scvtf = .{
1473315540 .Rd = d.alias.encode(.{ .V = true }),
1473415541 .Rn = n.alias.encode(.{}),
14735 .ftype = .fromVectorSize(ftype),
15542 .ftype = .fromScalarSize(ftype),
1473615543 .sf = sf,
1473715544 },
1473815545 } } },
......@@ -14762,8 +15569,8 @@ pub const Instruction = packed union {
1476215569 }
1476315570 /// C6.2.270 SDIV
1476415571 pub fn sdiv(d: Register, n: Register, m: Register) Instruction {
14765 const sf = d.format.integer;
14766 assert(n.format.integer == sf and m.format.integer == sf);
15572 const sf = d.format.general;
15573 assert(n.format.general == sf and m.format.general == sf);
1476715574 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1476815575 .sdiv = .{
1476915576 .Rd = d.alias.encode(.{}),
......@@ -14787,7 +15594,7 @@ pub const Instruction = packed union {
1478715594 }
1478815595 /// C6.2.282 SMADDL
1478915596 pub fn smaddl(d: Register, n: Register, m: Register, a: Register) Instruction {
14790 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);
15597 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
1479115598 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1479215599 .smaddl = .{
1479315600 .Rd = d.alias.encode(.{}),
......@@ -14805,7 +15612,7 @@ pub const Instruction = packed union {
1480515612 }
1480615613 /// C7.2.279 SMOV
1480715614 pub fn smov(d: Register, n: Register) Instruction {
14808 const sf = d.format.integer;
15615 const sf = d.format.general;
1480915616 const vs = n.format.element.size;
1481015617 switch (vs) {
1481115618 else => unreachable,
......@@ -14828,7 +15635,7 @@ pub const Instruction = packed union {
1482815635 }
1482915636 /// C6.2.287 SMSUBL
1483015637 pub fn smsubl(d: Register, n: Register, m: Register, a: Register) Instruction {
14831 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);
15638 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
1483215639 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1483315640 .smsubl = .{
1483415641 .Rd = d.alias.encode(.{}),
......@@ -14840,7 +15647,7 @@ pub const Instruction = packed union {
1484015647 }
1484115648 /// C6.2.288 SMULH
1484215649 pub fn smulh(d: Register, n: Register, m: Register) Instruction {
14843 assert(d.format.integer == .doubleword and n.format.integer == .doubleword and m.format.integer == .doubleword);
15650 assert(d.format.general == .doubleword and n.format.general == .doubleword and m.format.general == .doubleword);
1484415651 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1484515652 .smulh = .{
1484615653 .Rd = d.alias.encode(.{}),
......@@ -14859,7 +15666,7 @@ pub const Instruction = packed union {
1485915666 .sqabs = .{
1486015667 .Rd = d.alias.encode(.{ .V = true }),
1486115668 .Rn = n.alias.encode(.{ .V = true }),
14862 .size = .fromVectorSize(elem_size),
15669 .size = .fromScalarSize(elem_size),
1486315670 },
1486415671 } } };
1486515672 },
......@@ -14881,17 +15688,17 @@ pub const Instruction = packed union {
1488115688 switch (d.format) {
1488215689 else => unreachable,
1488315690 .scalar => |elem_size| {
14884 assert(elem_size == n.format.scalar);
15691 assert(elem_size == n.format.scalar.n());
1488515692 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
1488615693 .sqxtn = .{
1488715694 .Rd = d.alias.encode(.{ .V = true }),
1488815695 .Rn = n.alias.encode(.{ .V = true }),
14889 .size = .fromVectorSize(elem_size),
15696 .size = .fromScalarSize(elem_size),
1489015697 },
1489115698 } } };
1489215699 },
1489315700 .vector => |arrangement| {
14894 assert(arrangement != .@"1d" and n.format.vector == arrangement);
15701 assert(arrangement.len() == n.format.vector.len() and arrangement.elemSize() == n.format.vector.elemSize().n());
1489515702 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
1489615703 .sqxtn = .{
1489715704 .Rd = d.alias.encode(.{ .V = true }),
......@@ -14903,6 +15710,19 @@ pub const Instruction = packed union {
1490315710 },
1490415711 }
1490515712 }
15713 /// C7.2.308 SQXTN2
15714 pub fn sqxtn2(d: Register, n: Register) Instruction {
15715 const arrangement = d.format.vector;
15716 assert(arrangement.len() == n.format.vector.len() * 2 and arrangement.elemSize() == n.format.vector.elemSize().n());
15717 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
15718 .sqxtn = .{
15719 .Rd = d.alias.encode(.{ .V = true }),
15720 .Rn = n.alias.encode(.{ .V = true }),
15721 .size = arrangement.elemSize(),
15722 .Q = arrangement.size(),
15723 },
15724 } } };
15725 }
1490615726 /// C6.2.321 STP
1490715727 /// C7.2.330 STP (SIMD&FP)
1490815728 pub fn stp(t1: Register, t2: Register, form: union(enum) {
......@@ -14913,11 +15733,11 @@ pub const Instruction = packed union {
1491315733 }) Instruction {
1491415734 switch (t1.format) {
1491515735 else => unreachable,
14916 .integer => |sf| {
14917 assert(t2.format.integer == sf);
15736 .general => |sf| {
15737 assert(t2.format.general == sf);
1491815738 form: switch (form) {
1491915739 .post_index => |post_index| {
14920 assert(post_index.base.format.integer == .doubleword);
15740 assert(post_index.base.format.general == .doubleword);
1492115741 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{
1492215742 .stp = .{
1492315743 .Rt = t1.alias.encode(.{}),
......@@ -14929,7 +15749,7 @@ pub const Instruction = packed union {
1492915749 } } } };
1493015750 },
1493115751 .pre_index => |pre_index| {
14932 assert(pre_index.base.format.integer == .doubleword);
15752 assert(pre_index.base.format.general == .doubleword);
1493315753 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{
1493415754 .stp = .{
1493515755 .Rt = t1.alias.encode(.{}),
......@@ -14941,7 +15761,7 @@ pub const Instruction = packed union {
1494115761 } } } };
1494215762 },
1494315763 .signed_offset => |signed_offset| {
14944 assert(signed_offset.base.format.integer == .doubleword);
15764 assert(signed_offset.base.format.general == .doubleword);
1494515765 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{
1494615766 .stp = .{
1494715767 .Rt = t1.alias.encode(.{}),
......@@ -14959,7 +15779,7 @@ pub const Instruction = packed union {
1495915779 assert(t2.format.scalar == vs);
1496015780 form: switch (form) {
1496115781 .post_index => |post_index| {
14962 assert(post_index.base.format.integer == .doubleword);
15782 assert(post_index.base.format.general == .doubleword);
1496315783 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{
1496415784 .stp = .{
1496515785 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -14971,7 +15791,7 @@ pub const Instruction = packed union {
1497115791 } } } };
1497215792 },
1497315793 .signed_offset => |signed_offset| {
14974 assert(signed_offset.base.format.integer == .doubleword);
15794 assert(signed_offset.base.format.general == .doubleword);
1497515795 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{
1497615796 .stp = .{
1497715797 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -14983,7 +15803,7 @@ pub const Instruction = packed union {
1498315803 } } } };
1498415804 },
1498515805 .pre_index => |pre_index| {
14986 assert(pre_index.base.format.integer == .doubleword);
15806 assert(pre_index.base.format.general == .doubleword);
1498715807 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{
1498815808 .stp = .{
1498915809 .Rt = t1.alias.encode(.{ .V = true }),
......@@ -15009,9 +15829,9 @@ pub const Instruction = packed union {
1500915829 }) Instruction {
1501015830 switch (t.format) {
1501115831 else => unreachable,
15012 .integer => |sf| form: switch (form) {
15832 .general => |sf| form: switch (form) {
1501315833 .post_index => |post_index| {
15014 assert(post_index.base.format.integer == .doubleword);
15834 assert(post_index.base.format.general == .doubleword);
1501515835 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1501615836 .str = .{
1501715837 .Rt = t.alias.encode(.{}),
......@@ -15022,7 +15842,7 @@ pub const Instruction = packed union {
1502215842 } } } };
1502315843 },
1502415844 .pre_index => |pre_index| {
15025 assert(pre_index.base.format.integer == .doubleword);
15845 assert(pre_index.base.format.general == .doubleword);
1502615846 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1502715847 .str = .{
1502815848 .Rt = t.alias.encode(.{}),
......@@ -15033,7 +15853,7 @@ pub const Instruction = packed union {
1503315853 } } } };
1503415854 },
1503515855 .unsigned_offset => |unsigned_offset| {
15036 assert(unsigned_offset.base.format.integer == .doubleword);
15856 assert(unsigned_offset.base.format.general == .doubleword);
1503715857 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1503815858 .str = .{
1503915859 .Rt = t.alias.encode(.{}),
......@@ -15047,7 +15867,7 @@ pub const Instruction = packed union {
1504715867 },
1504815868 .scalar => |vs| form: switch (form) {
1504915869 .post_index => |post_index| {
15050 assert(post_index.base.format.integer == .doubleword);
15870 assert(post_index.base.format.general == .doubleword);
1505115871 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{
1505215872 .str = .{
1505315873 .Rt = t.alias.encode(.{ .V = true }),
......@@ -15059,7 +15879,7 @@ pub const Instruction = packed union {
1505915879 } } } };
1506015880 },
1506115881 .pre_index => |pre_index| {
15062 assert(pre_index.base.format.integer == .doubleword);
15882 assert(pre_index.base.format.general == .doubleword);
1506315883 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{
1506415884 .str = .{
1506515885 .Rt = t.alias.encode(.{ .V = true }),
......@@ -15071,7 +15891,7 @@ pub const Instruction = packed union {
1507115891 } } } };
1507215892 },
1507315893 .unsigned_offset => |unsigned_offset| {
15074 assert(unsigned_offset.base.format.integer == .doubleword);
15894 assert(unsigned_offset.base.format.general == .doubleword);
1507515895 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{
1507615896 .str = .{
1507715897 .Rt = t.alias.encode(.{ .V = true }),
......@@ -15093,10 +15913,10 @@ pub const Instruction = packed union {
1509315913 unsigned_offset: struct { base: Register, offset: u12 = 0 },
1509415914 base: Register,
1509515915 }) Instruction {
15096 assert(t.format.integer == .word);
15916 assert(t.format.general == .word);
1509715917 form: switch (form) {
1509815918 .post_index => |post_index| {
15099 assert(post_index.base.format.integer == .doubleword);
15919 assert(post_index.base.format.general == .doubleword);
1510015920 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1510115921 .strb = .{
1510215922 .Rt = t.alias.encode(.{}),
......@@ -15106,7 +15926,7 @@ pub const Instruction = packed union {
1510615926 } } } };
1510715927 },
1510815928 .pre_index => |pre_index| {
15109 assert(pre_index.base.format.integer == .doubleword);
15929 assert(pre_index.base.format.general == .doubleword);
1511015930 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1511115931 .strb = .{
1511215932 .Rt = t.alias.encode(.{}),
......@@ -15116,7 +15936,7 @@ pub const Instruction = packed union {
1511615936 } } } };
1511715937 },
1511815938 .unsigned_offset => |unsigned_offset| {
15119 assert(unsigned_offset.base.format.integer == .doubleword);
15939 assert(unsigned_offset.base.format.general == .doubleword);
1512015940 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1512115941 .strb = .{
1512215942 .Rt = t.alias.encode(.{}),
......@@ -15135,10 +15955,10 @@ pub const Instruction = packed union {
1513515955 unsigned_offset: struct { base: Register, offset: u13 = 0 },
1513615956 base: Register,
1513715957 }) Instruction {
15138 assert(t.format.integer == .word);
15958 assert(t.format.general == .word);
1513915959 form: switch (form) {
1514015960 .post_index => |post_index| {
15141 assert(post_index.base.format.integer == .doubleword);
15961 assert(post_index.base.format.general == .doubleword);
1514215962 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
1514315963 .strh = .{
1514415964 .Rt = t.alias.encode(.{}),
......@@ -15148,7 +15968,7 @@ pub const Instruction = packed union {
1514815968 } } } };
1514915969 },
1515015970 .pre_index => |pre_index| {
15151 assert(pre_index.base.format.integer == .doubleword);
15971 assert(pre_index.base.format.general == .doubleword);
1515215972 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
1515315973 .strh = .{
1515415974 .Rt = t.alias.encode(.{}),
......@@ -15158,7 +15978,7 @@ pub const Instruction = packed union {
1515815978 } } } };
1515915979 },
1516015980 .unsigned_offset => |unsigned_offset| {
15161 assert(unsigned_offset.base.format.integer == .doubleword);
15981 assert(unsigned_offset.base.format.general == .doubleword);
1516215982 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
1516315983 .strh = .{
1516415984 .Rt = t.alias.encode(.{}),
......@@ -15173,10 +15993,10 @@ pub const Instruction = packed union {
1517315993 /// C6.2.346 STUR
1517415994 /// C7.2.333 STUR (SIMD&FP)
1517515995 pub fn stur(t: Register, n: Register, simm: i9) Instruction {
15176 assert(n.format.integer == .doubleword);
15996 assert(n.format.general == .doubleword);
1517715997 switch (t.format) {
1517815998 else => unreachable,
15179 .integer => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
15999 .general => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1518016000 .stur = .{
1518116001 .Rt = t.alias.encode(.{}),
1518216002 .Rn = n.alias.encode(.{ .sp = true }),
......@@ -15197,7 +16017,7 @@ pub const Instruction = packed union {
1519716017 }
1519816018 /// C6.2.347 STURB
1519916019 pub fn sturb(t: Register, n: Register, simm: i9) Instruction {
15200 assert(t.format.integer == .word and n.format.integer == .doubleword);
16020 assert(t.format.general == .word and n.format.general == .doubleword);
1520116021 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1520216022 .sturb = .{
1520316023 .Rt = t.alias.encode(.{}),
......@@ -15208,7 +16028,7 @@ pub const Instruction = packed union {
1520816028 }
1520916029 /// C6.2.348 STURH
1521016030 pub fn sturh(t: Register, n: Register, simm: i9) Instruction {
15211 assert(t.format.integer == .word and n.format.integer == .doubleword);
16031 assert(t.format.general == .word and n.format.general == .doubleword);
1521216032 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
1521316033 .sturh = .{
1521416034 .Rt = t.alias.encode(.{}),
......@@ -15233,11 +16053,11 @@ pub const Instruction = packed union {
1523316053 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1523416054 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1523516055 }) Instruction {
15236 const sf = d.format.integer;
15237 assert(n.format.integer == sf);
16056 const sf = d.format.general;
16057 assert(n.format.general == sf);
1523816058 form: switch (form) {
1523916059 .extended_register_explicit => |extended_register_explicit| {
15240 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());
16060 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
1524116061 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
1524216062 .sub = .{
1524316063 .Rd = d.alias.encode(.{ .sp = true }),
......@@ -15279,7 +16099,7 @@ pub const Instruction = packed union {
1527916099 else
1528016100 .{ .shifted_register = .{ .register = register } },
1528116101 .shifted_register_explicit => |shifted_register_explicit| {
15282 assert(shifted_register_explicit.register.format.integer == sf);
16102 assert(shifted_register_explicit.register.format.general == sf);
1528316103 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
1528416104 .sub = .{
1528516105 .Rd = d.alias.encode(.{}),
......@@ -15323,11 +16143,11 @@ pub const Instruction = packed union {
1532316143 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
1532416144 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
1532516145 }) Instruction {
15326 const sf = d.format.integer;
15327 assert(n.format.integer == sf);
16146 const sf = d.format.general;
16147 assert(n.format.general == sf);
1532816148 form: switch (form) {
1532916149 .extended_register_explicit => |extended_register_explicit| {
15330 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());
16150 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
1533116151 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
1533216152 .subs = .{
1533316153 .Rd = d.alias.encode(.{}),
......@@ -15369,7 +16189,7 @@ pub const Instruction = packed union {
1536916189 else
1537016190 .{ .shifted_register = .{ .register = register } },
1537116191 .shifted_register_explicit => |shifted_register_explicit| {
15372 assert(shifted_register_explicit.register.format.integer == sf);
16192 assert(shifted_register_explicit.register.format.general == sf);
1537316193 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
1537416194 .subs = .{
1537516195 .Rd = d.alias.encode(.{}),
......@@ -15407,7 +16227,7 @@ pub const Instruction = packed union {
1540716227 .suqadd = .{
1540816228 .Rd = d.alias.encode(.{ .V = true }),
1540916229 .Rn = n.alias.encode(.{ .V = true }),
15410 .size = .fromVectorSize(elem_size),
16230 .size = .fromScalarSize(elem_size),
1541116231 },
1541216232 } } };
1541316233 },
......@@ -15432,7 +16252,7 @@ pub const Instruction = packed union {
1543216252 }
1543316253 /// C6.2.372 SYS
1543416254 pub fn sys(op1: u3, n: u4, m: u4, op2: u3, t: Register) Instruction {
15435 assert(t.format.integer == .doubleword);
16255 assert(t.format.general == .doubleword);
1543616256 return .{ .branch_exception_generating_system = .{ .system = .{
1543716257 .sys = .{
1543816258 .Rt = t.alias.encode(.{}),
......@@ -15445,7 +16265,7 @@ pub const Instruction = packed union {
1544516265 }
1544616266 /// C6.2.373 SYSL
1544716267 pub fn sysl(t: Register, op1: u3, n: u4, m: u4, op2: u3) Instruction {
15448 assert(t.format.integer == .doubleword);
16268 assert(t.format.general == .doubleword);
1544916269 return .{ .branch_exception_generating_system = .{ .system = .{
1545016270 .sysl = .{
1545116271 .Rt = t.alias.encode(.{}),
......@@ -15462,7 +16282,7 @@ pub const Instruction = packed union {
1546216282 .tbnz = .{
1546316283 .Rt = t.alias.encode(.{}),
1546416284 .imm14 = @intCast(@shrExact(label, 2)),
15465 .b40 = @truncate(switch (t.format.integer) {
16285 .b40 = @truncate(switch (t.format.general) {
1546616286 .word => @as(u5, @intCast(imm)),
1546716287 .doubleword => imm,
1546816288 }),
......@@ -15476,7 +16296,7 @@ pub const Instruction = packed union {
1547616296 .tbz = .{
1547716297 .Rt = t.alias.encode(.{}),
1547816298 .imm14 = @intCast(@shrExact(label, 2)),
15479 .b40 = @truncate(switch (t.format.integer) {
16299 .b40 = @truncate(switch (t.format.general) {
1548016300 .word => @as(u5, @intCast(imm)),
1548116301 .doubleword => imm,
1548216302 }),
......@@ -15492,8 +16312,8 @@ pub const Instruction = packed union {
1549216312 }
1549316313 /// C6.2.385 UBFM
1549416314 pub fn ubfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
15495 const sf = d.format.integer;
15496 assert(n.format.integer == sf and bitmask.validBitfield(sf));
16315 const sf = d.format.general;
16316 assert(n.format.general == sf and bitmask.validBitfield(sf));
1549716317 return .{ .data_processing_immediate = .{ .bitfield = .{
1549816318 .ubfm = .{
1549916319 .Rd = d.alias.encode(.{}),
......@@ -15524,16 +16344,16 @@ pub const Instruction = packed union {
1552416344 .ucvtf = .{
1552516345 .Rd = d.alias.encode(.{ .V = true }),
1552616346 .Rn = n.alias.encode(.{ .V = true }),
15527 .sz = .fromVectorSize(ftype),
16347 .sz = .fromScalarSize(ftype),
1552816348 },
1552916349 } } },
1553016350 }
1553116351 },
15532 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
16352 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
1553316353 .ucvtf = .{
1553416354 .Rd = d.alias.encode(.{ .V = true }),
1553516355 .Rn = n.alias.encode(.{}),
15536 .ftype = .fromVectorSize(ftype),
16356 .ftype = .fromScalarSize(ftype),
1553716357 .sf = sf,
1553816358 },
1553916359 } } },
......@@ -15569,8 +16389,8 @@ pub const Instruction = packed union {
1556916389 }
1557016390 /// C6.2.388 UDIV
1557116391 pub fn udiv(d: Register, n: Register, m: Register) Instruction {
15572 const sf = d.format.integer;
15573 assert(n.format.integer == sf and m.format.integer == sf);
16392 const sf = d.format.general;
16393 assert(n.format.general == sf and m.format.general == sf);
1557416394 return .{ .data_processing_register = .{ .data_processing_two_source = .{
1557516395 .udiv = .{
1557616396 .Rd = d.alias.encode(.{}),
......@@ -15582,7 +16402,7 @@ pub const Instruction = packed union {
1558216402 }
1558316403 /// C6.2.389 UMADDL
1558416404 pub fn umaddl(d: Register, n: Register, m: Register, a: Register) Instruction {
15585 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);
16405 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
1558616406 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1558716407 .umaddl = .{
1558816408 .Rd = d.alias.encode(.{}),
......@@ -15594,7 +16414,7 @@ pub const Instruction = packed union {
1559416414 }
1559516415 /// C6.2.391 UMSUBL
1559616416 pub fn umsubl(d: Register, n: Register, m: Register, a: Register) Instruction {
15597 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);
16417 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
1559816418 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1559916419 .umsubl = .{
1560016420 .Rd = d.alias.encode(.{}),
......@@ -15606,7 +16426,7 @@ pub const Instruction = packed union {
1560616426 }
1560716427 /// C7.2.371 UMOV
1560816428 pub fn umov(d: Register, n: Register) Instruction {
15609 const sf = d.format.integer;
16429 const sf = d.format.general;
1561016430 const vs = n.format.element.size;
1561116431 switch (vs) {
1561216432 else => unreachable,
......@@ -15630,7 +16450,7 @@ pub const Instruction = packed union {
1563016450 }
1563116451 /// C6.2.392 UMULH
1563216452 pub fn umulh(d: Register, n: Register, m: Register) Instruction {
15633 assert(d.format.integer == .doubleword and n.format.integer == .doubleword and m.format.integer == .doubleword);
16453 assert(d.format.general == .doubleword and n.format.general == .doubleword and m.format.general == .doubleword);
1563416454 return .{ .data_processing_register = .{ .data_processing_three_source = .{
1563516455 .umulh = .{
1563616456 .Rd = d.alias.encode(.{}),
src/codegen/aarch64/instructions.zon+3965-354
......@@ -3,60 +3,72 @@
33 .{
44 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>",
55 .symbols = .{
6 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
7 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
8 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
6 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
7 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
8 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
99 },
1010 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },
1111 },
1212 .{
1313 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",
1414 .symbols = .{
15 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
16 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
17 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
15 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
16 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
17 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1818 .extend = .{ .extend = .{ .size = .word } },
1919 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
2020 },
21 .encode = .{ .add, .Wd, .Wn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },
21 .encode = .{ .add, .Wd, .Wn, .{ .extended_register_explicit = .{
22 .register = .Wm,
23 .option = .extend,
24 .amount = .amount,
25 } } },
2226 },
2327 .{
2428 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>",
2529 .symbols = .{
26 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
27 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
28 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
30 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
31 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
32 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2933 },
3034 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },
3135 },
3236 .{
3337 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",
3438 .symbols = .{
35 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
36 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
37 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
39 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
40 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
41 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
3842 .extend = .{ .extend = .{ .size = .word } },
3943 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
4044 },
41 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },
45 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{
46 .register = .Wm,
47 .option = .extend,
48 .amount = .amount,
49 } } },
4250 },
4351 .{
4452 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",
4553 .symbols = .{
46 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
47 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
48 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
54 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
55 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
56 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4957 .extend = .{ .extend = .{ .size = .doubleword } },
5058 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
5159 },
52 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Xm, .option = .extend, .amount = .amount } } },
60 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{
61 .register = .Xm,
62 .option = .extend,
63 .amount = .amount,
64 } } },
5365 },
5466 // C6.2.4 ADD (immediate)
5567 .{
5668 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>",
5769 .symbols = .{
58 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
59 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
70 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
71 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
6072 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
6173 },
6274 .encode = .{ .add, .Wd, .Wn, .{ .immediate = .imm } },
......@@ -64,8 +76,8 @@
6476 .{
6577 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",
6678 .symbols = .{
67 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
68 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
79 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
80 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
6981 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
7082 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
7183 },
......@@ -74,8 +86,8 @@
7486 .{
7587 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>",
7688 .symbols = .{
77 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
78 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
89 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
90 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
7991 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
8092 },
8193 .encode = .{ .add, .Xd, .Xn, .{ .immediate = .imm } },
......@@ -83,8 +95,8 @@
8395 .{
8496 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",
8597 .symbols = .{
86 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
87 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
98 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
99 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
88100 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
89101 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
90102 },
......@@ -94,141 +106,165 @@
94106 .{
95107 .pattern = "ADD <Wd>, <Wn>, <Wm>",
96108 .symbols = .{
97 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
98 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
99 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
109 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
110 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
111 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
100112 },
101113 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },
102114 },
103115 .{
104116 .pattern = "ADD <Wd>, <Wn>, <Wm>, <shift> #<amount>",
105117 .symbols = .{
106 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
107 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
108 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
118 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
119 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
120 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
109121 .shift = .{ .shift = .{ .allow_ror = false } },
110122 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
111123 },
112 .encode = .{ .add, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
124 .encode = .{ .add, .Wd, .Wn, .{ .shifted_register_explicit = .{
125 .register = .Wm,
126 .shift = .shift,
127 .amount = .amount,
128 } } },
113129 },
114130 .{
115131 .pattern = "ADD <Xd>, <Xn>, <Xm>",
116132 .symbols = .{
117 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
118 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
119 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
133 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
134 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
135 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
120136 },
121137 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },
122138 },
123139 .{
124140 .pattern = "ADD <Xd>, <Xn>, <Xm>, <shift> #<amount>",
125141 .symbols = .{
126 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
127 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
128 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
142 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
143 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
144 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
129145 .shift = .{ .shift = .{ .allow_ror = false } },
130146 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
131147 },
132 .encode = .{ .add, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
148 .encode = .{ .add, .Xd, .Xn, .{ .shifted_register_explicit = .{
149 .register = .Xm,
150 .shift = .shift,
151 .amount = .amount,
152 } } },
133153 },
134154 // C6.2.13 AND (shifted register)
135155 .{
136156 .pattern = "AND <Wd>, <Wn>, <Wm>",
137157 .symbols = .{
138 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
139 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
140 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
158 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
159 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
160 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
141161 },
142162 .encode = .{ .@"and", .Wd, .Wn, .{ .register = .Wm } },
143163 },
144164 .{
145165 .pattern = "AND <Wd>, <Wn>, <Wm>, <shift> #<amount>",
146166 .symbols = .{
147 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
148 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
149 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
168 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
169 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
150170 .shift = .{ .shift = .{} },
151171 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
152172 },
153 .encode = .{ .@"and", .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
173 .encode = .{ .@"and", .Wd, .Wn, .{ .shifted_register_explicit = .{
174 .register = .Wm,
175 .shift = .shift,
176 .amount = .amount,
177 } } },
154178 },
155179 .{
156180 .pattern = "AND <Xd>, <Xn>, <Xm>",
157181 .symbols = .{
158 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
159 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
160 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
182 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
183 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
184 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
161185 },
162186 .encode = .{ .@"and", .Xd, .Xn, .{ .register = .Xm } },
163187 },
164188 .{
165189 .pattern = "AND <Xd>, <Xn>, <Xm>, <shift> #<amount>",
166190 .symbols = .{
167 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
168 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
169 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
191 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
192 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
193 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
170194 .shift = .{ .shift = .{} },
171195 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
172196 },
173 .encode = .{ .@"and", .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
197 .encode = .{ .@"and", .Xd, .Xn, .{ .shifted_register_explicit = .{
198 .register = .Xm,
199 .shift = .shift,
200 .amount = .amount,
201 } } },
174202 },
175203 // C6.2.15 ANDS (shifted register)
176204 .{
177205 .pattern = "ANDS <Wd>, <Wn>, <Wm>",
178206 .symbols = .{
179 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
180 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
181 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
207 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
208 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
209 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
182210 },
183211 .encode = .{ .ands, .Wd, .Wn, .{ .register = .Wm } },
184212 },
185213 .{
186214 .pattern = "ANDS <Wd>, <Wn>, <Wm>, <shift> #<amount>",
187215 .symbols = .{
188 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
189 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
190 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
216 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
217 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
218 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
191219 .shift = .{ .shift = .{} },
192220 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
193221 },
194 .encode = .{ .ands, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
222 .encode = .{ .ands, .Wd, .Wn, .{ .shifted_register_explicit = .{
223 .register = .Wm,
224 .shift = .shift,
225 .amount = .amount,
226 } } },
195227 },
196228 .{
197229 .pattern = "ANDS <Xd>, <Xn>, <Xm>",
198230 .symbols = .{
199 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
200 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
201 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
231 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
232 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
233 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
202234 },
203235 .encode = .{ .ands, .Xd, .Xn, .{ .register = .Xm } },
204236 },
205237 .{
206238 .pattern = "ANDS <Xd>, <Xn>, <Xm>, <shift> #<amount>",
207239 .symbols = .{
208 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
209 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
210 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
240 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
241 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
242 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
211243 .shift = .{ .shift = .{} },
212244 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
213245 },
214 .encode = .{ .ands, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
246 .encode = .{ .ands, .Xd, .Xn, .{ .shifted_register_explicit = .{
247 .register = .Xm,
248 .shift = .shift,
249 .amount = .amount,
250 } } },
215251 },
216252 // C6.2.16 ASR (register)
217253 .{
218254 .pattern = "ASR <Wd>, <Wn>, <Wm>",
219255 .symbols = .{
220 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
221 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
222 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
256 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
257 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
258 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
223259 },
224260 .encode = .{ .asrv, .Wd, .Wn, .Wm },
225261 },
226262 .{
227263 .pattern = "ASR <Xd>, <Xn>, <Xm>",
228264 .symbols = .{
229 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
230 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
231 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
265 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
266 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
267 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
232268 },
233269 .encode = .{ .asrv, .Xd, .Xn, .Xm },
234270 },
......@@ -236,8 +272,8 @@
236272 .{
237273 .pattern = "ASR <Wd>, <Wn>, #<shift>",
238274 .symbols = .{
239 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
240 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
275 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
276 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
241277 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
242278 },
243279 .encode = .{ .sbfm, .Wd, .Wn, .{ .N = .word, .immr = .shift, .imms = 31 } },
......@@ -245,8 +281,8 @@
245281 .{
246282 .pattern = "ASR <Xd>, <Xn>, #<shift>",
247283 .symbols = .{
248 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
249 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
284 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
285 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
250286 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
251287 },
252288 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .shift, .imms = 63 } },
......@@ -255,35 +291,27 @@
255291 .{
256292 .pattern = "ASRV <Wd>, <Wn>, <Wm>",
257293 .symbols = .{
258 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
259 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
260 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
294 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
295 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
296 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
261297 },
262298 .encode = .{ .asrv, .Wd, .Wn, .Wm },
263299 },
264300 .{
265301 .pattern = "ASRV <Xd>, <Xn>, <Xm>",
266302 .symbols = .{
267 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
268 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
269 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
303 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
304 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
305 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
270306 },
271307 .encode = .{ .asrv, .Xd, .Xn, .Xm },
272308 },
273 // C6.2.35 BLR
274 .{
275 .pattern = "BLR <Xn>",
276 .symbols = .{
277 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
278 },
279 .encode = .{ .blr, .Xn },
280 },
281309 // C6.2.30 BFM
282310 .{
283311 .pattern = "BFM <Wd>, <Wn>, #<immr>, #<imms>",
284312 .symbols = .{
285 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
286 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
313 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
314 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
287315 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
288316 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
289317 },
......@@ -292,18 +320,26 @@
292320 .{
293321 .pattern = "BFM <Xd>, <Xn>, #<immr>, #<imms>",
294322 .symbols = .{
295 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
296 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
323 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
324 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
297325 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
298326 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
299327 },
300328 .encode = .{ .bfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
301329 },
330 // C6.2.35 BLR
331 .{
332 .pattern = "BLR <Xn>",
333 .symbols = .{
334 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
335 },
336 .encode = .{ .blr, .Xn },
337 },
302338 // C6.2.37 BR
303339 .{
304340 .pattern = "BR <Xn>",
305341 .symbols = .{
306 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
342 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
307343 },
308344 .encode = .{ .br, .Xn },
309345 },
......@@ -328,60 +364,94 @@
328364 },
329365 .encode = .{ .clrex, .imm },
330366 },
367 // C6.2.57 CLS
368 .{
369 .pattern = "CLS <Wd>, <Wn>",
370 .symbols = .{
371 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
372 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
373 },
374 .encode = .{ .cls, .Wd, .Wn },
375 },
376 .{
377 .pattern = "CLS <Xd>, <Xn>",
378 .symbols = .{
379 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
380 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
381 },
382 .encode = .{ .cls, .Xd, .Xn },
383 },
384 // C6.2.58 CLZ
385 .{
386 .pattern = "CLZ <Wd>, <Wn>",
387 .symbols = .{
388 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
389 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
390 },
391 .encode = .{ .clz, .Wd, .Wn },
392 },
393 .{
394 .pattern = "CLZ <Xd>, <Xn>",
395 .symbols = .{
396 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
397 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
398 },
399 .encode = .{ .clz, .Xd, .Xn },
400 },
331401 // C6.2.109 DC
332402 .{
333403 .pattern = "DC IVAC, <Xt>",
334404 .symbols = .{
335 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
405 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
336406 },
337407 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b001, .Xt },
338408 },
339409 .{
340410 .pattern = "DC ISW, <Xt>",
341411 .symbols = .{
342 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
412 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
343413 },
344414 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b010, .Xt },
345415 },
346416 .{
347417 .pattern = "DC CSW, <Xt>",
348418 .symbols = .{
349 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
419 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
350420 },
351421 .encode = .{ .sys, 0b000, 0b0111, 0b1010, 0b010, .Xt },
352422 },
353423 .{
354424 .pattern = "DC CISW, <Xt>",
355425 .symbols = .{
356 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
426 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
357427 },
358428 .encode = .{ .sys, 0b000, 0b0111, 0b1110, 0b010, .Xt },
359429 },
360430 .{
361431 .pattern = "DC ZVA, <Xt>",
362432 .symbols = .{
363 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
433 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
364434 },
365435 .encode = .{ .sys, 0b011, 0b0111, 0b0100, 0b001, .Xt },
366436 },
367437 .{
368438 .pattern = "DC CVAC, <Xt>",
369439 .symbols = .{
370 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
440 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
371441 },
372442 .encode = .{ .sys, 0b011, 0b0111, 0b1010, 0b001, .Xt },
373443 },
374444 .{
375445 .pattern = "DC CVAU, <Xt>",
376446 .symbols = .{
377 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
447 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
378448 },
379449 .encode = .{ .sys, 0b011, 0b0111, 0b1011, 0b001, .Xt },
380450 },
381451 .{
382452 .pattern = "DC CIVAC, <Xt>",
383453 .symbols = .{
384 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
454 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
385455 },
386456 .encode = .{ .sys, 0b011, 0b0111, 0b1110, 0b001, .Xt },
387457 },
......@@ -443,50 +513,58 @@
443513 .{
444514 .pattern = "EOR <Wd>, <Wn>, <Wm>",
445515 .symbols = .{
446 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
447 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
448 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
516 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
517 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
518 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
449519 },
450520 .encode = .{ .eor, .Wd, .Wn, .{ .register = .Wm } },
451521 },
452522 .{
453523 .pattern = "EOR <Wd>, <Wn>, <Wm>, <shift> #<amount>",
454524 .symbols = .{
455 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
456 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
457 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
525 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
526 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
527 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
458528 .shift = .{ .shift = .{} },
459529 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
460530 },
461 .encode = .{ .eor, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
531 .encode = .{ .eor, .Wd, .Wn, .{ .shifted_register_explicit = .{
532 .register = .Wm,
533 .shift = .shift,
534 .amount = .amount,
535 } } },
462536 },
463537 .{
464538 .pattern = "EOR <Xd>, <Xn>, <Xm>",
465539 .symbols = .{
466 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
467 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
468 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
540 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
541 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
542 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
469543 },
470544 .encode = .{ .eor, .Xd, .Xn, .{ .register = .Xm } },
471545 },
472546 .{
473547 .pattern = "EOR <Xd>, <Xn>, <Xm>, <shift> #<amount>",
474548 .symbols = .{
475 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
476 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
477 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
549 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
550 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
551 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
478552 .shift = .{ .shift = .{} },
479553 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
480554 },
481 .encode = .{ .eor, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
555 .encode = .{ .eor, .Xd, .Xn, .{ .shifted_register_explicit = .{
556 .register = .Xm,
557 .shift = .shift,
558 .amount = .amount,
559 } } },
482560 },
483561 // C6.2.124 EXTR
484562 .{
485563 .pattern = "EXTR <Wd>, <Wn>, <Wm>, #<lsb>",
486564 .symbols = .{
487 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
488 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
489 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
565 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
566 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
567 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
490568 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
491569 },
492570 .encode = .{ .extr, .Wd, .Wn, .Wm, .lsb },
......@@ -494,9 +572,9 @@
494572 .{
495573 .pattern = "EXTR <Xd>, <Xn>, <Xm>, #<lsb>",
496574 .symbols = .{
497 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
498 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
499 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
575 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
576 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
577 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
500578 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
501579 },
502580 .encode = .{ .extr, .Xd, .Xn, .Xm, .lsb },
......@@ -528,43 +606,37 @@
528606 // C6.2.129 IC
529607 .{
530608 .pattern = "IC IALLUIS",
531 .symbols = .{
532 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
533 },
609 .symbols = .{},
534610 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .xzr },
535611 },
536612 .{
537613 .pattern = "IC IALLUIS, <Xt>",
538614 .symbols = .{
539 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
615 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
540616 },
541617 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .Xt },
542618 },
543619 .{
544620 .pattern = "IC IALLU",
545 .symbols = .{
546 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
547 },
621 .symbols = .{},
548622 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .xzr },
549623 },
550624 .{
551625 .pattern = "IC IALLU, <Xt>",
552626 .symbols = .{
553 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
627 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
554628 },
555629 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .Xt },
556630 },
557631 .{
558632 .pattern = "IC IVAU",
559 .symbols = .{
560 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
561 },
633 .symbols = .{},
562634 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .xzr },
563635 },
564636 .{
565637 .pattern = "IC IVAU, <Xt>",
566638 .symbols = .{
567 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
639 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
568640 },
569641 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .Xt },
570642 },
......@@ -592,9 +664,9 @@
592664 .{
593665 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",
594666 .symbols = .{
595 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
596 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
597 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
667 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
668 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
669 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
598670 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
599671 },
600672 .encode = .{ .ldp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
......@@ -602,9 +674,9 @@
602674 .{
603675 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",
604676 .symbols = .{
605 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
606 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
607 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
677 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
678 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
679 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
608680 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
609681 },
610682 .encode = .{ .ldp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
......@@ -612,9 +684,9 @@
612684 .{
613685 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",
614686 .symbols = .{
615 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
616 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
617 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
687 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
688 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
689 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
618690 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
619691 },
620692 .encode = .{ .ldp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
......@@ -622,9 +694,9 @@
622694 .{
623695 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",
624696 .symbols = .{
625 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
626 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
627 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
697 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
698 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
699 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
628700 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
629701 },
630702 .encode = .{ .ldp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
......@@ -632,18 +704,18 @@
632704 .{
633705 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>]",
634706 .symbols = .{
635 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
636 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
637 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
707 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
708 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
709 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
638710 },
639711 .encode = .{ .ldp, .Wt1, .Wt2, .{ .base = .Xn } },
640712 },
641713 .{
642714 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",
643715 .symbols = .{
644 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
645 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
646 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
716 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
717 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
718 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
647719 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
648720 },
649721 .encode = .{ .ldp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
......@@ -651,18 +723,18 @@
651723 .{
652724 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>]",
653725 .symbols = .{
654 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
655 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
656 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
726 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
727 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
728 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
657729 },
658730 .encode = .{ .ldp, .Xt1, .Xt2, .{ .base = .Xn } },
659731 },
660732 .{
661733 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",
662734 .symbols = .{
663 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
664 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
665 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
735 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
736 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
737 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
666738 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
667739 },
668740 .encode = .{ .ldp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
......@@ -671,8 +743,8 @@
671743 .{
672744 .pattern = "LDR <Wt>, [<Xn|SP>], #<simm>",
673745 .symbols = .{
674 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
675 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
746 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
747 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
676748 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
677749 },
678750 .encode = .{ .ldr, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
......@@ -680,8 +752,8 @@
680752 .{
681753 .pattern = "LDR <Xt>, [<Xn|SP>], #<simm>",
682754 .symbols = .{
683 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
684 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
755 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
756 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
685757 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
686758 },
687759 .encode = .{ .ldr, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
......@@ -689,8 +761,8 @@
689761 .{
690762 .pattern = "LDR <Wt>, [<Xn|SP>, #<simm>]!",
691763 .symbols = .{
692 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
693 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
764 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
765 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
694766 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
695767 },
696768 .encode = .{ .ldr, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
......@@ -698,8 +770,8 @@
698770 .{
699771 .pattern = "LDR <Xt>, [<Xn|SP>, #<simm>]!",
700772 .symbols = .{
701 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
702 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
773 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
774 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
703775 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
704776 },
705777 .encode = .{ .ldr, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
......@@ -707,16 +779,16 @@
707779 .{
708780 .pattern = "LDR <Wt>, [<Xn|SP>]",
709781 .symbols = .{
710 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
711 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
782 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
783 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
712784 },
713785 .encode = .{ .ldr, .Wt, .{ .base = .Xn } },
714786 },
715787 .{
716788 .pattern = "LDR <Wt>, [<Xn|SP>, #<pimm>]",
717789 .symbols = .{
718 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
719 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
790 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
791 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
720792 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },
721793 },
722794 .encode = .{ .ldr, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
......@@ -724,16 +796,16 @@
724796 .{
725797 .pattern = "LDR <Xt>, [<Xn|SP>]",
726798 .symbols = .{
727 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
728 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
799 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
800 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
729801 },
730802 .encode = .{ .ldr, .Xt, .{ .base = .Xn } },
731803 },
732804 .{
733805 .pattern = "LDR <Xt>, [<Xn|SP>, #<pimm>]",
734806 .symbols = .{
735 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
736 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
807 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
808 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
737809 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },
738810 },
739811 .encode = .{ .ldr, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
......@@ -742,18 +814,18 @@
742814 .{
743815 .pattern = "LSL <Wd>, <Wn>, <Wm>",
744816 .symbols = .{
745 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
746 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
747 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
817 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
818 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
819 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
748820 },
749821 .encode = .{ .lslv, .Wd, .Wn, .Wm },
750822 },
751823 .{
752824 .pattern = "LSL <Xd>, <Xn>, <Xm>",
753825 .symbols = .{
754 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
755 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
756 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
826 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
827 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
828 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
757829 },
758830 .encode = .{ .lslv, .Xd, .Xn, .Xm },
759831 },
......@@ -761,18 +833,18 @@
761833 .{
762834 .pattern = "LSLV <Wd>, <Wn>, <Wm>",
763835 .symbols = .{
764 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
765 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
766 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
836 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
837 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
838 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
767839 },
768840 .encode = .{ .lslv, .Wd, .Wn, .Wm },
769841 },
770842 .{
771843 .pattern = "LSLV <Xd>, <Xn>, <Xm>",
772844 .symbols = .{
773 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
774 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
775 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
845 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
846 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
847 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
776848 },
777849 .encode = .{ .lslv, .Xd, .Xn, .Xm },
778850 },
......@@ -780,18 +852,18 @@
780852 .{
781853 .pattern = "LSR <Wd>, <Wn>, <Wm>",
782854 .symbols = .{
783 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
784 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
785 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
855 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
856 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
857 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
786858 },
787859 .encode = .{ .lsrv, .Wd, .Wn, .Wm },
788860 },
789861 .{
790862 .pattern = "LSR <Xd>, <Xn>, <Xm>",
791863 .symbols = .{
792 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
793 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
794 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
864 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
865 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
866 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
795867 },
796868 .encode = .{ .lsrv, .Xd, .Xn, .Xm },
797869 },
......@@ -799,47 +871,87 @@
799871 .{
800872 .pattern = "LSRV <Wd>, <Wn>, <Wm>",
801873 .symbols = .{
802 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
803 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
804 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
874 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
875 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
876 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
805877 },
806878 .encode = .{ .lsrv, .Wd, .Wn, .Wm },
807879 },
808880 .{
809881 .pattern = "LSRV <Xd>, <Xn>, <Xm>",
810882 .symbols = .{
811 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
812 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
813 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
883 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
884 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
885 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
814886 },
815887 .encode = .{ .lsrv, .Xd, .Xn, .Xm },
816888 },
889 // C6.2.218 MADD
890 .{
891 .pattern = "MADD <Wd>, <Wn>, <Wm>, <Wa>",
892 .symbols = .{
893 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
894 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
895 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
896 .Wa = .{ .reg = .{ .format = .{ .general = .word } } },
897 },
898 .encode = .{ .madd, .Wd, .Wn, .Wm, .Wa },
899 },
900 .{
901 .pattern = "MADD <Xd>, <Xn>, <Xm>, <Xa>",
902 .symbols = .{
903 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
904 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
905 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
906 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
907 },
908 .encode = .{ .madd, .Xd, .Xn, .Xm, .Xa },
909 },
910 // C6.2.219 MNEG
911 .{
912 .pattern = "MNEG <Wd>, <Wn>, <Wm>",
913 .symbols = .{
914 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
915 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
916 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
917 },
918 .encode = .{ .msub, .Wd, .Wn, .Wm, .wzr },
919 },
920 .{
921 .pattern = "MNEG <Xd>, <Xn>, <Xm>",
922 .symbols = .{
923 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
924 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
925 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
926 },
927 .encode = .{ .msub, .Xd, .Xn, .Xm, .xzr },
928 },
817929 // C6.2.220 MOV (to/from SP)
818930 .{
819931 .pattern = "MOV WSP, <Wn|WSP>",
820932 .symbols = .{
821 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
933 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
822934 },
823935 .encode = .{ .add, .wsp, .Wn, .{ .immediate = 0 } },
824936 },
825937 .{
826938 .pattern = "MOV <Wd|WSP>, WSP",
827939 .symbols = .{
828 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
940 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
829941 },
830942 .encode = .{ .add, .Wd, .wsp, .{ .immediate = 0 } },
831943 },
832944 .{
833945 .pattern = "MOV SP, <Xn|SP>",
834946 .symbols = .{
835 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
947 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
836948 },
837949 .encode = .{ .add, .sp, .Xn, .{ .immediate = 0 } },
838950 },
839951 .{
840952 .pattern = "MOV <Xd|SP>, SP",
841953 .symbols = .{
842 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
954 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
843955 },
844956 .encode = .{ .add, .Xd, .sp, .{ .immediate = 0 } },
845957 },
......@@ -847,7 +959,7 @@
847959 .{
848960 .pattern = "MOV <Wd>, #<imm>",
849961 .symbols = .{
850 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
962 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
851963 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
852964 },
853965 .encode = .{ .movz, .Wd, .imm, .{ .lsl = .@"0" } },
......@@ -855,7 +967,7 @@
855967 .{
856968 .pattern = "MOV <Xd>, #<imm>",
857969 .symbols = .{
858 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
970 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
859971 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
860972 },
861973 .encode = .{ .movz, .Xd, .imm, .{ .lsl = .@"0" } },
......@@ -864,16 +976,16 @@
864976 .{
865977 .pattern = "MOV <Wd>, <Wm>",
866978 .symbols = .{
867 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
868 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
979 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
980 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
869981 },
870982 .encode = .{ .orr, .Wd, .wzr, .{ .register = .Wm } },
871983 },
872984 .{
873985 .pattern = "MOV <Xd>, <Xm>",
874986 .symbols = .{
875 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
876 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
987 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
988 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
877989 },
878990 .encode = .{ .orr, .Xd, .xzr, .{ .register = .Xm } },
879991 },
......@@ -881,7 +993,7 @@
881993 .{
882994 .pattern = "MOVK <Wd>, #<imm>",
883995 .symbols = .{
884 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
996 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
885997 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
886998 },
887999 .encode = .{ .movk, .Wd, .imm, .{} },
......@@ -889,7 +1001,7 @@
8891001 .{
8901002 .pattern = "MOVK <Wd>, #<imm>, LSL #<shift>",
8911003 .symbols = .{
892 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1004 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
8931005 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
8941006 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
8951007 },
......@@ -898,7 +1010,7 @@
8981010 .{
8991011 .pattern = "MOVK <Xd>, #<imm>",
9001012 .symbols = .{
901 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1013 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9021014 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9031015 },
9041016 .encode = .{ .movk, .Xd, .imm, .{} },
......@@ -906,7 +1018,7 @@
9061018 .{
9071019 .pattern = "MOVK <Xd>, #<imm>, LSL #<shift>",
9081020 .symbols = .{
909 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1021 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9101022 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9111023 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
9121024 },
......@@ -916,7 +1028,7 @@
9161028 .{
9171029 .pattern = "MOVN <Wd>, #<imm>",
9181030 .symbols = .{
919 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1031 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
9201032 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9211033 },
9221034 .encode = .{ .movn, .Wd, .imm, .{} },
......@@ -924,7 +1036,7 @@
9241036 .{
9251037 .pattern = "MOVN <Wd>, #<imm>, LSL #<shift>",
9261038 .symbols = .{
927 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1039 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
9281040 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9291041 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
9301042 },
......@@ -933,7 +1045,7 @@
9331045 .{
9341046 .pattern = "MOVN <Xd>, #<imm>",
9351047 .symbols = .{
936 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1048 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9371049 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9381050 },
9391051 .encode = .{ .movn, .Xd, .imm, .{} },
......@@ -941,7 +1053,7 @@
9411053 .{
9421054 .pattern = "MOVN <Xd>, #<imm>, LSL #<shift>",
9431055 .symbols = .{
944 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1056 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9451057 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9461058 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
9471059 },
......@@ -951,7 +1063,7 @@
9511063 .{
9521064 .pattern = "MOVZ <Wd>, #<imm>",
9531065 .symbols = .{
954 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1066 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
9551067 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9561068 },
9571069 .encode = .{ .movz, .Wd, .imm, .{} },
......@@ -959,7 +1071,7 @@
9591071 .{
9601072 .pattern = "MOVZ <Wd>, #<imm>, LSL #<shift>",
9611073 .symbols = .{
962 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1074 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
9631075 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9641076 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
9651077 },
......@@ -968,7 +1080,7 @@
9681080 .{
9691081 .pattern = "MOVZ <Xd>, #<imm>",
9701082 .symbols = .{
971 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1083 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9721084 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9731085 },
9741086 .encode = .{ .movz, .Xd, .imm, .{} },
......@@ -976,7 +1088,7 @@
9761088 .{
9771089 .pattern = "MOVZ <Xd>, #<imm>, LSL #<shift>",
9781090 .symbols = .{
979 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1091 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9801092 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
9811093 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
9821094 },
......@@ -986,7 +1098,7 @@
9861098 .{
9871099 .pattern = "MRS <Xt>, <systemreg>",
9881100 .symbols = .{
989 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1101 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
9901102 .systemreg = .systemreg,
9911103 },
9921104 .encode = .{ .mrs, .Xt, .systemreg },
......@@ -996,46 +1108,94 @@
9961108 .pattern = "MSR <systemreg>, <Xt>",
9971109 .symbols = .{
9981110 .systemreg = .systemreg,
999 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1111 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10001112 },
10011113 .encode = .{ .msr, .systemreg, .Xt },
10021114 },
1115 // C6.2.231 MSUB
1116 .{
1117 .pattern = "MSUB <Wd>, <Wn>, <Wm>, <Wa>",
1118 .symbols = .{
1119 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1120 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1121 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1122 .Wa = .{ .reg = .{ .format = .{ .general = .word } } },
1123 },
1124 .encode = .{ .msub, .Wd, .Wn, .Wm, .Wa },
1125 },
1126 .{
1127 .pattern = "MSUB <Xd>, <Xn>, <Xm>, <Xa>",
1128 .symbols = .{
1129 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1130 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1131 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1132 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1133 },
1134 .encode = .{ .msub, .Xd, .Xn, .Xm, .Xa },
1135 },
1136 // C6.2.232 MUL
1137 .{
1138 .pattern = "MUL <Wd>, <Wn>, <Wm>",
1139 .symbols = .{
1140 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1141 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1142 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1143 },
1144 .encode = .{ .madd, .Wd, .Wn, .Wm, .wzr },
1145 },
1146 .{
1147 .pattern = "MUL <Xd>, <Xn>, <Xm>",
1148 .symbols = .{
1149 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1150 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1151 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1152 },
1153 .encode = .{ .madd, .Xd, .Xn, .Xm, .xzr },
1154 },
10031155 // C6.2.234 NEG
10041156 .{
10051157 .pattern = "NEG <Wd>, <Wm>",
10061158 .symbols = .{
1007 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1008 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1159 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1160 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
10091161 },
10101162 .encode = .{ .sub, .Wd, .wzr, .{ .register = .Wm } },
10111163 },
10121164 .{
10131165 .pattern = "NEG <Wd>, <Wm>, <shift> #<amount>",
10141166 .symbols = .{
1015 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1016 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1168 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
10171169 .shift = .{ .shift = .{ .allow_ror = false } },
10181170 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
10191171 },
1020 .encode = .{ .sub, .Wd, .wzr, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
1172 .encode = .{ .sub, .Wd, .wzr, .{ .shifted_register_explicit = .{
1173 .register = .Wm,
1174 .shift = .shift,
1175 .amount = .amount,
1176 } } },
10211177 },
10221178 .{
10231179 .pattern = "NEG <Xd>, <Xm>",
10241180 .symbols = .{
1025 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1026 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1181 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1182 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10271183 },
10281184 .encode = .{ .sub, .Xd, .xzr, .{ .register = .Xm } },
10291185 },
10301186 .{
10311187 .pattern = "NEG <Xd>, <Xm>, <shift> #<amount>",
10321188 .symbols = .{
1033 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1034 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1189 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1190 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10351191 .shift = .{ .shift = .{ .allow_ror = false } },
10361192 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
10371193 },
1038 .encode = .{ .sub, .Xd, .xzr, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
1194 .encode = .{ .sub, .Xd, .xzr, .{ .shifted_register_explicit = .{
1195 .register = .Xm,
1196 .shift = .shift,
1197 .amount = .amount,
1198 } } },
10391199 },
10401200 // C6.2.238 NOP
10411201 .{
......@@ -1047,42 +1207,67 @@
10471207 .{
10481208 .pattern = "ORR <Wd>, <Wn>, <Wm>",
10491209 .symbols = .{
1050 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1051 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1052 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1210 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1211 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1212 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
10531213 },
10541214 .encode = .{ .orr, .Wd, .Wn, .{ .register = .Wm } },
10551215 },
10561216 .{
10571217 .pattern = "ORR <Wd>, <Wn>, <Wm>, <shift> #<amount>",
10581218 .symbols = .{
1059 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1060 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1061 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1219 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1220 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1221 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
10621222 .shift = .{ .shift = .{} },
10631223 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
10641224 },
1065 .encode = .{ .orr, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
1225 .encode = .{ .orr, .Wd, .Wn, .{ .shifted_register_explicit = .{
1226 .register = .Wm,
1227 .shift = .shift,
1228 .amount = .amount,
1229 } } },
10661230 },
10671231 .{
10681232 .pattern = "ORR <Xd>, <Xn>, <Xm>",
10691233 .symbols = .{
1070 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1071 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1072 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1234 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1235 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1236 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10731237 },
10741238 .encode = .{ .orr, .Xd, .Xn, .{ .register = .Xm } },
10751239 },
10761240 .{
10771241 .pattern = "ORR <Xd>, <Xn>, <Xm>, <shift> #<amount>",
10781242 .symbols = .{
1079 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1080 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1081 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1243 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1244 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1245 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10821246 .shift = .{ .shift = .{} },
10831247 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
10841248 },
1085 .encode = .{ .orr, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
1249 .encode = .{ .orr, .Xd, .Xn, .{ .shifted_register_explicit = .{
1250 .register = .Xm,
1251 .shift = .shift,
1252 .amount = .amount,
1253 } } },
1254 },
1255 // C6.2.253 RBIT
1256 .{
1257 .pattern = "RBIT <Wd>, <Wn>",
1258 .symbols = .{
1259 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1260 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1261 },
1262 .encode = .{ .rbit, .Wd, .Wn },
1263 },
1264 .{
1265 .pattern = "RBIT <Xd>, <Xn>",
1266 .symbols = .{
1267 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1268 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1269 },
1270 .encode = .{ .rbit, .Xd, .Xn },
10861271 },
10871272 // C6.2.254 RET
10881273 .{
......@@ -1093,16 +1278,68 @@
10931278 .{
10941279 .pattern = "RET <Xn>",
10951280 .symbols = .{
1096 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1281 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
10971282 },
10981283 .encode = .{ .ret, .Xn },
10991284 },
1285 // C6.2.256 REV
1286 .{
1287 .pattern = "REV <Wd>, <Wn>",
1288 .symbols = .{
1289 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1290 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1291 },
1292 .encode = .{ .rev, .Wd, .Wn },
1293 },
1294 .{
1295 .pattern = "REV <Xd>, <Xn>",
1296 .symbols = .{
1297 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1298 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1299 },
1300 .encode = .{ .rev, .Xd, .Xn },
1301 },
1302 // C6.2.257 REV16
1303 .{
1304 .pattern = "REV16 <Wd>, <Wn>",
1305 .symbols = .{
1306 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1307 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1308 },
1309 .encode = .{ .rev16, .Wd, .Wn },
1310 },
1311 .{
1312 .pattern = "REV16 <Xd>, <Xn>",
1313 .symbols = .{
1314 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1315 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1316 },
1317 .encode = .{ .rev16, .Xd, .Xn },
1318 },
1319 // C6.2.258 REV32
1320 .{
1321 .pattern = "REV32 <Xd>, <Xn>",
1322 .symbols = .{
1323 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1324 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1325 },
1326 .encode = .{ .rev32, .Xd, .Xn },
1327 },
1328 // C6.2.259 REV64
1329 .{
1330 .pattern = "REV64 <Xd>, <Xn>",
1331 .symbols = .{
1332 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1333 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1334 },
1335 .encode = .{ .rev, .Xd, .Xn },
1336 },
11001337 // C6.2.261 ROR (immediate)
11011338 .{
11021339 .pattern = "ROR <Wd>, <Ws>, #<shift>",
11031340 .symbols = .{
1104 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1105 .Ws = .{ .reg = .{ .format = .{ .integer = .word } } },
1341 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1342 .Ws = .{ .reg = .{ .format = .{ .general = .word } } },
11061343 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
11071344 },
11081345 .encode = .{ .extr, .Wd, .Ws, .Ws, .shift },
......@@ -1110,8 +1347,8 @@
11101347 .{
11111348 .pattern = "ROR <Xd>, <Xs>, #<shift>",
11121349 .symbols = .{
1113 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1114 .Xs = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1350 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1351 .Xs = .{ .reg = .{ .format = .{ .general = .doubleword } } },
11151352 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
11161353 },
11171354 .encode = .{ .extr, .Xd, .Xs, .Xs, .shift },
......@@ -1120,18 +1357,18 @@
11201357 .{
11211358 .pattern = "ROR <Wd>, <Wn>, <Wm>",
11221359 .symbols = .{
1123 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1124 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1125 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1360 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1361 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1362 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
11261363 },
11271364 .encode = .{ .rorv, .Wd, .Wn, .Wm },
11281365 },
11291366 .{
11301367 .pattern = "ROR <Xd>, <Xn>, <Xm>",
11311368 .symbols = .{
1132 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1133 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1134 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1369 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1370 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1371 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
11351372 },
11361373 .encode = .{ .rorv, .Xd, .Xn, .Xm },
11371374 },
......@@ -1139,18 +1376,18 @@
11391376 .{
11401377 .pattern = "RORV <Wd>, <Wn>, <Wm>",
11411378 .symbols = .{
1142 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1143 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1144 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1379 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1380 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1381 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
11451382 },
11461383 .encode = .{ .rorv, .Wd, .Wn, .Wm },
11471384 },
11481385 .{
11491386 .pattern = "RORV <Xd>, <Xn>, <Xm>",
11501387 .symbols = .{
1151 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1152 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1153 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1388 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1389 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1390 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
11541391 },
11551392 .encode = .{ .rorv, .Xd, .Xn, .Xm },
11561393 },
......@@ -1158,8 +1395,8 @@
11581395 .{
11591396 .pattern = "SBFM <Wd>, <Wn>, #<immr>, #<imms>",
11601397 .symbols = .{
1161 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1162 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1398 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1399 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
11631400 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
11641401 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
11651402 },
......@@ -1168,13 +1405,32 @@
11681405 .{
11691406 .pattern = "SBFM <Xd>, <Xn>, #<immr>, #<imms>",
11701407 .symbols = .{
1171 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1172 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1408 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1409 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
11731410 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
11741411 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
11751412 },
11761413 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
11771414 },
1415 // C6.2.270 SDIV
1416 .{
1417 .pattern = "SDIV <Wd>, <Wn>, <Wm>",
1418 .symbols = .{
1419 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1420 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1421 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1422 },
1423 .encode = .{ .sdiv, .Wd, .Wn, .Wm },
1424 },
1425 .{
1426 .pattern = "SDIV <Xd>, <Xn>, <Xm>",
1427 .symbols = .{
1428 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1429 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1430 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1431 },
1432 .encode = .{ .sdiv, .Xd, .Xn, .Xm },
1433 },
11781434 // C6.2.280 SEV
11791435 .{
11801436 .pattern = "SEV",
......@@ -1187,6 +1443,17 @@
11871443 .symbols = .{},
11881444 .encode = .{.sevl},
11891445 },
1446 // C6.2.282 SMADDL
1447 .{
1448 .pattern = "SMADDL <Xd>, <Wn>, <Wm>, <Xa>",
1449 .symbols = .{
1450 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1451 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1452 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1453 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1454 },
1455 .encode = .{ .smaddl, .Xd, .Wn, .Wm, .Xa },
1456 },
11901457 // C6.2.283 SMC
11911458 .{
11921459 .pattern = "SMC #<imm>",
......@@ -1195,13 +1462,54 @@
11951462 },
11961463 .encode = .{ .smc, .imm },
11971464 },
1465 // C6.2.284 SMNEGL
1466 .{
1467 .pattern = "SMNEGL <Xd>, <Wn>, <Wm>",
1468 .symbols = .{
1469 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1470 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1471 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1472 },
1473 .encode = .{ .smsubl, .Xd, .Wn, .Wm, .xzr },
1474 },
1475 // C6.2.287 SMSUBL
1476 .{
1477 .pattern = "SMSUBL <Xd>, <Wn>, <Wm>, <Xa>",
1478 .symbols = .{
1479 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1480 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1481 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1482 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1483 },
1484 .encode = .{ .smsubl, .Xd, .Wn, .Wm, .Xa },
1485 },
1486 // C6.2.288 SMULH
1487 .{
1488 .pattern = "SMULH <Xd>, <Xn>, <Xm>",
1489 .symbols = .{
1490 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1491 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1492 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1493 },
1494 .encode = .{ .smulh, .Xd, .Xn, .Xm },
1495 },
1496 // C6.2.289 SMULL
1497 .{
1498 .pattern = "SMULL <Xd>, <Wn>, <Wm>",
1499 .symbols = .{
1500 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1501 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1502 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1503 },
1504 .encode = .{ .smaddl, .Xd, .Wn, .Wm, .xzr },
1505 },
11981506 // C6.2.321 STP
11991507 .{
12001508 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",
12011509 .symbols = .{
1202 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
1203 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
1204 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1510 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1511 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1512 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12051513 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
12061514 },
12071515 .encode = .{ .stp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
......@@ -1209,9 +1517,9 @@
12091517 .{
12101518 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",
12111519 .symbols = .{
1212 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1213 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1214 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1520 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1521 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1522 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12151523 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
12161524 },
12171525 .encode = .{ .stp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
......@@ -1219,9 +1527,9 @@
12191527 .{
12201528 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",
12211529 .symbols = .{
1222 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
1223 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
1224 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1530 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1531 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1532 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12251533 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
12261534 },
12271535 .encode = .{ .stp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
......@@ -1229,9 +1537,9 @@
12291537 .{
12301538 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",
12311539 .symbols = .{
1232 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1233 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1234 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1540 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1541 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1542 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12351543 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
12361544 },
12371545 .encode = .{ .stp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
......@@ -1239,18 +1547,18 @@
12391547 .{
12401548 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>]",
12411549 .symbols = .{
1242 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
1243 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
1244 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1550 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1551 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1552 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12451553 },
12461554 .encode = .{ .stp, .Wt1, .Wt2, .{ .base = .Xn } },
12471555 },
12481556 .{
12491557 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",
12501558 .symbols = .{
1251 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },
1252 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },
1253 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1559 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1560 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1561 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12541562 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
12551563 },
12561564 .encode = .{ .stp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
......@@ -1258,18 +1566,18 @@
12581566 .{
12591567 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>]",
12601568 .symbols = .{
1261 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1262 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1263 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1569 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1570 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1571 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12641572 },
12651573 .encode = .{ .stp, .Xt1, .Xt2, .{ .base = .Xn } },
12661574 },
12671575 .{
12681576 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",
12691577 .symbols = .{
1270 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1271 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1272 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1578 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1579 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1580 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12731581 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
12741582 },
12751583 .encode = .{ .stp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
......@@ -1278,8 +1586,8 @@
12781586 .{
12791587 .pattern = "STR <Wt>, [<Xn|SP>], #<simm>",
12801588 .symbols = .{
1281 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
1282 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1589 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1590 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12831591 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
12841592 },
12851593 .encode = .{ .str, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
......@@ -1287,8 +1595,8 @@
12871595 .{
12881596 .pattern = "STR <Xt>, [<Xn|SP>], #<simm>",
12891597 .symbols = .{
1290 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1291 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1598 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1599 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
12921600 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
12931601 },
12941602 .encode = .{ .str, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
......@@ -1296,8 +1604,8 @@
12961604 .{
12971605 .pattern = "STR <Wt>, [<Xn|SP>, #<simm>]!",
12981606 .symbols = .{
1299 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
1300 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1607 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1608 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13011609 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
13021610 },
13031611 .encode = .{ .str, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
......@@ -1305,8 +1613,8 @@
13051613 .{
13061614 .pattern = "STR <Xt>, [<Xn|SP>, #<simm>]!",
13071615 .symbols = .{
1308 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1309 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1616 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1617 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13101618 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
13111619 },
13121620 .encode = .{ .str, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
......@@ -1314,16 +1622,16 @@
13141622 .{
13151623 .pattern = "STR <Wt>, [<Xn|SP>]",
13161624 .symbols = .{
1317 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
1318 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1625 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1626 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13191627 },
13201628 .encode = .{ .str, .Wt, .{ .base = .Xn } },
13211629 },
13221630 .{
13231631 .pattern = "STR <Wt>, [<Xn|SP>, #<pimm>]",
13241632 .symbols = .{
1325 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },
1326 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1633 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1634 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13271635 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },
13281636 },
13291637 .encode = .{ .str, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
......@@ -1331,16 +1639,16 @@
13311639 .{
13321640 .pattern = "STR <Xt>, [<Xn|SP>]",
13331641 .symbols = .{
1334 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1335 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1642 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1643 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13361644 },
13371645 .encode = .{ .str, .Xt, .{ .base = .Xn } },
13381646 },
13391647 .{
13401648 .pattern = "STR <Xt>, [<Xn|SP>, #<pimm>]",
13411649 .symbols = .{
1342 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1343 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1650 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1651 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
13441652 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },
13451653 },
13461654 .encode = .{ .str, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
......@@ -1349,60 +1657,72 @@
13491657 .{
13501658 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>",
13511659 .symbols = .{
1352 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1353 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1354 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1660 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1661 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1662 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
13551663 },
13561664 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },
13571665 },
13581666 .{
13591667 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",
13601668 .symbols = .{
1361 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1362 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1363 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1669 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1670 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1671 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
13641672 .extend = .{ .extend = .{ .size = .word } },
13651673 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
13661674 },
1367 .encode = .{ .sub, .Wd, .Wn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },
1675 .encode = .{ .sub, .Wd, .Wn, .{ .extended_register_explicit = .{
1676 .register = .Wm,
1677 .option = .extend,
1678 .amount = .amount,
1679 } } },
13681680 },
13691681 .{
13701682 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>",
13711683 .symbols = .{
1372 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1373 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1374 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1684 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1685 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1686 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
13751687 },
13761688 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },
13771689 },
13781690 .{
13791691 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",
13801692 .symbols = .{
1381 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1382 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1383 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1693 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1694 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1695 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
13841696 .extend = .{ .extend = .{ .size = .word } },
13851697 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
13861698 },
1387 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },
1699 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{
1700 .register = .Wm,
1701 .option = .extend,
1702 .amount = .amount,
1703 } } },
13881704 },
13891705 .{
13901706 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",
13911707 .symbols = .{
1392 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1393 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1394 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1708 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1709 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1710 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
13951711 .extend = .{ .extend = .{ .size = .doubleword } },
13961712 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
13971713 },
1398 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Xm, .option = .extend, .amount = .amount } } },
1714 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{
1715 .register = .Xm,
1716 .option = .extend,
1717 .amount = .amount,
1718 } } },
13991719 },
14001720 // C6.2.357 SUB (immediate)
14011721 .{
14021722 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>",
14031723 .symbols = .{
1404 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1405 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1724 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1725 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
14061726 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
14071727 },
14081728 .encode = .{ .sub, .Wd, .Wn, .{ .immediate = .imm } },
......@@ -1410,8 +1730,8 @@
14101730 .{
14111731 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",
14121732 .symbols = .{
1413 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1414 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },
1733 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1734 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
14151735 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
14161736 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
14171737 },
......@@ -1420,8 +1740,8 @@
14201740 .{
14211741 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>",
14221742 .symbols = .{
1423 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1424 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1743 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1744 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
14251745 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
14261746 },
14271747 .encode = .{ .sub, .Xd, .Xn, .{ .immediate = .imm } },
......@@ -1429,8 +1749,8 @@
14291749 .{
14301750 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",
14311751 .symbols = .{
1432 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1433 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },
1752 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1753 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
14341754 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
14351755 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
14361756 },
......@@ -1440,42 +1760,50 @@
14401760 .{
14411761 .pattern = "SUB <Wd>, <Wn>, <Wm>",
14421762 .symbols = .{
1443 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1444 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1445 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1763 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1764 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1765 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
14461766 },
14471767 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },
14481768 },
14491769 .{
14501770 .pattern = "SUB <Wd>, <Wn>, <Wm>, <shift> #<amount>",
14511771 .symbols = .{
1452 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1453 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1454 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },
1772 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1773 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1774 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
14551775 .shift = .{ .shift = .{ .allow_ror = false } },
14561776 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
14571777 },
1458 .encode = .{ .sub, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },
1778 .encode = .{ .sub, .Wd, .Wn, .{ .shifted_register_explicit = .{
1779 .register = .Wm,
1780 .shift = .shift,
1781 .amount = .amount,
1782 } } },
14591783 },
14601784 .{
14611785 .pattern = "SUB <Xd>, <Xn>, <Xm>",
14621786 .symbols = .{
1463 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1464 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1465 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1787 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1788 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1789 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
14661790 },
14671791 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },
14681792 },
14691793 .{
14701794 .pattern = "SUB <Xd>, <Xn>, <Xm>, <shift> #<amount>",
14711795 .symbols = .{
1472 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1473 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1474 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1796 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1797 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1798 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
14751799 .shift = .{ .shift = .{ .allow_ror = false } },
14761800 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
14771801 },
1478 .encode = .{ .sub, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },
1802 .encode = .{ .sub, .Xd, .Xn, .{ .shifted_register_explicit = .{
1803 .register = .Xm,
1804 .shift = .shift,
1805 .amount = .amount,
1806 } } },
14791807 },
14801808 // C6.2.365 SVC
14811809 .{
......@@ -1497,8 +1825,8 @@
14971825 .{
14981826 .pattern = "UBFM <Wd>, <Wn>, #<immr>, #<imms>",
14991827 .symbols = .{
1500 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },
1501 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },
1828 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1829 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
15021830 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
15031831 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
15041832 },
......@@ -1507,13 +1835,32 @@
15071835 .{
15081836 .pattern = "UBFM <Xd>, <Xn>, #<immr>, #<imms>",
15091837 .symbols = .{
1510 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1511 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
1838 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1839 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
15121840 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
15131841 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
15141842 },
15151843 .encode = .{ .ubfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
15161844 },
1845 // C6.2.388 UDIV
1846 .{
1847 .pattern = "UDIV <Wd>, <Wn>, <Wm>",
1848 .symbols = .{
1849 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1850 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1851 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1852 },
1853 .encode = .{ .udiv, .Wd, .Wn, .Wm },
1854 },
1855 .{
1856 .pattern = "UDIV <Xd>, <Xn>, <Xm>",
1857 .symbols = .{
1858 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1859 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1860 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1861 },
1862 .encode = .{ .udiv, .Xd, .Xn, .Xm },
1863 },
15171864 // C6.2.387 UDF
15181865 .{
15191866 .pattern = "UDF #<imm>",
......@@ -1522,6 +1869,58 @@
15221869 },
15231870 .encode = .{ .udf, .imm },
15241871 },
1872 // C6.2.389 UMADDL
1873 .{
1874 .pattern = "UMADDL <Xd>, <Wn>, <Wm>, <Xa>",
1875 .symbols = .{
1876 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1877 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1878 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1879 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1880 },
1881 .encode = .{ .umaddl, .Xd, .Wn, .Wm, .Xa },
1882 },
1883 // C6.2.390 UMNEGL
1884 .{
1885 .pattern = "UMNEGL <Xd>, <Wn>, <Wm>",
1886 .symbols = .{
1887 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1888 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1889 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1890 },
1891 .encode = .{ .umsubl, .Xd, .Wn, .Wm, .xzr },
1892 },
1893 // C6.2.391 UMSUBL
1894 .{
1895 .pattern = "UMSUBL <Xd>, <Wn>, <Wm>, <Xa>",
1896 .symbols = .{
1897 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1898 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1899 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1900 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1901 },
1902 .encode = .{ .umsubl, .Xd, .Wn, .Wm, .Xa },
1903 },
1904 // C6.2.292 UMULH
1905 .{
1906 .pattern = "UMULH <Xd>, <Xn>, <Xm>",
1907 .symbols = .{
1908 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1909 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1910 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1911 },
1912 .encode = .{ .umulh, .Xd, .Xn, .Xm },
1913 },
1914 // C6.2.393 UMULL
1915 .{
1916 .pattern = "UMULL <Xd>, <Wn>, <Wm>",
1917 .symbols = .{
1918 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1919 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1920 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1921 },
1922 .encode = .{ .umaddl, .Xd, .Wn, .Wm, .xzr },
1923 },
15251924 // C6.2.396 WFE
15261925 .{
15271926 .pattern = "WFE",
......@@ -1540,4 +1939,3216 @@
15401939 .symbols = .{},
15411940 .encode = .{.yield},
15421941 },
1942
1943 // C7.2.1 ABS
1944 .{
1945 .pattern = "ABS <Vd>, <Vn>",
1946 .symbols = .{
1947 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1948 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1949 },
1950 .encode = .{ .abs, .Vd, .Vn },
1951 },
1952 .{
1953 .pattern = "ABS <Vd>.<T>, <Vn>.<T>",
1954 .symbols = .{
1955 .Vd = .{ .reg_alias = .vector },
1956 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
1957 .Vn = .{ .reg_alias = .vector },
1958 },
1959 .encode = .{
1960 .abs,
1961 .{ .alias = .Vd, .format = .{ .vector = .T } },
1962 .{ .alias = .Vn, .format = .{ .vector = .T } },
1963 },
1964 },
1965 // C7.2.28 CMEQ (zero)
1966 .{
1967 .pattern = "CMEQ <Vd>, <Vn>, #<0>",
1968 .symbols = .{
1969 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1970 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1971 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1972 },
1973 .encode = .{ .cmeq, .Vd, .Vn, .zero },
1974 },
1975 .{
1976 .pattern = "CMEQ <Vd>.<T>, <Vn>.<T>, #<0>",
1977 .symbols = .{
1978 .Vd = .{ .reg_alias = .vector },
1979 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
1980 .Vn = .{ .reg_alias = .vector },
1981 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1982 },
1983 .encode = .{
1984 .cmeq,
1985 .{ .alias = .Vd, .format = .{ .vector = .T } },
1986 .{ .alias = .Vn, .format = .{ .vector = .T } },
1987 .zero,
1988 },
1989 },
1990 // C7.2.30 CMGE (zero)
1991 .{
1992 .pattern = "CMGE <Vd>, <Vn>, #<0>",
1993 .symbols = .{
1994 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1995 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1996 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1997 },
1998 .encode = .{ .cmge, .Vd, .Vn, .zero },
1999 },
2000 .{
2001 .pattern = "CMGE <Vd>.<T>, <Vn>.<T>, #<0>",
2002 .symbols = .{
2003 .Vd = .{ .reg_alias = .vector },
2004 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2005 .Vn = .{ .reg_alias = .vector },
2006 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2007 },
2008 .encode = .{
2009 .cmge,
2010 .{ .alias = .Vd, .format = .{ .vector = .T } },
2011 .{ .alias = .Vn, .format = .{ .vector = .T } },
2012 .zero,
2013 },
2014 },
2015 // C7.2.32 CMGT (zero)
2016 .{
2017 .pattern = "CMGT <Vd>, <Vn>, #<0>",
2018 .symbols = .{
2019 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2020 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2021 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2022 },
2023 .encode = .{ .cmgt, .Vd, .Vn, .zero },
2024 },
2025 .{
2026 .pattern = "CMGT <Vd>.<T>, <Vn>.<T>, #<0>",
2027 .symbols = .{
2028 .Vd = .{ .reg_alias = .vector },
2029 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2030 .Vn = .{ .reg_alias = .vector },
2031 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2032 },
2033 .encode = .{
2034 .cmgt,
2035 .{ .alias = .Vd, .format = .{ .vector = .T } },
2036 .{ .alias = .Vn, .format = .{ .vector = .T } },
2037 .zero,
2038 },
2039 },
2040 // C7.2.35 CMLE (zero)
2041 .{
2042 .pattern = "CMLE <Vd>, <Vn>, #<0>",
2043 .symbols = .{
2044 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2045 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2046 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2047 },
2048 .encode = .{ .cmle, .Vd, .Vn, .zero },
2049 },
2050 .{
2051 .pattern = "CMLE <Vd>.<T>, <Vn>.<T>, #<0>",
2052 .symbols = .{
2053 .Vd = .{ .reg_alias = .vector },
2054 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2055 .Vn = .{ .reg_alias = .vector },
2056 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2057 },
2058 .encode = .{
2059 .cmle,
2060 .{ .alias = .Vd, .format = .{ .vector = .T } },
2061 .{ .alias = .Vn, .format = .{ .vector = .T } },
2062 .zero,
2063 },
2064 },
2065 // C7.2.36 CMLT (zero)
2066 .{
2067 .pattern = "CMLT <Vd>, <Vn>, #<0>",
2068 .symbols = .{
2069 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2070 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2071 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2072 },
2073 .encode = .{ .cmlt, .Vd, .Vn, .zero },
2074 },
2075 .{
2076 .pattern = "CMLT <Vd>.<T>, <Vn>.<T>, #<0>",
2077 .symbols = .{
2078 .Vd = .{ .reg_alias = .vector },
2079 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2080 .Vn = .{ .reg_alias = .vector },
2081 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2082 },
2083 .encode = .{
2084 .cmlt,
2085 .{ .alias = .Vd, .format = .{ .vector = .T } },
2086 .{ .alias = .Vn, .format = .{ .vector = .T } },
2087 .zero,
2088 },
2089 },
2090 // C7.2.38 CNT
2091 .{
2092 .pattern = "CNT <Vd>.<T>, <Vn>.<T>",
2093 .symbols = .{
2094 .Vd = .{ .reg_alias = .vector },
2095 .T = .{ .arrangement = .{ .elem_size = .byte } },
2096 .Vn = .{ .reg_alias = .vector },
2097 },
2098 .encode = .{
2099 .cnt,
2100 .{ .alias = .Vd, .format = .{ .vector = .T } },
2101 .{ .alias = .Vn, .format = .{ .vector = .T } },
2102 },
2103 },
2104 // C7.2.39 DUP (element)
2105 .{
2106 .pattern = "DUP <Vd>, <Vn>.B[<index>]",
2107 .symbols = .{
2108 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
2109 .Vn = .{ .reg_alias = .vector },
2110 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
2111 },
2112 .encode = .{
2113 .dup,
2114 .Vd,
2115 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
2116 },
2117 },
2118 .{
2119 .pattern = "DUP <Vd>, <Vn>.H[<index>]",
2120 .symbols = .{
2121 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2122 .Vn = .{ .reg_alias = .vector },
2123 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
2124 },
2125 .encode = .{
2126 .dup,
2127 .Vd,
2128 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
2129 },
2130 },
2131 .{
2132 .pattern = "DUP <Vd>, <Vn>.S[<index>]",
2133 .symbols = .{
2134 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2135 .Vn = .{ .reg_alias = .vector },
2136 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
2137 },
2138 .encode = .{
2139 .dup,
2140 .Vd,
2141 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
2142 },
2143 },
2144 .{
2145 .pattern = "DUP <Vd>, <Vn>.D[<index>]",
2146 .symbols = .{
2147 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2148 .Vn = .{ .reg_alias = .vector },
2149 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
2150 },
2151 .encode = .{
2152 .dup,
2153 .Vd,
2154 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
2155 },
2156 },
2157 .{
2158 .pattern = "DUP <Vd>.<T>, <Vn>.B[<index>]",
2159 .symbols = .{
2160 .Vd = .{ .reg_alias = .vector },
2161 .T = .{ .arrangement = .{ .elem_size = .byte } },
2162 .Vn = .{ .reg_alias = .vector },
2163 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
2164 },
2165 .encode = .{
2166 .dup,
2167 .{ .alias = .Vd, .format = .{ .vector = .T } },
2168 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
2169 },
2170 },
2171 .{
2172 .pattern = "DUP <Vd>.<T>, <Vn>.H[<index>]",
2173 .symbols = .{
2174 .Vd = .{ .reg_alias = .vector },
2175 .T = .{ .arrangement = .{ .elem_size = .half } },
2176 .Vn = .{ .reg_alias = .vector },
2177 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
2178 },
2179 .encode = .{
2180 .dup,
2181 .{ .alias = .Vd, .format = .{ .vector = .T } },
2182 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
2183 },
2184 },
2185 .{
2186 .pattern = "DUP <Vd>.<T>, <Vn>.S[<index>]",
2187 .symbols = .{
2188 .Vd = .{ .reg_alias = .vector },
2189 .T = .{ .arrangement = .{ .elem_size = .single } },
2190 .Vn = .{ .reg_alias = .vector },
2191 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
2192 },
2193 .encode = .{
2194 .dup,
2195 .{ .alias = .Vd, .format = .{ .vector = .T } },
2196 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
2197 },
2198 },
2199 .{
2200 .pattern = "DUP <Vd>.2D, <Vn>.D[<index>]",
2201 .symbols = .{
2202 .Vd = .{ .reg_alias = .vector },
2203 .Vn = .{ .reg_alias = .vector },
2204 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
2205 },
2206 .encode = .{
2207 .dup,
2208 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2209 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
2210 },
2211 },
2212 // C7.2.40 DUP (general)
2213 .{
2214 .pattern = "DUP <Vd>.<T>, <Wn>",
2215 .symbols = .{
2216 .Vd = .{ .reg_alias = .vector },
2217 .T = .{ .arrangement = .{ .allow_double = false } },
2218 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
2219 },
2220 .encode = .{ .dup, .{ .alias = .Vd, .format = .{ .vector = .T } }, .Wn },
2221 },
2222 .{
2223 .pattern = "DUP <Vd>.2D, <Xn>",
2224 .symbols = .{
2225 .Vd = .{ .reg_alias = .vector },
2226 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2227 },
2228 .encode = .{ .dup, .{ .alias = .Vd, .format = .{ .vector = .@"2d" } }, .Xn },
2229 },
2230 // C7.2.57 FCMEQ (zero)
2231 .{
2232 .requires = .{.fullfp16},
2233 .pattern = "FCMEQ <Hd>, <Hn>, #<0.0>",
2234 .symbols = .{
2235 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2236 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2237 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2238 },
2239 .encode = .{ .fcmeq, .Hd, .Hn, .zero },
2240 },
2241 .{
2242 .pattern = "FCMEQ <Sd>, <Sn>, #<0.0>",
2243 .symbols = .{
2244 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2245 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2246 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2247 },
2248 .encode = .{ .fcmeq, .Sd, .Sn, .zero },
2249 },
2250 .{
2251 .pattern = "FCMEQ <Dd>, <Dn>, #<0.0>",
2252 .symbols = .{
2253 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2254 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2255 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2256 },
2257 .encode = .{ .fcmeq, .Dd, .Dn, .zero },
2258 },
2259 .{
2260 .requires = .{.fullfp16},
2261 .pattern = "FCMEQ <Vd>.<T>, <Vn>.<T>, #<0.0>",
2262 .symbols = .{
2263 .Vd = .{ .reg_alias = .vector },
2264 .T = .{ .arrangement = .{ .elem_size = .half } },
2265 .Vn = .{ .reg_alias = .vector },
2266 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2267 },
2268 .encode = .{
2269 .fcmeq,
2270 .{ .alias = .Vd, .format = .{ .vector = .T } },
2271 .{ .alias = .Vn, .format = .{ .vector = .T } },
2272 .zero,
2273 },
2274 },
2275 .{
2276 .pattern = "FCMEQ <Vd>.<T>, <Vn>.<T>, #<0.0>",
2277 .symbols = .{
2278 .Vd = .{ .reg_alias = .vector },
2279 .T = .{ .arrangement = .{ .elem_size = .single } },
2280 .Vn = .{ .reg_alias = .vector },
2281 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2282 },
2283 .encode = .{
2284 .fcmeq,
2285 .{ .alias = .Vd, .format = .{ .vector = .T } },
2286 .{ .alias = .Vn, .format = .{ .vector = .T } },
2287 .zero,
2288 },
2289 },
2290 .{
2291 .pattern = "FCMEQ <Vd>.2D, <Vn>.2D, #<0.0>",
2292 .symbols = .{
2293 .Vd = .{ .reg_alias = .vector },
2294 .Vn = .{ .reg_alias = .vector },
2295 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2296 },
2297 .encode = .{
2298 .fcmeq,
2299 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2300 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2301 .zero,
2302 },
2303 },
2304 // C7.2.59 FCMGE (zero)
2305 .{
2306 .requires = .{.fullfp16},
2307 .pattern = "FCMGE <Hd>, <Hn>, #<0.0>",
2308 .symbols = .{
2309 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2310 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2311 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2312 },
2313 .encode = .{ .fcmge, .Hd, .Hn, .zero },
2314 },
2315 .{
2316 .pattern = "FCMGE <Sd>, <Sn>, #<0.0>",
2317 .symbols = .{
2318 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2319 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2320 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2321 },
2322 .encode = .{ .fcmge, .Sd, .Sn, .zero },
2323 },
2324 .{
2325 .pattern = "FCMGE <Dd>, <Dn>, #<0.0>",
2326 .symbols = .{
2327 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2328 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2329 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2330 },
2331 .encode = .{ .fcmge, .Dd, .Dn, .zero },
2332 },
2333 .{
2334 .requires = .{.fullfp16},
2335 .pattern = "FCMGE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2336 .symbols = .{
2337 .Vd = .{ .reg_alias = .vector },
2338 .T = .{ .arrangement = .{ .elem_size = .half } },
2339 .Vn = .{ .reg_alias = .vector },
2340 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2341 },
2342 .encode = .{
2343 .fcmge,
2344 .{ .alias = .Vd, .format = .{ .vector = .T } },
2345 .{ .alias = .Vn, .format = .{ .vector = .T } },
2346 .zero,
2347 },
2348 },
2349 .{
2350 .pattern = "FCMGE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2351 .symbols = .{
2352 .Vd = .{ .reg_alias = .vector },
2353 .T = .{ .arrangement = .{ .elem_size = .single } },
2354 .Vn = .{ .reg_alias = .vector },
2355 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2356 },
2357 .encode = .{
2358 .fcmge,
2359 .{ .alias = .Vd, .format = .{ .vector = .T } },
2360 .{ .alias = .Vn, .format = .{ .vector = .T } },
2361 .zero,
2362 },
2363 },
2364 .{
2365 .pattern = "FCMGE <Vd>.2D, <Vn>.2D, #<0.0>",
2366 .symbols = .{
2367 .Vd = .{ .reg_alias = .vector },
2368 .Vn = .{ .reg_alias = .vector },
2369 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2370 },
2371 .encode = .{
2372 .fcmge,
2373 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2374 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2375 .zero,
2376 },
2377 },
2378 // C7.2.61 FCMGT (zero)
2379 .{
2380 .requires = .{.fullfp16},
2381 .pattern = "FCMGT <Hd>, <Hn>, #<0.0>",
2382 .symbols = .{
2383 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2384 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2385 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2386 },
2387 .encode = .{ .fcmgt, .Hd, .Hn, .zero },
2388 },
2389 .{
2390 .pattern = "FCMGT <Sd>, <Sn>, #<0.0>",
2391 .symbols = .{
2392 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2393 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2394 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2395 },
2396 .encode = .{ .fcmgt, .Sd, .Sn, .zero },
2397 },
2398 .{
2399 .pattern = "FCMGT <Dd>, <Dn>, #<0.0>",
2400 .symbols = .{
2401 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2402 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2403 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2404 },
2405 .encode = .{ .fcmgt, .Dd, .Dn, .zero },
2406 },
2407 .{
2408 .requires = .{.fullfp16},
2409 .pattern = "FCMGT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2410 .symbols = .{
2411 .Vd = .{ .reg_alias = .vector },
2412 .T = .{ .arrangement = .{ .elem_size = .half } },
2413 .Vn = .{ .reg_alias = .vector },
2414 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2415 },
2416 .encode = .{
2417 .fcmgt,
2418 .{ .alias = .Vd, .format = .{ .vector = .T } },
2419 .{ .alias = .Vn, .format = .{ .vector = .T } },
2420 .zero,
2421 },
2422 },
2423 .{
2424 .pattern = "FCMGT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2425 .symbols = .{
2426 .Vd = .{ .reg_alias = .vector },
2427 .T = .{ .arrangement = .{ .elem_size = .single } },
2428 .Vn = .{ .reg_alias = .vector },
2429 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2430 },
2431 .encode = .{
2432 .fcmgt,
2433 .{ .alias = .Vd, .format = .{ .vector = .T } },
2434 .{ .alias = .Vn, .format = .{ .vector = .T } },
2435 .zero,
2436 },
2437 },
2438 .{
2439 .pattern = "FCMGT <Vd>.2D, <Vn>.2D, #<0.0>",
2440 .symbols = .{
2441 .Vd = .{ .reg_alias = .vector },
2442 .Vn = .{ .reg_alias = .vector },
2443 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2444 },
2445 .encode = .{
2446 .fcmgt,
2447 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2448 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2449 .zero,
2450 },
2451 },
2452 // C7.2.64 FCMLE (zero)
2453 .{
2454 .requires = .{.fullfp16},
2455 .pattern = "FCMLE <Hd>, <Hn>, #<0.0>",
2456 .symbols = .{
2457 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2458 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2459 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2460 },
2461 .encode = .{ .fcmle, .Hd, .Hn, .zero },
2462 },
2463 .{
2464 .pattern = "FCMLE <Sd>, <Sn>, #<0.0>",
2465 .symbols = .{
2466 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2467 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2468 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2469 },
2470 .encode = .{ .fcmle, .Sd, .Sn, .zero },
2471 },
2472 .{
2473 .pattern = "FCMLE <Dd>, <Dn>, #<0.0>",
2474 .symbols = .{
2475 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2476 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2477 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2478 },
2479 .encode = .{ .fcmle, .Dd, .Dn, .zero },
2480 },
2481 .{
2482 .requires = .{.fullfp16},
2483 .pattern = "FCMLE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2484 .symbols = .{
2485 .Vd = .{ .reg_alias = .vector },
2486 .T = .{ .arrangement = .{ .elem_size = .half } },
2487 .Vn = .{ .reg_alias = .vector },
2488 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2489 },
2490 .encode = .{
2491 .fcmle,
2492 .{ .alias = .Vd, .format = .{ .vector = .T } },
2493 .{ .alias = .Vn, .format = .{ .vector = .T } },
2494 .zero,
2495 },
2496 },
2497 .{
2498 .pattern = "FCMLE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2499 .symbols = .{
2500 .Vd = .{ .reg_alias = .vector },
2501 .T = .{ .arrangement = .{ .elem_size = .single } },
2502 .Vn = .{ .reg_alias = .vector },
2503 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2504 },
2505 .encode = .{
2506 .fcmle,
2507 .{ .alias = .Vd, .format = .{ .vector = .T } },
2508 .{ .alias = .Vn, .format = .{ .vector = .T } },
2509 .zero,
2510 },
2511 },
2512 .{
2513 .pattern = "FCMLE <Vd>.2D, <Vn>.2D, #<0.0>",
2514 .symbols = .{
2515 .Vd = .{ .reg_alias = .vector },
2516 .Vn = .{ .reg_alias = .vector },
2517 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2518 },
2519 .encode = .{
2520 .fcmle,
2521 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2522 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2523 .zero,
2524 },
2525 },
2526 // C7.2.65 FCMLT (zero)
2527 .{
2528 .requires = .{.fullfp16},
2529 .pattern = "FCMLT <Hd>, <Hn>, #<0.0>",
2530 .symbols = .{
2531 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2532 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2533 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2534 },
2535 .encode = .{ .fcmlt, .Hd, .Hn, .zero },
2536 },
2537 .{
2538 .pattern = "FCMLT <Sd>, <Sn>, #<0.0>",
2539 .symbols = .{
2540 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2541 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2542 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2543 },
2544 .encode = .{ .fcmlt, .Sd, .Sn, .zero },
2545 },
2546 .{
2547 .pattern = "FCMLT <Dd>, <Dn>, #<0.0>",
2548 .symbols = .{
2549 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2550 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2551 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2552 },
2553 .encode = .{ .fcmlt, .Dd, .Dn, .zero },
2554 },
2555 .{
2556 .requires = .{.fullfp16},
2557 .pattern = "FCMLT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2558 .symbols = .{
2559 .Vd = .{ .reg_alias = .vector },
2560 .T = .{ .arrangement = .{ .elem_size = .half } },
2561 .Vn = .{ .reg_alias = .vector },
2562 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2563 },
2564 .encode = .{
2565 .fcmlt,
2566 .{ .alias = .Vd, .format = .{ .vector = .T } },
2567 .{ .alias = .Vn, .format = .{ .vector = .T } },
2568 .zero,
2569 },
2570 },
2571 .{
2572 .pattern = "FCMLT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2573 .symbols = .{
2574 .Vd = .{ .reg_alias = .vector },
2575 .T = .{ .arrangement = .{ .elem_size = .single } },
2576 .Vn = .{ .reg_alias = .vector },
2577 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2578 },
2579 .encode = .{
2580 .fcmlt,
2581 .{ .alias = .Vd, .format = .{ .vector = .T } },
2582 .{ .alias = .Vn, .format = .{ .vector = .T } },
2583 .zero,
2584 },
2585 },
2586 .{
2587 .pattern = "FCMLT <Vd>.2D, <Vn>.2D, #<0.0>",
2588 .symbols = .{
2589 .Vd = .{ .reg_alias = .vector },
2590 .Vn = .{ .reg_alias = .vector },
2591 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2592 },
2593 .encode = .{
2594 .fcmlt,
2595 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2596 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2597 .zero,
2598 },
2599 },
2600 // C7.2.70 FCVTAS (vector)
2601 .{
2602 .requires = .{.fullfp16},
2603 .pattern = "FCVTAS <Hd>, <Hn>",
2604 .symbols = .{
2605 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2606 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2607 },
2608 .encode = .{ .fcvtas, .Hd, .Hn },
2609 },
2610 .{
2611 .pattern = "FCVTAS <Sd>, <Sn>",
2612 .symbols = .{
2613 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2614 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2615 },
2616 .encode = .{ .fcvtas, .Sd, .Sn },
2617 },
2618 .{
2619 .pattern = "FCVTAS <Dd>, <Dn>",
2620 .symbols = .{
2621 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2622 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2623 },
2624 .encode = .{ .fcvtas, .Dd, .Dn },
2625 },
2626 .{
2627 .requires = .{.fullfp16},
2628 .pattern = "FCVTAS <Vd>.<T>, <Vn>.<T>",
2629 .symbols = .{
2630 .Vd = .{ .reg_alias = .vector },
2631 .T = .{ .arrangement = .{ .elem_size = .half } },
2632 .Vn = .{ .reg_alias = .vector },
2633 },
2634 .encode = .{
2635 .fcvtas,
2636 .{ .alias = .Vd, .format = .{ .vector = .T } },
2637 .{ .alias = .Vn, .format = .{ .vector = .T } },
2638 },
2639 },
2640 .{
2641 .pattern = "FCVTAS <Vd>.<T>, <Vn>.<T>",
2642 .symbols = .{
2643 .Vd = .{ .reg_alias = .vector },
2644 .T = .{ .arrangement = .{ .elem_size = .single } },
2645 .Vn = .{ .reg_alias = .vector },
2646 },
2647 .encode = .{
2648 .fcvtas,
2649 .{ .alias = .Vd, .format = .{ .vector = .T } },
2650 .{ .alias = .Vn, .format = .{ .vector = .T } },
2651 },
2652 },
2653 .{
2654 .pattern = "FCVTAS <Vd>.2D, <Vn>.2D",
2655 .symbols = .{
2656 .Vd = .{ .reg_alias = .vector },
2657 .Vn = .{ .reg_alias = .vector },
2658 },
2659 .encode = .{
2660 .fcvtas,
2661 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2662 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2663 },
2664 },
2665 // C7.2.71 FCVTAS (scalar)
2666 .{
2667 .requires = .{.fullfp16},
2668 .pattern = "FCVTAS <Wd>, <Hn>",
2669 .symbols = .{
2670 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2671 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2672 },
2673 .encode = .{ .fcvtas, .Wd, .Hn },
2674 },
2675 .{
2676 .requires = .{.fullfp16},
2677 .pattern = "FCVTAS <Xd>, <Hn>",
2678 .symbols = .{
2679 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2680 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2681 },
2682 .encode = .{ .fcvtas, .Xd, .Hn },
2683 },
2684 .{
2685 .pattern = "FCVTAS <Wd>, <Sn>",
2686 .symbols = .{
2687 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2688 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2689 },
2690 .encode = .{ .fcvtas, .Wd, .Sn },
2691 },
2692 .{
2693 .pattern = "FCVTAS <Xd>, <Sn>",
2694 .symbols = .{
2695 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2696 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2697 },
2698 .encode = .{ .fcvtas, .Xd, .Sn },
2699 },
2700 .{
2701 .pattern = "FCVTAS <Wd>, <Dn>",
2702 .symbols = .{
2703 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2704 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2705 },
2706 .encode = .{ .fcvtas, .Wd, .Dn },
2707 },
2708 .{
2709 .pattern = "FCVTAS <Xd>, <Dn>",
2710 .symbols = .{
2711 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2712 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2713 },
2714 .encode = .{ .fcvtas, .Xd, .Dn },
2715 },
2716 // C7.2.72 FCVTAU (vector)
2717 .{
2718 .requires = .{.fullfp16},
2719 .pattern = "FCVTAU <Hd>, <Hn>",
2720 .symbols = .{
2721 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2722 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2723 },
2724 .encode = .{ .fcvtau, .Hd, .Hn },
2725 },
2726 .{
2727 .pattern = "FCVTAU <Sd>, <Sn>",
2728 .symbols = .{
2729 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2730 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2731 },
2732 .encode = .{ .fcvtau, .Sd, .Sn },
2733 },
2734 .{
2735 .pattern = "FCVTAU <Dd>, <Dn>",
2736 .symbols = .{
2737 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2738 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2739 },
2740 .encode = .{ .fcvtau, .Dd, .Dn },
2741 },
2742 .{
2743 .requires = .{.fullfp16},
2744 .pattern = "FCVTAU <Vd>.<T>, <Vn>.<T>",
2745 .symbols = .{
2746 .Vd = .{ .reg_alias = .vector },
2747 .T = .{ .arrangement = .{ .elem_size = .half } },
2748 .Vn = .{ .reg_alias = .vector },
2749 },
2750 .encode = .{
2751 .fcvtau,
2752 .{ .alias = .Vd, .format = .{ .vector = .T } },
2753 .{ .alias = .Vn, .format = .{ .vector = .T } },
2754 },
2755 },
2756 .{
2757 .pattern = "FCVTAU <Vd>.<T>, <Vn>.<T>",
2758 .symbols = .{
2759 .Vd = .{ .reg_alias = .vector },
2760 .T = .{ .arrangement = .{ .elem_size = .single } },
2761 .Vn = .{ .reg_alias = .vector },
2762 },
2763 .encode = .{
2764 .fcvtau,
2765 .{ .alias = .Vd, .format = .{ .vector = .T } },
2766 .{ .alias = .Vn, .format = .{ .vector = .T } },
2767 },
2768 },
2769 .{
2770 .pattern = "FCVTAU <Vd>.2D, <Vn>.2D",
2771 .symbols = .{
2772 .Vd = .{ .reg_alias = .vector },
2773 .Vn = .{ .reg_alias = .vector },
2774 },
2775 .encode = .{
2776 .fcvtau,
2777 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2778 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2779 },
2780 },
2781 // C7.2.73 FCVTAU (scalar)
2782 .{
2783 .requires = .{.fullfp16},
2784 .pattern = "FCVTAU <Wd>, <Hn>",
2785 .symbols = .{
2786 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2787 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2788 },
2789 .encode = .{ .fcvtau, .Wd, .Hn },
2790 },
2791 .{
2792 .requires = .{.fullfp16},
2793 .pattern = "FCVTAU <Xd>, <Hn>",
2794 .symbols = .{
2795 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2796 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2797 },
2798 .encode = .{ .fcvtau, .Xd, .Hn },
2799 },
2800 .{
2801 .pattern = "FCVTAU <Wd>, <Sn>",
2802 .symbols = .{
2803 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2804 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2805 },
2806 .encode = .{ .fcvtau, .Wd, .Sn },
2807 },
2808 .{
2809 .pattern = "FCVTAU <Xd>, <Sn>",
2810 .symbols = .{
2811 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2812 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2813 },
2814 .encode = .{ .fcvtau, .Xd, .Sn },
2815 },
2816 .{
2817 .pattern = "FCVTAU <Wd>, <Dn>",
2818 .symbols = .{
2819 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2820 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2821 },
2822 .encode = .{ .fcvtau, .Wd, .Dn },
2823 },
2824 .{
2825 .pattern = "FCVTAU <Xd>, <Dn>",
2826 .symbols = .{
2827 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2828 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2829 },
2830 .encode = .{ .fcvtau, .Xd, .Dn },
2831 },
2832 // C7.2.75 FCVTMS (vector)
2833 .{
2834 .requires = .{.fullfp16},
2835 .pattern = "FCVTMS <Hd>, <Hn>",
2836 .symbols = .{
2837 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2838 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2839 },
2840 .encode = .{ .fcvtms, .Hd, .Hn },
2841 },
2842 .{
2843 .pattern = "FCVTMS <Sd>, <Sn>",
2844 .symbols = .{
2845 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2846 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2847 },
2848 .encode = .{ .fcvtms, .Sd, .Sn },
2849 },
2850 .{
2851 .pattern = "FCVTMS <Dd>, <Dn>",
2852 .symbols = .{
2853 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2854 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2855 },
2856 .encode = .{ .fcvtms, .Dd, .Dn },
2857 },
2858 .{
2859 .requires = .{.fullfp16},
2860 .pattern = "FCVTMS <Vd>.<T>, <Vn>.<T>",
2861 .symbols = .{
2862 .Vd = .{ .reg_alias = .vector },
2863 .T = .{ .arrangement = .{ .elem_size = .half } },
2864 .Vn = .{ .reg_alias = .vector },
2865 },
2866 .encode = .{
2867 .fcvtms,
2868 .{ .alias = .Vd, .format = .{ .vector = .T } },
2869 .{ .alias = .Vn, .format = .{ .vector = .T } },
2870 },
2871 },
2872 .{
2873 .pattern = "FCVTMS <Vd>.<T>, <Vn>.<T>",
2874 .symbols = .{
2875 .Vd = .{ .reg_alias = .vector },
2876 .T = .{ .arrangement = .{ .elem_size = .single } },
2877 .Vn = .{ .reg_alias = .vector },
2878 },
2879 .encode = .{
2880 .fcvtms,
2881 .{ .alias = .Vd, .format = .{ .vector = .T } },
2882 .{ .alias = .Vn, .format = .{ .vector = .T } },
2883 },
2884 },
2885 .{
2886 .pattern = "FCVTMS <Vd>.2D, <Vn>.2D",
2887 .symbols = .{
2888 .Vd = .{ .reg_alias = .vector },
2889 .Vn = .{ .reg_alias = .vector },
2890 },
2891 .encode = .{
2892 .fcvtms,
2893 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2894 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2895 },
2896 },
2897 // C7.2.76 FCVTMS (scalar)
2898 .{
2899 .requires = .{.fullfp16},
2900 .pattern = "FCVTMS <Wd>, <Hn>",
2901 .symbols = .{
2902 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2903 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2904 },
2905 .encode = .{ .fcvtms, .Wd, .Hn },
2906 },
2907 .{
2908 .requires = .{.fullfp16},
2909 .pattern = "FCVTMS <Xd>, <Hn>",
2910 .symbols = .{
2911 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2912 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2913 },
2914 .encode = .{ .fcvtms, .Xd, .Hn },
2915 },
2916 .{
2917 .pattern = "FCVTMS <Wd>, <Sn>",
2918 .symbols = .{
2919 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2920 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2921 },
2922 .encode = .{ .fcvtms, .Wd, .Sn },
2923 },
2924 .{
2925 .pattern = "FCVTMS <Xd>, <Sn>",
2926 .symbols = .{
2927 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2928 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2929 },
2930 .encode = .{ .fcvtms, .Xd, .Sn },
2931 },
2932 .{
2933 .pattern = "FCVTMS <Wd>, <Dn>",
2934 .symbols = .{
2935 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2936 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2937 },
2938 .encode = .{ .fcvtms, .Wd, .Dn },
2939 },
2940 .{
2941 .pattern = "FCVTMS <Xd>, <Dn>",
2942 .symbols = .{
2943 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2944 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2945 },
2946 .encode = .{ .fcvtms, .Xd, .Dn },
2947 },
2948 // C7.2.77 FCVTMU (vector)
2949 .{
2950 .requires = .{.fullfp16},
2951 .pattern = "FCVTMU <Hd>, <Hn>",
2952 .symbols = .{
2953 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2954 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2955 },
2956 .encode = .{ .fcvtmu, .Hd, .Hn },
2957 },
2958 .{
2959 .pattern = "FCVTMU <Sd>, <Sn>",
2960 .symbols = .{
2961 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2962 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2963 },
2964 .encode = .{ .fcvtmu, .Sd, .Sn },
2965 },
2966 .{
2967 .pattern = "FCVTMU <Dd>, <Dn>",
2968 .symbols = .{
2969 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2970 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2971 },
2972 .encode = .{ .fcvtmu, .Dd, .Dn },
2973 },
2974 .{
2975 .requires = .{.fullfp16},
2976 .pattern = "FCVTMU <Vd>.<T>, <Vn>.<T>",
2977 .symbols = .{
2978 .Vd = .{ .reg_alias = .vector },
2979 .T = .{ .arrangement = .{ .elem_size = .half } },
2980 .Vn = .{ .reg_alias = .vector },
2981 },
2982 .encode = .{
2983 .fcvtmu,
2984 .{ .alias = .Vd, .format = .{ .vector = .T } },
2985 .{ .alias = .Vn, .format = .{ .vector = .T } },
2986 },
2987 },
2988 .{
2989 .pattern = "FCVTMU <Vd>.<T>, <Vn>.<T>",
2990 .symbols = .{
2991 .Vd = .{ .reg_alias = .vector },
2992 .T = .{ .arrangement = .{ .elem_size = .single } },
2993 .Vn = .{ .reg_alias = .vector },
2994 },
2995 .encode = .{
2996 .fcvtmu,
2997 .{ .alias = .Vd, .format = .{ .vector = .T } },
2998 .{ .alias = .Vn, .format = .{ .vector = .T } },
2999 },
3000 },
3001 .{
3002 .pattern = "FCVTMU <Vd>.2D, <Vn>.2D",
3003 .symbols = .{
3004 .Vd = .{ .reg_alias = .vector },
3005 .Vn = .{ .reg_alias = .vector },
3006 },
3007 .encode = .{
3008 .fcvtmu,
3009 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3010 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3011 },
3012 },
3013 // C7.2.78 FCVTMU (scalar)
3014 .{
3015 .requires = .{.fullfp16},
3016 .pattern = "FCVTMU <Wd>, <Hn>",
3017 .symbols = .{
3018 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3019 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3020 },
3021 .encode = .{ .fcvtmu, .Wd, .Hn },
3022 },
3023 .{
3024 .requires = .{.fullfp16},
3025 .pattern = "FCVTMU <Xd>, <Hn>",
3026 .symbols = .{
3027 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3028 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3029 },
3030 .encode = .{ .fcvtmu, .Xd, .Hn },
3031 },
3032 .{
3033 .pattern = "FCVTMU <Wd>, <Sn>",
3034 .symbols = .{
3035 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3036 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3037 },
3038 .encode = .{ .fcvtmu, .Wd, .Sn },
3039 },
3040 .{
3041 .pattern = "FCVTMU <Xd>, <Sn>",
3042 .symbols = .{
3043 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3044 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3045 },
3046 .encode = .{ .fcvtmu, .Xd, .Sn },
3047 },
3048 .{
3049 .pattern = "FCVTMU <Wd>, <Dn>",
3050 .symbols = .{
3051 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3052 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3053 },
3054 .encode = .{ .fcvtmu, .Wd, .Dn },
3055 },
3056 .{
3057 .pattern = "FCVTMU <Xd>, <Dn>",
3058 .symbols = .{
3059 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3060 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3061 },
3062 .encode = .{ .fcvtmu, .Xd, .Dn },
3063 },
3064 // C7.2.80 FCVTNS (vector)
3065 .{
3066 .requires = .{.fullfp16},
3067 .pattern = "FCVTNS <Hd>, <Hn>",
3068 .symbols = .{
3069 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3070 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3071 },
3072 .encode = .{ .fcvtns, .Hd, .Hn },
3073 },
3074 .{
3075 .pattern = "FCVTNS <Sd>, <Sn>",
3076 .symbols = .{
3077 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3078 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3079 },
3080 .encode = .{ .fcvtns, .Sd, .Sn },
3081 },
3082 .{
3083 .pattern = "FCVTNS <Dd>, <Dn>",
3084 .symbols = .{
3085 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3086 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3087 },
3088 .encode = .{ .fcvtns, .Dd, .Dn },
3089 },
3090 .{
3091 .requires = .{.fullfp16},
3092 .pattern = "FCVTNS <Vd>.<T>, <Vn>.<T>",
3093 .symbols = .{
3094 .Vd = .{ .reg_alias = .vector },
3095 .T = .{ .arrangement = .{ .elem_size = .half } },
3096 .Vn = .{ .reg_alias = .vector },
3097 },
3098 .encode = .{
3099 .fcvtns,
3100 .{ .alias = .Vd, .format = .{ .vector = .T } },
3101 .{ .alias = .Vn, .format = .{ .vector = .T } },
3102 },
3103 },
3104 .{
3105 .pattern = "FCVTNS <Vd>.<T>, <Vn>.<T>",
3106 .symbols = .{
3107 .Vd = .{ .reg_alias = .vector },
3108 .T = .{ .arrangement = .{ .elem_size = .single } },
3109 .Vn = .{ .reg_alias = .vector },
3110 },
3111 .encode = .{
3112 .fcvtns,
3113 .{ .alias = .Vd, .format = .{ .vector = .T } },
3114 .{ .alias = .Vn, .format = .{ .vector = .T } },
3115 },
3116 },
3117 .{
3118 .pattern = "FCVTNS <Vd>.2D, <Vn>.2D",
3119 .symbols = .{
3120 .Vd = .{ .reg_alias = .vector },
3121 .Vn = .{ .reg_alias = .vector },
3122 },
3123 .encode = .{
3124 .fcvtns,
3125 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3126 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3127 },
3128 },
3129 // C7.2.81 FCVTNS (scalar)
3130 .{
3131 .requires = .{.fullfp16},
3132 .pattern = "FCVTNS <Wd>, <Hn>",
3133 .symbols = .{
3134 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3135 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3136 },
3137 .encode = .{ .fcvtns, .Wd, .Hn },
3138 },
3139 .{
3140 .requires = .{.fullfp16},
3141 .pattern = "FCVTNS <Xd>, <Hn>",
3142 .symbols = .{
3143 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3144 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3145 },
3146 .encode = .{ .fcvtns, .Xd, .Hn },
3147 },
3148 .{
3149 .pattern = "FCVTNS <Wd>, <Sn>",
3150 .symbols = .{
3151 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3152 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3153 },
3154 .encode = .{ .fcvtns, .Wd, .Sn },
3155 },
3156 .{
3157 .pattern = "FCVTNS <Xd>, <Sn>",
3158 .symbols = .{
3159 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3160 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3161 },
3162 .encode = .{ .fcvtns, .Xd, .Sn },
3163 },
3164 .{
3165 .pattern = "FCVTNS <Wd>, <Dn>",
3166 .symbols = .{
3167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3168 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3169 },
3170 .encode = .{ .fcvtns, .Wd, .Dn },
3171 },
3172 .{
3173 .pattern = "FCVTNS <Xd>, <Dn>",
3174 .symbols = .{
3175 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3176 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3177 },
3178 .encode = .{ .fcvtns, .Xd, .Dn },
3179 },
3180 // C7.2.82 FCVTNU (vector)
3181 .{
3182 .requires = .{.fullfp16},
3183 .pattern = "FCVTNU <Hd>, <Hn>",
3184 .symbols = .{
3185 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3186 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3187 },
3188 .encode = .{ .fcvtnu, .Hd, .Hn },
3189 },
3190 .{
3191 .pattern = "FCVTNU <Sd>, <Sn>",
3192 .symbols = .{
3193 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3194 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3195 },
3196 .encode = .{ .fcvtnu, .Sd, .Sn },
3197 },
3198 .{
3199 .pattern = "FCVTNU <Dd>, <Dn>",
3200 .symbols = .{
3201 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3202 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3203 },
3204 .encode = .{ .fcvtnu, .Dd, .Dn },
3205 },
3206 .{
3207 .requires = .{.fullfp16},
3208 .pattern = "FCVTNU <Vd>.<T>, <Vn>.<T>",
3209 .symbols = .{
3210 .Vd = .{ .reg_alias = .vector },
3211 .T = .{ .arrangement = .{ .elem_size = .half } },
3212 .Vn = .{ .reg_alias = .vector },
3213 },
3214 .encode = .{
3215 .fcvtnu,
3216 .{ .alias = .Vd, .format = .{ .vector = .T } },
3217 .{ .alias = .Vn, .format = .{ .vector = .T } },
3218 },
3219 },
3220 .{
3221 .pattern = "FCVTNU <Vd>.<T>, <Vn>.<T>",
3222 .symbols = .{
3223 .Vd = .{ .reg_alias = .vector },
3224 .T = .{ .arrangement = .{ .elem_size = .single } },
3225 .Vn = .{ .reg_alias = .vector },
3226 },
3227 .encode = .{
3228 .fcvtnu,
3229 .{ .alias = .Vd, .format = .{ .vector = .T } },
3230 .{ .alias = .Vn, .format = .{ .vector = .T } },
3231 },
3232 },
3233 .{
3234 .pattern = "FCVTNU <Vd>.2D, <Vn>.2D",
3235 .symbols = .{
3236 .Vd = .{ .reg_alias = .vector },
3237 .Vn = .{ .reg_alias = .vector },
3238 },
3239 .encode = .{
3240 .fcvtnu,
3241 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3242 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3243 },
3244 },
3245 // C7.2.83 FCVTNU (scalar)
3246 .{
3247 .requires = .{.fullfp16},
3248 .pattern = "FCVTNU <Wd>, <Hn>",
3249 .symbols = .{
3250 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3251 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3252 },
3253 .encode = .{ .fcvtnu, .Wd, .Hn },
3254 },
3255 .{
3256 .requires = .{.fullfp16},
3257 .pattern = "FCVTNU <Xd>, <Hn>",
3258 .symbols = .{
3259 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3260 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3261 },
3262 .encode = .{ .fcvtnu, .Xd, .Hn },
3263 },
3264 .{
3265 .pattern = "FCVTNU <Wd>, <Sn>",
3266 .symbols = .{
3267 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3268 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3269 },
3270 .encode = .{ .fcvtnu, .Wd, .Sn },
3271 },
3272 .{
3273 .pattern = "FCVTNU <Xd>, <Sn>",
3274 .symbols = .{
3275 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3276 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3277 },
3278 .encode = .{ .fcvtnu, .Xd, .Sn },
3279 },
3280 .{
3281 .pattern = "FCVTNU <Wd>, <Dn>",
3282 .symbols = .{
3283 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3284 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3285 },
3286 .encode = .{ .fcvtnu, .Wd, .Dn },
3287 },
3288 .{
3289 .pattern = "FCVTNU <Xd>, <Dn>",
3290 .symbols = .{
3291 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3292 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3293 },
3294 .encode = .{ .fcvtnu, .Xd, .Dn },
3295 },
3296 // C7.2.84 FCVTPS (vector)
3297 .{
3298 .requires = .{.fullfp16},
3299 .pattern = "FCVTPS <Hd>, <Hn>",
3300 .symbols = .{
3301 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3302 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3303 },
3304 .encode = .{ .fcvtps, .Hd, .Hn },
3305 },
3306 .{
3307 .pattern = "FCVTPS <Sd>, <Sn>",
3308 .symbols = .{
3309 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3310 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3311 },
3312 .encode = .{ .fcvtps, .Sd, .Sn },
3313 },
3314 .{
3315 .pattern = "FCVTPS <Dd>, <Dn>",
3316 .symbols = .{
3317 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3318 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3319 },
3320 .encode = .{ .fcvtps, .Dd, .Dn },
3321 },
3322 .{
3323 .requires = .{.fullfp16},
3324 .pattern = "FCVTPS <Vd>.<T>, <Vn>.<T>",
3325 .symbols = .{
3326 .Vd = .{ .reg_alias = .vector },
3327 .T = .{ .arrangement = .{ .elem_size = .half } },
3328 .Vn = .{ .reg_alias = .vector },
3329 },
3330 .encode = .{
3331 .fcvtps,
3332 .{ .alias = .Vd, .format = .{ .vector = .T } },
3333 .{ .alias = .Vn, .format = .{ .vector = .T } },
3334 },
3335 },
3336 .{
3337 .pattern = "FCVTPS <Vd>.<T>, <Vn>.<T>",
3338 .symbols = .{
3339 .Vd = .{ .reg_alias = .vector },
3340 .T = .{ .arrangement = .{ .elem_size = .single } },
3341 .Vn = .{ .reg_alias = .vector },
3342 },
3343 .encode = .{
3344 .fcvtps,
3345 .{ .alias = .Vd, .format = .{ .vector = .T } },
3346 .{ .alias = .Vn, .format = .{ .vector = .T } },
3347 },
3348 },
3349 .{
3350 .pattern = "FCVTPS <Vd>.2D, <Vn>.2D",
3351 .symbols = .{
3352 .Vd = .{ .reg_alias = .vector },
3353 .Vn = .{ .reg_alias = .vector },
3354 },
3355 .encode = .{
3356 .fcvtps,
3357 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3358 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3359 },
3360 },
3361 // C7.2.85 FCVTPS (scalar)
3362 .{
3363 .requires = .{.fullfp16},
3364 .pattern = "FCVTPS <Wd>, <Hn>",
3365 .symbols = .{
3366 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3367 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3368 },
3369 .encode = .{ .fcvtps, .Wd, .Hn },
3370 },
3371 .{
3372 .requires = .{.fullfp16},
3373 .pattern = "FCVTPS <Xd>, <Hn>",
3374 .symbols = .{
3375 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3376 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3377 },
3378 .encode = .{ .fcvtps, .Xd, .Hn },
3379 },
3380 .{
3381 .pattern = "FCVTPS <Wd>, <Sn>",
3382 .symbols = .{
3383 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3384 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3385 },
3386 .encode = .{ .fcvtps, .Wd, .Sn },
3387 },
3388 .{
3389 .pattern = "FCVTPS <Xd>, <Sn>",
3390 .symbols = .{
3391 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3392 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3393 },
3394 .encode = .{ .fcvtps, .Xd, .Sn },
3395 },
3396 .{
3397 .pattern = "FCVTPS <Wd>, <Dn>",
3398 .symbols = .{
3399 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3400 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3401 },
3402 .encode = .{ .fcvtps, .Wd, .Dn },
3403 },
3404 .{
3405 .pattern = "FCVTPS <Xd>, <Dn>",
3406 .symbols = .{
3407 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3408 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3409 },
3410 .encode = .{ .fcvtps, .Xd, .Dn },
3411 },
3412 // C7.2.86 FCVTPU (vector)
3413 .{
3414 .requires = .{.fullfp16},
3415 .pattern = "FCVTPU <Hd>, <Hn>",
3416 .symbols = .{
3417 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3418 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3419 },
3420 .encode = .{ .fcvtpu, .Hd, .Hn },
3421 },
3422 .{
3423 .pattern = "FCVTPU <Sd>, <Sn>",
3424 .symbols = .{
3425 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3426 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3427 },
3428 .encode = .{ .fcvtpu, .Sd, .Sn },
3429 },
3430 .{
3431 .pattern = "FCVTPU <Dd>, <Dn>",
3432 .symbols = .{
3433 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3434 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3435 },
3436 .encode = .{ .fcvtpu, .Dd, .Dn },
3437 },
3438 .{
3439 .requires = .{.fullfp16},
3440 .pattern = "FCVTPU <Vd>.<T>, <Vn>.<T>",
3441 .symbols = .{
3442 .Vd = .{ .reg_alias = .vector },
3443 .T = .{ .arrangement = .{ .elem_size = .half } },
3444 .Vn = .{ .reg_alias = .vector },
3445 },
3446 .encode = .{
3447 .fcvtpu,
3448 .{ .alias = .Vd, .format = .{ .vector = .T } },
3449 .{ .alias = .Vn, .format = .{ .vector = .T } },
3450 },
3451 },
3452 .{
3453 .pattern = "FCVTPU <Vd>.<T>, <Vn>.<T>",
3454 .symbols = .{
3455 .Vd = .{ .reg_alias = .vector },
3456 .T = .{ .arrangement = .{ .elem_size = .single } },
3457 .Vn = .{ .reg_alias = .vector },
3458 },
3459 .encode = .{
3460 .fcvtpu,
3461 .{ .alias = .Vd, .format = .{ .vector = .T } },
3462 .{ .alias = .Vn, .format = .{ .vector = .T } },
3463 },
3464 },
3465 .{
3466 .pattern = "FCVTPU <Vd>.2D, <Vn>.2D",
3467 .symbols = .{
3468 .Vd = .{ .reg_alias = .vector },
3469 .Vn = .{ .reg_alias = .vector },
3470 },
3471 .encode = .{
3472 .fcvtpu,
3473 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3474 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3475 },
3476 },
3477 // C7.2.87 FCVTPU (scalar)
3478 .{
3479 .requires = .{.fullfp16},
3480 .pattern = "FCVTPU <Wd>, <Hn>",
3481 .symbols = .{
3482 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3483 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3484 },
3485 .encode = .{ .fcvtpu, .Wd, .Hn },
3486 },
3487 .{
3488 .requires = .{.fullfp16},
3489 .pattern = "FCVTPU <Xd>, <Hn>",
3490 .symbols = .{
3491 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3492 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3493 },
3494 .encode = .{ .fcvtpu, .Xd, .Hn },
3495 },
3496 .{
3497 .pattern = "FCVTPU <Wd>, <Sn>",
3498 .symbols = .{
3499 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3500 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3501 },
3502 .encode = .{ .fcvtpu, .Wd, .Sn },
3503 },
3504 .{
3505 .pattern = "FCVTPU <Xd>, <Sn>",
3506 .symbols = .{
3507 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3508 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3509 },
3510 .encode = .{ .fcvtpu, .Xd, .Sn },
3511 },
3512 .{
3513 .pattern = "FCVTPU <Wd>, <Dn>",
3514 .symbols = .{
3515 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3516 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3517 },
3518 .encode = .{ .fcvtpu, .Wd, .Dn },
3519 },
3520 .{
3521 .pattern = "FCVTPU <Xd>, <Dn>",
3522 .symbols = .{
3523 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3524 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3525 },
3526 .encode = .{ .fcvtpu, .Xd, .Dn },
3527 },
3528 // C7.2.90 FCVTZS (vector, integer)
3529 .{
3530 .requires = .{.fullfp16},
3531 .pattern = "FCVTZS <Hd>, <Hn>",
3532 .symbols = .{
3533 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3534 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3535 },
3536 .encode = .{ .fcvtzs, .Hd, .Hn },
3537 },
3538 .{
3539 .pattern = "FCVTZS <Sd>, <Sn>",
3540 .symbols = .{
3541 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3542 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3543 },
3544 .encode = .{ .fcvtzs, .Sd, .Sn },
3545 },
3546 .{
3547 .pattern = "FCVTZS <Dd>, <Dn>",
3548 .symbols = .{
3549 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3550 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3551 },
3552 .encode = .{ .fcvtzs, .Dd, .Dn },
3553 },
3554 .{
3555 .requires = .{.fullfp16},
3556 .pattern = "FCVTZS <Vd>.<T>, <Vn>.<T>",
3557 .symbols = .{
3558 .Vd = .{ .reg_alias = .vector },
3559 .T = .{ .arrangement = .{ .elem_size = .half } },
3560 .Vn = .{ .reg_alias = .vector },
3561 },
3562 .encode = .{
3563 .fcvtzs,
3564 .{ .alias = .Vd, .format = .{ .vector = .T } },
3565 .{ .alias = .Vn, .format = .{ .vector = .T } },
3566 },
3567 },
3568 .{
3569 .pattern = "FCVTZS <Vd>.<T>, <Vn>.<T>",
3570 .symbols = .{
3571 .Vd = .{ .reg_alias = .vector },
3572 .T = .{ .arrangement = .{ .elem_size = .single } },
3573 .Vn = .{ .reg_alias = .vector },
3574 },
3575 .encode = .{
3576 .fcvtzs,
3577 .{ .alias = .Vd, .format = .{ .vector = .T } },
3578 .{ .alias = .Vn, .format = .{ .vector = .T } },
3579 },
3580 },
3581 .{
3582 .pattern = "FCVTZS <Vd>.2D, <Vn>.2D",
3583 .symbols = .{
3584 .Vd = .{ .reg_alias = .vector },
3585 .Vn = .{ .reg_alias = .vector },
3586 },
3587 .encode = .{
3588 .fcvtzs,
3589 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3590 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3591 },
3592 },
3593 // C7.2.92 FCVTZS (scalar, integer)
3594 .{
3595 .requires = .{.fullfp16},
3596 .pattern = "FCVTZS <Wd>, <Hn>",
3597 .symbols = .{
3598 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3599 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3600 },
3601 .encode = .{ .fcvtzs, .Wd, .Hn },
3602 },
3603 .{
3604 .requires = .{.fullfp16},
3605 .pattern = "FCVTZS <Xd>, <Hn>",
3606 .symbols = .{
3607 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3608 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3609 },
3610 .encode = .{ .fcvtzs, .Xd, .Hn },
3611 },
3612 .{
3613 .pattern = "FCVTZS <Wd>, <Sn>",
3614 .symbols = .{
3615 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3616 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3617 },
3618 .encode = .{ .fcvtzs, .Wd, .Sn },
3619 },
3620 .{
3621 .pattern = "FCVTZS <Xd>, <Sn>",
3622 .symbols = .{
3623 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3624 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3625 },
3626 .encode = .{ .fcvtzs, .Xd, .Sn },
3627 },
3628 .{
3629 .pattern = "FCVTZS <Wd>, <Dn>",
3630 .symbols = .{
3631 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3632 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3633 },
3634 .encode = .{ .fcvtzs, .Wd, .Dn },
3635 },
3636 .{
3637 .pattern = "FCVTZS <Xd>, <Dn>",
3638 .symbols = .{
3639 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3640 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3641 },
3642 .encode = .{ .fcvtzs, .Xd, .Dn },
3643 },
3644 // C7.2.94 FCVTZU (vector, integer)
3645 .{
3646 .requires = .{.fullfp16},
3647 .pattern = "FCVTZU <Hd>, <Hn>",
3648 .symbols = .{
3649 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3650 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3651 },
3652 .encode = .{ .fcvtzu, .Hd, .Hn },
3653 },
3654 .{
3655 .pattern = "FCVTZU <Sd>, <Sn>",
3656 .symbols = .{
3657 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3658 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3659 },
3660 .encode = .{ .fcvtzu, .Sd, .Sn },
3661 },
3662 .{
3663 .pattern = "FCVTZU <Dd>, <Dn>",
3664 .symbols = .{
3665 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3666 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3667 },
3668 .encode = .{ .fcvtzu, .Dd, .Dn },
3669 },
3670 .{
3671 .requires = .{.fullfp16},
3672 .pattern = "FCVTZU <Vd>.<T>, <Vn>.<T>",
3673 .symbols = .{
3674 .Vd = .{ .reg_alias = .vector },
3675 .T = .{ .arrangement = .{ .elem_size = .half } },
3676 .Vn = .{ .reg_alias = .vector },
3677 },
3678 .encode = .{
3679 .fcvtzu,
3680 .{ .alias = .Vd, .format = .{ .vector = .T } },
3681 .{ .alias = .Vn, .format = .{ .vector = .T } },
3682 },
3683 },
3684 .{
3685 .pattern = "FCVTZU <Vd>.<T>, <Vn>.<T>",
3686 .symbols = .{
3687 .Vd = .{ .reg_alias = .vector },
3688 .T = .{ .arrangement = .{ .elem_size = .single } },
3689 .Vn = .{ .reg_alias = .vector },
3690 },
3691 .encode = .{
3692 .fcvtzu,
3693 .{ .alias = .Vd, .format = .{ .vector = .T } },
3694 .{ .alias = .Vn, .format = .{ .vector = .T } },
3695 },
3696 },
3697 .{
3698 .pattern = "FCVTZU <Vd>.2D, <Vn>.2D",
3699 .symbols = .{
3700 .Vd = .{ .reg_alias = .vector },
3701 .Vn = .{ .reg_alias = .vector },
3702 },
3703 .encode = .{
3704 .fcvtzu,
3705 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3706 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3707 },
3708 },
3709 // C7.2.96 FCVTZU (scalar, integer)
3710 .{
3711 .requires = .{.fullfp16},
3712 .pattern = "FCVTZU <Wd>, <Hn>",
3713 .symbols = .{
3714 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3715 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3716 },
3717 .encode = .{ .fcvtzu, .Wd, .Hn },
3718 },
3719 .{
3720 .requires = .{.fullfp16},
3721 .pattern = "FCVTZU <Xd>, <Hn>",
3722 .symbols = .{
3723 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3724 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3725 },
3726 .encode = .{ .fcvtzu, .Xd, .Hn },
3727 },
3728 .{
3729 .pattern = "FCVTZU <Wd>, <Sn>",
3730 .symbols = .{
3731 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3732 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3733 },
3734 .encode = .{ .fcvtzu, .Wd, .Sn },
3735 },
3736 .{
3737 .pattern = "FCVTZU <Xd>, <Sn>",
3738 .symbols = .{
3739 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3740 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3741 },
3742 .encode = .{ .fcvtzu, .Xd, .Sn },
3743 },
3744 .{
3745 .pattern = "FCVTZU <Wd>, <Dn>",
3746 .symbols = .{
3747 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3748 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3749 },
3750 .encode = .{ .fcvtzu, .Wd, .Dn },
3751 },
3752 .{
3753 .pattern = "FCVTZU <Xd>, <Dn>",
3754 .symbols = .{
3755 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3756 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3757 },
3758 .encode = .{ .fcvtzu, .Xd, .Dn },
3759 },
3760 // C7.2.129 FMOV (vector, immediate)
3761 .{
3762 .requires = .{.fullfp16},
3763 .pattern = "FMOV <Vd>.<T>, #<imm>",
3764 .symbols = .{
3765 .Vd = .{ .reg_alias = .vector },
3766 .T = .{ .arrangement = .{ .elem_size = .half } },
3767 .imm = .{ .fimm = .{} },
3768 },
3769 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .T } }, .{ .immediate = .imm } },
3770 },
3771 .{
3772 .pattern = "FMOV <Vd>.<T>, #<imm>",
3773 .symbols = .{
3774 .Vd = .{ .reg_alias = .vector },
3775 .T = .{ .arrangement = .{ .elem_size = .single } },
3776 .imm = .{ .fimm = .{} },
3777 },
3778 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .T } }, .{ .immediate = .imm } },
3779 },
3780 .{
3781 .pattern = "FMOV <Vd>.2D, #<imm>",
3782 .symbols = .{
3783 .Vd = .{ .reg_alias = .vector },
3784 .imm = .{ .fimm = .{} },
3785 },
3786 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .@"2d" } }, .{ .immediate = .imm } },
3787 },
3788 // C7.2.130 FMOV (register)
3789 .{
3790 .requires = .{.fullfp16},
3791 .pattern = "FMOV <Hd>, <Hn>",
3792 .symbols = .{
3793 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3794 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3795 },
3796 .encode = .{ .fmov, .Hd, .{ .register = .Hn } },
3797 },
3798 .{
3799 .pattern = "FMOV <Sd>, <Sn>",
3800 .symbols = .{
3801 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3802 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3803 },
3804 .encode = .{ .fmov, .Sd, .{ .register = .Sn } },
3805 },
3806 .{
3807 .pattern = "FMOV <Dd>, <Dn>",
3808 .symbols = .{
3809 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3810 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3811 },
3812 .encode = .{ .fmov, .Dd, .{ .register = .Dn } },
3813 },
3814 // C7.2.131 FMOV (general)
3815 .{
3816 .requires = .{.fullfp16},
3817 .pattern = "FMOV <Wd>, <Hn>",
3818 .symbols = .{
3819 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3820 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3821 },
3822 .encode = .{ .fmov, .Wd, .{ .register = .Hn } },
3823 },
3824 .{
3825 .requires = .{.fullfp16},
3826 .pattern = "FMOV <Xd>, <Hn>",
3827 .symbols = .{
3828 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3829 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3830 },
3831 .encode = .{ .fmov, .Xd, .{ .register = .Hn } },
3832 },
3833 .{
3834 .requires = .{.fullfp16},
3835 .pattern = "FMOV <Hd>, <Wn>",
3836 .symbols = .{
3837 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3838 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
3839 },
3840 .encode = .{ .fmov, .Hd, .{ .register = .Wn } },
3841 },
3842 .{
3843 .pattern = "FMOV <Sd>, <Wn>",
3844 .symbols = .{
3845 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3846 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
3847 },
3848 .encode = .{ .fmov, .Sd, .{ .register = .Wn } },
3849 },
3850 .{
3851 .pattern = "FMOV <Wd>, <Sn>",
3852 .symbols = .{
3853 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3854 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3855 },
3856 .encode = .{ .fmov, .Wd, .{ .register = .Sn } },
3857 },
3858 .{
3859 .requires = .{.fullfp16},
3860 .pattern = "FMOV <Hd>, <Xn>",
3861 .symbols = .{
3862 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3863 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3864 },
3865 .encode = .{ .fmov, .Hd, .{ .register = .Xn } },
3866 },
3867 .{
3868 .pattern = "FMOV <Dd>, <Xn>",
3869 .symbols = .{
3870 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3871 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3872 },
3873 .encode = .{ .fmov, .Dd, .{ .register = .Xn } },
3874 },
3875 .{
3876 .pattern = "FMOV <Vd>.D[<index>], <Xn>",
3877 .symbols = .{
3878 .Vd = .{ .reg_alias = .vector },
3879 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 }, .min_valid = 1 } },
3880 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3881 },
3882 .encode = .{
3883 .fmov,
3884 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
3885 .{ .register = .Xn },
3886 },
3887 },
3888 .{
3889 .pattern = "FMOV <Xd>, <Dn>",
3890 .symbols = .{
3891 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3892 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3893 },
3894 .encode = .{ .fmov, .Xd, .{ .register = .Dn } },
3895 },
3896 .{
3897 .pattern = "FMOV <Xd>, <Vn>.D[<index>]",
3898 .symbols = .{
3899 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3900 .Vn = .{ .reg_alias = .vector },
3901 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 }, .min_valid = 1 } },
3902 },
3903 .encode = .{ .fmov, .Xd, .{
3904 .register = .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
3905 } },
3906 },
3907 // C7.2.132 FMOV (scalar, immediate)
3908 .{
3909 .requires = .{.fullfp16},
3910 .pattern = "FMOV <Hd>, #<imm>",
3911 .symbols = .{
3912 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3913 .imm = .{ .fimm = .{} },
3914 },
3915 .encode = .{ .fmov, .Hd, .{ .immediate = .imm } },
3916 },
3917 .{
3918 .pattern = "FMOV <Sd>, #<imm>",
3919 .symbols = .{
3920 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3921 .imm = .{ .fimm = .{} },
3922 },
3923 .encode = .{ .fmov, .Sd, .{ .immediate = .imm } },
3924 },
3925 .{
3926 .pattern = "FMOV <Dd>, #<imm>",
3927 .symbols = .{
3928 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3929 .imm = .{ .fimm = .{} },
3930 },
3931 .encode = .{ .fmov, .Dd, .{ .immediate = .imm } },
3932 },
3933 // C7.2.157 FRINTI (vector)
3934 .{
3935 .requires = .{.fullfp16},
3936 .pattern = "FRINTI <Vd>.<T>, <Vn>.<T>",
3937 .symbols = .{
3938 .Vd = .{ .reg_alias = .vector },
3939 .T = .{ .arrangement = .{ .elem_size = .half } },
3940 .Vn = .{ .reg_alias = .vector },
3941 },
3942 .encode = .{
3943 .frinti,
3944 .{ .alias = .Vd, .format = .{ .vector = .T } },
3945 .{ .alias = .Vn, .format = .{ .vector = .T } },
3946 },
3947 },
3948 .{
3949 .pattern = "FRINTI <Vd>.<T>, <Vn>.<T>",
3950 .symbols = .{
3951 .Vd = .{ .reg_alias = .vector },
3952 .T = .{ .arrangement = .{ .elem_size = .single } },
3953 .Vn = .{ .reg_alias = .vector },
3954 },
3955 .encode = .{
3956 .frinti,
3957 .{ .alias = .Vd, .format = .{ .vector = .T } },
3958 .{ .alias = .Vn, .format = .{ .vector = .T } },
3959 },
3960 },
3961 .{
3962 .pattern = "FRINTI <Vd>.2D, <Vn>.2D",
3963 .symbols = .{
3964 .Vd = .{ .reg_alias = .vector },
3965 .Vn = .{ .reg_alias = .vector },
3966 },
3967 .encode = .{
3968 .frinti,
3969 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3970 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3971 },
3972 },
3973 // C7.2.168 FRINTI (scalar)
3974 .{
3975 .requires = .{.fullfp16},
3976 .pattern = "FRINTI <Hd>, <Hn>",
3977 .symbols = .{
3978 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3979 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3980 },
3981 .encode = .{ .frinti, .Hd, .Hn },
3982 },
3983 .{
3984 .pattern = "FRINTI <Sd>, <Sn>",
3985 .symbols = .{
3986 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3987 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3988 },
3989 .encode = .{ .frinti, .Sd, .Sn },
3990 },
3991 .{
3992 .pattern = "FRINTI <Dd>, <Dn>",
3993 .symbols = .{
3994 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3995 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3996 },
3997 .encode = .{ .frinti, .Dd, .Dn },
3998 },
3999 // C7.2.159 FRINTM (vector)
4000 .{
4001 .requires = .{.fullfp16},
4002 .pattern = "FRINTM <Vd>.<T>, <Vn>.<T>",
4003 .symbols = .{
4004 .Vd = .{ .reg_alias = .vector },
4005 .T = .{ .arrangement = .{ .elem_size = .half } },
4006 .Vn = .{ .reg_alias = .vector },
4007 },
4008 .encode = .{
4009 .frintm,
4010 .{ .alias = .Vd, .format = .{ .vector = .T } },
4011 .{ .alias = .Vn, .format = .{ .vector = .T } },
4012 },
4013 },
4014 .{
4015 .pattern = "FRINTM <Vd>.<T>, <Vn>.<T>",
4016 .symbols = .{
4017 .Vd = .{ .reg_alias = .vector },
4018 .T = .{ .arrangement = .{ .elem_size = .single } },
4019 .Vn = .{ .reg_alias = .vector },
4020 },
4021 .encode = .{
4022 .frintm,
4023 .{ .alias = .Vd, .format = .{ .vector = .T } },
4024 .{ .alias = .Vn, .format = .{ .vector = .T } },
4025 },
4026 },
4027 .{
4028 .pattern = "FRINTM <Vd>.2D, <Vn>.2D",
4029 .symbols = .{
4030 .Vd = .{ .reg_alias = .vector },
4031 .Vn = .{ .reg_alias = .vector },
4032 },
4033 .encode = .{
4034 .frintm,
4035 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4036 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4037 },
4038 },
4039 // C7.2.160 FRINTM (scalar)
4040 .{
4041 .requires = .{.fullfp16},
4042 .pattern = "FRINTM <Hd>, <Hn>",
4043 .symbols = .{
4044 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4045 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4046 },
4047 .encode = .{ .frintm, .Hd, .Hn },
4048 },
4049 .{
4050 .pattern = "FRINTM <Sd>, <Sn>",
4051 .symbols = .{
4052 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4053 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4054 },
4055 .encode = .{ .frintm, .Sd, .Sn },
4056 },
4057 .{
4058 .pattern = "FRINTM <Dd>, <Dn>",
4059 .symbols = .{
4060 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4061 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4062 },
4063 .encode = .{ .frintm, .Dd, .Dn },
4064 },
4065 // C7.2.161 FRINTN (vector)
4066 .{
4067 .requires = .{.fullfp16},
4068 .pattern = "FRINTN <Vd>.<T>, <Vn>.<T>",
4069 .symbols = .{
4070 .Vd = .{ .reg_alias = .vector },
4071 .T = .{ .arrangement = .{ .elem_size = .half } },
4072 .Vn = .{ .reg_alias = .vector },
4073 },
4074 .encode = .{
4075 .frintn,
4076 .{ .alias = .Vd, .format = .{ .vector = .T } },
4077 .{ .alias = .Vn, .format = .{ .vector = .T } },
4078 },
4079 },
4080 .{
4081 .pattern = "FRINTN <Vd>.<T>, <Vn>.<T>",
4082 .symbols = .{
4083 .Vd = .{ .reg_alias = .vector },
4084 .T = .{ .arrangement = .{ .elem_size = .single } },
4085 .Vn = .{ .reg_alias = .vector },
4086 },
4087 .encode = .{
4088 .frintn,
4089 .{ .alias = .Vd, .format = .{ .vector = .T } },
4090 .{ .alias = .Vn, .format = .{ .vector = .T } },
4091 },
4092 },
4093 .{
4094 .pattern = "FRINTN <Vd>.2D, <Vn>.2D",
4095 .symbols = .{
4096 .Vd = .{ .reg_alias = .vector },
4097 .Vn = .{ .reg_alias = .vector },
4098 },
4099 .encode = .{
4100 .frintn,
4101 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4102 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4103 },
4104 },
4105 // C7.2.162 FRINTN (scalar)
4106 .{
4107 .requires = .{.fullfp16},
4108 .pattern = "FRINTN <Hd>, <Hn>",
4109 .symbols = .{
4110 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4111 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4112 },
4113 .encode = .{ .frintn, .Hd, .Hn },
4114 },
4115 .{
4116 .pattern = "FRINTN <Sd>, <Sn>",
4117 .symbols = .{
4118 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4119 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4120 },
4121 .encode = .{ .frintn, .Sd, .Sn },
4122 },
4123 .{
4124 .pattern = "FRINTN <Dd>, <Dn>",
4125 .symbols = .{
4126 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4127 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4128 },
4129 .encode = .{ .frintn, .Dd, .Dn },
4130 },
4131 // C7.2.163 FRINTP (vector)
4132 .{
4133 .requires = .{.fullfp16},
4134 .pattern = "FRINTP <Vd>.<T>, <Vn>.<T>",
4135 .symbols = .{
4136 .Vd = .{ .reg_alias = .vector },
4137 .T = .{ .arrangement = .{ .elem_size = .half } },
4138 .Vn = .{ .reg_alias = .vector },
4139 },
4140 .encode = .{
4141 .frintp,
4142 .{ .alias = .Vd, .format = .{ .vector = .T } },
4143 .{ .alias = .Vn, .format = .{ .vector = .T } },
4144 },
4145 },
4146 .{
4147 .pattern = "FRINTP <Vd>.<T>, <Vn>.<T>",
4148 .symbols = .{
4149 .Vd = .{ .reg_alias = .vector },
4150 .T = .{ .arrangement = .{ .elem_size = .single } },
4151 .Vn = .{ .reg_alias = .vector },
4152 },
4153 .encode = .{
4154 .frintp,
4155 .{ .alias = .Vd, .format = .{ .vector = .T } },
4156 .{ .alias = .Vn, .format = .{ .vector = .T } },
4157 },
4158 },
4159 .{
4160 .pattern = "FRINTP <Vd>.2D, <Vn>.2D",
4161 .symbols = .{
4162 .Vd = .{ .reg_alias = .vector },
4163 .Vn = .{ .reg_alias = .vector },
4164 },
4165 .encode = .{
4166 .frintp,
4167 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4168 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4169 },
4170 },
4171 // C7.2.164 FRINTP (scalar)
4172 .{
4173 .requires = .{.fullfp16},
4174 .pattern = "FRINTP <Hd>, <Hn>",
4175 .symbols = .{
4176 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4177 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4178 },
4179 .encode = .{ .frintp, .Hd, .Hn },
4180 },
4181 .{
4182 .pattern = "FRINTP <Sd>, <Sn>",
4183 .symbols = .{
4184 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4185 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4186 },
4187 .encode = .{ .frintp, .Sd, .Sn },
4188 },
4189 .{
4190 .pattern = "FRINTP <Dd>, <Dn>",
4191 .symbols = .{
4192 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4193 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4194 },
4195 .encode = .{ .frintp, .Dd, .Dn },
4196 },
4197 // C7.2.167 FRINTZ (vector)
4198 .{
4199 .requires = .{.fullfp16},
4200 .pattern = "FRINTZ <Vd>.<T>, <Vn>.<T>",
4201 .symbols = .{
4202 .Vd = .{ .reg_alias = .vector },
4203 .T = .{ .arrangement = .{ .elem_size = .half } },
4204 .Vn = .{ .reg_alias = .vector },
4205 },
4206 .encode = .{
4207 .frintz,
4208 .{ .alias = .Vd, .format = .{ .vector = .T } },
4209 .{ .alias = .Vn, .format = .{ .vector = .T } },
4210 },
4211 },
4212 .{
4213 .pattern = "FRINTZ <Vd>.<T>, <Vn>.<T>",
4214 .symbols = .{
4215 .Vd = .{ .reg_alias = .vector },
4216 .T = .{ .arrangement = .{ .elem_size = .single } },
4217 .Vn = .{ .reg_alias = .vector },
4218 },
4219 .encode = .{
4220 .frintz,
4221 .{ .alias = .Vd, .format = .{ .vector = .T } },
4222 .{ .alias = .Vn, .format = .{ .vector = .T } },
4223 },
4224 },
4225 .{
4226 .pattern = "FRINTZ <Vd>.2D, <Vn>.2D",
4227 .symbols = .{
4228 .Vd = .{ .reg_alias = .vector },
4229 .Vn = .{ .reg_alias = .vector },
4230 },
4231 .encode = .{
4232 .frintz,
4233 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4234 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4235 },
4236 },
4237 // C7.2.168 FRINTZ (scalar)
4238 .{
4239 .requires = .{.fullfp16},
4240 .pattern = "FRINTZ <Hd>, <Hn>",
4241 .symbols = .{
4242 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4243 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4244 },
4245 .encode = .{ .frintz, .Hd, .Hn },
4246 },
4247 .{
4248 .pattern = "FRINTZ <Sd>, <Sn>",
4249 .symbols = .{
4250 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4251 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4252 },
4253 .encode = .{ .frintz, .Sd, .Sn },
4254 },
4255 .{
4256 .pattern = "FRINTZ <Dd>, <Dn>",
4257 .symbols = .{
4258 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4259 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4260 },
4261 .encode = .{ .frintz, .Dd, .Dn },
4262 },
4263 // C7.2.175 INS (element)
4264 .{
4265 .pattern = "INS <Vd>.B[<index1>], <Vn>.B[<index2>]",
4266 .symbols = .{
4267 .Vd = .{ .reg_alias = .vector },
4268 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4269 .Vn = .{ .reg_alias = .vector },
4270 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4271 },
4272 .encode = .{
4273 .ins,
4274 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index1 } } },
4275 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index2 } } },
4276 },
4277 },
4278 .{
4279 .pattern = "INS <Vd>.H[<index1>], <Vn>.H[<index2>]",
4280 .symbols = .{
4281 .Vd = .{ .reg_alias = .vector },
4282 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4283 .Vn = .{ .reg_alias = .vector },
4284 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4285 },
4286 .encode = .{
4287 .ins,
4288 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index1 } } },
4289 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index2 } } },
4290 },
4291 },
4292 .{
4293 .pattern = "INS <Vd>.S[<index1>], <Vn>.S[<index2>]",
4294 .symbols = .{
4295 .Vd = .{ .reg_alias = .vector },
4296 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4297 .Vn = .{ .reg_alias = .vector },
4298 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4299 },
4300 .encode = .{
4301 .ins,
4302 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index1 } } },
4303 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index2 } } },
4304 },
4305 },
4306 .{
4307 .pattern = "INS <Vd>.D[<index1>], <Vn>.D[<index2>]",
4308 .symbols = .{
4309 .Vd = .{ .reg_alias = .vector },
4310 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4311 .Vn = .{ .reg_alias = .vector },
4312 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4313 },
4314 .encode = .{
4315 .ins,
4316 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index1 } } },
4317 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index2 } } },
4318 },
4319 },
4320 // C7.2.176 INS (general)
4321 .{
4322 .pattern = "INS <Vd>.B[<index>], <Wn>",
4323 .symbols = .{
4324 .Vd = .{ .reg_alias = .vector },
4325 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4326 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4327 },
4328 .encode = .{
4329 .ins,
4330 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4331 .Wn,
4332 },
4333 },
4334 .{
4335 .pattern = "INS <Vd>.H[<index>], <Wn>",
4336 .symbols = .{
4337 .Vd = .{ .reg_alias = .vector },
4338 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4339 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4340 },
4341 .encode = .{
4342 .ins,
4343 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index } } },
4344 .Wn,
4345 },
4346 },
4347 .{
4348 .pattern = "INS <Vd>.S[<index>], <Wn>",
4349 .symbols = .{
4350 .Vd = .{ .reg_alias = .vector },
4351 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4352 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4353 },
4354 .encode = .{
4355 .ins,
4356 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index } } },
4357 .Wn,
4358 },
4359 },
4360 .{
4361 .pattern = "INS <Vd>.D[<index>], <Xn>",
4362 .symbols = .{
4363 .Vd = .{ .reg_alias = .vector },
4364 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4365 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4366 },
4367 .encode = .{
4368 .ins,
4369 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
4370 .Xn,
4371 },
4372 },
4373 // C7.2.199 MOV (scalar)
4374 .{
4375 .pattern = "MOV <Vd>, <Vn>.B[<index>]",
4376 .symbols = .{
4377 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4378 .Vn = .{ .reg_alias = .vector },
4379 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4380 },
4381 .encode = .{
4382 .dup,
4383 .Vd,
4384 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4385 },
4386 },
4387 .{
4388 .pattern = "MOV <Vd>, <Vn>.H[<index>]",
4389 .symbols = .{
4390 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4391 .Vn = .{ .reg_alias = .vector },
4392 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4393 },
4394 .encode = .{
4395 .dup,
4396 .Vd,
4397 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4398 },
4399 },
4400 .{
4401 .pattern = "MOV <Vd>, <Vn>.S[<index>]",
4402 .symbols = .{
4403 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4404 .Vn = .{ .reg_alias = .vector },
4405 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4406 },
4407 .encode = .{
4408 .dup,
4409 .Vd,
4410 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4411 },
4412 },
4413 .{
4414 .pattern = "MOV <Vd>, <Vn>.D[<index>]",
4415 .symbols = .{
4416 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4417 .Vn = .{ .reg_alias = .vector },
4418 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4419 },
4420 .encode = .{
4421 .dup,
4422 .Vd,
4423 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
4424 },
4425 },
4426 // C7.2.200 MOV (element)
4427 .{
4428 .pattern = "MOV <Vd>.B[<index1>], <Vn>.B[<index2>]",
4429 .symbols = .{
4430 .Vd = .{ .reg_alias = .vector },
4431 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4432 .Vn = .{ .reg_alias = .vector },
4433 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4434 },
4435 .encode = .{
4436 .ins,
4437 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index1 } } },
4438 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index2 } } },
4439 },
4440 },
4441 .{
4442 .pattern = "MOV <Vd>.H[<index1>], <Vn>.H[<index2>]",
4443 .symbols = .{
4444 .Vd = .{ .reg_alias = .vector },
4445 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4446 .Vn = .{ .reg_alias = .vector },
4447 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4448 },
4449 .encode = .{
4450 .ins,
4451 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index1 } } },
4452 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index2 } } },
4453 },
4454 },
4455 .{
4456 .pattern = "MOV <Vd>.S[<index1>], <Vn>.S[<index2>]",
4457 .symbols = .{
4458 .Vd = .{ .reg_alias = .vector },
4459 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4460 .Vn = .{ .reg_alias = .vector },
4461 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4462 },
4463 .encode = .{
4464 .ins,
4465 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index1 } } },
4466 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index2 } } },
4467 },
4468 },
4469 .{
4470 .pattern = "MOV <Vd>.D[<index1>], <Vn>.D[<index2>]",
4471 .symbols = .{
4472 .Vd = .{ .reg_alias = .vector },
4473 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4474 .Vn = .{ .reg_alias = .vector },
4475 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4476 },
4477 .encode = .{
4478 .ins,
4479 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index1 } } },
4480 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index2 } } },
4481 },
4482 },
4483 // C7.2.201 MOV (from general)
4484 .{
4485 .pattern = "MOV <Vd>.B[<index>], <Wn>",
4486 .symbols = .{
4487 .Vd = .{ .reg_alias = .vector },
4488 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4489 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4490 },
4491 .encode = .{
4492 .ins,
4493 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4494 .Wn,
4495 },
4496 },
4497 .{
4498 .pattern = "MOV <Vd>.H[<index>], <Wn>",
4499 .symbols = .{
4500 .Vd = .{ .reg_alias = .vector },
4501 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4502 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4503 },
4504 .encode = .{
4505 .ins,
4506 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index } } },
4507 .Wn,
4508 },
4509 },
4510 .{
4511 .pattern = "MOV <Vd>.S[<index>], <Wn>",
4512 .symbols = .{
4513 .Vd = .{ .reg_alias = .vector },
4514 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4515 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4516 },
4517 .encode = .{
4518 .ins,
4519 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index } } },
4520 .Wn,
4521 },
4522 },
4523 .{
4524 .pattern = "MOV <Vd>.D[<index>], <Xn>",
4525 .symbols = .{
4526 .Vd = .{ .reg_alias = .vector },
4527 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4528 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4529 },
4530 .encode = .{
4531 .ins,
4532 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
4533 .Xn,
4534 },
4535 },
4536 // C7.2.202 MOV (vector)
4537 .{
4538 .pattern = "MOV <Vd>.<T>, <Vn>.<T>",
4539 .symbols = .{
4540 .Vd = .{ .reg_alias = .vector },
4541 .T = .{ .arrangement = .{ .elem_size = .byte } },
4542 .Vn = .{ .reg_alias = .vector },
4543 },
4544 .encode = .{
4545 .orr,
4546 .{ .alias = .Vd, .format = .{ .vector = .T } },
4547 .{ .alias = .Vn, .format = .{ .vector = .T } },
4548 .{ .register = .{ .alias = .Vn, .format = .{ .vector = .T } } },
4549 },
4550 },
4551 // C7.2.203 MOV (to general)
4552 .{
4553 .pattern = "MOV <Wd>, <Vn>.S[<index>]",
4554 .symbols = .{
4555 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4556 .Vn = .{ .reg_alias = .vector },
4557 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4558 },
4559 .encode = .{
4560 .umov,
4561 .Wd,
4562 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4563 },
4564 },
4565 .{
4566 .pattern = "MOV <Xd>, <Vn>.D[<index>]",
4567 .symbols = .{
4568 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4569 .Vn = .{ .reg_alias = .vector },
4570 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4571 },
4572 .encode = .{
4573 .umov,
4574 .Xd,
4575 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
4576 },
4577 },
4578 // C7.2.209 NEG (vector)
4579 .{
4580 .pattern = "NEG <Vd>, <Vn>",
4581 .symbols = .{
4582 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4583 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4584 },
4585 .encode = .{ .neg, .Vd, .Vn },
4586 },
4587 .{
4588 .pattern = "NEG <Vd>.<T>, <Vn>.<T>",
4589 .symbols = .{
4590 .Vd = .{ .reg_alias = .vector },
4591 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4592 .Vn = .{ .reg_alias = .vector },
4593 },
4594 .encode = .{
4595 .neg,
4596 .{ .alias = .Vd, .format = .{ .vector = .T } },
4597 .{ .alias = .Vn, .format = .{ .vector = .T } },
4598 },
4599 },
4600 // C7.2.210 NOT
4601 .{
4602 .pattern = "NOT <Vd>.<T>, <Vn>.<T>",
4603 .symbols = .{
4604 .Vd = .{ .reg_alias = .vector },
4605 .T = .{ .arrangement = .{ .elem_size = .byte } },
4606 .Vn = .{ .reg_alias = .vector },
4607 },
4608 .encode = .{
4609 .not,
4610 .{ .alias = .Vd, .format = .{ .vector = .T } },
4611 .{ .alias = .Vn, .format = .{ .vector = .T } },
4612 },
4613 },
4614 // C7.2.234 SCVTF (vector, integer)
4615 .{
4616 .requires = .{.fullfp16},
4617 .pattern = "SCVTF <Hd>, <Hn>",
4618 .symbols = .{
4619 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4620 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4621 },
4622 .encode = .{ .scvtf, .Hd, .Hn },
4623 },
4624 .{
4625 .pattern = "SCVTF <Sd>, <Sn>",
4626 .symbols = .{
4627 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4628 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4629 },
4630 .encode = .{ .scvtf, .Sd, .Sn },
4631 },
4632 .{
4633 .pattern = "SCVTF <Dd>, <Dn>",
4634 .symbols = .{
4635 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4636 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4637 },
4638 .encode = .{ .scvtf, .Dd, .Dn },
4639 },
4640 .{
4641 .requires = .{.fullfp16},
4642 .pattern = "SCVTF <Vd>.<T>, <Vn>.<T>",
4643 .symbols = .{
4644 .Vd = .{ .reg_alias = .vector },
4645 .T = .{ .arrangement = .{ .elem_size = .half } },
4646 .Vn = .{ .reg_alias = .vector },
4647 },
4648 .encode = .{
4649 .scvtf,
4650 .{ .alias = .Vd, .format = .{ .vector = .T } },
4651 .{ .alias = .Vn, .format = .{ .vector = .T } },
4652 },
4653 },
4654 .{
4655 .pattern = "SCVTF <Vd>.<T>, <Vn>.<T>",
4656 .symbols = .{
4657 .Vd = .{ .reg_alias = .vector },
4658 .T = .{ .arrangement = .{ .elem_size = .single } },
4659 .Vn = .{ .reg_alias = .vector },
4660 },
4661 .encode = .{
4662 .scvtf,
4663 .{ .alias = .Vd, .format = .{ .vector = .T } },
4664 .{ .alias = .Vn, .format = .{ .vector = .T } },
4665 },
4666 },
4667 .{
4668 .pattern = "SCVTF <Vd>.2D, <Vn>.2D",
4669 .symbols = .{
4670 .Vd = .{ .reg_alias = .vector },
4671 .Vn = .{ .reg_alias = .vector },
4672 },
4673 .encode = .{
4674 .scvtf,
4675 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4676 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4677 },
4678 },
4679 // C7.2.236 SCVTF (scalar, integer)
4680 .{
4681 .requires = .{.fullfp16},
4682 .pattern = "SCVTF <Hd>, <Wn>",
4683 .symbols = .{
4684 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4685 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4686 },
4687 .encode = .{ .scvtf, .Hd, .Wn },
4688 },
4689 .{
4690 .pattern = "SCVTF <Sd>, <Wn>",
4691 .symbols = .{
4692 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4693 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4694 },
4695 .encode = .{ .scvtf, .Sd, .Wn },
4696 },
4697 .{
4698 .pattern = "SCVTF <Dd>, <Wn>",
4699 .symbols = .{
4700 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4701 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4702 },
4703 .encode = .{ .scvtf, .Dd, .Wn },
4704 },
4705 .{
4706 .requires = .{.fullfp16},
4707 .pattern = "SCVTF <Hd>, <Xn>",
4708 .symbols = .{
4709 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4710 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4711 },
4712 .encode = .{ .scvtf, .Hd, .Xn },
4713 },
4714 .{
4715 .pattern = "SCVTF <Sd>, <Xn>",
4716 .symbols = .{
4717 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4718 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4719 },
4720 .encode = .{ .scvtf, .Sd, .Xn },
4721 },
4722 .{
4723 .pattern = "SCVTF <Dd>, <Xn>",
4724 .symbols = .{
4725 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4726 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4727 },
4728 .encode = .{ .scvtf, .Dd, .Xn },
4729 },
4730 // C7.2.279 SMOV
4731 .{
4732 .pattern = "SMOV <Wd>, <Vn>.B[<index>]",
4733 .symbols = .{
4734 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4735 .Vn = .{ .reg_alias = .vector },
4736 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4737 },
4738 .encode = .{
4739 .smov,
4740 .Wd,
4741 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4742 },
4743 },
4744 .{
4745 .pattern = "SMOV <Xd>, <Vn>.B[<index>]",
4746 .symbols = .{
4747 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4748 .Vn = .{ .reg_alias = .vector },
4749 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4750 },
4751 .encode = .{
4752 .smov,
4753 .Xd,
4754 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4755 },
4756 },
4757 .{
4758 .pattern = "SMOV <Wd>, <Vn>.H[<index>]",
4759 .symbols = .{
4760 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4761 .Vn = .{ .reg_alias = .vector },
4762 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4763 },
4764 .encode = .{
4765 .smov,
4766 .Wd,
4767 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4768 },
4769 },
4770 .{
4771 .pattern = "SMOV <Xd>, <Vn>.H[<index>]",
4772 .symbols = .{
4773 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4774 .Vn = .{ .reg_alias = .vector },
4775 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4776 },
4777 .encode = .{
4778 .smov,
4779 .Xd,
4780 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4781 },
4782 },
4783 .{
4784 .pattern = "SMOV <Xd>, <Vn>.S[<index>]",
4785 .symbols = .{
4786 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4787 .Vn = .{ .reg_alias = .vector },
4788 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4789 },
4790 .encode = .{
4791 .smov,
4792 .Xd,
4793 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4794 },
4795 },
4796 // C7.2.282 SQABS
4797 .{
4798 .pattern = "SQABS <Vd>, <Vn>",
4799 .symbols = .{
4800 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4801 .Vn = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4802 },
4803 .encode = .{ .sqabs, .Vd, .Vn },
4804 },
4805 .{
4806 .pattern = "SQABS <Vd>, <Vn>",
4807 .symbols = .{
4808 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4809 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4810 },
4811 .encode = .{ .sqabs, .Vd, .Vn },
4812 },
4813 .{
4814 .pattern = "SQABS <Vd>, <Vn>",
4815 .symbols = .{
4816 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4817 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4818 },
4819 .encode = .{ .sqabs, .Vd, .Vn },
4820 },
4821 .{
4822 .pattern = "SQABS <Vd>, <Vn>",
4823 .symbols = .{
4824 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4825 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4826 },
4827 .encode = .{ .sqabs, .Vd, .Vn },
4828 },
4829 .{
4830 .pattern = "SQABS <Vd>.<T>, <Vn>.<T>",
4831 .symbols = .{
4832 .Vd = .{ .reg_alias = .vector },
4833 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4834 .Vn = .{ .reg_alias = .vector },
4835 },
4836 .encode = .{
4837 .sqabs,
4838 .{ .alias = .Vd, .format = .{ .vector = .T } },
4839 .{ .alias = .Vn, .format = .{ .vector = .T } },
4840 },
4841 },
4842 // C7.2.308 SQXTN, SQXTN2
4843 .{
4844 .pattern = "SQXTN <Vd>, <Vn>",
4845 .symbols = .{
4846 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4847 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4848 },
4849 .encode = .{ .sqxtn, .Vd, .Vn },
4850 },
4851 .{
4852 .pattern = "SQXTN <Vd>, <Vn>",
4853 .symbols = .{
4854 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4855 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4856 },
4857 .encode = .{ .sqxtn, .Vd, .Vn },
4858 },
4859 .{
4860 .pattern = "SQXTN <Vd>, <Vn>",
4861 .symbols = .{
4862 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4863 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4864 },
4865 .encode = .{ .sqxtn, .Vd, .Vn },
4866 },
4867 .{
4868 .pattern = "SQXTN <Vd>.8B, <Vn>.8H",
4869 .symbols = .{
4870 .Vd = .{ .reg_alias = .vector },
4871 .Vn = .{ .reg_alias = .vector },
4872 },
4873 .encode = .{
4874 .sqxtn,
4875 .{ .alias = .Vd, .format = .{ .vector = .@"8b" } },
4876 .{ .alias = .Vn, .format = .{ .vector = .@"8h" } },
4877 },
4878 },
4879 .{
4880 .pattern = "SQXTN2 <Vd>.16B, <Vn>.8H",
4881 .symbols = .{
4882 .Vd = .{ .reg_alias = .vector },
4883 .Vn = .{ .reg_alias = .vector },
4884 },
4885 .encode = .{
4886 .sqxtn2,
4887 .{ .alias = .Vd, .format = .{ .vector = .@"16b" } },
4888 .{ .alias = .Vn, .format = .{ .vector = .@"8h" } },
4889 },
4890 },
4891 .{
4892 .pattern = "SQXTN <Vd>.4H, <Vn>.4S",
4893 .symbols = .{
4894 .Vd = .{ .reg_alias = .vector },
4895 .Vn = .{ .reg_alias = .vector },
4896 },
4897 .encode = .{
4898 .sqxtn,
4899 .{ .alias = .Vd, .format = .{ .vector = .@"4h" } },
4900 .{ .alias = .Vn, .format = .{ .vector = .@"4s" } },
4901 },
4902 },
4903 .{
4904 .pattern = "SQXTN2 <Vd>.8H, <Vn>.4S",
4905 .symbols = .{
4906 .Vd = .{ .reg_alias = .vector },
4907 .Vn = .{ .reg_alias = .vector },
4908 },
4909 .encode = .{
4910 .sqxtn2,
4911 .{ .alias = .Vd, .format = .{ .vector = .@"8h" } },
4912 .{ .alias = .Vn, .format = .{ .vector = .@"4s" } },
4913 },
4914 },
4915 .{
4916 .pattern = "SQXTN <Vd>.2S, <Vn>.2D",
4917 .symbols = .{
4918 .Vd = .{ .reg_alias = .vector },
4919 .Vn = .{ .reg_alias = .vector },
4920 },
4921 .encode = .{
4922 .sqxtn,
4923 .{ .alias = .Vd, .format = .{ .vector = .@"2s" } },
4924 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4925 },
4926 },
4927 .{
4928 .pattern = "SQXTN2 <Vd>.4S, <Vn>.2D",
4929 .symbols = .{
4930 .Vd = .{ .reg_alias = .vector },
4931 .Vn = .{ .reg_alias = .vector },
4932 },
4933 .encode = .{
4934 .sqxtn2,
4935 .{ .alias = .Vd, .format = .{ .vector = .@"4s" } },
4936 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4937 },
4938 },
4939 // C7.2.337 SUQADD
4940 .{
4941 .pattern = "SUQADD <Vd>, <Vn>",
4942 .symbols = .{
4943 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4944 .Vn = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4945 },
4946 .encode = .{ .suqadd, .Vd, .Vn },
4947 },
4948 .{
4949 .pattern = "SUQADD <Vd>, <Vn>",
4950 .symbols = .{
4951 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4952 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4953 },
4954 .encode = .{ .suqadd, .Vd, .Vn },
4955 },
4956 .{
4957 .pattern = "SUQADD <Vd>, <Vn>",
4958 .symbols = .{
4959 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4960 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4961 },
4962 .encode = .{ .suqadd, .Vd, .Vn },
4963 },
4964 .{
4965 .pattern = "SUQADD <Vd>, <Vn>",
4966 .symbols = .{
4967 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4968 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4969 },
4970 .encode = .{ .suqadd, .Vd, .Vn },
4971 },
4972 .{
4973 .pattern = "SUQADD <Vd>.<T>, <Vn>.<T>",
4974 .symbols = .{
4975 .Vd = .{ .reg_alias = .vector },
4976 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4977 .Vn = .{ .reg_alias = .vector },
4978 },
4979 .encode = .{
4980 .suqadd,
4981 .{ .alias = .Vd, .format = .{ .vector = .T } },
4982 .{ .alias = .Vn, .format = .{ .vector = .T } },
4983 },
4984 },
4985 // C7.2.353 UCVTF (vector, integer)
4986 .{
4987 .requires = .{.fullfp16},
4988 .pattern = "UCVTF <Hd>, <Hn>",
4989 .symbols = .{
4990 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4991 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4992 },
4993 .encode = .{ .ucvtf, .Hd, .Hn },
4994 },
4995 .{
4996 .pattern = "UCVTF <Sd>, <Sn>",
4997 .symbols = .{
4998 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4999 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
5000 },
5001 .encode = .{ .ucvtf, .Sd, .Sn },
5002 },
5003 .{
5004 .pattern = "UCVTF <Dd>, <Dn>",
5005 .symbols = .{
5006 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5007 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
5008 },
5009 .encode = .{ .ucvtf, .Dd, .Dn },
5010 },
5011 .{
5012 .requires = .{.fullfp16},
5013 .pattern = "UCVTF <Vd>.<T>, <Vn>.<T>",
5014 .symbols = .{
5015 .Vd = .{ .reg_alias = .vector },
5016 .T = .{ .arrangement = .{ .elem_size = .half } },
5017 .Vn = .{ .reg_alias = .vector },
5018 },
5019 .encode = .{
5020 .ucvtf,
5021 .{ .alias = .Vd, .format = .{ .vector = .T } },
5022 .{ .alias = .Vn, .format = .{ .vector = .T } },
5023 },
5024 },
5025 .{
5026 .pattern = "UCVTF <Vd>.<T>, <Vn>.<T>",
5027 .symbols = .{
5028 .Vd = .{ .reg_alias = .vector },
5029 .T = .{ .arrangement = .{ .elem_size = .single } },
5030 .Vn = .{ .reg_alias = .vector },
5031 },
5032 .encode = .{
5033 .ucvtf,
5034 .{ .alias = .Vd, .format = .{ .vector = .T } },
5035 .{ .alias = .Vn, .format = .{ .vector = .T } },
5036 },
5037 },
5038 .{
5039 .pattern = "UCVTF <Vd>.2D, <Vn>.2D",
5040 .symbols = .{
5041 .Vd = .{ .reg_alias = .vector },
5042 .Vn = .{ .reg_alias = .vector },
5043 },
5044 .encode = .{
5045 .ucvtf,
5046 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
5047 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
5048 },
5049 },
5050 // C7.2.355 UCVTF (scalar, integer)
5051 .{
5052 .requires = .{.fullfp16},
5053 .pattern = "UCVTF <Hd>, <Wn>",
5054 .symbols = .{
5055 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
5056 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5057 },
5058 .encode = .{ .ucvtf, .Hd, .Wn },
5059 },
5060 .{
5061 .pattern = "UCVTF <Sd>, <Wn>",
5062 .symbols = .{
5063 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
5064 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5065 },
5066 .encode = .{ .ucvtf, .Sd, .Wn },
5067 },
5068 .{
5069 .pattern = "UCVTF <Dd>, <Wn>",
5070 .symbols = .{
5071 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5072 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5073 },
5074 .encode = .{ .ucvtf, .Dd, .Wn },
5075 },
5076 .{
5077 .requires = .{.fullfp16},
5078 .pattern = "UCVTF <Hd>, <Xn>",
5079 .symbols = .{
5080 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
5081 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5082 },
5083 .encode = .{ .ucvtf, .Hd, .Xn },
5084 },
5085 .{
5086 .pattern = "UCVTF <Sd>, <Xn>",
5087 .symbols = .{
5088 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
5089 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5090 },
5091 .encode = .{ .ucvtf, .Sd, .Xn },
5092 },
5093 .{
5094 .pattern = "UCVTF <Dd>, <Xn>",
5095 .symbols = .{
5096 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5097 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5098 },
5099 .encode = .{ .ucvtf, .Dd, .Xn },
5100 },
5101 // C7.2.371 UMOV
5102 .{
5103 .pattern = "UMOV <Wd>, <Vn>.B[<index>]",
5104 .symbols = .{
5105 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5106 .Vn = .{ .reg_alias = .vector },
5107 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
5108 },
5109 .encode = .{
5110 .umov,
5111 .Wd,
5112 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
5113 },
5114 },
5115 .{
5116 .pattern = "UMOV <Wd>, <Vn>.H[<index>]",
5117 .symbols = .{
5118 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5119 .Vn = .{ .reg_alias = .vector },
5120 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
5121 },
5122 .encode = .{
5123 .umov,
5124 .Wd,
5125 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
5126 },
5127 },
5128 .{
5129 .pattern = "UMOV <Wd>, <Vn>.S[<index>]",
5130 .symbols = .{
5131 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5132 .Vn = .{ .reg_alias = .vector },
5133 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
5134 },
5135 .encode = .{
5136 .umov,
5137 .Wd,
5138 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
5139 },
5140 },
5141 .{
5142 .pattern = "UMOV <Xd>, <Vn>.D[<index>]",
5143 .symbols = .{
5144 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5145 .Vn = .{ .reg_alias = .vector },
5146 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
5147 },
5148 .encode = .{
5149 .umov,
5150 .Xd,
5151 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
5152 },
5153 },
15435154}
src/link/MachO/Atom.zig+7-7
......@@ -829,21 +829,21 @@ fn resolveRelocInner(
829829 const rd, const rn = switch (aarch64.encoding.Instruction.read(inst_code).decode()) {
830830 else => unreachable,
831831 .data_processing_immediate => |decoded| .{
832 decoded.add_subtract_immediate.group.Rd.decodeInteger(.doubleword, .{ .sp = true }),
833 decoded.add_subtract_immediate.group.Rn.decodeInteger(.doubleword, .{ .sp = true }),
832 decoded.add_subtract_immediate.group.Rd.decode(.{ .sp = true }),
833 decoded.add_subtract_immediate.group.Rn.decode(.{ .sp = true }),
834834 },
835835 .load_store => |decoded| .{
836 decoded.register_unsigned_immediate.integer.group.Rt.decodeInteger(.doubleword, .{}),
837 decoded.register_unsigned_immediate.group.Rn.decodeInteger(.doubleword, .{ .sp = true }),
836 decoded.register_unsigned_immediate.integer.group.Rt.decode(.{}),
837 decoded.register_unsigned_immediate.group.Rn.decode(.{ .sp = true }),
838838 },
839839 };
840840
841841 try writer.writeInt(u32, @bitCast(@as(
842842 aarch64.encoding.Instruction,
843 if (sym.getSectionFlags().tlv_ptr) .ldr(rd, .{ .unsigned_offset = .{
844 .base = rn,
843 if (sym.getSectionFlags().tlv_ptr) .ldr(rd.x(), .{ .unsigned_offset = .{
844 .base = rn.x(),
845845 .offset = try divExact(self, rel, @truncate(target), 8, macho_file) * 8,
846 } }) else .add(rd, rn, .{ .immediate = @truncate(target) }),
846 } }) else .add(rd.x(), rn.x(), .{ .immediate = @truncate(target) }),
847847 )), .little);
848848 },
849849 }