authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2025-07-29 07:40:16-04:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2025-08-11 15:47:51-07:00
logd625158354a02a18e9ae7975a144f30838884d5c
tree1bbf76812c30408509dbd8f6da756986530fbee9
parent59de7e3a5725f0c4eeb64bc464db85e019af7446

aarch64: implement more assembler instructions

8 files changed, 7899 insertions(+), 1787 deletions(-)

lib/std/mem.zig+10-14
...@@ -674,7 +674,7 @@ test lessThan {...@@ -674,7 +674,7 @@ test lessThan {
674 try testing.expect(lessThan(u8, "", "a"));674 try testing.expect(lessThan(u8, "", "a"));
675}675}
676676
677const eqlBytes_allowed = switch (builtin.zig_backend) {677const use_vectors = switch (builtin.zig_backend) {
678 // These backends don't support vectors yet.678 // These backends don't support vectors yet.
679 .stage2_aarch64,679 .stage2_aarch64,
680 .stage2_powerpc,680 .stage2_powerpc,
...@@ -682,16 +682,17 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {...@@ -682,16 +682,17 @@ const eqlBytes_allowed = switch (builtin.zig_backend) {
682 => false,682 => false,
683 // The SPIR-V backend does not support the optimized path yet.683 // The SPIR-V backend does not support the optimized path yet.
684 .stage2_spirv => false,684 .stage2_spirv => false,
685 // The naive memory comparison implementation is more useful for fuzzers to685 else => true,
686 // find interesting inputs.
687 else => !builtin.fuzz,
688};686};
689687
688// The naive memory comparison implementation is more useful for fuzzers to find interesting inputs.
689const use_vectors_for_comparison = use_vectors and !builtin.fuzz;
690
690/// Returns true if and only if the slices have the same length and all elements691/// Returns true if and only if the slices have the same length and all elements
691/// compare true using equality operator.692/// compare true using equality operator.
692pub fn eql(comptime T: type, a: []const T, b: []const T) bool {693pub fn eql(comptime T: type, a: []const T, b: []const T) bool {
693 if (!@inComptime() and @sizeOf(T) != 0 and std.meta.hasUniqueRepresentation(T) and694 if (!@inComptime() and @sizeOf(T) != 0 and std.meta.hasUniqueRepresentation(T) and
694 eqlBytes_allowed)695 use_vectors_for_comparison)
695 {696 {
696 return eqlBytes(sliceAsBytes(a), sliceAsBytes(b));697 return eqlBytes(sliceAsBytes(a), sliceAsBytes(b));
697 }698 }
...@@ -726,7 +727,7 @@ test eql {...@@ -726,7 +727,7 @@ test eql {
726727
727/// std.mem.eql heavily optimized for slices of bytes.728/// std.mem.eql heavily optimized for slices of bytes.
728fn eqlBytes(a: []const u8, b: []const u8) bool {729fn eqlBytes(a: []const u8, b: []const u8) bool {
729 comptime assert(eqlBytes_allowed);730 comptime assert(use_vectors_for_comparison);
730731
731 if (a.len != b.len) return false;732 if (a.len != b.len) return false;
732 if (a.len == 0 or a.ptr == b.ptr) return true;733 if (a.len == 0 or a.ptr == b.ptr) return true;
...@@ -1088,15 +1089,10 @@ test len {...@@ -1088,15 +1089,10 @@ test len {
1088 try testing.expect(len(c_ptr) == 2);1089 try testing.expect(len(c_ptr) == 2);
1089}1090}
10901091
1091const backend_supports_vectors = switch (builtin.zig_backend) {
1092 .stage2_llvm, .stage2_c => true,
1093 else => false,
1094};
1095
1096pub fn indexOfSentinel(comptime T: type, comptime sentinel: T, p: [*:sentinel]const T) usize {1092pub fn indexOfSentinel(comptime T: type, comptime sentinel: T, p: [*:sentinel]const T) usize {
1097 var i: usize = 0;1093 var i: usize = 0;
10981094
1099 if (backend_supports_vectors and1095 if (use_vectors_for_comparison and
1100 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/177171096 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/17717
1101 !@inComptime() and1097 !@inComptime() and
1102 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))1098 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))
...@@ -1263,7 +1259,7 @@ pub fn indexOfScalarPos(comptime T: type, slice: []const T, start_index: usize,...@@ -1263,7 +1259,7 @@ pub fn indexOfScalarPos(comptime T: type, slice: []const T, start_index: usize,
1263 if (start_index >= slice.len) return null;1259 if (start_index >= slice.len) return null;
12641260
1265 var i: usize = start_index;1261 var i: usize = start_index;
1266 if (backend_supports_vectors and1262 if (use_vectors_for_comparison and
1267 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/177171263 !std.debug.inValgrind() and // https://github.com/ziglang/zig/issues/17717
1268 !@inComptime() and1264 !@inComptime() and
1269 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))1265 (@typeInfo(T) == .int or @typeInfo(T) == .float) and std.math.isPowerOfTwo(@bitSizeOf(T)))
...@@ -3609,7 +3605,7 @@ inline fn reverseVector(comptime N: usize, comptime T: type, a: []T) [N]T {...@@ -3609,7 +3605,7 @@ inline fn reverseVector(comptime N: usize, comptime T: type, a: []T) [N]T {
3609pub fn reverse(comptime T: type, items: []T) void {3605pub fn reverse(comptime T: type, items: []T) void {
3610 var i: usize = 0;3606 var i: usize = 0;
3611 const end = items.len / 2;3607 const end = items.len / 2;
3612 if (backend_supports_vectors and3608 if (use_vectors and
3613 !@inComptime() and3609 !@inComptime() and
3614 @bitSizeOf(T) > 0 and3610 @bitSizeOf(T) > 0 and
3615 std.math.isPowerOfTwo(@bitSizeOf(T)))3611 std.math.isPowerOfTwo(@bitSizeOf(T)))
src/codegen/aarch64/Assemble.zig+1280-25
...@@ -6,7 +6,7 @@ pub const Operand = union(enum) {...@@ -6,7 +6,7 @@ pub const Operand = union(enum) {
6};6};
77
8pub fn nextInstruction(as: *Assemble) !?Instruction {8pub fn nextInstruction(as: *Assemble) !?Instruction {
9 @setEvalBranchQuota(42_000);9 @setEvalBranchQuota(140_000);
10 comptime var ct_token_buf: [token_buf_len]u8 = undefined;10 comptime var ct_token_buf: [token_buf_len]u8 = undefined;
11 var token_buf: [token_buf_len]u8 = undefined;11 var token_buf: [token_buf_len]u8 = undefined;
12 const original_source = while (true) {12 const original_source = while (true) {
...@@ -30,8 +30,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {...@@ -30,8 +30,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
30 inline for (instructions) |instruction| {30 inline for (instructions) |instruction| {
31 next_pattern: {31 next_pattern: {
32 as.source = original_source;32 as.source = original_source;
33 const Symbols = @TypeOf(instruction.symbols);
33 var symbols: Symbols: {34 var symbols: Symbols: {
34 const symbols = @typeInfo(@TypeOf(instruction.symbols)).@"struct".fields;35 const symbols = @typeInfo(Symbols).@"struct".fields;
35 var symbol_fields: [symbols.len]std.builtin.Type.StructField = undefined;36 var symbol_fields: [symbols.len]std.builtin.Type.StructField = undefined;
36 for (&symbol_fields, symbols) |*symbol_field, symbol| {37 for (&symbol_fields, symbols) |*symbol_field, symbol| {
37 const Storage = zonCast(SymbolSpec, @field(instruction.symbols, symbol.name), .{}).Storage();38 const Storage = zonCast(SymbolSpec, @field(instruction.symbols, symbol.name), .{}).Storage();
...@@ -50,6 +51,8 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {...@@ -50,6 +51,8 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
50 .is_tuple = false,51 .is_tuple = false,
51 } });52 } });
52 } = undefined;53 } = undefined;
54 const Symbol = std.meta.FieldEnum(Symbols);
55 comptime var unused_symbols: std.enums.EnumSet(Symbol) = .initFull();
53 comptime var pattern_as: Assemble = .{ .source = instruction.pattern, .operands = undefined };56 comptime var pattern_as: Assemble = .{ .source = instruction.pattern, .operands = undefined };
54 inline while (true) {57 inline while (true) {
55 const pattern_token = comptime pattern_as.nextToken(&ct_token_buf, .{ .placeholders = true }) catch |err|58 const pattern_token = comptime pattern_as.nextToken(&ct_token_buf, .{ .placeholders = true }) catch |err|
...@@ -60,6 +63,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {...@@ -60,6 +63,9 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
60 std.zig.fmtString(source_token),63 std.zig.fmtString(source_token),
61 });64 });
62 if (pattern_token.len == 0) {65 if (pattern_token.len == 0) {
66 comptime var unused_symbol_it = unused_symbols.iterator();
67 inline while (comptime unused_symbol_it.next()) |unused_symbol|
68 @compileError(@tagName(unused_symbol) ++ " unused while parsing '" ++ instruction.pattern ++ "'");
63 switch (source_token.len) {69 switch (source_token.len) {
64 0 => {},70 0 => {},
65 else => switch (source_token[0]) {71 else => switch (source_token[0]) {
...@@ -76,9 +82,14 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {...@@ -76,9 +82,14 @@ pub fn nextInstruction(as: *Assemble) !?Instruction {
76 } else if (pattern_token[0] == '<') {82 } else if (pattern_token[0] == '<') {
77 const symbol_name = comptime pattern_token[1 .. std.mem.indexOfScalarPos(u8, pattern_token, 1, '|') orelse83 const symbol_name = comptime pattern_token[1 .. std.mem.indexOfScalarPos(u8, pattern_token, 1, '|') orelse
78 pattern_token.len - 1];84 pattern_token.len - 1];
79 const symbol = &@field(symbols, symbol_name);85 const symbol = @field(Symbol, symbol_name);
80 symbol.* = zonCast(SymbolSpec, @field(instruction.symbols, symbol_name), .{}).parse(source_token) orelse break :next_pattern;86 const symbol_ptr = &@field(symbols, symbol_name);
81 log.debug("{s} = {any}", .{ symbol_name, symbol.* });87 const symbol_value = zonCast(SymbolSpec, @field(instruction.symbols, symbol_name), .{}).parse(source_token) orelse break :next_pattern;
88 if (comptime unused_symbols.contains(symbol)) {
89 log.debug("{s} = {any}", .{ symbol_name, symbol_value });
90 symbol_ptr.* = symbol_value;
91 comptime unused_symbols.remove(symbol);
92 } else if (symbol_ptr.* != symbol_value) break :next_pattern;
82 } else if (!toUpperEqlAssertUpper(source_token, pattern_token)) break :next_pattern;93 } else if (!toUpperEqlAssertUpper(source_token, pattern_token)) break :next_pattern;
83 }94 }
84 }95 }
...@@ -121,9 +132,9 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {...@@ -121,9 +132,9 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {
121 const Symbol = @TypeOf(symbol);132 const Symbol = @TypeOf(symbol);
122 switch (@typeInfo(Result)) {133 switch (@typeInfo(Result)) {
123 .@"enum" => switch (@typeInfo(Symbol)) {134 .@"enum" => switch (@typeInfo(Symbol)) {
124 .int => |symbol_int| {135 .int => |info| {
125 var buf: [136 var buf: [
126 std.fmt.count("{d}", .{switch (symbol_int.signedness) {137 std.fmt.count("{d}", .{switch (info.signedness) {
127 .signed => std.math.minInt(Symbol),138 .signed => std.math.minInt(Symbol),
128 .unsigned => std.math.maxInt(Symbol),139 .unsigned => std.math.maxInt(Symbol),
129 }})140 }})
...@@ -134,7 +145,15 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {...@@ -134,7 +145,15 @@ fn zonCast(comptime Result: type, zon_value: anytype, symbols: anytype) Result {
134 },145 },
135 else => return symbol,146 else => return symbol,
136 }147 }
137 } else return if (@hasDecl(Result, @tagName(zon_value))) @field(Result, @tagName(zon_value)) else zon_value,148 } else {
149 const Container = switch (@typeInfo(Result)) {
150 else => struct {},
151 .@"struct", .@"enum", .@"union", .@"opaque" => Result,
152 .optional => |info| info.child,
153 .error_union => |info| info.payload,
154 };
155 return if (@hasDecl(Container, @tagName(zon_value))) @field(Container, @tagName(zon_value)) else zon_value;
156 },
138 else => @compileError(std.fmt.comptimePrint("unsupported zon type: {} <- {any}", .{ Result, zon_value })),157 else => @compileError(std.fmt.comptimePrint("unsupported zon type: {} <- {any}", .{ Result, zon_value })),
139 }158 }
140}159}
...@@ -210,10 +229,22 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {...@@ -210,10 +229,22 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {
210 },229 },
211 }230 }
212 } else continue :c invalid_syntax,231 } else continue :c invalid_syntax,
213 '-', '0'...'9', 'A'...'Z', '_', 'a'...'z' => {232 '+', '-', '.', '0'...'9', 'A'...'Z', '_', 'a'...'z' => {
214 var index: usize = 1;233 var index: usize = 1;
215 while (switch (as.source[index]) {234 while (more: switch (as.source[index]) {
216 '0'...'9', 'A'...'Z', '_', 'a'...'z' => true,235 '0'...'9' => true,
236 'A'...'Z', '_', 'a'...'z' => switch (as.source[0]) {
237 else => true,
238 '.' => {
239 index = 1;
240 break :more false;
241 },
242 },
243 '.' => switch (as.source[0]) {
244 else => unreachable,
245 '+', '-', '.', '0'...'9' => true,
246 'A'...'Z', '_', 'a'...'z' => false,
247 },
217 else => false,248 else => false,
218 }) index += 1;249 }) index += 1;
219 defer as.source = as.source[index..];250 defer as.source = as.source[index..];
...@@ -237,22 +268,33 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {...@@ -237,22 +268,33 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {
237}268}
238269
239const SymbolSpec = union(enum) {270const SymbolSpec = union(enum) {
271 reg_alias: aarch64.encoding.Register.Format.Alias,
240 reg: struct { format: aarch64.encoding.Register.Format, allow_sp: bool = false },272 reg: struct { format: aarch64.encoding.Register.Format, allow_sp: bool = false },
273 arrangement: struct {
274 elem_size: ?Instruction.DataProcessingVector.Size = null,
275 allow_double: bool = true,
276 min_valid_len: comptime_int = 0,
277 },
241 systemreg,278 systemreg,
242 imm: struct {279 imm: struct {
243 type: std.builtin.Type.Int,280 type: std.builtin.Type.Int,
244 multiple_of: comptime_int = 1,281 multiple_of: ?comptime_int = null,
282 min_valid: ?comptime_int = null,
245 max_valid: ?comptime_int = null,283 max_valid: ?comptime_int = null,
246 },284 },
247 extend: struct { size: aarch64.encoding.Register.IntegerSize },285 fimm: struct { only_valid: ?f16 = null },
286 extend: struct { size: aarch64.encoding.Register.GeneralSize },
248 shift: struct { allow_ror: bool = true },287 shift: struct { allow_ror: bool = true },
249 barrier: struct { only_sy: bool = false },288 barrier: struct { only_sy: bool = false },
250289
251 fn Storage(comptime spec: SymbolSpec) type {290 fn Storage(comptime spec: SymbolSpec) type {
252 return switch (spec) {291 return switch (spec) {
292 .reg_alias => aarch64.encoding.Register.Alias,
253 .reg => aarch64.encoding.Register,293 .reg => aarch64.encoding.Register,
294 .arrangement => aarch64.encoding.Register.Arrangement,
254 .systemreg => aarch64.encoding.Register.System,295 .systemreg => aarch64.encoding.Register.System,
255 .imm => |imm| @Type(.{ .int = imm.type }),296 .imm => |imm| @Type(.{ .int = imm.type }),
297 .fimm => f16,
256 .extend => Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option,298 .extend => Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option,
257 .shift => Instruction.DataProcessingRegister.Shift.Op,299 .shift => Instruction.DataProcessingRegister.Shift.Op,
258 .barrier => Instruction.BranchExceptionGeneratingSystem.Barriers.Option,300 .barrier => Instruction.BranchExceptionGeneratingSystem.Barriers.Option,
...@@ -262,12 +304,27 @@ const SymbolSpec = union(enum) {...@@ -262,12 +304,27 @@ const SymbolSpec = union(enum) {
262 fn parse(comptime spec: SymbolSpec, token: []const u8) ?Storage(spec) {304 fn parse(comptime spec: SymbolSpec, token: []const u8) ?Storage(spec) {
263 const Result = Storage(spec);305 const Result = Storage(spec);
264 switch (spec) {306 switch (spec) {
307 .reg_alias => |reg_alias_spec| {
308 const reg = aarch64.encoding.Register.parse(token) orelse {
309 log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});
310 return null;
311 };
312 if (reg.format != .alias or reg.format.alias != reg_alias_spec) {
313 log.debug("invalid register size: \"{f}\"", .{std.zig.fmtString(token)});
314 return null;
315 }
316 return reg.alias;
317 },
265 .reg => |reg_spec| {318 .reg => |reg_spec| {
266 const reg = Result.parse(token) orelse {319 const reg = Result.parse(token) orelse {
267 log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});320 log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});
268 return null;321 return null;
269 };322 };
270 if (reg.format.integer != reg_spec.format.integer) {323 if (switch (reg_spec.format) {
324 .alias, .vector, .element, .scalable => comptime unreachable,
325 .general => |general_spec| reg.format != .general or reg.format.general != general_spec,
326 .scalar => |scalar_spec| reg.format != .scalar or reg.format.scalar != scalar_spec,
327 }) {
271 log.debug("invalid register size: \"{f}\"", .{std.zig.fmtString(token)});328 log.debug("invalid register size: \"{f}\"", .{std.zig.fmtString(token)});
272 return null;329 return null;
273 }330 }
...@@ -277,6 +334,35 @@ const SymbolSpec = union(enum) {...@@ -277,6 +334,35 @@ const SymbolSpec = union(enum) {
277 }334 }
278 return reg;335 return reg;
279 },336 },
337 .arrangement => |arrangement_spec| {
338 var buf: [
339 max_len: {
340 var max_len = 0;
341 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
342 break :max_len max_len;
343 } + 1
344 ]u8 = undefined;
345 const arrangement = std.meta.stringToEnum(Result, std.ascii.lowerString(
346 &buf,
347 token[0..@min(token.len, buf.len)],
348 )) orelse {
349 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
350 return null;
351 };
352 if (arrangement_spec.elem_size) |elem_size| if (arrangement.elemSize() != elem_size) {
353 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
354 return null;
355 };
356 if (!arrangement_spec.allow_double and arrangement.elemSize() == .double) {
357 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
358 return null;
359 }
360 if (arrangement.len() < arrangement_spec.min_valid_len) {
361 log.debug("invalid arrangement: \"{f}\"", .{std.zig.fmtString(token)});
362 return null;
363 }
364 return arrangement;
365 },
280 .systemreg => {366 .systemreg => {
281 const systemreg = Result.parse(token) orelse {367 const systemreg = Result.parse(token) orelse {
282 log.debug("invalid system register: \"{f}\"", .{std.zig.fmtString(token)});368 log.debug("invalid system register: \"{f}\"", .{std.zig.fmtString(token)});
...@@ -290,26 +376,57 @@ const SymbolSpec = union(enum) {...@@ -290,26 +376,57 @@ const SymbolSpec = union(enum) {
290 log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});376 log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});
291 return null;377 return null;
292 };378 };
293 if (@rem(imm, imm_spec.multiple_of) != 0) {379 if (imm_spec.multiple_of) |multiple_of| if (@rem(imm, multiple_of) != 0) {
294 log.debug("invalid immediate usage: \"{f}\"", .{std.zig.fmtString(token)});380 log.debug("invalid immediate usage: \"{f}\"", .{std.zig.fmtString(token)});
295 return null;381 return null;
296 }382 };
383 if (imm_spec.min_valid) |min_valid| if (imm < min_valid) {
384 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
385 return null;
386 };
297 if (imm_spec.max_valid) |max_valid| if (imm > max_valid) {387 if (imm_spec.max_valid) |max_valid| if (imm > max_valid) {
298 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});388 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
299 return null;389 return null;
300 };390 };
301 return imm;391 return imm;
302 },392 },
393 .fimm => |fimm_spec| {
394 const full_fimm = std.fmt.parseFloat(f128, token) catch {
395 log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});
396 return null;
397 };
398 const fimm: f16 = @floatCast(full_fimm);
399 if (fimm != full_fimm) {
400 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
401 return null;
402 }
403 if (fimm_spec.only_valid) |only_valid| {
404 if (@as(u16, @bitCast(fimm)) != @as(u16, @bitCast(only_valid))) {
405 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
406 return null;
407 }
408 } else {
409 const Repr = std.math.FloatRepr(f16);
410 const repr: Repr = @bitCast(fimm);
411 if (repr.mantissa & std.math.maxInt(Repr.Mantissa) >> 5 != 0 or switch (repr.exponent) {
412 .denormal, .infinite => true,
413 else => std.math.cast(i3, repr.exponent.unbias() - 1) == null,
414 }) {
415 log.debug("out of range immediate: \"{f}\"", .{std.zig.fmtString(token)});
416 return null;
417 }
418 }
419 return fimm;
420 },
303 .extend => |extend_spec| {421 .extend => |extend_spec| {
304 const Option = Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option;
305 var buf: [422 var buf: [
306 max_len: {423 max_len: {
307 var max_len = 0;424 var max_len = 0;
308 for (@typeInfo(Option).@"enum".fields) |field| max_len = @max(max_len, field.name.len);425 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
309 break :max_len max_len;426 break :max_len max_len;
310 } + 1427 } + 1
311 ]u8 = undefined;428 ]u8 = undefined;
312 const extend = std.meta.stringToEnum(Option, std.ascii.lowerString(429 const extend = std.meta.stringToEnum(Result, std.ascii.lowerString(
313 &buf,430 &buf,
314 token[0..@min(token.len, buf.len)],431 token[0..@min(token.len, buf.len)],
315 )) orelse {432 )) orelse {
...@@ -323,15 +440,14 @@ const SymbolSpec = union(enum) {...@@ -323,15 +440,14 @@ const SymbolSpec = union(enum) {
323 return extend;440 return extend;
324 },441 },
325 .shift => |shift_spec| {442 .shift => |shift_spec| {
326 const ShiftOp = Instruction.DataProcessingRegister.Shift.Op;
327 var buf: [443 var buf: [
328 max_len: {444 max_len: {
329 var max_len = 0;445 var max_len = 0;
330 for (@typeInfo(ShiftOp).@"enum".fields) |field| max_len = @max(max_len, field.name.len);446 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
331 break :max_len max_len;447 break :max_len max_len;
332 } + 1448 } + 1
333 ]u8 = undefined;449 ]u8 = undefined;
334 const shift = std.meta.stringToEnum(ShiftOp, std.ascii.lowerString(450 const shift = std.meta.stringToEnum(Result, std.ascii.lowerString(
335 &buf,451 &buf,
336 token[0..@min(token.len, buf.len)],452 token[0..@min(token.len, buf.len)],
337 )) orelse {453 )) orelse {
...@@ -345,15 +461,14 @@ const SymbolSpec = union(enum) {...@@ -345,15 +461,14 @@ const SymbolSpec = union(enum) {
345 return shift;461 return shift;
346 },462 },
347 .barrier => |barrier_spec| {463 .barrier => |barrier_spec| {
348 const Option = Instruction.BranchExceptionGeneratingSystem.Barriers.Option;
349 var buf: [464 var buf: [
350 max_len: {465 max_len: {
351 var max_len = 0;466 var max_len = 0;
352 for (@typeInfo(Option).@"enum".fields) |field| max_len = @max(max_len, field.name.len);467 for (@typeInfo(Result).@"enum".fields) |field| max_len = @max(max_len, field.name.len);
353 break :max_len max_len;468 break :max_len max_len;
354 } + 1469 } + 1
355 ]u8 = undefined;470 ]u8 = undefined;
356 const barrier = std.meta.stringToEnum(Option, std.ascii.lowerString(471 const barrier = std.meta.stringToEnum(Result, std.ascii.lowerString(
357 &buf,472 &buf,
358 token[0..@min(token.len, buf.len)],473 token[0..@min(token.len, buf.len)],
359 )) orelse {474 )) orelse {
...@@ -778,6 +893,76 @@ test "add sub" {...@@ -778,6 +893,76 @@ test "add sub" {
778893
779 try std.testing.expect(null == try as.nextInstruction());894 try std.testing.expect(null == try as.nextInstruction());
780}895}
896test "bit manipulation" {
897 var as: Assemble = .{
898 .source =
899 \\rbit w0, w1
900 \\rbit w2, wzr
901 \\rbit x3, x4
902 \\rbit xzr, x5
903 \\
904 \\rev16 w0, w1
905 \\rev16 w2, wzr
906 \\rev16 x3, x4
907 \\rev16 xzr, x5
908 \\
909 \\rev32 x3, x4
910 \\rev32 xzr, x5
911 \\
912 \\rev w0, w1
913 \\rev w2, wzr
914 \\rev x3, x4
915 \\rev xzr, x5
916 \\
917 \\rev64 x3, x4
918 \\rev64 xzr, x5
919 \\
920 \\clz w0, w1
921 \\clz w2, wzr
922 \\clz x3, x4
923 \\clz xzr, x5
924 \\
925 \\cls w0, w1
926 \\cls w2, wzr
927 \\cls x3, x4
928 \\cls xzr, x5
929 ,
930 .operands = .empty,
931 };
932
933 try std.testing.expectFmt("rbit w0, w1", "{f}", .{(try as.nextInstruction()).?});
934 try std.testing.expectFmt("rbit w2, wzr", "{f}", .{(try as.nextInstruction()).?});
935 try std.testing.expectFmt("rbit x3, x4", "{f}", .{(try as.nextInstruction()).?});
936 try std.testing.expectFmt("rbit xzr, x5", "{f}", .{(try as.nextInstruction()).?});
937
938 try std.testing.expectFmt("rev16 w0, w1", "{f}", .{(try as.nextInstruction()).?});
939 try std.testing.expectFmt("rev16 w2, wzr", "{f}", .{(try as.nextInstruction()).?});
940 try std.testing.expectFmt("rev16 x3, x4", "{f}", .{(try as.nextInstruction()).?});
941 try std.testing.expectFmt("rev16 xzr, x5", "{f}", .{(try as.nextInstruction()).?});
942
943 try std.testing.expectFmt("rev32 x3, x4", "{f}", .{(try as.nextInstruction()).?});
944 try std.testing.expectFmt("rev32 xzr, x5", "{f}", .{(try as.nextInstruction()).?});
945
946 try std.testing.expectFmt("rev w0, w1", "{f}", .{(try as.nextInstruction()).?});
947 try std.testing.expectFmt("rev w2, wzr", "{f}", .{(try as.nextInstruction()).?});
948 try std.testing.expectFmt("rev x3, x4", "{f}", .{(try as.nextInstruction()).?});
949 try std.testing.expectFmt("rev xzr, x5", "{f}", .{(try as.nextInstruction()).?});
950
951 try std.testing.expectFmt("rev x3, x4", "{f}", .{(try as.nextInstruction()).?});
952 try std.testing.expectFmt("rev xzr, x5", "{f}", .{(try as.nextInstruction()).?});
953
954 try std.testing.expectFmt("clz w0, w1", "{f}", .{(try as.nextInstruction()).?});
955 try std.testing.expectFmt("clz w2, wzr", "{f}", .{(try as.nextInstruction()).?});
956 try std.testing.expectFmt("clz x3, x4", "{f}", .{(try as.nextInstruction()).?});
957 try std.testing.expectFmt("clz xzr, x5", "{f}", .{(try as.nextInstruction()).?});
958
959 try std.testing.expectFmt("cls w0, w1", "{f}", .{(try as.nextInstruction()).?});
960 try std.testing.expectFmt("cls w2, wzr", "{f}", .{(try as.nextInstruction()).?});
961 try std.testing.expectFmt("cls x3, x4", "{f}", .{(try as.nextInstruction()).?});
962 try std.testing.expectFmt("cls xzr, x5", "{f}", .{(try as.nextInstruction()).?});
963
964 try std.testing.expect(null == try as.nextInstruction());
965}
781test "bitfield" {966test "bitfield" {
782 var as: Assemble = .{967 var as: Assemble = .{
783 .source =968 .source =
...@@ -852,6 +1037,24 @@ test "branch register" {...@@ -852,6 +1037,24 @@ test "branch register" {
8521037
853 try std.testing.expect(null == try as.nextInstruction());1038 try std.testing.expect(null == try as.nextInstruction());
854}1039}
1040test "division" {
1041 var as: Assemble = .{
1042 .source =
1043 \\udiv w0, w1, w2
1044 \\udiv x3, x4, xzr
1045 \\sdiv w5, wzr, w6
1046 \\sdiv x7, x8, x9
1047 ,
1048 .operands = .empty,
1049 };
1050
1051 try std.testing.expectFmt("udiv w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
1052 try std.testing.expectFmt("udiv x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
1053 try std.testing.expectFmt("sdiv w5, wzr, w6", "{f}", .{(try as.nextInstruction()).?});
1054 try std.testing.expectFmt("sdiv x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
1055
1056 try std.testing.expect(null == try as.nextInstruction());
1057}
855test "exception generating" {1058test "exception generating" {
856 var as: Assemble = .{1059 var as: Assemble = .{
857 .source =1060 .source =
...@@ -1579,6 +1782,91 @@ test "mov" {...@@ -1579,6 +1782,91 @@ test "mov" {
1579 \\MOVZ XZR, #0xffff, lsl #161782 \\MOVZ XZR, #0xffff, lsl #16
1580 \\MOVZ XZR, #0xffff, lsl #321783 \\MOVZ XZR, #0xffff, lsl #32
1581 \\MOVZ XZR, #0xffff, lsl #481784 \\MOVZ XZR, #0xffff, lsl #48
1785 \\
1786 \\DUP B0, V1.B[15]
1787 \\DUP H2, V3.H[7]
1788 \\DUP S4, V5.S[3]
1789 \\DUP D6, V7.D[1]
1790 \\
1791 \\DUP V0.8B, V1.B[0]
1792 \\DUP V2.16B, V3.B[15]
1793 \\DUP V4.4H, V5.H[0]
1794 \\DUP V6.8H, V7.H[7]
1795 \\DUP V8.2S, V9.S[0]
1796 \\DUP V10.4S, V11.S[3]
1797 \\DUP V12.2D, V13.D[1]
1798 \\
1799 \\DUP V0.8B, W1
1800 \\DUP V2.16B, W3
1801 \\DUP V4.4H, W5
1802 \\DUP V6.8H, W7
1803 \\DUP V8.2S, W9
1804 \\DUP V10.4S, W11
1805 \\DUP V12.2D, X13
1806 \\
1807 \\FMOV V0.4H, #-31
1808 \\FMOV V1.8H, #-2.625
1809 \\FMOV V2.2S, #-1
1810 \\FMOV V3.4S, #-.2421875
1811 \\FMOV V4.2D, #.2421875
1812 \\FMOV H5, H6
1813 \\FMOV S7, S8
1814 \\FMOV D9, D10
1815 \\FMOV W11, H12
1816 \\FMOV X13, H14
1817 \\FMOV H15, W16
1818 \\FMOV S17, W18
1819 \\FMOV W19, S20
1820 \\FMOV H21, X22
1821 \\FMOV D23, X24
1822 \\FMOV V25.D[0x1], X26
1823 \\FMOV X27, D28
1824 \\FMOV X29, V30 . D [ 0X1 ]
1825 \\FMOV H31, #1
1826 \\FMOV S30, #2.625
1827 \\FMOV D29, #31
1828 \\
1829 \\INS V0.B[0], V1.B[15]
1830 \\INS V2.H[0], V3.H[7]
1831 \\INS V4.S[0], V5.S[3]
1832 \\INS V6.D[0], V7.D[1]
1833 \\
1834 \\INS V0.B[15], W1
1835 \\INS V2.H[7], W3
1836 \\INS V4.S[3], W5
1837 \\INS V6.D[1], X7
1838 \\
1839 \\MOV B0, V1.B [ 0xf]
1840 \\MOV H2, V3.H [ 0x7]
1841 \\MOV S4, V5.S [ 0x3]
1842 \\MOV D6, V7.D [ 0x1]
1843 \\
1844 \\MOV V0.B[0], V1.B[15]
1845 \\MOV V2.H[0], V3.H[7]
1846 \\MOV V4.S[0], V5.S[3]
1847 \\MOV V6.D[0], V7.D[1]
1848 \\
1849 \\MOV V0.B[15], W1
1850 \\MOV V2.H[7], W3
1851 \\MOV V4.S[3], W5
1852 \\MOV V6.D[1], X7
1853 \\
1854 \\MOV V0.8B, V1.8B
1855 \\MOV V2.16B, V3.16B
1856 \\
1857 \\MOV W0, V1.S[0x3]
1858 \\MOV X2, V3.D[0x1]
1859 \\
1860 \\SMOV W0, V1.B[0xF]
1861 \\SMOV W2, V3.H[0x7]
1862 \\SMOV X4, V5.B[0xF]
1863 \\SMOV X6, V7.H[0x7]
1864 \\SMOV X8, V9.S[0x3]
1865 \\
1866 \\UMOV W0, V1.B[0xF]
1867 \\UMOV W2, V3.H[0x7]
1868 \\UMOV W4, V5.S[0x3]
1869 \\UMOV X6, V7.D[0x1]
1582 ,1870 ,
1583 .operands = .empty,1871 .operands = .empty,
1584 };1872 };
...@@ -1661,6 +1949,171 @@ test "mov" {...@@ -1661,6 +1949,171 @@ test "mov" {
1661 try std.testing.expectFmt("mov xzr, #0xffff00000000", "{f}", .{(try as.nextInstruction()).?});1949 try std.testing.expectFmt("mov xzr, #0xffff00000000", "{f}", .{(try as.nextInstruction()).?});
1662 try std.testing.expectFmt("mov xzr, #-0x1000000000000", "{f}", .{(try as.nextInstruction()).?});1950 try std.testing.expectFmt("mov xzr, #-0x1000000000000", "{f}", .{(try as.nextInstruction()).?});
16631951
1952 try std.testing.expectFmt("mov b0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
1953 try std.testing.expectFmt("mov h2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
1954 try std.testing.expectFmt("mov s4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
1955 try std.testing.expectFmt("mov d6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
1956
1957 try std.testing.expectFmt("dup v0.8b, v1.b[0]", "{f}", .{(try as.nextInstruction()).?});
1958 try std.testing.expectFmt("dup v2.16b, v3.b[15]", "{f}", .{(try as.nextInstruction()).?});
1959 try std.testing.expectFmt("dup v4.4h, v5.h[0]", "{f}", .{(try as.nextInstruction()).?});
1960 try std.testing.expectFmt("dup v6.8h, v7.h[7]", "{f}", .{(try as.nextInstruction()).?});
1961 try std.testing.expectFmt("dup v8.2s, v9.s[0]", "{f}", .{(try as.nextInstruction()).?});
1962 try std.testing.expectFmt("dup v10.4s, v11.s[3]", "{f}", .{(try as.nextInstruction()).?});
1963 try std.testing.expectFmt("dup v12.2d, v13.d[1]", "{f}", .{(try as.nextInstruction()).?});
1964
1965 try std.testing.expectFmt("dup v0.8b, w1", "{f}", .{(try as.nextInstruction()).?});
1966 try std.testing.expectFmt("dup v2.16b, w3", "{f}", .{(try as.nextInstruction()).?});
1967 try std.testing.expectFmt("dup v4.4h, w5", "{f}", .{(try as.nextInstruction()).?});
1968 try std.testing.expectFmt("dup v6.8h, w7", "{f}", .{(try as.nextInstruction()).?});
1969 try std.testing.expectFmt("dup v8.2s, w9", "{f}", .{(try as.nextInstruction()).?});
1970 try std.testing.expectFmt("dup v10.4s, w11", "{f}", .{(try as.nextInstruction()).?});
1971 try std.testing.expectFmt("dup v12.2d, x13", "{f}", .{(try as.nextInstruction()).?});
1972
1973 try std.testing.expectFmt("fmov v0.4h, #-31.0", "{f}", .{(try as.nextInstruction()).?});
1974 try std.testing.expectFmt("fmov v1.8h, #-2.625", "{f}", .{(try as.nextInstruction()).?});
1975 try std.testing.expectFmt("fmov v2.2s, #-1.0", "{f}", .{(try as.nextInstruction()).?});
1976 try std.testing.expectFmt("fmov v3.4s, #-0.2421875", "{f}", .{(try as.nextInstruction()).?});
1977 try std.testing.expectFmt("fmov v4.2d, #0.2421875", "{f}", .{(try as.nextInstruction()).?});
1978 try std.testing.expectFmt("fmov h5, h6", "{f}", .{(try as.nextInstruction()).?});
1979 try std.testing.expectFmt("fmov s7, s8", "{f}", .{(try as.nextInstruction()).?});
1980 try std.testing.expectFmt("fmov d9, d10", "{f}", .{(try as.nextInstruction()).?});
1981 try std.testing.expectFmt("fmov w11, h12", "{f}", .{(try as.nextInstruction()).?});
1982 try std.testing.expectFmt("fmov x13, h14", "{f}", .{(try as.nextInstruction()).?});
1983 try std.testing.expectFmt("fmov h15, w16", "{f}", .{(try as.nextInstruction()).?});
1984 try std.testing.expectFmt("fmov s17, w18", "{f}", .{(try as.nextInstruction()).?});
1985 try std.testing.expectFmt("fmov w19, s20", "{f}", .{(try as.nextInstruction()).?});
1986 try std.testing.expectFmt("fmov h21, x22", "{f}", .{(try as.nextInstruction()).?});
1987 try std.testing.expectFmt("fmov d23, x24", "{f}", .{(try as.nextInstruction()).?});
1988 try std.testing.expectFmt("fmov v25.d[1], x26", "{f}", .{(try as.nextInstruction()).?});
1989 try std.testing.expectFmt("fmov x27, d28", "{f}", .{(try as.nextInstruction()).?});
1990 try std.testing.expectFmt("fmov x29, v30.d[1]", "{f}", .{(try as.nextInstruction()).?});
1991 try std.testing.expectFmt("fmov h31, #1.0", "{f}", .{(try as.nextInstruction()).?});
1992 try std.testing.expectFmt("fmov s30, #2.625", "{f}", .{(try as.nextInstruction()).?});
1993 try std.testing.expectFmt("fmov d29, #31.0", "{f}", .{(try as.nextInstruction()).?});
1994
1995 try std.testing.expectFmt("mov v0.b[0], v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
1996 try std.testing.expectFmt("mov v2.h[0], v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
1997 try std.testing.expectFmt("mov v4.s[0], v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
1998 try std.testing.expectFmt("mov v6.d[0], v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
1999
2000 try std.testing.expectFmt("mov v0.b[15], w1", "{f}", .{(try as.nextInstruction()).?});
2001 try std.testing.expectFmt("mov v2.h[7], w3", "{f}", .{(try as.nextInstruction()).?});
2002 try std.testing.expectFmt("mov v4.s[3], w5", "{f}", .{(try as.nextInstruction()).?});
2003 try std.testing.expectFmt("mov v6.d[1], x7", "{f}", .{(try as.nextInstruction()).?});
2004
2005 try std.testing.expectFmt("mov b0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2006 try std.testing.expectFmt("mov h2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2007 try std.testing.expectFmt("mov s4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2008 try std.testing.expectFmt("mov d6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2009
2010 try std.testing.expectFmt("mov v0.b[0], v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2011 try std.testing.expectFmt("mov v2.h[0], v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2012 try std.testing.expectFmt("mov v4.s[0], v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2013 try std.testing.expectFmt("mov v6.d[0], v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2014
2015 try std.testing.expectFmt("mov v0.b[15], w1", "{f}", .{(try as.nextInstruction()).?});
2016 try std.testing.expectFmt("mov v2.h[7], w3", "{f}", .{(try as.nextInstruction()).?});
2017 try std.testing.expectFmt("mov v4.s[3], w5", "{f}", .{(try as.nextInstruction()).?});
2018 try std.testing.expectFmt("mov v6.d[1], x7", "{f}", .{(try as.nextInstruction()).?});
2019
2020 try std.testing.expectFmt("mov v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2021 try std.testing.expectFmt("mov v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2022
2023 try std.testing.expectFmt("mov w0, v1.s[3]", "{f}", .{(try as.nextInstruction()).?});
2024 try std.testing.expectFmt("mov x2, v3.d[1]", "{f}", .{(try as.nextInstruction()).?});
2025
2026 try std.testing.expectFmt("smov w0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2027 try std.testing.expectFmt("smov w2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2028 try std.testing.expectFmt("smov x4, v5.b[15]", "{f}", .{(try as.nextInstruction()).?});
2029 try std.testing.expectFmt("smov x6, v7.h[7]", "{f}", .{(try as.nextInstruction()).?});
2030 try std.testing.expectFmt("smov x8, v9.s[3]", "{f}", .{(try as.nextInstruction()).?});
2031
2032 try std.testing.expectFmt("umov w0, v1.b[15]", "{f}", .{(try as.nextInstruction()).?});
2033 try std.testing.expectFmt("umov w2, v3.h[7]", "{f}", .{(try as.nextInstruction()).?});
2034 try std.testing.expectFmt("mov w4, v5.s[3]", "{f}", .{(try as.nextInstruction()).?});
2035 try std.testing.expectFmt("mov x6, v7.d[1]", "{f}", .{(try as.nextInstruction()).?});
2036
2037 try std.testing.expect(null == try as.nextInstruction());
2038}
2039test "multiply" {
2040 var as: Assemble = .{
2041 .source =
2042 \\madd w0, w1, w2, w3
2043 \\madd w4, w5, w6, wzr
2044 \\mul w7, w8, w9
2045 \\madd x10, x11, x12, x13
2046 \\madd x14, x15, x16, xzr
2047 \\mul x17, x18, x19
2048 \\
2049 \\msub w0, w1, w2, w3
2050 \\msub w4, w5, w6, wzr
2051 \\mneg w7, w8, w9
2052 \\msub x10, x11, x12, x13
2053 \\msub x14, x15, x16, xzr
2054 \\mneg x17, x18, x19
2055 \\
2056 \\smaddl x0, w1, w2, x3
2057 \\smaddl x4, w5, w6, xzr
2058 \\smull x7, w8, w9
2059 \\
2060 \\smsubl x0, w1, w2, x3
2061 \\smsubl x4, w5, w6, xzr
2062 \\smnegl x7, w8, w9
2063 \\
2064 \\smulh x0, x1, x2
2065 \\smulh x3, x4, xzr
2066 \\
2067 \\umaddl x0, w1, w2, x3
2068 \\umaddl x4, w5, w6, xzr
2069 \\umull x7, w8, w9
2070 \\
2071 \\umsubl x0, w1, w2, x3
2072 \\umsubl x4, w5, w6, xzr
2073 \\umnegl x7, w8, w9
2074 \\
2075 \\umulh x0, x1, x2
2076 \\umulh x3, x4, xzr
2077 ,
2078 .operands = .empty,
2079 };
2080
2081 try std.testing.expectFmt("madd w0, w1, w2, w3", "{f}", .{(try as.nextInstruction()).?});
2082 try std.testing.expectFmt("mul w4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2083 try std.testing.expectFmt("mul w7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2084 try std.testing.expectFmt("madd x10, x11, x12, x13", "{f}", .{(try as.nextInstruction()).?});
2085 try std.testing.expectFmt("mul x14, x15, x16", "{f}", .{(try as.nextInstruction()).?});
2086 try std.testing.expectFmt("mul x17, x18, x19", "{f}", .{(try as.nextInstruction()).?});
2087
2088 try std.testing.expectFmt("msub w0, w1, w2, w3", "{f}", .{(try as.nextInstruction()).?});
2089 try std.testing.expectFmt("mneg w4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2090 try std.testing.expectFmt("mneg w7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2091 try std.testing.expectFmt("msub x10, x11, x12, x13", "{f}", .{(try as.nextInstruction()).?});
2092 try std.testing.expectFmt("mneg x14, x15, x16", "{f}", .{(try as.nextInstruction()).?});
2093 try std.testing.expectFmt("mneg x17, x18, x19", "{f}", .{(try as.nextInstruction()).?});
2094
2095 try std.testing.expectFmt("smaddl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2096 try std.testing.expectFmt("smull x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2097 try std.testing.expectFmt("smull x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2098
2099 try std.testing.expectFmt("smsubl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2100 try std.testing.expectFmt("smnegl x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2101 try std.testing.expectFmt("smnegl x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2102
2103 try std.testing.expectFmt("smulh x0, x1, x2", "{f}", .{(try as.nextInstruction()).?});
2104 try std.testing.expectFmt("smulh x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
2105
2106 try std.testing.expectFmt("umaddl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2107 try std.testing.expectFmt("umull x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2108 try std.testing.expectFmt("umull x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2109
2110 try std.testing.expectFmt("umsubl x0, w1, w2, x3", "{f}", .{(try as.nextInstruction()).?});
2111 try std.testing.expectFmt("umnegl x4, w5, w6", "{f}", .{(try as.nextInstruction()).?});
2112 try std.testing.expectFmt("umnegl x7, w8, w9", "{f}", .{(try as.nextInstruction()).?});
2113
2114 try std.testing.expectFmt("umulh x0, x1, x2", "{f}", .{(try as.nextInstruction()).?});
2115 try std.testing.expectFmt("umulh x3, x4, xzr", "{f}", .{(try as.nextInstruction()).?});
2116
1664 try std.testing.expect(null == try as.nextInstruction());2117 try std.testing.expect(null == try as.nextInstruction());
1665}2118}
1666test "reserved" {2119test "reserved" {
...@@ -1675,6 +2128,808 @@ test "reserved" {...@@ -1675,6 +2128,808 @@ test "reserved" {
16752128
1676 try std.testing.expect(null == try as.nextInstruction());2129 try std.testing.expect(null == try as.nextInstruction());
1677}2130}
2131test "shift" {
2132 var as: Assemble = .{
2133 .source =
2134 \\lsl w0, w1, w2
2135 \\lslv w3, w4, wzr
2136 \\lsl x5, x6, xzr
2137 \\lslv x7, x8, x9
2138 \\
2139 \\lsr w0, w1, w2
2140 \\lsrv w3, w4, wzr
2141 \\lsr x5, x6, xzr
2142 \\lsrv x7, x8, x9
2143 \\
2144 \\asr w0, w1, w2
2145 \\asrv w3, w4, wzr
2146 \\asr x5, x6, xzr
2147 \\asrv x7, x8, x9
2148 \\
2149 \\ror w0, w1, w2
2150 \\rorv w3, w4, wzr
2151 \\ror x5, x6, xzr
2152 \\rorv x7, x8, x9
2153 ,
2154 .operands = .empty,
2155 };
2156
2157 try std.testing.expectFmt("lsl w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2158 try std.testing.expectFmt("lsl w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2159 try std.testing.expectFmt("lsl x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2160 try std.testing.expectFmt("lsl x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2161
2162 try std.testing.expectFmt("lsr w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2163 try std.testing.expectFmt("lsr w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2164 try std.testing.expectFmt("lsr x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2165 try std.testing.expectFmt("lsr x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2166
2167 try std.testing.expectFmt("asr w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2168 try std.testing.expectFmt("asr w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2169 try std.testing.expectFmt("asr x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2170 try std.testing.expectFmt("asr x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2171
2172 try std.testing.expectFmt("ror w0, w1, w2", "{f}", .{(try as.nextInstruction()).?});
2173 try std.testing.expectFmt("ror w3, w4, wzr", "{f}", .{(try as.nextInstruction()).?});
2174 try std.testing.expectFmt("ror x5, x6, xzr", "{f}", .{(try as.nextInstruction()).?});
2175 try std.testing.expectFmt("ror x7, x8, x9", "{f}", .{(try as.nextInstruction()).?});
2176
2177 try std.testing.expect(null == try as.nextInstruction());
2178}
2179test "unary vector" {
2180 var as: Assemble = .{
2181 .source =
2182 \\SUQADD B0, B1
2183 \\SUQADD H2, H3
2184 \\SUQADD S4, S5
2185 \\SUQADD D6, D7
2186 \\SUQADD V8.8B, V9.8B
2187 \\SUQADD V10.16B, V11.16B
2188 \\SUQADD V12.4H, V13.4H
2189 \\SUQADD V14.8H, V15.8H
2190 \\SUQADD V16.2S, V17.2S
2191 \\SUQADD V18.4S, V19.4S
2192 \\SUQADD V20.2D, V21.2D
2193 \\
2194 \\CNT V0.8B, V1.8B
2195 \\CNT V2.16B, V3.16B
2196 \\
2197 \\SQABS B0, B1
2198 \\SQABS H2, H3
2199 \\SQABS S4, S5
2200 \\SQABS D6, D7
2201 \\SQABS V8.8B, V9.8B
2202 \\SQABS V10.16B, V11.16B
2203 \\SQABS V12.4H, V13.4H
2204 \\SQABS V14.8H, V15.8H
2205 \\SQABS V16.2S, V17.2S
2206 \\SQABS V18.4S, V19.4S
2207 \\SQABS V20.2D, V21.2D
2208 \\
2209 \\CMGT D0, D1, #00
2210 \\CMGT V2.8B, V3.8B, #0
2211 \\CMGT V4.16B, V5.16B, #0
2212 \\CMGT V6.4H, V7.4H, #0
2213 \\CMGT V8.8H, V9.8H, #0
2214 \\CMGT V10.2S, V11.2S, #0
2215 \\CMGT V12.4S, V13.4S, #0
2216 \\CMGT V14.2D, V15.2D, #0
2217 \\
2218 \\CMEQ D0, D1, #00
2219 \\CMEQ V2.8B, V3.8B, #0
2220 \\CMEQ V4.16B, V5.16B, #0
2221 \\CMEQ V6.4H, V7.4H, #0
2222 \\CMEQ V8.8H, V9.8H, #0
2223 \\CMEQ V10.2S, V11.2S, #0
2224 \\CMEQ V12.4S, V13.4S, #0
2225 \\CMEQ V14.2D, V15.2D, #0
2226 \\
2227 \\CMLT D0, D1, #00
2228 \\CMLT V2.8B, V3.8B, #0
2229 \\CMLT V4.16B, V5.16B, #0
2230 \\CMLT V6.4H, V7.4H, #0
2231 \\CMLT V8.8H, V9.8H, #0
2232 \\CMLT V10.2S, V11.2S, #0
2233 \\CMLT V12.4S, V13.4S, #0
2234 \\CMLT V14.2D, V15.2D, #0
2235 \\
2236 \\ABS D0, D1
2237 \\ABS V2.8B, V3.8B
2238 \\ABS V4.16B, V5.16B
2239 \\ABS V6.4H, V7.4H
2240 \\ABS V8.8H, V9.8H
2241 \\ABS V10.2S, V11.2S
2242 \\ABS V12.4S, V13.4S
2243 \\ABS V14.2D, V15.2D
2244 \\
2245 \\SQXTN B0, H1
2246 \\SQXTN H2, S3
2247 \\SQXTN S4, D5
2248 \\SQXTN V6.8B, V7.8H
2249 \\SQXTN2 V8.16B, V9.8H
2250 \\SQXTN V10.4H, V11.4S
2251 \\SQXTN2 V12.8H, V13.4S
2252 \\SQXTN V14.2S, V15.2D
2253 \\SQXTN2 V16.4S, V17.2D
2254 \\
2255 \\FRINTN V0.4H, V1.4H
2256 \\FRINTN V2.8H, V3.8H
2257 \\FRINTN V4.2S, V5.2S
2258 \\FRINTN V6.4S, V7.4S
2259 \\FRINTN V8.2D, V9.2D
2260 \\FRINTN H10, H11
2261 \\FRINTN S12, S13
2262 \\FRINTN D14, D15
2263 \\
2264 \\FRINTM V0.4H, V1.4H
2265 \\FRINTM V2.8H, V3.8H
2266 \\FRINTM V4.2S, V5.2S
2267 \\FRINTM V6.4S, V7.4S
2268 \\FRINTM V8.2D, V9.2D
2269 \\FRINTM H10, H11
2270 \\FRINTM S12, S13
2271 \\FRINTM D14, D15
2272 \\
2273 \\FCVTNS H0, H1
2274 \\FCVTNS S2, S3
2275 \\FCVTNS D4, D5
2276 \\FCVTNS V6.4H, V7.4H
2277 \\FCVTNS V8.8H, V9.8H
2278 \\FCVTNS V10.2S, V11.2S
2279 \\FCVTNS V12.4S, V13.4S
2280 \\FCVTNS V14.2D, V15.2D
2281 \\FCVTNS W16, H17
2282 \\FCVTNS X18, H19
2283 \\FCVTNS W20, S21
2284 \\FCVTNS X22, S23
2285 \\FCVTNS W24, D25
2286 \\FCVTNS X26, D27
2287 \\
2288 \\FCVTMS H0, H1
2289 \\FCVTMS S2, S3
2290 \\FCVTMS D4, D5
2291 \\FCVTMS V6.4H, V7.4H
2292 \\FCVTMS V8.8H, V9.8H
2293 \\FCVTMS V10.2S, V11.2S
2294 \\FCVTMS V12.4S, V13.4S
2295 \\FCVTMS V14.2D, V15.2D
2296 \\FCVTMS W16, H17
2297 \\FCVTMS X18, H19
2298 \\FCVTMS W20, S21
2299 \\FCVTMS X22, S23
2300 \\FCVTMS W24, D25
2301 \\FCVTMS X26, D27
2302 \\
2303 \\FCVTAS H0, H1
2304 \\FCVTAS S2, S3
2305 \\FCVTAS D4, D5
2306 \\FCVTAS V6.4H, V7.4H
2307 \\FCVTAS V8.8H, V9.8H
2308 \\FCVTAS V10.2S, V11.2S
2309 \\FCVTAS V12.4S, V13.4S
2310 \\FCVTAS V14.2D, V15.2D
2311 \\FCVTAS W16, H17
2312 \\FCVTAS X18, H19
2313 \\FCVTAS W20, S21
2314 \\FCVTAS X22, S23
2315 \\FCVTAS W24, D25
2316 \\FCVTAS X26, D27
2317 \\
2318 \\SCVTF H0, H1
2319 \\SCVTF S2, S3
2320 \\SCVTF D4, D5
2321 \\SCVTF V6.4H, V7.4H
2322 \\SCVTF V8.8H, V9.8H
2323 \\SCVTF V10.2S, V11.2S
2324 \\SCVTF V12.4S, V13.4S
2325 \\SCVTF V14.2D, V15.2D
2326 \\SCVTF H16, W17
2327 \\SCVTF H18, X19
2328 \\SCVTF S20, W21
2329 \\SCVTF S22, X23
2330 \\SCVTF D24, W25
2331 \\SCVTF D26, X27
2332 \\
2333 \\FCMGT H0, H1, #0.0
2334 \\FCMGT S2, S3, # 0.0
2335 \\FCMGT D4, D5, #+0.0
2336 \\FCMGT V6.4H, V7.4H, # +0.0
2337 \\FCMGT V8.8H, V9.8H, #0
2338 \\FCMGT V10.2S, V11.2S, # 0
2339 \\FCMGT V12.4S, V13.4S, #+0
2340 \\FCMGT V14.2D, V15.2D, # +0
2341 \\
2342 \\FCMEQ H0, H1, #0.0
2343 \\FCMEQ S2, S3, # 0.0
2344 \\FCMEQ D4, D5, #+0.0
2345 \\FCMEQ V6.4H, V7.4H, # +0.0
2346 \\FCMEQ V8.8H, V9.8H, #0
2347 \\FCMEQ V10.2S, V11.2S, # 0
2348 \\FCMEQ V12.4S, V13.4S, #+0
2349 \\FCMEQ V14.2D, V15.2D, # +0
2350 \\
2351 \\FCMLT H0, H1, #0.0
2352 \\FCMLT S2, S3, # 0.0
2353 \\FCMLT D4, D5, #+0.0
2354 \\FCMLT V6.4H, V7.4H, # +0.0
2355 \\FCMLT V8.8H, V9.8H, #0
2356 \\FCMLT V10.2S, V11.2S, # 0
2357 \\FCMLT V12.4S, V13.4S, #+0
2358 \\FCMLT V14.2D, V15.2D, # +0
2359 \\
2360 \\FRINTP V0.4H, V1.4H
2361 \\FRINTP V2.8H, V3.8H
2362 \\FRINTP V4.2S, V5.2S
2363 \\FRINTP V6.4S, V7.4S
2364 \\FRINTP V8.2D, V9.2D
2365 \\FRINTP H10, H11
2366 \\FRINTP S12, S13
2367 \\FRINTP D14, D15
2368 \\
2369 \\FRINTZ V0.4H, V1.4H
2370 \\FRINTZ V2.8H, V3.8H
2371 \\FRINTZ V4.2S, V5.2S
2372 \\FRINTZ V6.4S, V7.4S
2373 \\FRINTZ V8.2D, V9.2D
2374 \\FRINTZ H10, H11
2375 \\FRINTZ S12, S13
2376 \\FRINTZ D14, D15
2377 \\
2378 \\FCVTPS H0, H1
2379 \\FCVTPS S2, S3
2380 \\FCVTPS D4, D5
2381 \\FCVTPS V6.4H, V7.4H
2382 \\FCVTPS V8.8H, V9.8H
2383 \\FCVTPS V10.2S, V11.2S
2384 \\FCVTPS V12.4S, V13.4S
2385 \\FCVTPS V14.2D, V15.2D
2386 \\FCVTPS W16, H17
2387 \\FCVTPS X18, H19
2388 \\FCVTPS W20, S21
2389 \\FCVTPS X22, S23
2390 \\FCVTPS W24, D25
2391 \\FCVTPS X26, D27
2392 \\
2393 \\FCVTZS H0, H1
2394 \\FCVTZS S2, S3
2395 \\FCVTZS D4, D5
2396 \\FCVTZS V6.4H, V7.4H
2397 \\FCVTZS V8.8H, V9.8H
2398 \\FCVTZS V10.2S, V11.2S
2399 \\FCVTZS V12.4S, V13.4S
2400 \\FCVTZS V14.2D, V15.2D
2401 \\FCVTZS W16, H17
2402 \\FCVTZS X18, H19
2403 \\FCVTZS W20, S21
2404 \\FCVTZS X22, S23
2405 \\FCVTZS W24, D25
2406 \\FCVTZS X26, D27
2407 \\
2408 \\CMGE D0, D1, #00
2409 \\CMGE V2.8B, V3.8B, #0
2410 \\CMGE V4.16B, V5.16B, #0
2411 \\CMGE V6.4H, V7.4H, #0
2412 \\CMGE V8.8H, V9.8H, #0
2413 \\CMGE V10.2S, V11.2S, #0
2414 \\CMGE V12.4S, V13.4S, #0
2415 \\CMGE V14.2D, V15.2D, #0
2416 \\
2417 \\CMLE D0, D1, #00
2418 \\CMLE V2.8B, V3.8B, #0
2419 \\CMLE V4.16B, V5.16B, #0
2420 \\CMLE V6.4H, V7.4H, #0
2421 \\CMLE V8.8H, V9.8H, #0
2422 \\CMLE V10.2S, V11.2S, #0
2423 \\CMLE V12.4S, V13.4S, #0
2424 \\CMLE V14.2D, V15.2D, #0
2425 \\
2426 \\NEG D0, D1
2427 \\NEG V2.8B, V3.8B
2428 \\NEG V4.16B, V5.16B
2429 \\NEG V6.4H, V7.4H
2430 \\NEG V8.8H, V9.8H
2431 \\NEG V10.2S, V11.2S
2432 \\NEG V12.4S, V13.4S
2433 \\NEG V14.2D, V15.2D
2434 \\
2435 \\FCVTNU H0, H1
2436 \\FCVTNU S2, S3
2437 \\FCVTNU D4, D5
2438 \\FCVTNU V6.4H, V7.4H
2439 \\FCVTNU V8.8H, V9.8H
2440 \\FCVTNU V10.2S, V11.2S
2441 \\FCVTNU V12.4S, V13.4S
2442 \\FCVTNU V14.2D, V15.2D
2443 \\FCVTNU W16, H17
2444 \\FCVTNU X18, H19
2445 \\FCVTNU W20, S21
2446 \\FCVTNU X22, S23
2447 \\FCVTNU W24, D25
2448 \\FCVTNU X26, D27
2449 \\
2450 \\FCVTMU H0, H1
2451 \\FCVTMU S2, S3
2452 \\FCVTMU D4, D5
2453 \\FCVTMU V6.4H, V7.4H
2454 \\FCVTMU V8.8H, V9.8H
2455 \\FCVTMU V10.2S, V11.2S
2456 \\FCVTMU V12.4S, V13.4S
2457 \\FCVTMU V14.2D, V15.2D
2458 \\FCVTMU W16, H17
2459 \\FCVTMU X18, H19
2460 \\FCVTMU W20, S21
2461 \\FCVTMU X22, S23
2462 \\FCVTMU W24, D25
2463 \\FCVTMU X26, D27
2464 \\
2465 \\FCVTAU H0, H1
2466 \\FCVTAU S2, S3
2467 \\FCVTAU D4, D5
2468 \\FCVTAU V6.4H, V7.4H
2469 \\FCVTAU V8.8H, V9.8H
2470 \\FCVTAU V10.2S, V11.2S
2471 \\FCVTAU V12.4S, V13.4S
2472 \\FCVTAU V14.2D, V15.2D
2473 \\FCVTAU W16, H17
2474 \\FCVTAU X18, H19
2475 \\FCVTAU W20, S21
2476 \\FCVTAU X22, S23
2477 \\FCVTAU W24, D25
2478 \\FCVTAU X26, D27
2479 \\
2480 \\UCVTF H0, H1
2481 \\UCVTF S2, S3
2482 \\UCVTF D4, D5
2483 \\UCVTF V6.4H, V7.4H
2484 \\UCVTF V8.8H, V9.8H
2485 \\UCVTF V10.2S, V11.2S
2486 \\UCVTF V12.4S, V13.4S
2487 \\UCVTF V14.2D, V15.2D
2488 \\UCVTF H16, W17
2489 \\UCVTF H18, X19
2490 \\UCVTF S20, W21
2491 \\UCVTF S22, X23
2492 \\UCVTF D24, W25
2493 \\UCVTF D26, X27
2494 \\
2495 \\NOT V0.8B, V1.8B
2496 \\NOT V2.16B, V3.16B
2497 \\
2498 \\FCMGE H0, H1, #0.0
2499 \\FCMGE S2, S3, # 0.0
2500 \\FCMGE D4, D5, #+0.0
2501 \\FCMGE V6.4H, V7.4H, # +0.0
2502 \\FCMGE V8.8H, V9.8H, #0
2503 \\FCMGE V10.2S, V11.2S, # 0
2504 \\FCMGE V12.4S, V13.4S, #+0
2505 \\FCMGE V14.2D, V15.2D, # +0
2506 \\
2507 \\FCMLE H0, H1, #0.0
2508 \\FCMLE S2, S3, # 0.0
2509 \\FCMLE D4, D5, #+0.0
2510 \\FCMLE V6.4H, V7.4H, # +0.0
2511 \\FCMLE V8.8H, V9.8H, #0
2512 \\FCMLE V10.2S, V11.2S, # 0
2513 \\FCMLE V12.4S, V13.4S, #+0
2514 \\FCMLE V14.2D, V15.2D, # +0
2515 \\
2516 \\FRINTI V0.4H, V1.4H
2517 \\FRINTI V2.8H, V3.8H
2518 \\FRINTI V4.2S, V5.2S
2519 \\FRINTI V6.4S, V7.4S
2520 \\FRINTI V8.2D, V9.2D
2521 \\FRINTI H10, H11
2522 \\FRINTI S12, S13
2523 \\FRINTI D14, D15
2524 \\
2525 \\FCVTPU H0, H1
2526 \\FCVTPU S2, S3
2527 \\FCVTPU D4, D5
2528 \\FCVTPU V6.4H, V7.4H
2529 \\FCVTPU V8.8H, V9.8H
2530 \\FCVTPU V10.2S, V11.2S
2531 \\FCVTPU V12.4S, V13.4S
2532 \\FCVTPU V14.2D, V15.2D
2533 \\FCVTPU W16, H17
2534 \\FCVTPU X18, H19
2535 \\FCVTPU W20, S21
2536 \\FCVTPU X22, S23
2537 \\FCVTPU W24, D25
2538 \\FCVTPU X26, D27
2539 \\
2540 \\FCVTZU H0, H1
2541 \\FCVTZU S2, S3
2542 \\FCVTZU D4, D5
2543 \\FCVTZU V6.4H, V7.4H
2544 \\FCVTZU V8.8H, V9.8H
2545 \\FCVTZU V10.2S, V11.2S
2546 \\FCVTZU V12.4S, V13.4S
2547 \\FCVTZU V14.2D, V15.2D
2548 \\FCVTZU W16, H17
2549 \\FCVTZU X18, H19
2550 \\FCVTZU W20, S21
2551 \\FCVTZU X22, S23
2552 \\FCVTZU W24, D25
2553 \\FCVTZU X26, D27
2554 ,
2555 .operands = .empty,
2556 };
2557
2558 try std.testing.expectFmt("suqadd b0, b1", "{f}", .{(try as.nextInstruction()).?});
2559 try std.testing.expectFmt("suqadd h2, h3", "{f}", .{(try as.nextInstruction()).?});
2560 try std.testing.expectFmt("suqadd s4, s5", "{f}", .{(try as.nextInstruction()).?});
2561 try std.testing.expectFmt("suqadd d6, d7", "{f}", .{(try as.nextInstruction()).?});
2562 try std.testing.expectFmt("suqadd v8.8b, v9.8b", "{f}", .{(try as.nextInstruction()).?});
2563 try std.testing.expectFmt("suqadd v10.16b, v11.16b", "{f}", .{(try as.nextInstruction()).?});
2564 try std.testing.expectFmt("suqadd v12.4h, v13.4h", "{f}", .{(try as.nextInstruction()).?});
2565 try std.testing.expectFmt("suqadd v14.8h, v15.8h", "{f}", .{(try as.nextInstruction()).?});
2566 try std.testing.expectFmt("suqadd v16.2s, v17.2s", "{f}", .{(try as.nextInstruction()).?});
2567 try std.testing.expectFmt("suqadd v18.4s, v19.4s", "{f}", .{(try as.nextInstruction()).?});
2568 try std.testing.expectFmt("suqadd v20.2d, v21.2d", "{f}", .{(try as.nextInstruction()).?});
2569
2570 try std.testing.expectFmt("cnt v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2571 try std.testing.expectFmt("cnt v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2572
2573 try std.testing.expectFmt("sqabs b0, b1", "{f}", .{(try as.nextInstruction()).?});
2574 try std.testing.expectFmt("sqabs h2, h3", "{f}", .{(try as.nextInstruction()).?});
2575 try std.testing.expectFmt("sqabs s4, s5", "{f}", .{(try as.nextInstruction()).?});
2576 try std.testing.expectFmt("sqabs d6, d7", "{f}", .{(try as.nextInstruction()).?});
2577 try std.testing.expectFmt("sqabs v8.8b, v9.8b", "{f}", .{(try as.nextInstruction()).?});
2578 try std.testing.expectFmt("sqabs v10.16b, v11.16b", "{f}", .{(try as.nextInstruction()).?});
2579 try std.testing.expectFmt("sqabs v12.4h, v13.4h", "{f}", .{(try as.nextInstruction()).?});
2580 try std.testing.expectFmt("sqabs v14.8h, v15.8h", "{f}", .{(try as.nextInstruction()).?});
2581 try std.testing.expectFmt("sqabs v16.2s, v17.2s", "{f}", .{(try as.nextInstruction()).?});
2582 try std.testing.expectFmt("sqabs v18.4s, v19.4s", "{f}", .{(try as.nextInstruction()).?});
2583 try std.testing.expectFmt("sqabs v20.2d, v21.2d", "{f}", .{(try as.nextInstruction()).?});
2584
2585 try std.testing.expectFmt("cmgt d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2586 try std.testing.expectFmt("cmgt v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2587 try std.testing.expectFmt("cmgt v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2588 try std.testing.expectFmt("cmgt v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2589 try std.testing.expectFmt("cmgt v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2590 try std.testing.expectFmt("cmgt v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2591 try std.testing.expectFmt("cmgt v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2592 try std.testing.expectFmt("cmgt v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2593
2594 try std.testing.expectFmt("cmeq d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2595 try std.testing.expectFmt("cmeq v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2596 try std.testing.expectFmt("cmeq v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2597 try std.testing.expectFmt("cmeq v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2598 try std.testing.expectFmt("cmeq v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2599 try std.testing.expectFmt("cmeq v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2600 try std.testing.expectFmt("cmeq v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2601 try std.testing.expectFmt("cmeq v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2602
2603 try std.testing.expectFmt("cmlt d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2604 try std.testing.expectFmt("cmlt v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2605 try std.testing.expectFmt("cmlt v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2606 try std.testing.expectFmt("cmlt v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2607 try std.testing.expectFmt("cmlt v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2608 try std.testing.expectFmt("cmlt v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2609 try std.testing.expectFmt("cmlt v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2610 try std.testing.expectFmt("cmlt v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2611
2612 try std.testing.expectFmt("abs d0, d1", "{f}", .{(try as.nextInstruction()).?});
2613 try std.testing.expectFmt("abs v2.8b, v3.8b", "{f}", .{(try as.nextInstruction()).?});
2614 try std.testing.expectFmt("abs v4.16b, v5.16b", "{f}", .{(try as.nextInstruction()).?});
2615 try std.testing.expectFmt("abs v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2616 try std.testing.expectFmt("abs v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2617 try std.testing.expectFmt("abs v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2618 try std.testing.expectFmt("abs v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2619 try std.testing.expectFmt("abs v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2620
2621 try std.testing.expectFmt("sqxtn b0, h1", "{f}", .{(try as.nextInstruction()).?});
2622 try std.testing.expectFmt("sqxtn h2, s3", "{f}", .{(try as.nextInstruction()).?});
2623 try std.testing.expectFmt("sqxtn s4, d5", "{f}", .{(try as.nextInstruction()).?});
2624 try std.testing.expectFmt("sqxtn v6.8b, v7.8h", "{f}", .{(try as.nextInstruction()).?});
2625 try std.testing.expectFmt("sqxtn2 v8.16b, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2626 try std.testing.expectFmt("sqxtn v10.4h, v11.4s", "{f}", .{(try as.nextInstruction()).?});
2627 try std.testing.expectFmt("sqxtn2 v12.8h, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2628 try std.testing.expectFmt("sqxtn v14.2s, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2629 try std.testing.expectFmt("sqxtn2 v16.4s, v17.2d", "{f}", .{(try as.nextInstruction()).?});
2630
2631 try std.testing.expectFmt("frintn v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2632 try std.testing.expectFmt("frintn v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2633 try std.testing.expectFmt("frintn v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2634 try std.testing.expectFmt("frintn v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2635 try std.testing.expectFmt("frintn v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2636 try std.testing.expectFmt("frintn h10, h11", "{f}", .{(try as.nextInstruction()).?});
2637 try std.testing.expectFmt("frintn s12, s13", "{f}", .{(try as.nextInstruction()).?});
2638 try std.testing.expectFmt("frintn d14, d15", "{f}", .{(try as.nextInstruction()).?});
2639
2640 try std.testing.expectFmt("frintm v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2641 try std.testing.expectFmt("frintm v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2642 try std.testing.expectFmt("frintm v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2643 try std.testing.expectFmt("frintm v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2644 try std.testing.expectFmt("frintm v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2645 try std.testing.expectFmt("frintm h10, h11", "{f}", .{(try as.nextInstruction()).?});
2646 try std.testing.expectFmt("frintm s12, s13", "{f}", .{(try as.nextInstruction()).?});
2647 try std.testing.expectFmt("frintm d14, d15", "{f}", .{(try as.nextInstruction()).?});
2648
2649 try std.testing.expectFmt("fcvtns h0, h1", "{f}", .{(try as.nextInstruction()).?});
2650 try std.testing.expectFmt("fcvtns s2, s3", "{f}", .{(try as.nextInstruction()).?});
2651 try std.testing.expectFmt("fcvtns d4, d5", "{f}", .{(try as.nextInstruction()).?});
2652 try std.testing.expectFmt("fcvtns v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2653 try std.testing.expectFmt("fcvtns v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2654 try std.testing.expectFmt("fcvtns v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2655 try std.testing.expectFmt("fcvtns v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2656 try std.testing.expectFmt("fcvtns v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2657 try std.testing.expectFmt("fcvtns w16, h17", "{f}", .{(try as.nextInstruction()).?});
2658 try std.testing.expectFmt("fcvtns x18, h19", "{f}", .{(try as.nextInstruction()).?});
2659 try std.testing.expectFmt("fcvtns w20, s21", "{f}", .{(try as.nextInstruction()).?});
2660 try std.testing.expectFmt("fcvtns x22, s23", "{f}", .{(try as.nextInstruction()).?});
2661 try std.testing.expectFmt("fcvtns w24, d25", "{f}", .{(try as.nextInstruction()).?});
2662 try std.testing.expectFmt("fcvtns x26, d27", "{f}", .{(try as.nextInstruction()).?});
2663
2664 try std.testing.expectFmt("fcvtms h0, h1", "{f}", .{(try as.nextInstruction()).?});
2665 try std.testing.expectFmt("fcvtms s2, s3", "{f}", .{(try as.nextInstruction()).?});
2666 try std.testing.expectFmt("fcvtms d4, d5", "{f}", .{(try as.nextInstruction()).?});
2667 try std.testing.expectFmt("fcvtms v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2668 try std.testing.expectFmt("fcvtms v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2669 try std.testing.expectFmt("fcvtms v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2670 try std.testing.expectFmt("fcvtms v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2671 try std.testing.expectFmt("fcvtms v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2672 try std.testing.expectFmt("fcvtms w16, h17", "{f}", .{(try as.nextInstruction()).?});
2673 try std.testing.expectFmt("fcvtms x18, h19", "{f}", .{(try as.nextInstruction()).?});
2674 try std.testing.expectFmt("fcvtms w20, s21", "{f}", .{(try as.nextInstruction()).?});
2675 try std.testing.expectFmt("fcvtms x22, s23", "{f}", .{(try as.nextInstruction()).?});
2676 try std.testing.expectFmt("fcvtms w24, d25", "{f}", .{(try as.nextInstruction()).?});
2677 try std.testing.expectFmt("fcvtms x26, d27", "{f}", .{(try as.nextInstruction()).?});
2678
2679 try std.testing.expectFmt("fcvtas h0, h1", "{f}", .{(try as.nextInstruction()).?});
2680 try std.testing.expectFmt("fcvtas s2, s3", "{f}", .{(try as.nextInstruction()).?});
2681 try std.testing.expectFmt("fcvtas d4, d5", "{f}", .{(try as.nextInstruction()).?});
2682 try std.testing.expectFmt("fcvtas v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2683 try std.testing.expectFmt("fcvtas v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2684 try std.testing.expectFmt("fcvtas v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2685 try std.testing.expectFmt("fcvtas v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2686 try std.testing.expectFmt("fcvtas v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2687 try std.testing.expectFmt("fcvtas w16, h17", "{f}", .{(try as.nextInstruction()).?});
2688 try std.testing.expectFmt("fcvtas x18, h19", "{f}", .{(try as.nextInstruction()).?});
2689 try std.testing.expectFmt("fcvtas w20, s21", "{f}", .{(try as.nextInstruction()).?});
2690 try std.testing.expectFmt("fcvtas x22, s23", "{f}", .{(try as.nextInstruction()).?});
2691 try std.testing.expectFmt("fcvtas w24, d25", "{f}", .{(try as.nextInstruction()).?});
2692 try std.testing.expectFmt("fcvtas x26, d27", "{f}", .{(try as.nextInstruction()).?});
2693
2694 try std.testing.expectFmt("scvtf h0, h1", "{f}", .{(try as.nextInstruction()).?});
2695 try std.testing.expectFmt("scvtf s2, s3", "{f}", .{(try as.nextInstruction()).?});
2696 try std.testing.expectFmt("scvtf d4, d5", "{f}", .{(try as.nextInstruction()).?});
2697 try std.testing.expectFmt("scvtf v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2698 try std.testing.expectFmt("scvtf v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2699 try std.testing.expectFmt("scvtf v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2700 try std.testing.expectFmt("scvtf v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2701 try std.testing.expectFmt("scvtf v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2702 try std.testing.expectFmt("scvtf h16, w17", "{f}", .{(try as.nextInstruction()).?});
2703 try std.testing.expectFmt("scvtf h18, x19", "{f}", .{(try as.nextInstruction()).?});
2704 try std.testing.expectFmt("scvtf s20, w21", "{f}", .{(try as.nextInstruction()).?});
2705 try std.testing.expectFmt("scvtf s22, x23", "{f}", .{(try as.nextInstruction()).?});
2706 try std.testing.expectFmt("scvtf d24, w25", "{f}", .{(try as.nextInstruction()).?});
2707 try std.testing.expectFmt("scvtf d26, x27", "{f}", .{(try as.nextInstruction()).?});
2708
2709 try std.testing.expectFmt("fcmgt h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2710 try std.testing.expectFmt("fcmgt s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2711 try std.testing.expectFmt("fcmgt d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2712 try std.testing.expectFmt("fcmgt v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2713 try std.testing.expectFmt("fcmgt v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2714 try std.testing.expectFmt("fcmgt v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2715 try std.testing.expectFmt("fcmgt v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2716 try std.testing.expectFmt("fcmgt v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2717
2718 try std.testing.expectFmt("fcmeq h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2719 try std.testing.expectFmt("fcmeq s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2720 try std.testing.expectFmt("fcmeq d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2721 try std.testing.expectFmt("fcmeq v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2722 try std.testing.expectFmt("fcmeq v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2723 try std.testing.expectFmt("fcmeq v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2724 try std.testing.expectFmt("fcmeq v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2725 try std.testing.expectFmt("fcmeq v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2726
2727 try std.testing.expectFmt("fcmlt h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2728 try std.testing.expectFmt("fcmlt s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2729 try std.testing.expectFmt("fcmlt d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2730 try std.testing.expectFmt("fcmlt v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2731 try std.testing.expectFmt("fcmlt v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2732 try std.testing.expectFmt("fcmlt v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2733 try std.testing.expectFmt("fcmlt v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2734 try std.testing.expectFmt("fcmlt v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2735
2736 try std.testing.expectFmt("frintp v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2737 try std.testing.expectFmt("frintp v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2738 try std.testing.expectFmt("frintp v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2739 try std.testing.expectFmt("frintp v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2740 try std.testing.expectFmt("frintp v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2741 try std.testing.expectFmt("frintp h10, h11", "{f}", .{(try as.nextInstruction()).?});
2742 try std.testing.expectFmt("frintp s12, s13", "{f}", .{(try as.nextInstruction()).?});
2743 try std.testing.expectFmt("frintp d14, d15", "{f}", .{(try as.nextInstruction()).?});
2744
2745 try std.testing.expectFmt("frintz v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2746 try std.testing.expectFmt("frintz v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2747 try std.testing.expectFmt("frintz v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2748 try std.testing.expectFmt("frintz v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2749 try std.testing.expectFmt("frintz v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2750 try std.testing.expectFmt("frintz h10, h11", "{f}", .{(try as.nextInstruction()).?});
2751 try std.testing.expectFmt("frintz s12, s13", "{f}", .{(try as.nextInstruction()).?});
2752 try std.testing.expectFmt("frintz d14, d15", "{f}", .{(try as.nextInstruction()).?});
2753
2754 try std.testing.expectFmt("fcvtps h0, h1", "{f}", .{(try as.nextInstruction()).?});
2755 try std.testing.expectFmt("fcvtps s2, s3", "{f}", .{(try as.nextInstruction()).?});
2756 try std.testing.expectFmt("fcvtps d4, d5", "{f}", .{(try as.nextInstruction()).?});
2757 try std.testing.expectFmt("fcvtps v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2758 try std.testing.expectFmt("fcvtps v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2759 try std.testing.expectFmt("fcvtps v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2760 try std.testing.expectFmt("fcvtps v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2761 try std.testing.expectFmt("fcvtps v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2762 try std.testing.expectFmt("fcvtps w16, h17", "{f}", .{(try as.nextInstruction()).?});
2763 try std.testing.expectFmt("fcvtps x18, h19", "{f}", .{(try as.nextInstruction()).?});
2764 try std.testing.expectFmt("fcvtps w20, s21", "{f}", .{(try as.nextInstruction()).?});
2765 try std.testing.expectFmt("fcvtps x22, s23", "{f}", .{(try as.nextInstruction()).?});
2766 try std.testing.expectFmt("fcvtps w24, d25", "{f}", .{(try as.nextInstruction()).?});
2767 try std.testing.expectFmt("fcvtps x26, d27", "{f}", .{(try as.nextInstruction()).?});
2768
2769 try std.testing.expectFmt("fcvtzs h0, h1", "{f}", .{(try as.nextInstruction()).?});
2770 try std.testing.expectFmt("fcvtzs s2, s3", "{f}", .{(try as.nextInstruction()).?});
2771 try std.testing.expectFmt("fcvtzs d4, d5", "{f}", .{(try as.nextInstruction()).?});
2772 try std.testing.expectFmt("fcvtzs v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2773 try std.testing.expectFmt("fcvtzs v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2774 try std.testing.expectFmt("fcvtzs v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2775 try std.testing.expectFmt("fcvtzs v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2776 try std.testing.expectFmt("fcvtzs v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2777 try std.testing.expectFmt("fcvtzs w16, h17", "{f}", .{(try as.nextInstruction()).?});
2778 try std.testing.expectFmt("fcvtzs x18, h19", "{f}", .{(try as.nextInstruction()).?});
2779 try std.testing.expectFmt("fcvtzs w20, s21", "{f}", .{(try as.nextInstruction()).?});
2780 try std.testing.expectFmt("fcvtzs x22, s23", "{f}", .{(try as.nextInstruction()).?});
2781 try std.testing.expectFmt("fcvtzs w24, d25", "{f}", .{(try as.nextInstruction()).?});
2782 try std.testing.expectFmt("fcvtzs x26, d27", "{f}", .{(try as.nextInstruction()).?});
2783
2784 try std.testing.expectFmt("cmge d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2785 try std.testing.expectFmt("cmge v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2786 try std.testing.expectFmt("cmge v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2787 try std.testing.expectFmt("cmge v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2788 try std.testing.expectFmt("cmge v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2789 try std.testing.expectFmt("cmge v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2790 try std.testing.expectFmt("cmge v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2791 try std.testing.expectFmt("cmge v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2792
2793 try std.testing.expectFmt("cmle d0, d1, #0", "{f}", .{(try as.nextInstruction()).?});
2794 try std.testing.expectFmt("cmle v2.8b, v3.8b, #0", "{f}", .{(try as.nextInstruction()).?});
2795 try std.testing.expectFmt("cmle v4.16b, v5.16b, #0", "{f}", .{(try as.nextInstruction()).?});
2796 try std.testing.expectFmt("cmle v6.4h, v7.4h, #0", "{f}", .{(try as.nextInstruction()).?});
2797 try std.testing.expectFmt("cmle v8.8h, v9.8h, #0", "{f}", .{(try as.nextInstruction()).?});
2798 try std.testing.expectFmt("cmle v10.2s, v11.2s, #0", "{f}", .{(try as.nextInstruction()).?});
2799 try std.testing.expectFmt("cmle v12.4s, v13.4s, #0", "{f}", .{(try as.nextInstruction()).?});
2800 try std.testing.expectFmt("cmle v14.2d, v15.2d, #0", "{f}", .{(try as.nextInstruction()).?});
2801
2802 try std.testing.expectFmt("neg d0, d1", "{f}", .{(try as.nextInstruction()).?});
2803 try std.testing.expectFmt("neg v2.8b, v3.8b", "{f}", .{(try as.nextInstruction()).?});
2804 try std.testing.expectFmt("neg v4.16b, v5.16b", "{f}", .{(try as.nextInstruction()).?});
2805 try std.testing.expectFmt("neg v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2806 try std.testing.expectFmt("neg v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2807 try std.testing.expectFmt("neg v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2808 try std.testing.expectFmt("neg v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2809 try std.testing.expectFmt("neg v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2810
2811 try std.testing.expectFmt("fcvtnu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2812 try std.testing.expectFmt("fcvtnu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2813 try std.testing.expectFmt("fcvtnu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2814 try std.testing.expectFmt("fcvtnu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2815 try std.testing.expectFmt("fcvtnu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2816 try std.testing.expectFmt("fcvtnu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2817 try std.testing.expectFmt("fcvtnu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2818 try std.testing.expectFmt("fcvtnu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2819 try std.testing.expectFmt("fcvtnu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2820 try std.testing.expectFmt("fcvtnu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2821 try std.testing.expectFmt("fcvtnu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2822 try std.testing.expectFmt("fcvtnu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2823 try std.testing.expectFmt("fcvtnu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2824 try std.testing.expectFmt("fcvtnu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2825
2826 try std.testing.expectFmt("fcvtmu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2827 try std.testing.expectFmt("fcvtmu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2828 try std.testing.expectFmt("fcvtmu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2829 try std.testing.expectFmt("fcvtmu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2830 try std.testing.expectFmt("fcvtmu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2831 try std.testing.expectFmt("fcvtmu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2832 try std.testing.expectFmt("fcvtmu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2833 try std.testing.expectFmt("fcvtmu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2834 try std.testing.expectFmt("fcvtmu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2835 try std.testing.expectFmt("fcvtmu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2836 try std.testing.expectFmt("fcvtmu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2837 try std.testing.expectFmt("fcvtmu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2838 try std.testing.expectFmt("fcvtmu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2839 try std.testing.expectFmt("fcvtmu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2840
2841 try std.testing.expectFmt("fcvtau h0, h1", "{f}", .{(try as.nextInstruction()).?});
2842 try std.testing.expectFmt("fcvtau s2, s3", "{f}", .{(try as.nextInstruction()).?});
2843 try std.testing.expectFmt("fcvtau d4, d5", "{f}", .{(try as.nextInstruction()).?});
2844 try std.testing.expectFmt("fcvtau v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2845 try std.testing.expectFmt("fcvtau v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2846 try std.testing.expectFmt("fcvtau v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2847 try std.testing.expectFmt("fcvtau v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2848 try std.testing.expectFmt("fcvtau v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2849 try std.testing.expectFmt("fcvtau w16, h17", "{f}", .{(try as.nextInstruction()).?});
2850 try std.testing.expectFmt("fcvtau x18, h19", "{f}", .{(try as.nextInstruction()).?});
2851 try std.testing.expectFmt("fcvtau w20, s21", "{f}", .{(try as.nextInstruction()).?});
2852 try std.testing.expectFmt("fcvtau x22, s23", "{f}", .{(try as.nextInstruction()).?});
2853 try std.testing.expectFmt("fcvtau w24, d25", "{f}", .{(try as.nextInstruction()).?});
2854 try std.testing.expectFmt("fcvtau x26, d27", "{f}", .{(try as.nextInstruction()).?});
2855
2856 try std.testing.expectFmt("ucvtf h0, h1", "{f}", .{(try as.nextInstruction()).?});
2857 try std.testing.expectFmt("ucvtf s2, s3", "{f}", .{(try as.nextInstruction()).?});
2858 try std.testing.expectFmt("ucvtf d4, d5", "{f}", .{(try as.nextInstruction()).?});
2859 try std.testing.expectFmt("ucvtf v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2860 try std.testing.expectFmt("ucvtf v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2861 try std.testing.expectFmt("ucvtf v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2862 try std.testing.expectFmt("ucvtf v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2863 try std.testing.expectFmt("ucvtf v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2864 try std.testing.expectFmt("ucvtf h16, w17", "{f}", .{(try as.nextInstruction()).?});
2865 try std.testing.expectFmt("ucvtf h18, x19", "{f}", .{(try as.nextInstruction()).?});
2866 try std.testing.expectFmt("ucvtf s20, w21", "{f}", .{(try as.nextInstruction()).?});
2867 try std.testing.expectFmt("ucvtf s22, x23", "{f}", .{(try as.nextInstruction()).?});
2868 try std.testing.expectFmt("ucvtf d24, w25", "{f}", .{(try as.nextInstruction()).?});
2869 try std.testing.expectFmt("ucvtf d26, x27", "{f}", .{(try as.nextInstruction()).?});
2870
2871 try std.testing.expectFmt("not v0.8b, v1.8b", "{f}", .{(try as.nextInstruction()).?});
2872 try std.testing.expectFmt("not v2.16b, v3.16b", "{f}", .{(try as.nextInstruction()).?});
2873
2874 try std.testing.expectFmt("fcmge h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2875 try std.testing.expectFmt("fcmge s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2876 try std.testing.expectFmt("fcmge d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2877 try std.testing.expectFmt("fcmge v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2878 try std.testing.expectFmt("fcmge v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2879 try std.testing.expectFmt("fcmge v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2880 try std.testing.expectFmt("fcmge v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2881 try std.testing.expectFmt("fcmge v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2882
2883 try std.testing.expectFmt("fcmle h0, h1, #0.0", "{f}", .{(try as.nextInstruction()).?});
2884 try std.testing.expectFmt("fcmle s2, s3, #0.0", "{f}", .{(try as.nextInstruction()).?});
2885 try std.testing.expectFmt("fcmle d4, d5, #0.0", "{f}", .{(try as.nextInstruction()).?});
2886 try std.testing.expectFmt("fcmle v6.4h, v7.4h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2887 try std.testing.expectFmt("fcmle v8.8h, v9.8h, #0.0", "{f}", .{(try as.nextInstruction()).?});
2888 try std.testing.expectFmt("fcmle v10.2s, v11.2s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2889 try std.testing.expectFmt("fcmle v12.4s, v13.4s, #0.0", "{f}", .{(try as.nextInstruction()).?});
2890 try std.testing.expectFmt("fcmle v14.2d, v15.2d, #0.0", "{f}", .{(try as.nextInstruction()).?});
2891
2892 try std.testing.expectFmt("frinti v0.4h, v1.4h", "{f}", .{(try as.nextInstruction()).?});
2893 try std.testing.expectFmt("frinti v2.8h, v3.8h", "{f}", .{(try as.nextInstruction()).?});
2894 try std.testing.expectFmt("frinti v4.2s, v5.2s", "{f}", .{(try as.nextInstruction()).?});
2895 try std.testing.expectFmt("frinti v6.4s, v7.4s", "{f}", .{(try as.nextInstruction()).?});
2896 try std.testing.expectFmt("frinti v8.2d, v9.2d", "{f}", .{(try as.nextInstruction()).?});
2897 try std.testing.expectFmt("frinti h10, h11", "{f}", .{(try as.nextInstruction()).?});
2898 try std.testing.expectFmt("frinti s12, s13", "{f}", .{(try as.nextInstruction()).?});
2899 try std.testing.expectFmt("frinti d14, d15", "{f}", .{(try as.nextInstruction()).?});
2900
2901 try std.testing.expectFmt("fcvtpu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2902 try std.testing.expectFmt("fcvtpu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2903 try std.testing.expectFmt("fcvtpu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2904 try std.testing.expectFmt("fcvtpu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2905 try std.testing.expectFmt("fcvtpu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2906 try std.testing.expectFmt("fcvtpu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2907 try std.testing.expectFmt("fcvtpu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2908 try std.testing.expectFmt("fcvtpu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2909 try std.testing.expectFmt("fcvtpu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2910 try std.testing.expectFmt("fcvtpu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2911 try std.testing.expectFmt("fcvtpu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2912 try std.testing.expectFmt("fcvtpu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2913 try std.testing.expectFmt("fcvtpu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2914 try std.testing.expectFmt("fcvtpu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2915
2916 try std.testing.expectFmt("fcvtzu h0, h1", "{f}", .{(try as.nextInstruction()).?});
2917 try std.testing.expectFmt("fcvtzu s2, s3", "{f}", .{(try as.nextInstruction()).?});
2918 try std.testing.expectFmt("fcvtzu d4, d5", "{f}", .{(try as.nextInstruction()).?});
2919 try std.testing.expectFmt("fcvtzu v6.4h, v7.4h", "{f}", .{(try as.nextInstruction()).?});
2920 try std.testing.expectFmt("fcvtzu v8.8h, v9.8h", "{f}", .{(try as.nextInstruction()).?});
2921 try std.testing.expectFmt("fcvtzu v10.2s, v11.2s", "{f}", .{(try as.nextInstruction()).?});
2922 try std.testing.expectFmt("fcvtzu v12.4s, v13.4s", "{f}", .{(try as.nextInstruction()).?});
2923 try std.testing.expectFmt("fcvtzu v14.2d, v15.2d", "{f}", .{(try as.nextInstruction()).?});
2924 try std.testing.expectFmt("fcvtzu w16, h17", "{f}", .{(try as.nextInstruction()).?});
2925 try std.testing.expectFmt("fcvtzu x18, h19", "{f}", .{(try as.nextInstruction()).?});
2926 try std.testing.expectFmt("fcvtzu w20, s21", "{f}", .{(try as.nextInstruction()).?});
2927 try std.testing.expectFmt("fcvtzu x22, s23", "{f}", .{(try as.nextInstruction()).?});
2928 try std.testing.expectFmt("fcvtzu w24, d25", "{f}", .{(try as.nextInstruction()).?});
2929 try std.testing.expectFmt("fcvtzu x26, d27", "{f}", .{(try as.nextInstruction()).?});
2930
2931 try std.testing.expect(null == try as.nextInstruction());
2932}
16782933
1679const aarch64 = @import("../aarch64.zig");2934const aarch64 = @import("../aarch64.zig");
1680const Assemble = @This();2935const Assemble = @This();
src/codegen/aarch64/Disassemble.zig+527-96
...@@ -3,9 +3,18 @@ mnemonic_operands_separator: []const u8 = " ",...@@ -3,9 +3,18 @@ mnemonic_operands_separator: []const u8 = " ",
3operands_separator: []const u8 = ", ",3operands_separator: []const u8 = ", ",
4enable_aliases: bool = true,4enable_aliases: bool = true,
55
6pub const Case = enum { lower, upper };6pub const Case = enum {
7 lower,
8 upper,
9 pub fn convert(case: Case, c: u8) u8 {
10 return switch (case) {
11 .lower => std.ascii.toLower(c),
12 .upper => std.ascii.toUpper(c),
13 };
14 }
15};
716
8pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void {17pub fn printInstruction(dis: Disassemble, inst: aarch64.encoding.Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void {
9 unallocated: switch (inst.decode()) {18 unallocated: switch (inst.decode()) {
10 .unallocated => break :unallocated,19 .unallocated => break :unallocated,
11 .reserved => |reserved| switch (reserved.decode()) {20 .reserved => |reserved| switch (reserved.decode()) {
...@@ -23,13 +32,13 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -23,13 +32,13 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
23 .pc_relative_addressing => |pc_relative_addressing| {32 .pc_relative_addressing => |pc_relative_addressing| {
24 const group = pc_relative_addressing.group;33 const group = pc_relative_addressing.group;
25 const imm = (@as(i33, group.immhi) << 2 | @as(i33, group.immlo) << 0) + @as(i33, switch (group.op) {34 const imm = (@as(i33, group.immhi) << 2 | @as(i33, group.immlo) << 0) + @as(i33, switch (group.op) {
26 .adr => Instruction.size,35 .adr => aarch64.encoding.Instruction.size,
27 .adrp => 0,36 .adrp => 0,
28 });37 });
29 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{38 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{
30 fmtCase(group.op, dis.case),39 fmtCase(group.op, dis.case),
31 dis.mnemonic_operands_separator,40 dis.mnemonic_operands_separator,
32 group.Rd.decodeInteger(.doubleword, .{}).fmtCase(dis.case),41 group.Rd.decode(.{}).x().fmtCase(dis.case),
33 dis.operands_separator,42 dis.operands_separator,
34 @as(u8, if (imm < 0) '-' else '+'),43 @as(u8, if (imm < 0) '-' else '+'),
35 switch (group.op) {44 switch (group.op) {
...@@ -45,8 +54,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -45,8 +54,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
45 const sf = group.sf;54 const sf = group.sf;
46 const sh = group.sh;55 const sh = group.sh;
47 const imm12 = group.imm12;56 const imm12 = group.imm12;
48 const Rn = group.Rn.decodeInteger(sf, .{ .sp = true });57 const Rn = group.Rn.decode(.{ .sp = true }).general(sf);
49 const Rd = group.Rd.decodeInteger(sf, .{ .sp = !S });58 const Rd = group.Rd.decode(.{ .sp = !S }).general(sf);
50 const elide_shift = sh == .@"0";59 const elide_shift = sh == .@"0";
51 if (dis.enable_aliases and op == .add and S == false and elide_shift and imm12 == 0 and60 if (dis.enable_aliases and op == .add and S == false and elide_shift and imm12 == 0 and
52 (Rn.alias == .sp or Rd.alias == .sp)) try writer.print("{f}{s}{f}{s}{f}", .{61 (Rn.alias == .sp or Rd.alias == .sp)) try writer.print("{f}{s}{f}{s}{f}", .{
...@@ -82,8 +91,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -82,8 +91,8 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
82 .word => @as(i32, @bitCast(@as(u32, @intCast(decoded_imm)))),91 .word => @as(i32, @bitCast(@as(u32, @intCast(decoded_imm)))),
83 .doubleword => @as(i64, @bitCast(decoded_imm)),92 .doubleword => @as(i64, @bitCast(decoded_imm)),
84 };93 };
85 const Rn = group.Rn.decodeInteger(sf, .{});94 const Rn = group.Rn.decode(.{}).general(sf);
86 const Rd = group.Rd.decodeInteger(sf, .{ .sp = decoded != .ands });95 const Rd = group.Rd.decode(.{ .sp = decoded != .ands }).general(sf);
87 return if (dis.enable_aliases and decoded == .orr and Rn.alias == .zr and !group.imm.moveWidePreferred(sf)) writer.print("{f}{s}{f}{s}#{s}0x{x}", .{96 return if (dis.enable_aliases and decoded == .orr and Rn.alias == .zr and !group.imm.moveWidePreferred(sf)) writer.print("{f}{s}{f}{s}#{s}0x{x}", .{
88 fmtCase(.mov, dis.case),97 fmtCase(.mov, dis.case),
89 dis.mnemonic_operands_separator,98 dis.mnemonic_operands_separator,
...@@ -115,7 +124,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -115,7 +124,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
115 const sf = group.sf;124 const sf = group.sf;
116 const hw = group.hw;125 const hw = group.hw;
117 const imm16 = group.imm16;126 const imm16 = group.imm16;
118 const Rd = group.Rd.decodeInteger(sf, .{});127 const Rd = group.Rd.decode(.{}).general(sf);
119 const elide_shift = hw == .@"0";128 const elide_shift = hw == .@"0";
120 if (dis.enable_aliases and switch (decoded) {129 if (dis.enable_aliases and switch (decoded) {
121 .unallocated => unreachable,130 .unallocated => unreachable,
...@@ -166,9 +175,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -166,9 +175,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
166 return writer.print("{f}{s}{f}{s}{f}{s}#{d}{s}#{d}", .{175 return writer.print("{f}{s}{f}{s}{f}{s}#{d}{s}#{d}", .{
167 fmtCase(decoded, dis.case),176 fmtCase(decoded, dis.case),
168 dis.mnemonic_operands_separator,177 dis.mnemonic_operands_separator,
169 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),178 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
170 dis.operands_separator,179 dis.operands_separator,
171 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),180 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
172 dis.operands_separator,181 dis.operands_separator,
173 group.imm.immr,182 group.imm.immr,
174 dis.operands_separator,183 dis.operands_separator,
...@@ -183,11 +192,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -183,11 +192,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
183 return writer.print("{f}{s}{f}{s}{f}{s}{f}{s}#{d}", .{192 return writer.print("{f}{s}{f}{s}{f}{s}{f}{s}#{d}", .{
184 fmtCase(decoded, dis.case),193 fmtCase(decoded, dis.case),
185 dis.mnemonic_operands_separator,194 dis.mnemonic_operands_separator,
186 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),195 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
187 dis.operands_separator,196 dis.operands_separator,
188 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),197 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
189 dis.operands_separator,198 dis.operands_separator,
190 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),199 group.Rm.decode(.{}).general(sf).fmtCase(dis.case),
191 dis.operands_separator,200 dis.operands_separator,
192 group.imms,201 group.imms,
193 });202 });
...@@ -248,7 +257,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -248,7 +257,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
248 const decoded = unconditional_branch_register.decode();257 const decoded = unconditional_branch_register.decode();
249 if (decoded == .unallocated) break :unallocated;258 if (decoded == .unallocated) break :unallocated;
250 const group = unconditional_branch_register.group;259 const group = unconditional_branch_register.group;
251 const Rn = group.Rn.decodeInteger(.doubleword, .{});260 const Rn = group.Rn.decode(.{}).x();
252 try writer.print("{f}", .{fmtCase(decoded, dis.case)});261 try writer.print("{f}", .{fmtCase(decoded, dis.case)});
253 return if (decoded != .ret or Rn.alias != .r30) try writer.print("{s}{f}", .{262 return if (decoded != .ret or Rn.alias != .r30) try writer.print("{s}{f}", .{
254 dis.mnemonic_operands_separator,263 dis.mnemonic_operands_separator,
...@@ -271,7 +280,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -271,7 +280,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
271 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{280 return writer.print("{f}{s}{f}{s}.{c}0x{x}", .{
272 fmtCase(group.op, dis.case),281 fmtCase(group.op, dis.case),
273 dis.mnemonic_operands_separator,282 dis.mnemonic_operands_separator,
274 group.Rt.decodeInteger(group.sf, .{}).fmtCase(dis.case),283 group.Rt.decode(.{}).general(group.sf).fmtCase(dis.case),
275 dis.operands_separator,284 dis.operands_separator,
276 @as(u8, if (imm < 0) '-' else '+'),285 @as(u8, if (imm < 0) '-' else '+'),
277 @abs(imm) << 2,286 @abs(imm) << 2,
...@@ -283,7 +292,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -283,7 +292,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
283 return writer.print("{f}{s}{f}{s}#0x{d}{s}.{c}0x{x}", .{292 return writer.print("{f}{s}{f}{s}#0x{d}{s}.{c}0x{x}", .{
284 fmtCase(group.op, dis.case),293 fmtCase(group.op, dis.case),
285 dis.mnemonic_operands_separator,294 dis.mnemonic_operands_separator,
286 group.Rt.decodeInteger(@enumFromInt(group.b5), .{}).fmtCase(dis.case),295 group.Rt.decode(.{}).general(@enumFromInt(group.b5)).fmtCase(dis.case),
287 dis.operands_separator,296 dis.operands_separator,
288 @as(u6, group.b5) << 5 |297 @as(u6, group.b5) << 5 |
289 @as(u6, group.b40) << 0,298 @as(u6, group.b40) << 0,
...@@ -303,15 +312,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -303,15 +312,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
303 const decoded = integer.decode();312 const decoded = integer.decode();
304 if (decoded == .unallocated) break :unallocated;313 if (decoded == .unallocated) break :unallocated;
305 const group = integer.group;314 const group = integer.group;
306 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);315 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
307 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{316 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
308 fmtCase(decoded, dis.case),317 fmtCase(decoded, dis.case),
309 dis.mnemonic_operands_separator,318 dis.mnemonic_operands_separator,
310 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),319 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
311 dis.operands_separator,320 dis.operands_separator,
312 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),321 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
313 dis.operands_separator,322 dis.operands_separator,
314 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),323 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
315 dis.operands_separator,324 dis.operands_separator,
316 if (group.imm7 < 0) "-" else "",325 if (group.imm7 < 0) "-" else "",
317 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),326 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),
...@@ -325,11 +334,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -325,11 +334,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
325 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{334 return writer.print("{f}{s}{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
326 fmtCase(decoded, dis.case),335 fmtCase(decoded, dis.case),
327 dis.mnemonic_operands_separator,336 dis.mnemonic_operands_separator,
328 group.Rt.decodeVector(vs).fmtCase(dis.case),337 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
329 dis.operands_separator,338 dis.operands_separator,
330 group.Rt2.decodeVector(vs).fmtCase(dis.case),339 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
331 dis.operands_separator,340 dis.operands_separator,
332 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),341 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
333 dis.operands_separator,342 dis.operands_separator,
334 if (group.imm7 < 0) "-" else "",343 if (group.imm7 < 0) "-" else "",
335 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),344 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),
...@@ -341,15 +350,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -341,15 +350,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
341 const decoded = integer.decode();350 const decoded = integer.decode();
342 if (decoded == .unallocated) break :unallocated;351 if (decoded == .unallocated) break :unallocated;
343 const group = integer.group;352 const group = integer.group;
344 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);353 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
345 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{354 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{
346 fmtCase(decoded, dis.case),355 fmtCase(decoded, dis.case),
347 dis.mnemonic_operands_separator,356 dis.mnemonic_operands_separator,
348 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),357 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
349 dis.operands_separator,358 dis.operands_separator,
350 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),359 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
351 dis.operands_separator,360 dis.operands_separator,
352 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),361 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
353 });362 });
354 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{363 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{
355 dis.operands_separator,364 dis.operands_separator,
...@@ -366,11 +375,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -366,11 +375,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
366 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{375 try writer.print("{f}{s}{f}{s}{f}{s}[{f}", .{
367 fmtCase(decoded, dis.case),376 fmtCase(decoded, dis.case),
368 dis.mnemonic_operands_separator,377 dis.mnemonic_operands_separator,
369 group.Rt.decodeVector(vs).fmtCase(dis.case),378 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
370 dis.operands_separator,379 dis.operands_separator,
371 group.Rt2.decodeVector(vs).fmtCase(dis.case),380 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
372 dis.operands_separator,381 dis.operands_separator,
373 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),382 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
374 });383 });
375 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{384 if (group.imm7 != 0) try writer.print("{s}#{s}0x{x}", .{
376 dis.operands_separator,385 dis.operands_separator,
...@@ -385,15 +394,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -385,15 +394,15 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
385 const decoded = integer.decode();394 const decoded = integer.decode();
386 if (decoded == .unallocated) break :unallocated;395 if (decoded == .unallocated) break :unallocated;
387 const group = integer.group;396 const group = integer.group;
388 const sf: aarch64.encoding.Register.IntegerSize = @enumFromInt(group.opc >> 1);397 const sf: aarch64.encoding.Register.GeneralSize = @enumFromInt(group.opc >> 1);
389 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{398 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
390 fmtCase(decoded, dis.case),399 fmtCase(decoded, dis.case),
391 dis.mnemonic_operands_separator,400 dis.mnemonic_operands_separator,
392 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),401 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
393 dis.operands_separator,402 dis.operands_separator,
394 group.Rt2.decodeInteger(sf, .{}).fmtCase(dis.case),403 group.Rt2.decode(.{}).general(sf).fmtCase(dis.case),
395 dis.operands_separator,404 dis.operands_separator,
396 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),405 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
397 dis.operands_separator,406 dis.operands_separator,
398 if (group.imm7 < 0) "-" else "",407 if (group.imm7 < 0) "-" else "",
399 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),408 @as(u10, @abs(group.imm7)) << (@as(u2, 2) + @intFromEnum(sf)),
...@@ -407,11 +416,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -407,11 +416,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
407 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{416 return writer.print("{f}{s}{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
408 fmtCase(decoded, dis.case),417 fmtCase(decoded, dis.case),
409 dis.mnemonic_operands_separator,418 dis.mnemonic_operands_separator,
410 group.Rt.decodeVector(vs).fmtCase(dis.case),419 group.Rt.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
411 dis.operands_separator,420 dis.operands_separator,
412 group.Rt2.decodeVector(vs).fmtCase(dis.case),421 group.Rt2.decode(.{ .V = true }).scalar(vs).fmtCase(dis.case),
413 dis.operands_separator,422 dis.operands_separator,
414 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),423 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
415 dis.operands_separator,424 dis.operands_separator,
416 if (group.imm7 < 0) "-" else "",425 if (group.imm7 < 0) "-" else "",
417 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),426 @as(u11, @abs(group.imm7)) << (@as(u3, 2) + @intFromEnum(vs)),
...@@ -422,7 +431,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -422,7 +431,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
422 .register_immediate_post_indexed => |register_immediate_post_indexed| switch (register_immediate_post_indexed.decode()) {431 .register_immediate_post_indexed => |register_immediate_post_indexed| switch (register_immediate_post_indexed.decode()) {
423 .integer => |integer| {432 .integer => |integer| {
424 const decoded = integer.decode();433 const decoded = integer.decode();
425 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {434 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
426 .unallocated => break :unallocated,435 .unallocated => break :unallocated,
427 .strb, .ldrb, .strh, .ldrh => .word,436 .strb, .ldrb, .strh, .ldrh => .word,
428 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {437 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
...@@ -436,9 +445,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -436,9 +445,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
436 return writer.print("{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{445 return writer.print("{f}{s}{f}{s}[{f}]{s}#{s}0x{x}", .{
437 fmtCase(decoded, dis.case),446 fmtCase(decoded, dis.case),
438 dis.mnemonic_operands_separator,447 dis.mnemonic_operands_separator,
439 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),448 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
440 dis.operands_separator,449 dis.operands_separator,
441 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),450 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
442 dis.operands_separator,451 dis.operands_separator,
443 if (group.imm9 < 0) "-" else "",452 if (group.imm9 < 0) "-" else "",
444 @abs(group.imm9),453 @abs(group.imm9),
...@@ -450,7 +459,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -450,7 +459,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
450 .register_immediate_pre_indexed => |register_immediate_pre_indexed| switch (register_immediate_pre_indexed.decode()) {459 .register_immediate_pre_indexed => |register_immediate_pre_indexed| switch (register_immediate_pre_indexed.decode()) {
451 .integer => |integer| {460 .integer => |integer| {
452 const decoded = integer.decode();461 const decoded = integer.decode();
453 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {462 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
454 .unallocated => break :unallocated,463 .unallocated => break :unallocated,
455 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {464 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
456 0b0 => .doubleword,465 0b0 => .doubleword,
...@@ -464,9 +473,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -464,9 +473,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
464 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{473 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
465 fmtCase(decoded, dis.case),474 fmtCase(decoded, dis.case),
466 dis.mnemonic_operands_separator,475 dis.mnemonic_operands_separator,
467 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),476 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
468 dis.operands_separator,477 dis.operands_separator,
469 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),478 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
470 dis.operands_separator,479 dis.operands_separator,
471 if (group.imm9 < 0) "-" else "",480 if (group.imm9 < 0) "-" else "",
472 @abs(group.imm9),481 @abs(group.imm9),
...@@ -479,9 +488,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -479,9 +488,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
479 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{488 return writer.print("{f}{s}{f}{s}[{f}{s}#{s}0x{x}]!", .{
480 fmtCase(decoded, dis.case),489 fmtCase(decoded, dis.case),
481 dis.mnemonic_operands_separator,490 dis.mnemonic_operands_separator,
482 group.Rt.decodeVector(group.opc1.decode(group.size)).fmtCase(dis.case),491 group.Rt.decode(.{ .V = true }).scalar(group.opc1.decode(group.size)).fmtCase(dis.case),
483 dis.operands_separator,492 dis.operands_separator,
484 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),493 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
485 dis.operands_separator,494 dis.operands_separator,
486 if (group.imm9 < 0) "-" else "",495 if (group.imm9 < 0) "-" else "",
487 @abs(group.imm9),496 @abs(group.imm9),
...@@ -491,7 +500,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -491,7 +500,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
491 .register_register_offset => |register_register_offset| switch (register_register_offset.decode()) {500 .register_register_offset => |register_register_offset| switch (register_register_offset.decode()) {
492 .integer => |integer| {501 .integer => |integer| {
493 const decoded = integer.decode();502 const decoded = integer.decode();
494 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {503 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
495 .unallocated, .prfm => break :unallocated,504 .unallocated, .prfm => break :unallocated,
496 .strb, .ldrb, .strh, .ldrh => .word,505 .strb, .ldrb, .strh, .ldrh => .word,
497 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {506 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
...@@ -505,11 +514,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -505,11 +514,11 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
505 try writer.print("{f}{s}{f}{s}[{f}{s}{f}", .{514 try writer.print("{f}{s}{f}{s}[{f}{s}{f}", .{
506 fmtCase(decoded, dis.case),515 fmtCase(decoded, dis.case),
507 dis.mnemonic_operands_separator,516 dis.mnemonic_operands_separator,
508 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),517 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
509 dis.operands_separator,518 dis.operands_separator,
510 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),519 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
511 dis.operands_separator,520 dis.operands_separator,
512 group.Rm.decodeInteger(group.option.sf(), .{}).fmtCase(dis.case),521 group.Rm.decode(.{}).general(group.option.sf()).fmtCase(dis.case),
513 });522 });
514 if (group.option != .lsl or group.S) {523 if (group.option != .lsl or group.S) {
515 try writer.print("{s}{f}", .{524 try writer.print("{s}{f}", .{
...@@ -527,7 +536,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -527,7 +536,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
527 .register_unsigned_immediate => |register_unsigned_immediate| switch (register_unsigned_immediate.decode()) {536 .register_unsigned_immediate => |register_unsigned_immediate| switch (register_unsigned_immediate.decode()) {
528 .integer => |integer| {537 .integer => |integer| {
529 const decoded = integer.decode();538 const decoded = integer.decode();
530 const sf: aarch64.encoding.Register.IntegerSize = switch (decoded) {539 const sf: aarch64.encoding.Register.GeneralSize = switch (decoded) {
531 .unallocated, .prfm => break :unallocated,540 .unallocated, .prfm => break :unallocated,
532 .strb, .ldrb, .strh, .ldrh => .word,541 .strb, .ldrb, .strh, .ldrh => .word,
533 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {542 inline .ldrsb, .ldrsh => |encoded| switch (encoded.opc0) {
...@@ -541,9 +550,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -541,9 +550,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
541 try writer.print("{f}{s}{f}{s}[{f}", .{550 try writer.print("{f}{s}{f}{s}[{f}", .{
542 fmtCase(decoded, dis.case),551 fmtCase(decoded, dis.case),
543 dis.mnemonic_operands_separator,552 dis.mnemonic_operands_separator,
544 group.Rt.decodeInteger(sf, .{}).fmtCase(dis.case),553 group.Rt.decode(.{}).general(sf).fmtCase(dis.case),
545 dis.operands_separator,554 dis.operands_separator,
546 group.Rn.decodeInteger(.doubleword, .{ .sp = true }).fmtCase(dis.case),555 group.Rn.decode(.{ .sp = true }).x().fmtCase(dis.case),
547 });556 });
548 if (group.imm12 > 0) try writer.print("{s}#0x{x}", .{557 if (group.imm12 > 0) try writer.print("{s}#0x{x}", .{
549 dis.operands_separator,558 dis.operands_separator,
...@@ -562,13 +571,21 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -562,13 +571,21 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
562 const group = data_processing_two_source.group;571 const group = data_processing_two_source.group;
563 const sf = group.sf;572 const sf = group.sf;
564 return writer.print("{f}{s}{f}{s}{f}{s}{f}", .{573 return writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
565 fmtCase(decoded, dis.case),574 if (dis.enable_aliases) fmtCase(@as(enum { udiv, sdiv, lsl, lsr, asr, ror }, switch (decoded) {
575 .unallocated => unreachable,
576 .udiv => .udiv,
577 .sdiv => .sdiv,
578 .lslv => .lsl,
579 .lsrv => .lsr,
580 .asrv => .asr,
581 .rorv => .ror,
582 }), dis.case) else fmtCase(decoded, dis.case),
566 dis.mnemonic_operands_separator,583 dis.mnemonic_operands_separator,
567 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),584 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
568 dis.operands_separator,585 dis.operands_separator,
569 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),586 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
570 dis.operands_separator,587 dis.operands_separator,
571 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),588 group.Rm.decode(.{}).general(sf).fmtCase(dis.case),
572 });589 });
573 },590 },
574 .data_processing_one_source => |data_processing_one_source| {591 .data_processing_one_source => |data_processing_one_source| {
...@@ -579,9 +596,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -579,9 +596,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
579 return writer.print("{f}{s}{f}{s}{f}", .{596 return writer.print("{f}{s}{f}{s}{f}", .{
580 fmtCase(decoded, dis.case),597 fmtCase(decoded, dis.case),
581 dis.mnemonic_operands_separator,598 dis.mnemonic_operands_separator,
582 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),599 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
583 dis.operands_separator,600 dis.operands_separator,
584 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),601 group.Rn.decode(.{}).general(sf).fmtCase(dis.case),
585 });602 });
586 },603 },
587 .logical_shifted_register => |logical_shifted_register| {604 .logical_shifted_register => |logical_shifted_register| {
...@@ -590,10 +607,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -590,10 +607,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
590 const group = logical_shifted_register.group;607 const group = logical_shifted_register.group;
591 const sf = group.sf;608 const sf = group.sf;
592 const shift = group.shift;609 const shift = group.shift;
593 const Rm = group.Rm.decodeInteger(sf, .{});610 const Rm = group.Rm.decode(.{}).general(sf);
594 const amount = group.imm6;611 const amount = group.imm6;
595 const Rn = group.Rn.decodeInteger(sf, .{});612 const Rn = group.Rn.decode(.{}).general(sf);
596 const Rd = group.Rd.decodeInteger(sf, .{});613 const Rd = group.Rd.decode(.{}).general(sf);
597 const elide_shift = shift == .lsl and amount == 0;614 const elide_shift = shift == .lsl and amount == 0;
598 if (dis.enable_aliases and switch (decoded) {615 if (dis.enable_aliases and switch (decoded) {
599 else => false,616 else => false,
...@@ -636,10 +653,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -636,10 +653,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
636 const group = add_subtract_shifted_register.group;653 const group = add_subtract_shifted_register.group;
637 const sf = group.sf;654 const sf = group.sf;
638 const shift = group.shift;655 const shift = group.shift;
639 const Rm = group.Rm.decodeInteger(sf, .{});656 const Rm = group.Rm.decode(.{}).general(sf);
640 const imm6 = group.imm6;657 const imm6 = group.imm6;
641 const Rn = group.Rn.decodeInteger(sf, .{});658 const Rn = group.Rn.decode(.{}).general(sf);
642 const Rd = group.Rd.decodeInteger(sf, .{});659 const Rd = group.Rd.decode(.{}).general(sf);
643 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{660 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
644 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {661 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {
645 .add => .cmn,662 .add => .cmn,
...@@ -678,9 +695,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -678,9 +695,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
678 if (decoded == .unallocated) break :unallocated;695 if (decoded == .unallocated) break :unallocated;
679 const group = add_subtract_extended_register.group;696 const group = add_subtract_extended_register.group;
680 const sf = group.sf;697 const sf = group.sf;
681 const Rm = group.Rm.decodeInteger(group.option.sf(), .{});698 const Rm = group.Rm.decode(.{}).general(group.option.sf());
682 const Rn = group.Rn.decodeInteger(sf, .{ .sp = true });699 const Rn = group.Rn.decode(.{ .sp = true }).general(sf);
683 const Rd = group.Rd.decodeInteger(sf, .{ .sp = true });700 const Rd = group.Rd.decode(.{ .sp = true }).general(sf);
684 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{701 if (dis.enable_aliases and group.S and Rd.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
685 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {702 fmtCase(@as(enum { cmn, cmp }, switch (group.op) {
686 .add => .cmn,703 .add => .cmn,
...@@ -699,7 +716,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -699,7 +716,7 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
699 dis.operands_separator,716 dis.operands_separator,
700 Rm.fmtCase(dis.case),717 Rm.fmtCase(dis.case),
701 });718 });
702 return if (group.option != @as(Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option, switch (sf) {719 return if (group.option != @as(aarch64.encoding.Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option, switch (sf) {
703 .word => .uxtw,720 .word => .uxtw,
704 .doubleword => .uxtx,721 .doubleword => .uxtx,
705 }) or group.imm3 != 0) writer.print("{s}{f} #{d}", .{722 }) or group.imm3 != 0) writer.print("{s}{f} #{d}", .{
...@@ -712,9 +729,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -712,9 +729,9 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
712 const decoded = add_subtract_with_carry.decode();729 const decoded = add_subtract_with_carry.decode();
713 const group = add_subtract_with_carry.group;730 const group = add_subtract_with_carry.group;
714 const sf = group.sf;731 const sf = group.sf;
715 const Rm = group.Rm.decodeInteger(sf, .{});732 const Rm = group.Rm.decode(.{}).general(sf);
716 const Rn = group.Rn.decodeInteger(sf, .{});733 const Rn = group.Rn.decode(.{}).general(sf);
717 const Rd = group.Rd.decodeInteger(sf, .{});734 const Rd = group.Rd.decode(.{}).general(sf);
718 return if (dis.enable_aliases and group.op == .sbc and Rn.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{735 return if (dis.enable_aliases and group.op == .sbc and Rn.alias == .zr) try writer.print("{f}{s}{f}{s}{f}", .{
719 fmtCase(@as(enum { ngc, ngcs }, switch (group.S) {736 fmtCase(@as(enum { ngc, ngcs }, switch (group.S) {
720 false => .ngc,737 false => .ngc,
...@@ -743,10 +760,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -743,10 +760,10 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
743 if (decoded == .unallocated) break :unallocated;760 if (decoded == .unallocated) break :unallocated;
744 const group = conditional_select.group;761 const group = conditional_select.group;
745 const sf = group.sf;762 const sf = group.sf;
746 const Rm = group.Rm.decodeInteger(sf, .{});763 const Rm = group.Rm.decode(.{}).general(sf);
747 const cond = group.cond;764 const cond = group.cond;
748 const Rn = group.Rn.decodeInteger(sf, .{});765 const Rn = group.Rn.decode(.{}).general(sf);
749 const Rd = group.Rd.decodeInteger(sf, .{});766 const Rd = group.Rd.decode(.{}).general(sf);
750 return if (dis.enable_aliases and group.op != group.op2 and Rm.alias == .zr and cond != .al and cond != .nv and Rn.alias == Rm.alias) writer.print("{f}{s}{f}{s}{f}", .{767 return if (dis.enable_aliases and group.op != group.op2 and Rm.alias == .zr and cond != .al and cond != .nv and Rn.alias == Rm.alias) writer.print("{f}{s}{f}{s}{f}", .{
751 fmtCase(@as(enum { cset, csetm }, switch (decoded) {768 fmtCase(@as(enum { cset, csetm }, switch (decoded) {
752 else => unreachable,769 else => unreachable,
...@@ -784,34 +801,447 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri...@@ -784,34 +801,447 @@ pub fn printInstruction(dis: Disassemble, inst: Instruction, writer: *std.Io.Wri
784 },801 },
785 .data_processing_three_source => |data_processing_three_source| {802 .data_processing_three_source => |data_processing_three_source| {
786 const decoded = data_processing_three_source.decode();803 const decoded = data_processing_three_source.decode();
787 if (decoded == .unallocated) break :unallocated;
788 const group = data_processing_three_source.group;804 const group = data_processing_three_source.group;
789 const sf = group.sf;805 const sf = group.sf;
806 const operand_sf = switch (decoded) {
807 .unallocated => break :unallocated,
808 .madd, .msub, .smulh, .umulh => sf,
809 .smaddl, .smsubl, .umaddl, .umsubl => .word,
810 };
811 const Ra = group.Ra.decode(.{}).general(sf);
812 const elide_addend = dis.enable_aliases and Ra.alias == .zr;
790 try writer.print("{f}{s}{f}{s}{f}{s}{f}", .{813 try writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
791 fmtCase(decoded, dis.case),814 if (elide_addend) fmtCase(@as(enum {
815 mul,
816 mneg,
817 smull,
818 smnegl,
819 smulh,
820 umull,
821 umnegl,
822 umulh,
823 }, switch (decoded) {
824 .unallocated => unreachable,
825 .madd => .mul,
826 .msub => .mneg,
827 .smaddl => .smull,
828 .smsubl => .smnegl,
829 .smulh => .smulh,
830 .umaddl => .umull,
831 .umsubl => .umnegl,
832 .umulh => .umulh,
833 }), dis.case) else fmtCase(decoded, dis.case),
792 dis.mnemonic_operands_separator,834 dis.mnemonic_operands_separator,
793 group.Rd.decodeInteger(sf, .{}).fmtCase(dis.case),835 group.Rd.decode(.{}).general(sf).fmtCase(dis.case),
794 dis.operands_separator,836 dis.operands_separator,
795 group.Rn.decodeInteger(sf, .{}).fmtCase(dis.case),837 group.Rn.decode(.{}).general(operand_sf).fmtCase(dis.case),
796 dis.operands_separator,838 dis.operands_separator,
797 group.Rm.decodeInteger(sf, .{}).fmtCase(dis.case),839 group.Rm.decode(.{}).general(operand_sf).fmtCase(dis.case),
798 });840 });
799 return switch (decoded) {841 return if (!elide_addend) switch (decoded) {
800 .unallocated => unreachable,842 .unallocated => unreachable,
801 .madd, .msub, .smaddl, .smsubl, .umaddl, .umsubl => writer.print("{s}{f}", .{843 .madd, .msub, .smaddl, .smsubl, .umaddl, .umsubl => writer.print("{s}{f}", .{
802 dis.operands_separator,844 dis.operands_separator,
803 group.Ra.decodeInteger(sf, .{}).fmtCase(dis.case),845 Ra.fmtCase(dis.case),
804 }),846 }),
805 .smulh, .umulh => {},847 .smulh, .umulh => {},
806 };848 };
807 },849 },
808 },850 },
809 .data_processing_vector => {},851 .data_processing_vector => |data_processing_vector| switch (data_processing_vector.decode()) {
852 .unallocated => break :unallocated,
853 .simd_scalar_copy => |simd_scalar_copy| {
854 const decoded = simd_scalar_copy.decode();
855 if (decoded == .unallocated) break :unallocated;
856 const group = simd_scalar_copy.group;
857 const elem_size = @ctz(group.imm5);
858 return writer.print("{f}{s}{f}{s}{f}", .{
859 if (dis.enable_aliases and decoded == .dup)
860 fmtCase(.mov, dis.case)
861 else
862 fmtCase(decoded, dis.case),
863 dis.mnemonic_operands_separator,
864 group.Rd.decode(.{ .V = true }).scalar(@enumFromInt(elem_size)).fmtCase(dis.case),
865 dis.operands_separator,
866 group.Rn.decode(.{ .V = true }).element(
867 @enumFromInt(elem_size),
868 @intCast(group.imm5 >> (elem_size + 1)),
869 ).fmtCase(dis.case),
870 });
871 },
872 .simd_scalar_two_register_miscellaneous_fp16 => |simd_scalar_two_register_miscellaneous_fp16| {
873 const decoded = simd_scalar_two_register_miscellaneous_fp16.decode();
874 if (decoded == .unallocated) break :unallocated;
875 const group = simd_scalar_two_register_miscellaneous_fp16.group;
876 try writer.print("{f}{s}{f}{s}{f}", .{
877 fmtCase(decoded, dis.case),
878 dis.mnemonic_operands_separator,
879 group.Rd.decode(.{ .V = true }).h().fmtCase(dis.case),
880 dis.operands_separator,
881 group.Rn.decode(.{ .V = true }).h().fmtCase(dis.case),
882 });
883 return switch (decoded) {
884 .unallocated => unreachable,
885 else => {},
886 .fcmgt,
887 .fcmeq,
888 .fcmlt,
889 .fcmge,
890 .fcmle,
891 => writer.print("{s}#0.0", .{dis.operands_separator}),
892 };
893 },
894 .simd_scalar_two_register_miscellaneous => |simd_scalar_two_register_miscellaneous| {
895 const decoded = simd_scalar_two_register_miscellaneous.decode();
896 const group = simd_scalar_two_register_miscellaneous.group;
897 const elem_size = switch (decoded) {
898 .unallocated => break :unallocated,
899 inline .fcvtns,
900 .fcvtms,
901 .fcvtas,
902 .scvtf,
903 .fcvtps,
904 .fcvtzs,
905 .fcvtxn,
906 .fcvtnu,
907 .fcvtmu,
908 .fcvtau,
909 .ucvtf,
910 .fcvtpu,
911 .fcvtzu,
912 => |f| f.sz.toScalarSize(),
913 else => group.size.toScalarSize(),
914 };
915 try writer.print("{f}{s}{f}{s}{f}", .{
916 fmtCase(decoded, dis.case),
917 dis.mnemonic_operands_separator,
918 group.Rd.decode(.{ .V = true }).scalar(elem_size).fmtCase(dis.case),
919 dis.operands_separator,
920 group.Rn.decode(.{ .V = true }).scalar(switch (decoded) {
921 .unallocated => unreachable,
922 else => elem_size,
923 .sqxtn => elem_size.w(),
924 }).fmtCase(dis.case),
925 });
926 return switch (decoded) {
927 .unallocated => unreachable,
928 else => {},
929 .cmgt,
930 .cmeq,
931 .cmlt,
932 .cmge,
933 .cmle,
934 => writer.print("{s}#0", .{dis.operands_separator}),
935 .fcmgt,
936 .fcmeq,
937 .fcmlt,
938 .fcmge,
939 .fcmle,
940 => writer.print("{s}#0.0", .{dis.operands_separator}),
941 };
942 },
943 .simd_scalar_pairwise => {},
944 .simd_copy => |simd_copy| {
945 const decoded = simd_copy.decode();
946 if (decoded == .unallocated) break :unallocated;
947 const group = simd_copy.group;
948 const elem_size = @ctz(group.imm5);
949 return writer.print("{f}{s}{f}{s}{f}", .{
950 if (dis.enable_aliases and switch (decoded) {
951 .unallocated => unreachable,
952 .dup, .smov => false,
953 .umov => elem_size >= 2,
954 .ins => true,
955 }) fmtCase(.mov, dis.case) else fmtCase(decoded, dis.case),
956 dis.mnemonic_operands_separator,
957 switch (decoded) {
958 .unallocated => unreachable,
959 .dup => |dup| group.Rd.decode(.{ .V = true }).vector(.wrap(.{
960 .size = dup.Q,
961 .elem_size = @enumFromInt(elem_size),
962 })),
963 inline .smov, .umov => |mov| group.Rd.decode(.{}).general(mov.Q),
964 .ins => group.Rd.decode(.{ .V = true }).element(
965 @enumFromInt(elem_size),
966 @intCast(group.imm5 >> (elem_size + 1)),
967 ),
968 }.fmtCase(dis.case),
969 dis.operands_separator,
970 switch (decoded) {
971 .unallocated => unreachable,
972 .dup => |dup| switch (dup.imm4) {
973 .element => group.Rn.decode(.{ .V = true }).element(
974 @enumFromInt(elem_size),
975 @intCast(group.imm5 >> (elem_size + 1)),
976 ),
977 .general => group.Rn.decode(.{}).general(switch (elem_size) {
978 0...2 => .word,
979 3 => .doubleword,
980 else => unreachable,
981 }),
982 _ => unreachable,
983 },
984 .smov, .umov => group.Rn.decode(.{ .V = true }).element(
985 @enumFromInt(elem_size),
986 @intCast(group.imm5 >> (elem_size + 1)),
987 ),
988 .ins => |ins| switch (ins.op) {
989 .element => group.Rn.decode(.{ .V = true }).element(
990 @enumFromInt(elem_size),
991 @intCast(group.imm4 >> @intCast(elem_size)),
992 ),
993 .general => group.Rn.decode(.{}).general(switch (elem_size) {
994 0...2 => .word,
995 3 => .doubleword,
996 else => unreachable,
997 }),
998 },
999 }.fmtCase(dis.case),
1000 });
1001 },
1002 .simd_two_register_miscellaneous_fp16 => |simd_two_register_miscellaneous_fp16| {
1003 const decoded = simd_two_register_miscellaneous_fp16.decode();
1004 if (decoded == .unallocated) break :unallocated;
1005 const group = simd_two_register_miscellaneous_fp16.group;
1006 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1007 .size = group.Q,
1008 .elem_size = .half,
1009 });
1010 try writer.print("{f}{s}{f}{s}{f}", .{
1011 fmtCase(decoded, dis.case),
1012 dis.mnemonic_operands_separator,
1013 group.Rd.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1014 dis.operands_separator,
1015 group.Rn.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1016 });
1017 return switch (decoded) {
1018 .unallocated => unreachable,
1019 else => {},
1020 .fcmgt,
1021 .fcmeq,
1022 .fcmlt,
1023 .fcmge,
1024 .fcmle,
1025 => writer.print("{s}#0.0", .{dis.operands_separator}),
1026 };
1027 },
1028 .simd_two_register_miscellaneous => |simd_two_register_miscellaneous| {
1029 const decoded = simd_two_register_miscellaneous.decode();
1030 const group = simd_two_register_miscellaneous.group;
1031 const elem_size = switch (decoded) {
1032 .unallocated => break :unallocated,
1033 inline .frintn,
1034 .frintm,
1035 .fcvtns,
1036 .fcvtms,
1037 .fcvtas,
1038 .scvtf,
1039 .frintp,
1040 .frintz,
1041 .fcvtps,
1042 .fcvtzs,
1043 .fcvtxn,
1044 .frinta,
1045 .frintx,
1046 .fcvtnu,
1047 .fcvtmu,
1048 .fcvtau,
1049 .ucvtf,
1050 .frinti,
1051 .fcvtpu,
1052 .fcvtzu,
1053 => |f| f.sz.toSize(),
1054 else => group.size,
1055 };
1056 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1057 .size = group.Q,
1058 .elem_size = elem_size,
1059 });
1060 try writer.print("{f}{s}{s}{f}{s}{f}", .{
1061 fmtCase(decoded, dis.case),
1062 switch (decoded) {
1063 .unallocated => unreachable,
1064 else => "",
1065 .sqxtn => switch (group.Q) {
1066 .double => "",
1067 .quad => "2",
1068 },
1069 },
1070 dis.mnemonic_operands_separator,
1071 group.Rd.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1072 dis.operands_separator,
1073 group.Rn.decode(.{ .V = true }).vector(switch (decoded) {
1074 .unallocated => unreachable,
1075 else => arrangement,
1076 .sqxtn => .wrap(.{
1077 .size = .quad,
1078 .elem_size = elem_size.w(),
1079 }),
1080 }).fmtCase(dis.case),
1081 });
1082 return switch (decoded) {
1083 .unallocated => unreachable,
1084 else => {},
1085 .cmgt,
1086 .cmeq,
1087 .cmlt,
1088 .cmge,
1089 .cmle,
1090 => writer.print("{s}#0", .{dis.operands_separator}),
1091 .fcmgt,
1092 .fcmeq,
1093 .fcmlt,
1094 .fcmge,
1095 .fcmle,
1096 => writer.print("{s}#0.0", .{dis.operands_separator}),
1097 };
1098 },
1099 .simd_across_lanes => |simd_across_lanes| {
1100 const decoded = simd_across_lanes.decode();
1101 if (decoded == .unallocated) break :unallocated;
1102 const group = simd_across_lanes.group;
1103 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1104 .size = group.Q,
1105 .elem_size = group.size,
1106 });
1107 return writer.print("{f}{s}{f}{s}{f}", .{
1108 fmtCase(decoded, dis.case),
1109 dis.mnemonic_operands_separator,
1110 group.Rd.decode(.{ .V = true }).scalar(group.size.toScalarSize()).fmtCase(dis.case),
1111 dis.operands_separator,
1112 group.Rn.decode(.{ .V = true }).vector(arrangement).fmtCase(dis.case),
1113 });
1114 },
1115 .simd_three_same => |simd_three_same| {
1116 const decoded = simd_three_same.decode();
1117 if (decoded == .unallocated) break :unallocated;
1118 const group = simd_three_same.group;
1119 const arrangement: aarch64.encoding.Register.Arrangement = .wrap(.{
1120 .size = group.Q,
1121 .elem_size = switch (decoded) {
1122 .unallocated => break :unallocated,
1123 .addp => group.size,
1124 .@"and", .bic, .orr, .orn, .eor, .bsl, .bit, .bif => .byte,
1125 },
1126 });
1127 const Rd = group.Rd.decode(.{ .V = true }).vector(arrangement);
1128 const Rn = group.Rn.decode(.{ .V = true }).vector(arrangement);
1129 const Rm = group.Rm.decode(.{ .V = true }).vector(arrangement);
1130 return if (dis.enable_aliases and decoded == .orr and Rm.alias == Rn.alias) try writer.print("{f}{s}{f}{s}{f}", .{
1131 fmtCase(.mov, dis.case),
1132 dis.mnemonic_operands_separator,
1133 Rd.fmtCase(dis.case),
1134 dis.operands_separator,
1135 Rn.fmtCase(dis.case),
1136 }) else try writer.print("{f}{s}{f}{s}{f}{s}{f}", .{
1137 fmtCase(decoded, dis.case),
1138 dis.mnemonic_operands_separator,
1139 Rd.fmtCase(dis.case),
1140 dis.operands_separator,
1141 Rn.fmtCase(dis.case),
1142 dis.operands_separator,
1143 Rm.fmtCase(dis.case),
1144 });
1145 },
1146 .simd_modified_immediate => |simd_modified_immediate| {
1147 const decoded = simd_modified_immediate.decode();
1148 if (decoded == .unallocated) break :unallocated;
1149 const group = simd_modified_immediate.group;
1150 const DataProcessingVector = aarch64.encoding.Instruction.DataProcessingVector;
1151 try writer.print("{f}{s}{f}", .{
1152 fmtCase(decoded, dis.case),
1153 dis.mnemonic_operands_separator,
1154 group.Rd.decode(.{ .V = true }).vector(.wrap(.{
1155 .size = group.Q,
1156 .elem_size = switch (group.o2) {
1157 0b1 => .half,
1158 0b0 => DataProcessingVector.Sz.toSize(@enumFromInt(group.op)),
1159 },
1160 })).fmtCase(dis.case),
1161 });
1162 return switch (decoded) {
1163 .unallocated => unreachable,
1164 .fmov => {
1165 const imm = DataProcessingVector.FloatImmediate.Fmov.Imm8.fromModified(.{
1166 .imm5 = group.imm5,
1167 .imm3 = group.imm3,
1168 }).decode();
1169 try writer.print("{s}#{d}{s}", .{
1170 dis.operands_separator,
1171 @as(f32, imm),
1172 if (imm == @trunc(imm)) ".0" else "",
1173 });
1174 },
1175 };
1176 },
1177 .convert_float_fixed => {},
1178 .convert_float_integer => |convert_float_integer| {
1179 const decoded = convert_float_integer.decode();
1180 if (decoded == .unallocated) break :unallocated;
1181 const group = convert_float_integer.group;
1182 const direction: enum { float_to_integer, integer_to_float } = switch (group.opcode) {
1183 0b000, 0b001, 0b100, 0b101, 0b110 => .float_to_integer,
1184 0b010, 0b011, 0b111 => .integer_to_float,
1185 };
1186 return writer.print("{f}{s}{f}{s}{f}", .{
1187 fmtCase(decoded, dis.case),
1188 dis.mnemonic_operands_separator,
1189 @as(aarch64.encoding.Register, switch (direction) {
1190 .float_to_integer => group.Rd.decode(.{}).general(group.sf),
1191 .integer_to_float => switch (group.ptype) {
1192 .single, .double, .half => group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()),
1193 .quad => group.Rd.decode(.{ .V = true }).@"d[]"(@intCast(group.rmode)),
1194 },
1195 }).fmtCase(dis.case),
1196 dis.operands_separator,
1197 @as(aarch64.encoding.Register, switch (direction) {
1198 .float_to_integer => switch (group.ptype) {
1199 .single, .double, .half => group.Rn.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()),
1200 .quad => group.Rn.decode(.{ .V = true }).@"d[]"(@intCast(group.rmode)),
1201 },
1202 .integer_to_float => group.Rn.decode(.{}).general(group.sf),
1203 }).fmtCase(dis.case),
1204 });
1205 },
1206 .float_data_processing_one_source => |float_data_processing_one_source| {
1207 const decoded = float_data_processing_one_source.decode();
1208 if (decoded == .unallocated) break :unallocated;
1209 const group = float_data_processing_one_source.group;
1210 return writer.print("{f}{s}{f}{s}{f}", .{
1211 fmtCase(decoded, dis.case),
1212 dis.mnemonic_operands_separator,
1213 group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1214 dis.operands_separator,
1215 group.Rn.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1216 });
1217 },
1218 .float_compare => {},
1219 .float_immediate => |float_immediate| {
1220 const decoded = float_immediate.decode();
1221 const group = float_immediate.group;
1222 const imm = switch (decoded) {
1223 .unallocated => break :unallocated,
1224 .fmov => |fmov| fmov.imm8.decode(),
1225 };
1226 return writer.print("{f}{s}{f}{s}#{d}{s}", .{
1227 fmtCase(decoded, dis.case),
1228 dis.mnemonic_operands_separator,
1229 group.Rd.decode(.{ .V = true }).scalar(group.ptype.toScalarSize()).fmtCase(dis.case),
1230 dis.operands_separator,
1231 @as(f32, imm),
1232 if (imm == @trunc(imm)) ".0" else "",
1233 });
1234 },
1235 .float_conditional_compare => {},
1236 .float_data_processing_two_source => {},
1237 .float_conditional_select => {},
1238 .float_data_processing_three_source => {},
1239 },
810 }1240 }
811 return writer.print(".{f}{s}0x{x:0>8}", .{1241 return writer.print(".{f}{s}0x{x:0>8}", .{
812 fmtCase(.word, dis.case),1242 fmtCase(.word, dis.case),
813 dis.mnemonic_operands_separator,1243 dis.mnemonic_operands_separator,
814 @as(Instruction.Backing, @bitCast(inst)),1244 @as(aarch64.encoding.Instruction.Backing, @bitCast(inst)),
815 });1245 });
816}1246}
8171247
...@@ -819,10 +1249,7 @@ fn fmtCase(tag: anytype, case: Case) struct {...@@ -819,10 +1249,7 @@ fn fmtCase(tag: anytype, case: Case) struct {
819 tag: []const u8,1249 tag: []const u8,
820 case: Case,1250 case: Case,
821 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {1251 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {
822 for (data.tag) |c| try writer.writeByte(switch (data.case) {1252 for (data.tag) |c| try writer.writeByte(data.case.convert(c));
823 .lower => std.ascii.toLower(c),
824 .upper => std.ascii.toUpper(c),
825 });
826 }1253 }
827} {1254} {
828 return .{ .tag = @tagName(tag), .case = case };1255 return .{ .tag = @tagName(tag), .case = case };
...@@ -834,7 +1261,8 @@ pub const RegisterFormatter = struct {...@@ -834,7 +1261,8 @@ pub const RegisterFormatter = struct {
834 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {1261 pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void {
835 switch (data.reg.format) {1262 switch (data.reg.format) {
836 .alias => try writer.print("{f}", .{fmtCase(data.reg.alias, data.case)}),1263 .alias => try writer.print("{f}", .{fmtCase(data.reg.alias, data.case)}),
837 .integer => |size| switch (data.reg.alias) {1264 .general => |size| switch (data.reg.alias) {
1265 else => unreachable,
838 .r0,1266 .r0,
839 .r1,1267 .r1,
840 .r2,1268 .r2,
...@@ -867,23 +1295,23 @@ pub const RegisterFormatter = struct {...@@ -867,23 +1295,23 @@ pub const RegisterFormatter = struct {
867 .r29,1295 .r29,
868 .r30,1296 .r30,
869 => |alias| try writer.print("{c}{d}", .{1297 => |alias| try writer.print("{c}{d}", .{
870 size.prefix(),1298 data.case.convert(size.prefix()),
871 @intFromEnum(alias.encode(.{})),1299 @intFromEnum(alias.encode(.{})),
872 }),1300 }),
873 .zr => try writer.print("{c}{f}", .{1301 .zr => try writer.print("{c}{f}", .{
874 size.prefix(),1302 data.case.convert(size.prefix()),
875 fmtCase(data.reg.alias, data.case),1303 fmtCase(data.reg.alias, data.case),
876 }),1304 }),
877 else => try writer.print("{s}{f}", .{1305 .sp => try writer.print("{s}{f}", .{
878 switch (size) {1306 switch (size) {
879 .word => "w",1307 .word => &.{data.case.convert('w')},
880 .doubleword => "",1308 .doubleword => "",
881 },1309 },
882 fmtCase(data.reg.alias, data.case),1310 fmtCase(data.reg.alias, data.case),
883 }),1311 }),
884 },1312 },
885 .scalar => |size| try writer.print("{c}{d}", .{1313 .scalar => |size| try writer.print("{c}{d}", .{
886 size.prefix(),1314 data.case.convert(size.prefix()),
887 @intFromEnum(data.reg.alias.encode(.{ .V = true })),1315 @intFromEnum(data.reg.alias.encode(.{ .V = true })),
888 }),1316 }),
889 .vector => |arrangement| try writer.print("{f}.{f}", .{1317 .vector => |arrangement| try writer.print("{f}.{f}", .{
...@@ -892,14 +1320,17 @@ pub const RegisterFormatter = struct {...@@ -892,14 +1320,17 @@ pub const RegisterFormatter = struct {
892 }),1320 }),
893 .element => |element| try writer.print("{f}.{c}[{d}]", .{1321 .element => |element| try writer.print("{f}.{c}[{d}]", .{
894 fmtCase(data.reg.alias, data.case),1322 fmtCase(data.reg.alias, data.case),
895 element.size.prefix(),1323 data.case.convert(element.size.prefix()),
896 element.index,1324 element.index,
897 }),1325 }),
1326 .scalable => try writer.print("{c}{d}", .{
1327 data.case.convert('z'),
1328 @intFromEnum(data.reg.alias.encode(.{ .V = true })),
1329 }),
898 }1330 }
899 }1331 }
900};1332};
9011333
902const aarch64 = @import("../aarch64.zig");1334const aarch64 = @import("../aarch64.zig");
903const Disassemble = @This();1335const Disassemble = @This();
904const Instruction = aarch64.encoding.Instruction;
905const std = @import("std");1336const std = @import("std");
src/codegen/aarch64/Mir.zig-1
...@@ -307,7 +307,6 @@ fn emitReloc(...@@ -307,7 +307,6 @@ fn emitReloc(
307 .single => .LDST32_ABS_LO12_NC,307 .single => .LDST32_ABS_LO12_NC,
308 .double => .LDST64_ABS_LO12_NC,308 .double => .LDST64_ABS_LO12_NC,
309 .quad => .LDST128_ABS_LO12_NC,309 .quad => .LDST128_ABS_LO12_NC,
310 .scalable, .predicate => unreachable,
311 },310 },
312 };311 };
313 try atom.addReloc(gpa, .{312 try atom.addReloc(gpa, .{
src/codegen/aarch64/Select.zig+1-1
...@@ -8186,7 +8186,7 @@ fn fail(isel: *Select, comptime format: []const u8, args: anytype) error{ OutOfM...@@ -8186,7 +8186,7 @@ fn fail(isel: *Select, comptime format: []const u8, args: anytype) error{ OutOfM
81868186
8187/// dst = src8187/// dst = src
8188fn movImmediate(isel: *Select, dst_reg: Register, src_imm: u64) !void {8188fn movImmediate(isel: *Select, dst_reg: Register, src_imm: u64) !void {
8189 const sf = dst_reg.format.integer;8189 const sf = dst_reg.format.general;
8190 if (src_imm == 0) {8190 if (src_imm == 0) {
8191 const zr: Register = switch (sf) {8191 const zr: Register = switch (sf) {
8192 .word => .wzr,8192 .word => .wzr,
src/codegen/aarch64/encoding.zig+2109-1289
...@@ -4,57 +4,75 @@ pub const Register = struct {...@@ -4,57 +4,75 @@ pub const Register = struct {
4 format: Format,4 format: Format,
55
6 pub const Format = union(enum) {6 pub const Format = union(enum) {
7 alias,7 alias: Format.Alias,
8 integer: IntegerSize,8 general: GeneralSize,
9 scalar: VectorSize,9 scalar: ScalarSize,
10 vector: Arrangement,10 vector: Arrangement,
11 element: struct { size: VectorSize, index: u4 },11 element: struct { size: ScalarSize, index: u4 },
12 scalable,
13
14 pub const Alias = enum { general, other, vector, predicate };
12 };15 };
1316
14 pub const IntegerSize = enum(u1) {17 pub const GeneralSize = enum(u1) {
15 word = 0b0,18 word = 0b0,
16 doubleword = 0b1,19 doubleword = 0b1,
1720
18 pub fn prefix(is: IntegerSize) u8 {21 pub fn prefix(gs: GeneralSize) u8 {
19 return (comptime std.enums.EnumArray(IntegerSize, u8).init(.{22 return (comptime std.enums.EnumArray(GeneralSize, u8).init(.{
20 .word = 'w',23 .word = 'w',
21 .doubleword = 'x',24 .doubleword = 'x',
22 })).get(is);25 })).get(gs);
23 }26 }
24 };27 };
2528
26 pub const VectorSize = enum(u3) {29 pub const ScalarSize = enum(u3) {
27 byte = 0,30 byte = 0,
28 half = 1,31 half = 1,
29 single = 2,32 single = 2,
30 double = 3,33 double = 3,
31 quad = 4,34 quad = 4,
32 scalable,
33 predicate,
3435
35 pub fn prefix(vs: VectorSize) u8 {36 pub fn n(ss: ScalarSize) ScalarSize {
36 return (comptime std.enums.EnumArray(VectorSize, u8).init(.{37 return @enumFromInt(@intFromEnum(ss) - 1);
38 }
39
40 pub fn w(ss: ScalarSize) ScalarSize {
41 return @enumFromInt(@intFromEnum(ss) + 1);
42 }
43
44 pub fn prefix(ss: ScalarSize) u8 {
45 return (comptime std.enums.EnumArray(ScalarSize, u8).init(.{
37 .byte = 'b',46 .byte = 'b',
38 .half = 'h',47 .half = 'h',
39 .single = 's',48 .single = 's',
40 .double = 'd',49 .double = 'd',
41 .quad = 'q',50 .quad = 'q',
42 .scalable = 'z',51 })).get(ss);
43 .predicate = 'p',
44 })).get(vs);
45 }52 }
46 };53 };
4754
48 pub const Arrangement = enum {55 pub const Arrangement = enum(u3) {
49 @"2d",56 @"2d" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .double }),
50 @"4s",57 @"4s" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .single }),
51 @"8h",58 @"8h" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .half }),
52 @"16b",59 @"16b" = @bitCast(Unwrapped{ .size = .quad, .elem_size = .byte }),
60
61 @"1d" = @bitCast(Unwrapped{ .size = .double, .elem_size = .double }),
62 @"2s" = @bitCast(Unwrapped{ .size = .double, .elem_size = .single }),
63 @"4h" = @bitCast(Unwrapped{ .size = .double, .elem_size = .half }),
64 @"8b" = @bitCast(Unwrapped{ .size = .double, .elem_size = .byte }),
5365
54 @"1d",66 pub const Unwrapped = packed struct {
55 @"2s",67 size: Instruction.DataProcessingVector.Q,
56 @"4h",68 elem_size: Instruction.DataProcessingVector.Size,
57 @"8b",69 };
70 pub fn wrap(unwrapped: Unwrapped) Arrangement {
71 return @enumFromInt(@as(@typeInfo(Arrangement).@"enum".tag_type, @bitCast(unwrapped)));
72 }
73 pub fn unwrap(arrangement: Arrangement) Unwrapped {
74 return @bitCast(@intFromEnum(arrangement));
75 }
5876
59 pub fn len(arrangement: Arrangement) u5 {77 pub fn len(arrangement: Arrangement) u5 {
60 return switch (arrangement) {78 return switch (arrangement) {
...@@ -67,625 +85,319 @@ pub const Register = struct {...@@ -67,625 +85,319 @@ pub const Register = struct {
67 }85 }
6886
69 pub fn size(arrangement: Arrangement) Instruction.DataProcessingVector.Q {87 pub fn size(arrangement: Arrangement) Instruction.DataProcessingVector.Q {
70 return switch (arrangement) {88 return arrangement.unwrap().size;
71 .@"2d", .@"4s", .@"8h", .@"16b" => .quad,
72 .@"1d", .@"2s", .@"4h", .@"8b" => .double,
73 };
74 }89 }
75
76 pub fn elemSize(arrangement: Arrangement) Instruction.DataProcessingVector.Size {90 pub fn elemSize(arrangement: Arrangement) Instruction.DataProcessingVector.Size {
77 return switch (arrangement) {91 return arrangement.unwrap().elem_size;
78 .@"2d", .@"1d" => .double,
79 .@"4s", .@"2s" => .single,
80 .@"8h", .@"4h" => .half,
81 .@"16b", .@"8b" => .byte,
82 };
83 }92 }
84
85 pub fn elemSz(arrangement: Arrangement) Instruction.DataProcessingVector.Sz {93 pub fn elemSz(arrangement: Arrangement) Instruction.DataProcessingVector.Sz {
86 return switch (arrangement) {94 return arrangement.elemSize().toSz();
87 else => unreachable,
88 .@"2d", .@"1d" => .double,
89 .@"4s", .@"2s" => .single,
90 };
91 }95 }
92 };96 };
9397
94 pub const x0: Register = .{ .alias = .r0, .format = .{ .integer = .doubleword } };98 pub const x0 = Alias.r0.x();
95 pub const x1: Register = .{ .alias = .r1, .format = .{ .integer = .doubleword } };99 pub const x1 = Alias.r1.x();
96 pub const x2: Register = .{ .alias = .r2, .format = .{ .integer = .doubleword } };100 pub const x2 = Alias.r2.x();
97 pub const x3: Register = .{ .alias = .r3, .format = .{ .integer = .doubleword } };101 pub const x3 = Alias.r3.x();
98 pub const x4: Register = .{ .alias = .r4, .format = .{ .integer = .doubleword } };102 pub const x4 = Alias.r4.x();
99 pub const x5: Register = .{ .alias = .r5, .format = .{ .integer = .doubleword } };103 pub const x5 = Alias.r5.x();
100 pub const x6: Register = .{ .alias = .r6, .format = .{ .integer = .doubleword } };104 pub const x6 = Alias.r6.x();
101 pub const x7: Register = .{ .alias = .r7, .format = .{ .integer = .doubleword } };105 pub const x7 = Alias.r7.x();
102 pub const x8: Register = .{ .alias = .r8, .format = .{ .integer = .doubleword } };106 pub const x8 = Alias.r8.x();
103 pub const x9: Register = .{ .alias = .r9, .format = .{ .integer = .doubleword } };107 pub const x9 = Alias.r9.x();
104 pub const x10: Register = .{ .alias = .r10, .format = .{ .integer = .doubleword } };108 pub const x10 = Alias.r10.x();
105 pub const x11: Register = .{ .alias = .r11, .format = .{ .integer = .doubleword } };109 pub const x11 = Alias.r11.x();
106 pub const x12: Register = .{ .alias = .r12, .format = .{ .integer = .doubleword } };110 pub const x12 = Alias.r12.x();
107 pub const x13: Register = .{ .alias = .r13, .format = .{ .integer = .doubleword } };111 pub const x13 = Alias.r13.x();
108 pub const x14: Register = .{ .alias = .r14, .format = .{ .integer = .doubleword } };112 pub const x14 = Alias.r14.x();
109 pub const x15: Register = .{ .alias = .r15, .format = .{ .integer = .doubleword } };113 pub const x15 = Alias.r15.x();
110 pub const x16: Register = .{ .alias = .r16, .format = .{ .integer = .doubleword } };114 pub const x16 = Alias.r16.x();
111 pub const x17: Register = .{ .alias = .r17, .format = .{ .integer = .doubleword } };115 pub const x17 = Alias.r17.x();
112 pub const x18: Register = .{ .alias = .r18, .format = .{ .integer = .doubleword } };116 pub const x18 = Alias.r18.x();
113 pub const x19: Register = .{ .alias = .r19, .format = .{ .integer = .doubleword } };117 pub const x19 = Alias.r19.x();
114 pub const x20: Register = .{ .alias = .r20, .format = .{ .integer = .doubleword } };118 pub const x20 = Alias.r20.x();
115 pub const x21: Register = .{ .alias = .r21, .format = .{ .integer = .doubleword } };119 pub const x21 = Alias.r21.x();
116 pub const x22: Register = .{ .alias = .r22, .format = .{ .integer = .doubleword } };120 pub const x22 = Alias.r22.x();
117 pub const x23: Register = .{ .alias = .r23, .format = .{ .integer = .doubleword } };121 pub const x23 = Alias.r23.x();
118 pub const x24: Register = .{ .alias = .r24, .format = .{ .integer = .doubleword } };122 pub const x24 = Alias.r24.x();
119 pub const x25: Register = .{ .alias = .r25, .format = .{ .integer = .doubleword } };123 pub const x25 = Alias.r25.x();
120 pub const x26: Register = .{ .alias = .r26, .format = .{ .integer = .doubleword } };124 pub const x26 = Alias.r26.x();
121 pub const x27: Register = .{ .alias = .r27, .format = .{ .integer = .doubleword } };125 pub const x27 = Alias.r27.x();
122 pub const x28: Register = .{ .alias = .r28, .format = .{ .integer = .doubleword } };126 pub const x28 = Alias.r28.x();
123 pub const x29: Register = .{ .alias = .r29, .format = .{ .integer = .doubleword } };127 pub const x29 = Alias.r29.x();
124 pub const x30: Register = .{ .alias = .r30, .format = .{ .integer = .doubleword } };128 pub const x30 = Alias.r30.x();
125 pub const xzr: Register = .{ .alias = .zr, .format = .{ .integer = .doubleword } };129 pub const xzr = Alias.zr.x();
126 pub const sp: Register = .{ .alias = .sp, .format = .{ .integer = .doubleword } };130 pub const sp = Alias.sp.x();
127131
128 pub const w0: Register = .{ .alias = .r0, .format = .{ .integer = .word } };132 pub const w0 = Alias.r0.w();
129 pub const w1: Register = .{ .alias = .r1, .format = .{ .integer = .word } };133 pub const w1 = Alias.r1.w();
130 pub const w2: Register = .{ .alias = .r2, .format = .{ .integer = .word } };134 pub const w2 = Alias.r2.w();
131 pub const w3: Register = .{ .alias = .r3, .format = .{ .integer = .word } };135 pub const w3 = Alias.r3.w();
132 pub const w4: Register = .{ .alias = .r4, .format = .{ .integer = .word } };136 pub const w4 = Alias.r4.w();
133 pub const w5: Register = .{ .alias = .r5, .format = .{ .integer = .word } };137 pub const w5 = Alias.r5.w();
134 pub const w6: Register = .{ .alias = .r6, .format = .{ .integer = .word } };138 pub const w6 = Alias.r6.w();
135 pub const w7: Register = .{ .alias = .r7, .format = .{ .integer = .word } };139 pub const w7 = Alias.r7.w();
136 pub const w8: Register = .{ .alias = .r8, .format = .{ .integer = .word } };140 pub const w8 = Alias.r8.w();
137 pub const w9: Register = .{ .alias = .r9, .format = .{ .integer = .word } };141 pub const w9 = Alias.r9.w();
138 pub const w10: Register = .{ .alias = .r10, .format = .{ .integer = .word } };142 pub const w10 = Alias.r10.w();
139 pub const w11: Register = .{ .alias = .r11, .format = .{ .integer = .word } };143 pub const w11 = Alias.r11.w();
140 pub const w12: Register = .{ .alias = .r12, .format = .{ .integer = .word } };144 pub const w12 = Alias.r12.w();
141 pub const w13: Register = .{ .alias = .r13, .format = .{ .integer = .word } };145 pub const w13 = Alias.r13.w();
142 pub const w14: Register = .{ .alias = .r14, .format = .{ .integer = .word } };146 pub const w14 = Alias.r14.w();
143 pub const w15: Register = .{ .alias = .r15, .format = .{ .integer = .word } };147 pub const w15 = Alias.r15.w();
144 pub const w16: Register = .{ .alias = .r16, .format = .{ .integer = .word } };148 pub const w16 = Alias.r16.w();
145 pub const w17: Register = .{ .alias = .r17, .format = .{ .integer = .word } };149 pub const w17 = Alias.r17.w();
146 pub const w18: Register = .{ .alias = .r18, .format = .{ .integer = .word } };150 pub const w18 = Alias.r18.w();
147 pub const w19: Register = .{ .alias = .r19, .format = .{ .integer = .word } };151 pub const w19 = Alias.r19.w();
148 pub const w20: Register = .{ .alias = .r20, .format = .{ .integer = .word } };152 pub const w20 = Alias.r20.w();
149 pub const w21: Register = .{ .alias = .r21, .format = .{ .integer = .word } };153 pub const w21 = Alias.r21.w();
150 pub const w22: Register = .{ .alias = .r22, .format = .{ .integer = .word } };154 pub const w22 = Alias.r22.w();
151 pub const w23: Register = .{ .alias = .r23, .format = .{ .integer = .word } };155 pub const w23 = Alias.r23.w();
152 pub const w24: Register = .{ .alias = .r24, .format = .{ .integer = .word } };156 pub const w24 = Alias.r24.w();
153 pub const w25: Register = .{ .alias = .r25, .format = .{ .integer = .word } };157 pub const w25 = Alias.r25.w();
154 pub const w26: Register = .{ .alias = .r26, .format = .{ .integer = .word } };158 pub const w26 = Alias.r26.w();
155 pub const w27: Register = .{ .alias = .r27, .format = .{ .integer = .word } };159 pub const w27 = Alias.r27.w();
156 pub const w28: Register = .{ .alias = .r28, .format = .{ .integer = .word } };160 pub const w28 = Alias.r28.w();
157 pub const w29: Register = .{ .alias = .r29, .format = .{ .integer = .word } };161 pub const w29 = Alias.r29.w();
158 pub const w30: Register = .{ .alias = .r30, .format = .{ .integer = .word } };162 pub const w30 = Alias.r30.w();
159 pub const wzr: Register = .{ .alias = .zr, .format = .{ .integer = .word } };163 pub const wzr = Alias.zr.w();
160 pub const wsp: Register = .{ .alias = .sp, .format = .{ .integer = .word } };164 pub const wsp = Alias.sp.w();
161165
162 pub const ip = x16;166 pub const ip = x16;
163 pub const ip0 = x16;167 pub const ip0 = x16;
164 pub const ip1 = x17;168 pub const ip1 = x17;
165 pub const fp = x29;169 pub const fp = x29;
166 pub const lr = x30;170 pub const lr = x30;
167 pub const pc: Register = .{ .alias = .pc, .format = .{ .integer = .doubleword } };171 pub const pc = Alias.pc.alias(.other);
168172
169 pub const q0: Register = .{ .alias = .v0, .format = .{ .scalar = .quad } };173 pub const q0 = Alias.v0.q();
170 pub const q1: Register = .{ .alias = .v1, .format = .{ .scalar = .quad } };174 pub const q1 = Alias.v1.q();
171 pub const q2: Register = .{ .alias = .v2, .format = .{ .scalar = .quad } };175 pub const q2 = Alias.v2.q();
172 pub const q3: Register = .{ .alias = .v3, .format = .{ .scalar = .quad } };176 pub const q3 = Alias.v3.q();
173 pub const q4: Register = .{ .alias = .v4, .format = .{ .scalar = .quad } };177 pub const q4 = Alias.v4.q();
174 pub const q5: Register = .{ .alias = .v5, .format = .{ .scalar = .quad } };178 pub const q5 = Alias.v5.q();
175 pub const q6: Register = .{ .alias = .v6, .format = .{ .scalar = .quad } };179 pub const q6 = Alias.v6.q();
176 pub const q7: Register = .{ .alias = .v7, .format = .{ .scalar = .quad } };180 pub const q7 = Alias.v7.q();
177 pub const q8: Register = .{ .alias = .v8, .format = .{ .scalar = .quad } };181 pub const q8 = Alias.v8.q();
178 pub const q9: Register = .{ .alias = .v9, .format = .{ .scalar = .quad } };182 pub const q9 = Alias.v9.q();
179 pub const q10: Register = .{ .alias = .v10, .format = .{ .scalar = .quad } };183 pub const q10 = Alias.v10.q();
180 pub const q11: Register = .{ .alias = .v11, .format = .{ .scalar = .quad } };184 pub const q11 = Alias.v11.q();
181 pub const q12: Register = .{ .alias = .v12, .format = .{ .scalar = .quad } };185 pub const q12 = Alias.v12.q();
182 pub const q13: Register = .{ .alias = .v13, .format = .{ .scalar = .quad } };186 pub const q13 = Alias.v13.q();
183 pub const q14: Register = .{ .alias = .v14, .format = .{ .scalar = .quad } };187 pub const q14 = Alias.v14.q();
184 pub const q15: Register = .{ .alias = .v15, .format = .{ .scalar = .quad } };188 pub const q15 = Alias.v15.q();
185 pub const q16: Register = .{ .alias = .v16, .format = .{ .scalar = .quad } };189 pub const q16 = Alias.v16.q();
186 pub const q17: Register = .{ .alias = .v17, .format = .{ .scalar = .quad } };190 pub const q17 = Alias.v17.q();
187 pub const q18: Register = .{ .alias = .v18, .format = .{ .scalar = .quad } };191 pub const q18 = Alias.v18.q();
188 pub const q19: Register = .{ .alias = .v19, .format = .{ .scalar = .quad } };192 pub const q19 = Alias.v19.q();
189 pub const q20: Register = .{ .alias = .v20, .format = .{ .scalar = .quad } };193 pub const q20 = Alias.v20.q();
190 pub const q21: Register = .{ .alias = .v21, .format = .{ .scalar = .quad } };194 pub const q21 = Alias.v21.q();
191 pub const q22: Register = .{ .alias = .v22, .format = .{ .scalar = .quad } };195 pub const q22 = Alias.v22.q();
192 pub const q23: Register = .{ .alias = .v23, .format = .{ .scalar = .quad } };196 pub const q23 = Alias.v23.q();
193 pub const q24: Register = .{ .alias = .v24, .format = .{ .scalar = .quad } };197 pub const q24 = Alias.v24.q();
194 pub const q25: Register = .{ .alias = .v25, .format = .{ .scalar = .quad } };198 pub const q25 = Alias.v25.q();
195 pub const q26: Register = .{ .alias = .v26, .format = .{ .scalar = .quad } };199 pub const q26 = Alias.v26.q();
196 pub const q27: Register = .{ .alias = .v27, .format = .{ .scalar = .quad } };200 pub const q27 = Alias.v27.q();
197 pub const q28: Register = .{ .alias = .v28, .format = .{ .scalar = .quad } };201 pub const q28 = Alias.v28.q();
198 pub const q29: Register = .{ .alias = .v29, .format = .{ .scalar = .quad } };202 pub const q29 = Alias.v29.q();
199 pub const q30: Register = .{ .alias = .v30, .format = .{ .scalar = .quad } };203 pub const q30 = Alias.v30.q();
200 pub const q31: Register = .{ .alias = .v31, .format = .{ .scalar = .quad } };204 pub const q31 = Alias.v31.q();
201205
202 pub const d0: Register = .{ .alias = .v0, .format = .{ .scalar = .double } };206 pub const d0 = Alias.v0.d();
203 pub const d1: Register = .{ .alias = .v1, .format = .{ .scalar = .double } };207 pub const d1 = Alias.v1.d();
204 pub const d2: Register = .{ .alias = .v2, .format = .{ .scalar = .double } };208 pub const d2 = Alias.v2.d();
205 pub const d3: Register = .{ .alias = .v3, .format = .{ .scalar = .double } };209 pub const d3 = Alias.v3.d();
206 pub const d4: Register = .{ .alias = .v4, .format = .{ .scalar = .double } };210 pub const d4 = Alias.v4.d();
207 pub const d5: Register = .{ .alias = .v5, .format = .{ .scalar = .double } };211 pub const d5 = Alias.v5.d();
208 pub const d6: Register = .{ .alias = .v6, .format = .{ .scalar = .double } };212 pub const d6 = Alias.v6.d();
209 pub const d7: Register = .{ .alias = .v7, .format = .{ .scalar = .double } };213 pub const d7 = Alias.v7.d();
210 pub const d8: Register = .{ .alias = .v8, .format = .{ .scalar = .double } };214 pub const d8 = Alias.v8.d();
211 pub const d9: Register = .{ .alias = .v9, .format = .{ .scalar = .double } };215 pub const d9 = Alias.v9.d();
212 pub const d10: Register = .{ .alias = .v10, .format = .{ .scalar = .double } };216 pub const d10 = Alias.v10.d();
213 pub const d11: Register = .{ .alias = .v11, .format = .{ .scalar = .double } };217 pub const d11 = Alias.v11.d();
214 pub const d12: Register = .{ .alias = .v12, .format = .{ .scalar = .double } };218 pub const d12 = Alias.v12.d();
215 pub const d13: Register = .{ .alias = .v13, .format = .{ .scalar = .double } };219 pub const d13 = Alias.v13.d();
216 pub const d14: Register = .{ .alias = .v14, .format = .{ .scalar = .double } };220 pub const d14 = Alias.v14.d();
217 pub const d15: Register = .{ .alias = .v15, .format = .{ .scalar = .double } };221 pub const d15 = Alias.v15.d();
218 pub const d16: Register = .{ .alias = .v16, .format = .{ .scalar = .double } };222 pub const d16 = Alias.v16.d();
219 pub const d17: Register = .{ .alias = .v17, .format = .{ .scalar = .double } };223 pub const d17 = Alias.v17.d();
220 pub const d18: Register = .{ .alias = .v18, .format = .{ .scalar = .double } };224 pub const d18 = Alias.v18.d();
221 pub const d19: Register = .{ .alias = .v19, .format = .{ .scalar = .double } };225 pub const d19 = Alias.v19.d();
222 pub const d20: Register = .{ .alias = .v20, .format = .{ .scalar = .double } };226 pub const d20 = Alias.v20.d();
223 pub const d21: Register = .{ .alias = .v21, .format = .{ .scalar = .double } };227 pub const d21 = Alias.v21.d();
224 pub const d22: Register = .{ .alias = .v22, .format = .{ .scalar = .double } };228 pub const d22 = Alias.v22.d();
225 pub const d23: Register = .{ .alias = .v23, .format = .{ .scalar = .double } };229 pub const d23 = Alias.v23.d();
226 pub const d24: Register = .{ .alias = .v24, .format = .{ .scalar = .double } };230 pub const d24 = Alias.v24.d();
227 pub const d25: Register = .{ .alias = .v25, .format = .{ .scalar = .double } };231 pub const d25 = Alias.v25.d();
228 pub const d26: Register = .{ .alias = .v26, .format = .{ .scalar = .double } };232 pub const d26 = Alias.v26.d();
229 pub const d27: Register = .{ .alias = .v27, .format = .{ .scalar = .double } };233 pub const d27 = Alias.v27.d();
230 pub const d28: Register = .{ .alias = .v28, .format = .{ .scalar = .double } };234 pub const d28 = Alias.v28.d();
231 pub const d29: Register = .{ .alias = .v29, .format = .{ .scalar = .double } };235 pub const d29 = Alias.v29.d();
232 pub const d30: Register = .{ .alias = .v30, .format = .{ .scalar = .double } };236 pub const d30 = Alias.v30.d();
233 pub const d31: Register = .{ .alias = .v31, .format = .{ .scalar = .double } };237 pub const d31 = Alias.v31.d();
234238
235 pub const s0: Register = .{ .alias = .v0, .format = .{ .scalar = .single } };239 pub const s0 = Alias.v0.s();
236 pub const s1: Register = .{ .alias = .v1, .format = .{ .scalar = .single } };240 pub const s1 = Alias.v1.s();
237 pub const s2: Register = .{ .alias = .v2, .format = .{ .scalar = .single } };241 pub const s2 = Alias.v2.s();
238 pub const s3: Register = .{ .alias = .v3, .format = .{ .scalar = .single } };242 pub const s3 = Alias.v3.s();
239 pub const s4: Register = .{ .alias = .v4, .format = .{ .scalar = .single } };243 pub const s4 = Alias.v4.s();
240 pub const s5: Register = .{ .alias = .v5, .format = .{ .scalar = .single } };244 pub const s5 = Alias.v5.s();
241 pub const s6: Register = .{ .alias = .v6, .format = .{ .scalar = .single } };245 pub const s6 = Alias.v6.s();
242 pub const s7: Register = .{ .alias = .v7, .format = .{ .scalar = .single } };246 pub const s7 = Alias.v7.s();
243 pub const s8: Register = .{ .alias = .v8, .format = .{ .scalar = .single } };247 pub const s8 = Alias.v8.s();
244 pub const s9: Register = .{ .alias = .v9, .format = .{ .scalar = .single } };248 pub const s9 = Alias.v9.s();
245 pub const s10: Register = .{ .alias = .v10, .format = .{ .scalar = .single } };249 pub const s10 = Alias.v10.s();
246 pub const s11: Register = .{ .alias = .v11, .format = .{ .scalar = .single } };250 pub const s11 = Alias.v11.s();
247 pub const s12: Register = .{ .alias = .v12, .format = .{ .scalar = .single } };251 pub const s12 = Alias.v12.s();
248 pub const s13: Register = .{ .alias = .v13, .format = .{ .scalar = .single } };252 pub const s13 = Alias.v13.s();
249 pub const s14: Register = .{ .alias = .v14, .format = .{ .scalar = .single } };253 pub const s14 = Alias.v14.s();
250 pub const s15: Register = .{ .alias = .v15, .format = .{ .scalar = .single } };254 pub const s15 = Alias.v15.s();
251 pub const s16: Register = .{ .alias = .v16, .format = .{ .scalar = .single } };255 pub const s16 = Alias.v16.s();
252 pub const s17: Register = .{ .alias = .v17, .format = .{ .scalar = .single } };256 pub const s17 = Alias.v17.s();
253 pub const s18: Register = .{ .alias = .v18, .format = .{ .scalar = .single } };257 pub const s18 = Alias.v18.s();
254 pub const s19: Register = .{ .alias = .v19, .format = .{ .scalar = .single } };258 pub const s19 = Alias.v19.s();
255 pub const s20: Register = .{ .alias = .v20, .format = .{ .scalar = .single } };259 pub const s20 = Alias.v20.s();
256 pub const s21: Register = .{ .alias = .v21, .format = .{ .scalar = .single } };260 pub const s21 = Alias.v21.s();
257 pub const s22: Register = .{ .alias = .v22, .format = .{ .scalar = .single } };261 pub const s22 = Alias.v22.s();
258 pub const s23: Register = .{ .alias = .v23, .format = .{ .scalar = .single } };262 pub const s23 = Alias.v23.s();
259 pub const s24: Register = .{ .alias = .v24, .format = .{ .scalar = .single } };263 pub const s24 = Alias.v24.s();
260 pub const s25: Register = .{ .alias = .v25, .format = .{ .scalar = .single } };264 pub const s25 = Alias.v25.s();
261 pub const s26: Register = .{ .alias = .v26, .format = .{ .scalar = .single } };265 pub const s26 = Alias.v26.s();
262 pub const s27: Register = .{ .alias = .v27, .format = .{ .scalar = .single } };266 pub const s27 = Alias.v27.s();
263 pub const s28: Register = .{ .alias = .v28, .format = .{ .scalar = .single } };267 pub const s28 = Alias.v28.s();
264 pub const s29: Register = .{ .alias = .v29, .format = .{ .scalar = .single } };268 pub const s29 = Alias.v29.s();
265 pub const s30: Register = .{ .alias = .v30, .format = .{ .scalar = .single } };269 pub const s30 = Alias.v30.s();
266 pub const s31: Register = .{ .alias = .v31, .format = .{ .scalar = .single } };270 pub const s31 = Alias.v31.s();
267271
268 pub const h0: Register = .{ .alias = .v0, .format = .{ .scalar = .half } };272 pub const h0 = Alias.v0.h();
269 pub const h1: Register = .{ .alias = .v1, .format = .{ .scalar = .half } };273 pub const h1 = Alias.v1.h();
270 pub const h2: Register = .{ .alias = .v2, .format = .{ .scalar = .half } };274 pub const h2 = Alias.v2.h();
271 pub const h3: Register = .{ .alias = .v3, .format = .{ .scalar = .half } };275 pub const h3 = Alias.v3.h();
272 pub const h4: Register = .{ .alias = .v4, .format = .{ .scalar = .half } };276 pub const h4 = Alias.v4.h();
273 pub const h5: Register = .{ .alias = .v5, .format = .{ .scalar = .half } };277 pub const h5 = Alias.v5.h();
274 pub const h6: Register = .{ .alias = .v6, .format = .{ .scalar = .half } };278 pub const h6 = Alias.v6.h();
275 pub const h7: Register = .{ .alias = .v7, .format = .{ .scalar = .half } };279 pub const h7 = Alias.v7.h();
276 pub const h8: Register = .{ .alias = .v8, .format = .{ .scalar = .half } };280 pub const h8 = Alias.v8.h();
277 pub const h9: Register = .{ .alias = .v9, .format = .{ .scalar = .half } };281 pub const h9 = Alias.v9.h();
278 pub const h10: Register = .{ .alias = .v10, .format = .{ .scalar = .half } };282 pub const h10 = Alias.v10.h();
279 pub const h11: Register = .{ .alias = .v11, .format = .{ .scalar = .half } };283 pub const h11 = Alias.v11.h();
280 pub const h12: Register = .{ .alias = .v12, .format = .{ .scalar = .half } };284 pub const h12 = Alias.v12.h();
281 pub const h13: Register = .{ .alias = .v13, .format = .{ .scalar = .half } };285 pub const h13 = Alias.v13.h();
282 pub const h14: Register = .{ .alias = .v14, .format = .{ .scalar = .half } };286 pub const h14 = Alias.v14.h();
283 pub const h15: Register = .{ .alias = .v15, .format = .{ .scalar = .half } };287 pub const h15 = Alias.v15.h();
284 pub const h16: Register = .{ .alias = .v16, .format = .{ .scalar = .half } };288 pub const h16 = Alias.v16.h();
285 pub const h17: Register = .{ .alias = .v17, .format = .{ .scalar = .half } };289 pub const h17 = Alias.v17.h();
286 pub const h18: Register = .{ .alias = .v18, .format = .{ .scalar = .half } };290 pub const h18 = Alias.v18.h();
287 pub const h19: Register = .{ .alias = .v19, .format = .{ .scalar = .half } };291 pub const h19 = Alias.v19.h();
288 pub const h20: Register = .{ .alias = .v20, .format = .{ .scalar = .half } };292 pub const h20 = Alias.v20.h();
289 pub const h21: Register = .{ .alias = .v21, .format = .{ .scalar = .half } };293 pub const h21 = Alias.v21.h();
290 pub const h22: Register = .{ .alias = .v22, .format = .{ .scalar = .half } };294 pub const h22 = Alias.v22.h();
291 pub const h23: Register = .{ .alias = .v23, .format = .{ .scalar = .half } };295 pub const h23 = Alias.v23.h();
292 pub const h24: Register = .{ .alias = .v24, .format = .{ .scalar = .half } };296 pub const h24 = Alias.v24.h();
293 pub const h25: Register = .{ .alias = .v25, .format = .{ .scalar = .half } };297 pub const h25 = Alias.v25.h();
294 pub const h26: Register = .{ .alias = .v26, .format = .{ .scalar = .half } };298 pub const h26 = Alias.v26.h();
295 pub const h27: Register = .{ .alias = .v27, .format = .{ .scalar = .half } };299 pub const h27 = Alias.v27.h();
296 pub const h28: Register = .{ .alias = .v28, .format = .{ .scalar = .half } };300 pub const h28 = Alias.v28.h();
297 pub const h29: Register = .{ .alias = .v29, .format = .{ .scalar = .half } };301 pub const h29 = Alias.v29.h();
298 pub const h30: Register = .{ .alias = .v30, .format = .{ .scalar = .half } };302 pub const h30 = Alias.v30.h();
299 pub const h31: Register = .{ .alias = .v31, .format = .{ .scalar = .half } };303 pub const h31 = Alias.v31.h();
300304
301 pub const b0: Register = .{ .alias = .v0, .format = .{ .scalar = .byte } };305 pub const b0 = Alias.v0.b();
302 pub const b1: Register = .{ .alias = .v1, .format = .{ .scalar = .byte } };306 pub const b1 = Alias.v1.b();
303 pub const b2: Register = .{ .alias = .v2, .format = .{ .scalar = .byte } };307 pub const b2 = Alias.v2.b();
304 pub const b3: Register = .{ .alias = .v3, .format = .{ .scalar = .byte } };308 pub const b3 = Alias.v3.b();
305 pub const b4: Register = .{ .alias = .v4, .format = .{ .scalar = .byte } };309 pub const b4 = Alias.v4.b();
306 pub const b5: Register = .{ .alias = .v5, .format = .{ .scalar = .byte } };310 pub const b5 = Alias.v5.b();
307 pub const b6: Register = .{ .alias = .v6, .format = .{ .scalar = .byte } };311 pub const b6 = Alias.v6.b();
308 pub const b7: Register = .{ .alias = .v7, .format = .{ .scalar = .byte } };312 pub const b7 = Alias.v7.b();
309 pub const b8: Register = .{ .alias = .v8, .format = .{ .scalar = .byte } };313 pub const b8 = Alias.v8.b();
310 pub const b9: Register = .{ .alias = .v9, .format = .{ .scalar = .byte } };314 pub const b9 = Alias.v9.b();
311 pub const b10: Register = .{ .alias = .v10, .format = .{ .scalar = .byte } };315 pub const b10 = Alias.v10.b();
312 pub const b11: Register = .{ .alias = .v11, .format = .{ .scalar = .byte } };316 pub const b11 = Alias.v11.b();
313 pub const b12: Register = .{ .alias = .v12, .format = .{ .scalar = .byte } };317 pub const b12 = Alias.v12.b();
314 pub const b13: Register = .{ .alias = .v13, .format = .{ .scalar = .byte } };318 pub const b13 = Alias.v13.b();
315 pub const b14: Register = .{ .alias = .v14, .format = .{ .scalar = .byte } };319 pub const b14 = Alias.v14.b();
316 pub const b15: Register = .{ .alias = .v15, .format = .{ .scalar = .byte } };320 pub const b15 = Alias.v15.b();
317 pub const b16: Register = .{ .alias = .v16, .format = .{ .scalar = .byte } };321 pub const b16 = Alias.v16.b();
318 pub const b17: Register = .{ .alias = .v17, .format = .{ .scalar = .byte } };322 pub const b17 = Alias.v17.b();
319 pub const b18: Register = .{ .alias = .v18, .format = .{ .scalar = .byte } };323 pub const b18 = Alias.v18.b();
320 pub const b19: Register = .{ .alias = .v19, .format = .{ .scalar = .byte } };324 pub const b19 = Alias.v19.b();
321 pub const b20: Register = .{ .alias = .v20, .format = .{ .scalar = .byte } };325 pub const b20 = Alias.v20.b();
322 pub const b21: Register = .{ .alias = .v21, .format = .{ .scalar = .byte } };326 pub const b21 = Alias.v21.b();
323 pub const b22: Register = .{ .alias = .v22, .format = .{ .scalar = .byte } };327 pub const b22 = Alias.v22.b();
324 pub const b23: Register = .{ .alias = .v23, .format = .{ .scalar = .byte } };328 pub const b23 = Alias.v23.b();
325 pub const b24: Register = .{ .alias = .v24, .format = .{ .scalar = .byte } };329 pub const b24 = Alias.v24.b();
326 pub const b25: Register = .{ .alias = .v25, .format = .{ .scalar = .byte } };330 pub const b25 = Alias.v25.b();
327 pub const b26: Register = .{ .alias = .v26, .format = .{ .scalar = .byte } };331 pub const b26 = Alias.v26.b();
328 pub const b27: Register = .{ .alias = .v27, .format = .{ .scalar = .byte } };332 pub const b27 = Alias.v27.b();
329 pub const b28: Register = .{ .alias = .v28, .format = .{ .scalar = .byte } };333 pub const b28 = Alias.v28.b();
330 pub const b29: Register = .{ .alias = .v29, .format = .{ .scalar = .byte } };334 pub const b29 = Alias.v29.b();
331 pub const b30: Register = .{ .alias = .v30, .format = .{ .scalar = .byte } };335 pub const b30 = Alias.v30.b();
332 pub const b31: Register = .{ .alias = .v31, .format = .{ .scalar = .byte } };336 pub const b31 = Alias.v31.b();
333337
334 pub const fpcr: Register = .{ .alias = .fpcr, .format = .{ .integer = .doubleword } };338 pub const fpcr = Alias.fpcr.alias(.other);
335 pub const fpsr: Register = .{ .alias = .fpsr, .format = .{ .integer = .doubleword } };339 pub const fpsr = Alias.fpsr.alias(.other);
336340
337 pub const z0: Register = .{ .alias = .v0, .format = .{ .scalar = .scalable } };341 pub const z0 = Alias.v0.z();
338 pub const z1: Register = .{ .alias = .v1, .format = .{ .scalar = .scalable } };342 pub const z1 = Alias.v1.z();
339 pub const z2: Register = .{ .alias = .v2, .format = .{ .scalar = .scalable } };343 pub const z2 = Alias.v2.z();
340 pub const z3: Register = .{ .alias = .v3, .format = .{ .scalar = .scalable } };344 pub const z3 = Alias.v3.z();
341 pub const z4: Register = .{ .alias = .v4, .format = .{ .scalar = .scalable } };345 pub const z4 = Alias.v4.z();
342 pub const z5: Register = .{ .alias = .v5, .format = .{ .scalar = .scalable } };346 pub const z5 = Alias.v5.z();
343 pub const z6: Register = .{ .alias = .v6, .format = .{ .scalar = .scalable } };347 pub const z6 = Alias.v6.z();
344 pub const z7: Register = .{ .alias = .v7, .format = .{ .scalar = .scalable } };348 pub const z7 = Alias.v7.z();
345 pub const z8: Register = .{ .alias = .v8, .format = .{ .scalar = .scalable } };349 pub const z8 = Alias.v8.z();
346 pub const z9: Register = .{ .alias = .v9, .format = .{ .scalar = .scalable } };350 pub const z9 = Alias.v9.z();
347 pub const z10: Register = .{ .alias = .v10, .format = .{ .scalar = .scalable } };351 pub const z10 = Alias.v10.z();
348 pub const z11: Register = .{ .alias = .v11, .format = .{ .scalar = .scalable } };352 pub const z11 = Alias.v11.z();
349 pub const z12: Register = .{ .alias = .v12, .format = .{ .scalar = .scalable } };353 pub const z12 = Alias.v12.z();
350 pub const z13: Register = .{ .alias = .v13, .format = .{ .scalar = .scalable } };354 pub const z13 = Alias.v13.z();
351 pub const z14: Register = .{ .alias = .v14, .format = .{ .scalar = .scalable } };355 pub const z14 = Alias.v14.z();
352 pub const z15: Register = .{ .alias = .v15, .format = .{ .scalar = .scalable } };356 pub const z15 = Alias.v15.z();
353 pub const z16: Register = .{ .alias = .v16, .format = .{ .scalar = .scalable } };357 pub const z16 = Alias.v16.z();
354 pub const z17: Register = .{ .alias = .v17, .format = .{ .scalar = .scalable } };358 pub const z17 = Alias.v17.z();
355 pub const z18: Register = .{ .alias = .v18, .format = .{ .scalar = .scalable } };359 pub const z18 = Alias.v18.z();
356 pub const z19: Register = .{ .alias = .v19, .format = .{ .scalar = .scalable } };360 pub const z19 = Alias.v19.z();
357 pub const z20: Register = .{ .alias = .v20, .format = .{ .scalar = .scalable } };361 pub const z20 = Alias.v20.z();
358 pub const z21: Register = .{ .alias = .v21, .format = .{ .scalar = .scalable } };362 pub const z21 = Alias.v21.z();
359 pub const z22: Register = .{ .alias = .v22, .format = .{ .scalar = .scalable } };363 pub const z22 = Alias.v22.z();
360 pub const z23: Register = .{ .alias = .v23, .format = .{ .scalar = .scalable } };364 pub const z23 = Alias.v23.z();
361 pub const z24: Register = .{ .alias = .v24, .format = .{ .scalar = .scalable } };365 pub const z24 = Alias.v24.z();
362 pub const z25: Register = .{ .alias = .v25, .format = .{ .scalar = .scalable } };366 pub const z25 = Alias.v25.z();
363 pub const z26: Register = .{ .alias = .v26, .format = .{ .scalar = .scalable } };367 pub const z26 = Alias.v26.z();
364 pub const z27: Register = .{ .alias = .v27, .format = .{ .scalar = .scalable } };368 pub const z27 = Alias.v27.z();
365 pub const z28: Register = .{ .alias = .v28, .format = .{ .scalar = .scalable } };369 pub const z28 = Alias.v28.z();
366 pub const z29: Register = .{ .alias = .v29, .format = .{ .scalar = .scalable } };370 pub const z29 = Alias.v29.z();
367 pub const z30: Register = .{ .alias = .v30, .format = .{ .scalar = .scalable } };371 pub const z30 = Alias.v30.z();
368 pub const z31: Register = .{ .alias = .v31, .format = .{ .scalar = .scalable } };372 pub const z31 = Alias.v31.z();
369373
370 pub const p0: Register = .{ .alias = .v0, .format = .{ .scalar = .predicate } };374 pub const p0 = Alias.p0.p();
371 pub const p1: Register = .{ .alias = .v1, .format = .{ .scalar = .predicate } };375 pub const p1 = Alias.p1.p();
372 pub const p2: Register = .{ .alias = .v2, .format = .{ .scalar = .predicate } };376 pub const p2 = Alias.p2.p();
373 pub const p3: Register = .{ .alias = .v3, .format = .{ .scalar = .predicate } };377 pub const p3 = Alias.p3.p();
374 pub const p4: Register = .{ .alias = .v4, .format = .{ .scalar = .predicate } };378 pub const p4 = Alias.p4.p();
375 pub const p5: Register = .{ .alias = .v5, .format = .{ .scalar = .predicate } };379 pub const p5 = Alias.p5.p();
376 pub const p6: Register = .{ .alias = .v6, .format = .{ .scalar = .predicate } };380 pub const p6 = Alias.p6.p();
377 pub const p7: Register = .{ .alias = .v7, .format = .{ .scalar = .predicate } };381 pub const p7 = Alias.p7.p();
378 pub const p8: Register = .{ .alias = .v8, .format = .{ .scalar = .predicate } };382 pub const p8 = Alias.p8.p();
379 pub const p9: Register = .{ .alias = .v9, .format = .{ .scalar = .predicate } };383 pub const p9 = Alias.p9.p();
380 pub const p10: Register = .{ .alias = .v10, .format = .{ .scalar = .predicate } };384 pub const p10 = Alias.p10.p();
381 pub const p11: Register = .{ .alias = .v11, .format = .{ .scalar = .predicate } };385 pub const p11 = Alias.p11.p();
382 pub const p12: Register = .{ .alias = .v12, .format = .{ .scalar = .predicate } };386 pub const p12 = Alias.p12.p();
383 pub const p13: Register = .{ .alias = .v13, .format = .{ .scalar = .predicate } };387 pub const p13 = Alias.p13.p();
384 pub const p14: Register = .{ .alias = .v14, .format = .{ .scalar = .predicate } };388 pub const p14 = Alias.p14.p();
385 pub const p15: Register = .{ .alias = .v15, .format = .{ .scalar = .predicate } };389 pub const p15 = Alias.p15.p();
386390
387 pub const ffr: Register = .{ .alias = .ffr, .format = .{ .integer = .doubleword } };391 pub const ffr = Alias.ffr.alias(.other);
388392
389 pub const Encoded = enum(u5) {393 pub const Encoded = enum(u5) {
390 _,394 _,
391395
392 pub fn decodeInteger(enc: Encoded, sf_enc: IntegerSize, opts: struct { sp: bool = false }) Register {396 pub fn decode(enc: Encoded, opts: struct { sp: bool = false, V: bool = false }) Alias {
393 return switch (sf_enc) {397 return switch (opts.V) {
394 .word => switch (@intFromEnum(enc)) {398 false => @enumFromInt(@intFromEnum(Alias.r0) + @intFromEnum(enc) +
395 0 => .w0,399 @intFromBool(opts.sp and enc == comptime Alias.sp.encode(.{ .sp = true }))),
396 1 => .w1,400 true => @enumFromInt(@intFromEnum(Alias.v0) + @intFromEnum(enc)),
397 2 => .w2,
398 3 => .w3,
399 4 => .w4,
400 5 => .w5,
401 6 => .w6,
402 7 => .w7,
403 8 => .w8,
404 9 => .w9,
405 10 => .w10,
406 11 => .w11,
407 12 => .w12,
408 13 => .w13,
409 14 => .w14,
410 15 => .w15,
411 16 => .w16,
412 17 => .w17,
413 18 => .w18,
414 19 => .w19,
415 20 => .w20,
416 21 => .w21,
417 22 => .w22,
418 23 => .w23,
419 24 => .w24,
420 25 => .w25,
421 26 => .w26,
422 27 => .w27,
423 28 => .w28,
424 29 => .w29,
425 30 => .w30,
426 31 => if (opts.sp) .wsp else .wzr,
427 },
428 .doubleword => switch (@intFromEnum(enc)) {
429 0 => .x0,
430 1 => .x1,
431 2 => .x2,
432 3 => .x3,
433 4 => .x4,
434 5 => .x5,
435 6 => .x6,
436 7 => .x7,
437 8 => .x8,
438 9 => .x9,
439 10 => .x10,
440 11 => .x11,
441 12 => .x12,
442 13 => .x13,
443 14 => .x14,
444 15 => .x15,
445 16 => .x16,
446 17 => .x17,
447 18 => .x18,
448 19 => .x19,
449 20 => .x20,
450 21 => .x21,
451 22 => .x22,
452 23 => .x23,
453 24 => .x24,
454 25 => .x25,
455 26 => .x26,
456 27 => .x27,
457 28 => .x28,
458 29 => .x29,
459 30 => .x30,
460 31 => if (opts.sp) .sp else .xzr,
461 },
462 };
463 }
464
465 pub fn decodeVector(enc: Encoded, vs_enc: VectorSize) Register {
466 return switch (vs_enc) {
467 .byte => switch (@intFromEnum(enc)) {
468 0 => .b0,
469 1 => .b1,
470 2 => .b2,
471 3 => .b3,
472 4 => .b4,
473 5 => .b5,
474 6 => .b6,
475 7 => .b7,
476 8 => .b8,
477 9 => .b9,
478 10 => .b10,
479 11 => .b11,
480 12 => .b12,
481 13 => .b13,
482 14 => .b14,
483 15 => .b15,
484 16 => .b16,
485 17 => .b17,
486 18 => .b18,
487 19 => .b19,
488 20 => .b20,
489 21 => .b21,
490 22 => .b22,
491 23 => .b23,
492 24 => .b24,
493 25 => .b25,
494 26 => .b26,
495 27 => .b27,
496 28 => .b28,
497 29 => .b29,
498 30 => .b30,
499 31 => .b31,
500 },
501 .half => switch (@intFromEnum(enc)) {
502 0 => .h0,
503 1 => .h1,
504 2 => .h2,
505 3 => .h3,
506 4 => .h4,
507 5 => .h5,
508 6 => .h6,
509 7 => .h7,
510 8 => .h8,
511 9 => .h9,
512 10 => .h10,
513 11 => .h11,
514 12 => .h12,
515 13 => .h13,
516 14 => .h14,
517 15 => .h15,
518 16 => .h16,
519 17 => .h17,
520 18 => .h18,
521 19 => .h19,
522 20 => .h20,
523 21 => .h21,
524 22 => .h22,
525 23 => .h23,
526 24 => .h24,
527 25 => .h25,
528 26 => .h26,
529 27 => .h27,
530 28 => .h28,
531 29 => .h29,
532 30 => .h30,
533 31 => .h31,
534 },
535 .single => switch (@intFromEnum(enc)) {
536 0 => .s0,
537 1 => .s1,
538 2 => .s2,
539 3 => .s3,
540 4 => .s4,
541 5 => .s5,
542 6 => .s6,
543 7 => .s7,
544 8 => .s8,
545 9 => .s9,
546 10 => .s10,
547 11 => .s11,
548 12 => .s12,
549 13 => .s13,
550 14 => .s14,
551 15 => .s15,
552 16 => .s16,
553 17 => .s17,
554 18 => .s18,
555 19 => .s19,
556 20 => .s20,
557 21 => .s21,
558 22 => .s22,
559 23 => .s23,
560 24 => .s24,
561 25 => .s25,
562 26 => .s26,
563 27 => .s27,
564 28 => .s28,
565 29 => .s29,
566 30 => .s30,
567 31 => .s31,
568 },
569 .double => switch (@intFromEnum(enc)) {
570 0 => .d0,
571 1 => .d1,
572 2 => .d2,
573 3 => .d3,
574 4 => .d4,
575 5 => .d5,
576 6 => .d6,
577 7 => .d7,
578 8 => .d8,
579 9 => .d9,
580 10 => .d10,
581 11 => .d11,
582 12 => .d12,
583 13 => .d13,
584 14 => .d14,
585 15 => .d15,
586 16 => .d16,
587 17 => .d17,
588 18 => .d18,
589 19 => .d19,
590 20 => .d20,
591 21 => .d21,
592 22 => .d22,
593 23 => .d23,
594 24 => .d24,
595 25 => .d25,
596 26 => .d26,
597 27 => .d27,
598 28 => .d28,
599 29 => .d29,
600 30 => .d30,
601 31 => .d31,
602 },
603 .quad => switch (@intFromEnum(enc)) {
604 0 => .q0,
605 1 => .q1,
606 2 => .q2,
607 3 => .q3,
608 4 => .q4,
609 5 => .q5,
610 6 => .q6,
611 7 => .q7,
612 8 => .q8,
613 9 => .q9,
614 10 => .q10,
615 11 => .q11,
616 12 => .q12,
617 13 => .q13,
618 14 => .q14,
619 15 => .q15,
620 16 => .q16,
621 17 => .q17,
622 18 => .q18,
623 19 => .q19,
624 20 => .q20,
625 21 => .q21,
626 22 => .q22,
627 23 => .q23,
628 24 => .q24,
629 25 => .q25,
630 26 => .q26,
631 27 => .q27,
632 28 => .q28,
633 29 => .q29,
634 30 => .q30,
635 31 => .q31,
636 },
637 .scalable => switch (@intFromEnum(enc)) {
638 0 => .z0,
639 1 => .z1,
640 2 => .z2,
641 3 => .z3,
642 4 => .z4,
643 5 => .z5,
644 6 => .z6,
645 7 => .z7,
646 8 => .z8,
647 9 => .z9,
648 10 => .z10,
649 11 => .z11,
650 12 => .z12,
651 13 => .z13,
652 14 => .z14,
653 15 => .z15,
654 16 => .z16,
655 17 => .z17,
656 18 => .z18,
657 19 => .z19,
658 20 => .z20,
659 21 => .z21,
660 22 => .z22,
661 23 => .z23,
662 24 => .z24,
663 25 => .z25,
664 26 => .z26,
665 27 => .z27,
666 28 => .z28,
667 29 => .z29,
668 30 => .z30,
669 31 => .z31,
670 },
671 .predicate => switch (@as(u4, @intCast(@intFromEnum(enc)))) {
672 0 => .p0,
673 1 => .p1,
674 2 => .p2,
675 3 => .p3,
676 4 => .p4,
677 5 => .p5,
678 6 => .p6,
679 7 => .p7,
680 8 => .p8,
681 9 => .p9,
682 10 => .p10,
683 11 => .p11,
684 12 => .p12,
685 13 => .p13,
686 14 => .p14,
687 15 => .p15,
688 },
689 };401 };
690 }402 }
691 };403 };
...@@ -789,97 +501,105 @@ pub const Register = struct {...@@ -789,97 +501,105 @@ pub const Register = struct {
789 pub const fp: Alias = .r29;501 pub const fp: Alias = .r29;
790 pub const lr: Alias = .r30;502 pub const lr: Alias = .r30;
791503
504 pub fn alias(ra: Alias, fa: Format.Alias) Register {
505 switch (fa) {
506 .general => assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp)),
507 .other => switch (ra) {
508 else => unreachable,
509 .pc, .fpcr, .fpsr, .ffr => {},
510 },
511 .vector => assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31)),
512 .predicate => assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15)),
513 }
514 return .{ .alias = ra, .format = .{ .alias = fa } };
515 }
516 pub fn general(ra: Alias, gs: GeneralSize) Register {
517 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));
518 return .{ .alias = ra, .format = .{ .general = gs } };
519 }
520 pub fn scalar(ra: Alias, ss: ScalarSize) Register {
521 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
522 return .{ .alias = ra, .format = .{ .scalar = ss } };
523 }
524 pub fn vector(ra: Alias, arrangement: Arrangement) Register {
525 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
526 return .{ .alias = ra, .format = .{ .vector = arrangement } };
527 }
528 pub fn element(ra: Alias, ss: ScalarSize, index: u4) Register {
529 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
530 return .{ .alias = ra, .format = .{ .element = .{ .size = ss, .index = index } } };
531 }
532 pub fn z(ra: Alias) Register {
533 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
534 return .{ .alias = ra, .format = .scalable };
535 }
536 pub fn p(ra: Alias) Register {
537 assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15));
538 return .{ .alias = ra, .format = .{ .scalar = .predicate } };
539 }
540
792 pub fn r(ra: Alias) Register {541 pub fn r(ra: Alias) Register {
793 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.pc));542 return ra.alias(.general);
794 return .{ .alias = ra, .format = .alias };
795 }543 }
796 pub fn x(ra: Alias) Register {544 pub fn x(ra: Alias) Register {
797 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));545 return ra.general(.doubleword);
798 return .{ .alias = ra, .format = .{ .integer = .doubleword } };
799 }546 }
800 pub fn w(ra: Alias) Register {547 pub fn w(ra: Alias) Register {
801 assert(@intFromEnum(ra) >= @intFromEnum(Alias.r0) and @intFromEnum(ra) <= @intFromEnum(Alias.sp));548 return ra.general(.word);
802 return .{ .alias = ra, .format = .{ .integer = .word } };
803 }549 }
804 pub fn v(ra: Alias) Register {550 pub fn v(ra: Alias) Register {
805 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));551 return ra.alias(.vector);
806 return .{ .alias = ra, .format = .alias };
807 }552 }
808 pub fn q(ra: Alias) Register {553 pub fn q(ra: Alias) Register {
809 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));554 return ra.scalar(.quad);
810 return .{ .alias = ra, .format = .{ .scalar = .quad } };
811 }555 }
812 pub fn d(ra: Alias) Register {556 pub fn d(ra: Alias) Register {
813 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));557 return ra.scalar(.double);
814 return .{ .alias = ra, .format = .{ .scalar = .double } };
815 }558 }
816 pub fn s(ra: Alias) Register {559 pub fn s(ra: Alias) Register {
817 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));560 return ra.scalar(.single);
818 return .{ .alias = ra, .format = .{ .scalar = .single } };
819 }561 }
820 pub fn h(ra: Alias) Register {562 pub fn h(ra: Alias) Register {
821 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));563 return ra.scalar(.half);
822 return .{ .alias = ra, .format = .{ .scalar = .half } };
823 }564 }
824 pub fn b(ra: Alias) Register {565 pub fn b(ra: Alias) Register {
825 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));566 return ra.scalar(.byte);
826 return .{ .alias = ra, .format = .{ .scalar = .byte } };
827 }
828 pub fn z(ra: Alias) Register {
829 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));
830 return .{ .alias = ra, .format = .{ .scalar = .scalable } };
831 }
832 pub fn p(ra: Alias) Register {
833 assert(@intFromEnum(ra) >= @intFromEnum(Alias.p0) and @intFromEnum(ra) <= @intFromEnum(Alias.p15));
834 return .{ .alias = ra, .format = .{ .scalar = .predicate } };
835 }567 }
836 pub fn @"2d"(ra: Alias) Register {568 pub fn @"2d"(ra: Alias) Register {
837 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));569 return ra.vector(.@"2d");
838 return .{ .alias = ra, .format = .{ .vector = .@"2d" } };
839 }570 }
840 pub fn @"4s"(ra: Alias) Register {571 pub fn @"4s"(ra: Alias) Register {
841 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));572 return ra.vector(.@"4s");
842 return .{ .alias = ra, .format = .{ .vector = .@"4s" } };
843 }573 }
844 pub fn @"8h"(ra: Alias) Register {574 pub fn @"8h"(ra: Alias) Register {
845 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));575 return ra.vector(.@"8h");
846 return .{ .alias = ra, .format = .{ .vector = .@"8h" } };
847 }576 }
848 pub fn @"16b"(ra: Alias) Register {577 pub fn @"16b"(ra: Alias) Register {
849 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));578 return ra.vector(.@"16b");
850 return .{ .alias = ra, .format = .{ .vector = .@"16b" } };
851 }579 }
852 pub fn @"1d"(ra: Alias) Register {580 pub fn @"1d"(ra: Alias) Register {
853 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));581 return ra.vector(.@"1d");
854 return .{ .alias = ra, .format = .{ .vector = .@"1d" } };
855 }582 }
856 pub fn @"2s"(ra: Alias) Register {583 pub fn @"2s"(ra: Alias) Register {
857 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));584 return ra.vector(.@"2s");
858 return .{ .alias = ra, .format = .{ .vector = .@"2s" } };
859 }585 }
860 pub fn @"4h"(ra: Alias) Register {586 pub fn @"4h"(ra: Alias) Register {
861 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));587 return ra.vector(.@"4h");
862 return .{ .alias = ra, .format = .{ .vector = .@"4h" } };
863 }588 }
864 pub fn @"8b"(ra: Alias) Register {589 pub fn @"8b"(ra: Alias) Register {
865 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));590 return ra.vector(.@"8b");
866 return .{ .alias = ra, .format = .{ .vector = .@"8b" } };
867 }591 }
868 pub fn @"d[]"(ra: Alias, index: u1) Register {592 pub fn @"d[]"(ra: Alias, index: u1) Register {
869 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));593 return ra.element(.double, index);
870 return .{ .alias = ra, .format = .{ .element = .{ .size = .double, .index = index } } };
871 }594 }
872 pub fn @"s[]"(ra: Alias, index: u2) Register {595 pub fn @"s[]"(ra: Alias, index: u2) Register {
873 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));596 return ra.element(.single, index);
874 return .{ .alias = ra, .format = .{ .element = .{ .size = .single, .index = index } } };
875 }597 }
876 pub fn @"h[]"(ra: Alias, index: u3) Register {598 pub fn @"h[]"(ra: Alias, index: u3) Register {
877 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));599 return ra.element(.half, index);
878 return .{ .alias = ra, .format = .{ .element = .{ .size = .half, .index = index } } };
879 }600 }
880 pub fn @"b[]"(ra: Alias, index: u4) Register {601 pub fn @"b[]"(ra: Alias, index: u4) Register {
881 assert(@intFromEnum(ra) >= @intFromEnum(Alias.v0) and @intFromEnum(ra) <= @intFromEnum(Alias.v31));602 return ra.element(.byte, index);
882 return .{ .alias = ra, .format = .{ .element = .{ .size = .byte, .index = index } } };
883 }603 }
884604
885 pub fn isVector(ra: Alias) bool {605 pub fn isVector(ra: Alias) bool {
...@@ -1061,23 +781,23 @@ pub const Register = struct {...@@ -1061,23 +781,23 @@ pub const Register = struct {
1061 pub fn size(reg: Register) ?u5 {781 pub fn size(reg: Register) ?u5 {
1062 return format: switch (reg.format) {782 return format: switch (reg.format) {
1063 .alias => unreachable,783 .alias => unreachable,
1064 .integer => |sf| switch (sf) {784 .general => |sf| switch (sf) {
1065 .word => 4,785 .word => 4,
1066 .doubleword => 8,786 .doubleword => 8,
1067 },787 },
1068 .vector => |vs| switch (vs) {788 .scalar => |elem_size| switch (elem_size) {
1069 .byte => 1,789 .byte => 1,
1070 .word => 2,790 .half => 2,
1071 .single => 4,791 .single => 4,
1072 .double => 8,792 .double => 8,
1073 .quad => 16,793 .quad => 16,
1074 .scalable, .predicate => null,
1075 },794 },
1076 .arrangement => |arrangement| switch (arrangement) {795 .vector => |arrangement| switch (arrangement) {
1077 .@"2d", .@"4s", .@"8h", .@"16b" => 16,796 .@"2d", .@"4s", .@"8h", .@"16b" => 16,
1078 .@"1d", .@"2s", .@"4h", .@"8b" => 8,797 .@"1d", .@"2s", .@"4h", .@"8b" => 8,
1079 },798 },
1080 .element => |element| continue :format .{ .vector = element.size },799 .element => |element| continue :format .{ .scalar = element.size },
800 .scalable => null,
1081 };801 };
1082 }802 }
1083803
...@@ -1087,21 +807,21 @@ pub const Register = struct {...@@ -1087,21 +807,21 @@ pub const Register = struct {
1087 'r' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {807 'r' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1088 0...30 => .{808 0...30 => .{
1089 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),809 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1090 .format = .alias,810 .format = .{ .alias = .general },
1091 },811 },
1092 31 => null,812 31 => null,
1093 } else |_| null,813 } else |_| null,
1094 'x' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {814 'x' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1095 0...30 => .{815 0...30 => .{
1096 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),816 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1097 .format = .{ .integer = .doubleword },817 .format = .{ .general = .doubleword },
1098 },818 },
1099 31 => null,819 31 => null,
1100 } else |_| if (toLowerEqlAssertLower(reg, "xzr")) .xzr else null,820 } else |_| if (toLowerEqlAssertLower(reg, "xzr")) .xzr else null,
1101 'w' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {821 'w' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| switch (n) {
1102 0...30 => .{822 0...30 => .{
1103 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),823 .alias = @enumFromInt(@intFromEnum(Alias.r0) + n),
1104 .format = .{ .integer = .word },824 .format = .{ .general = .word },
1105 },825 },
1106 31 => null,826 31 => null,
1107 } else |_| if (toLowerEqlAssertLower(reg, "wzr"))827 } else |_| if (toLowerEqlAssertLower(reg, "wzr"))
...@@ -1120,7 +840,7 @@ pub const Register = struct {...@@ -1120,7 +840,7 @@ pub const Register = struct {
1120 'p' => return if (toLowerEqlAssertLower(reg, "pc")) .pc else null,840 'p' => return if (toLowerEqlAssertLower(reg, "pc")) .pc else null,
1121 'v' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{841 'v' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{
1122 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),842 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),
1123 .format = .alias,843 .format = .{ .alias = .vector },
1124 } else |_| null,844 } else |_| null,
1125 'q' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{845 'q' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .{
1126 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),846 .alias = @enumFromInt(@intFromEnum(Alias.v0) + n),
...@@ -1788,6 +1508,17 @@ pub const Instruction = packed union {...@@ -1788,6 +1508,17 @@ pub const Instruction = packed union {
1788 adr = 0b0,1508 adr = 0b0,
1789 adrp = 0b1,1509 adrp = 0b1,
1790 };1510 };
1511
1512 pub const Decoded = union(enum) {
1513 adr: Adr,
1514 adrp: Adrp,
1515 };
1516 pub fn decode(inst: @This()) @This().Decoded {
1517 return switch (inst.group.op) {
1518 .adr => .{ .adr = inst.adr },
1519 .adrp => .{ .adrp = inst.adrp },
1520 };
1521 }
1791 };1522 };
17921523
1793 /// Add/subtract (immediate)1524 /// Add/subtract (immediate)
...@@ -1806,7 +1537,7 @@ pub const Instruction = packed union {...@@ -1806,7 +1537,7 @@ pub const Instruction = packed union {
1806 decoded23: u6 = 0b100010,1537 decoded23: u6 = 0b100010,
1807 S: bool,1538 S: bool,
1808 op: AddSubtractOp,1539 op: AddSubtractOp,
1809 sf: Register.IntegerSize,1540 sf: Register.GeneralSize,
1810 };1541 };
18111542
1812 /// C6.2.4 ADD (immediate)1543 /// C6.2.4 ADD (immediate)
...@@ -1818,7 +1549,7 @@ pub const Instruction = packed union {...@@ -1818,7 +1549,7 @@ pub const Instruction = packed union {
1818 decoded23: u6 = 0b100010,1549 decoded23: u6 = 0b100010,
1819 S: bool = false,1550 S: bool = false,
1820 op: AddSubtractOp = .add,1551 op: AddSubtractOp = .add,
1821 sf: Register.IntegerSize,1552 sf: Register.GeneralSize,
1822 };1553 };
18231554
1824 /// C6.2.8 ADDS (immediate)1555 /// C6.2.8 ADDS (immediate)
...@@ -1830,7 +1561,7 @@ pub const Instruction = packed union {...@@ -1830,7 +1561,7 @@ pub const Instruction = packed union {
1830 decoded23: u6 = 0b100010,1561 decoded23: u6 = 0b100010,
1831 S: bool = true,1562 S: bool = true,
1832 op: AddSubtractOp = .add,1563 op: AddSubtractOp = .add,
1833 sf: Register.IntegerSize,1564 sf: Register.GeneralSize,
1834 };1565 };
18351566
1836 /// C6.2.357 SUB (immediate)1567 /// C6.2.357 SUB (immediate)
...@@ -1842,7 +1573,7 @@ pub const Instruction = packed union {...@@ -1842,7 +1573,7 @@ pub const Instruction = packed union {
1842 decoded23: u6 = 0b100010,1573 decoded23: u6 = 0b100010,
1843 S: bool = false,1574 S: bool = false,
1844 op: AddSubtractOp = .sub,1575 op: AddSubtractOp = .sub,
1845 sf: Register.IntegerSize,1576 sf: Register.GeneralSize,
1846 };1577 };
18471578
1848 /// C6.2.363 SUBS (immediate)1579 /// C6.2.363 SUBS (immediate)
...@@ -1854,18 +1585,39 @@ pub const Instruction = packed union {...@@ -1854,18 +1585,39 @@ pub const Instruction = packed union {
1854 decoded23: u6 = 0b100010,1585 decoded23: u6 = 0b100010,
1855 S: bool = true,1586 S: bool = true,
1856 op: AddSubtractOp = .sub,1587 op: AddSubtractOp = .sub,
1857 sf: Register.IntegerSize,1588 sf: Register.GeneralSize,
1858 };1589 };
18591590
1860 pub const Shift = enum(u1) {1591 pub const Shift = enum(u1) {
1861 @"0" = 0b0,1592 @"0" = 0b0,
1862 @"12" = 0b1,1593 @"12" = 0b1,
1863 };1594 };
1595
1596 pub const Decoded = union(enum) {
1597 add: Add,
1598 adds: Adds,
1599 sub: Sub,
1600 subs: Subs,
1601 };
1602 pub fn decode(inst: @This()) @This().Decaded {
1603 return switch (inst.group.op) {
1604 .add => switch (inst.group.S) {
1605 false => .{ .add = inst.add },
1606 true => .{ .addc = inst.addc },
1607 },
1608 .sub => switch (inst.group.S) {
1609 false => .{ .sub = inst.sub },
1610 true => .{ .subc = inst.subc },
1611 },
1612 };
1613 }
1864 };1614 };
18651615
1866 /// Add/subtract (immediate, with tags)1616 /// Add/subtract (immediate, with tags)
1867 pub const AddSubtractImmediateWithTags = packed union {1617 pub const AddSubtractImmediateWithTags = packed union {
1868 group: @This().Group,1618 group: @This().Group,
1619 addg: Addg,
1620 subg: Subg,
18691621
1870 pub const Group = packed struct {1622 pub const Group = packed struct {
1871 Rd: Register.Encoded,1623 Rd: Register.Encoded,
...@@ -1877,8 +1629,57 @@ pub const Instruction = packed union {...@@ -1877,8 +1629,57 @@ pub const Instruction = packed union {
1877 decoded23: u6 = 0b100011,1629 decoded23: u6 = 0b100011,
1878 S: bool,1630 S: bool,
1879 op: AddSubtractOp,1631 op: AddSubtractOp,
1880 sf: Register.IntegerSize,1632 sf: Register.GeneralSize,
1633 };
1634
1635 /// C6.2.6 ADDG
1636 pub const Addg = packed struct {
1637 Xd: Register.Encoded,
1638 Xn: Register.Encoded,
1639 uimm4: u4,
1640 op3: u2 = 0b00,
1641 uimm6: u6,
1642 o2: u1 = 0b0,
1643 decoded23: u6 = 0b100011,
1644 S: bool = false,
1645 op: AddSubtractOp = .add,
1646 sf: Register.GeneralSize = .doubleword,
1647 };
1648
1649 /// C6.2.359 SUBG
1650 pub const Subg = packed struct {
1651 Xd: Register.Encoded,
1652 Xn: Register.Encoded,
1653 uimm4: u4,
1654 op3: u2 = 0b00,
1655 uimm6: u6,
1656 o2: u1 = 0b0,
1657 decoded23: u6 = 0b100011,
1658 S: bool = false,
1659 op: AddSubtractOp = .sub,
1660 sf: Register.GeneralSize = .doubleword,
1661 };
1662
1663 pub const Decoded = union(enum) {
1664 unallocated,
1665 addg: Addg,
1666 subg: Subg,
1881 };1667 };
1668 pub fn decode(inst: @This()) @This().Decoded {
1669 return switch (inst.group.o2) {
1670 0b1 => .unallocated,
1671 0b0 => switch (inst.group.sf) {
1672 .word => .unallocated,
1673 .doubleword => switch (inst.group.S) {
1674 true => .unallocated,
1675 false => switch (inst.group.op) {
1676 .add => .{ .addg = inst.addg },
1677 .sub => .{ .subg = inst.subg },
1678 },
1679 },
1680 },
1681 };
1682 }
1882 };1683 };
18831684
1884 /// Logical (immediate)1685 /// Logical (immediate)
...@@ -1895,7 +1696,7 @@ pub const Instruction = packed union {...@@ -1895,7 +1696,7 @@ pub const Instruction = packed union {
1895 imm: Bitmask,1696 imm: Bitmask,
1896 decoded23: u6 = 0b100100,1697 decoded23: u6 = 0b100100,
1897 opc: LogicalOpc,1698 opc: LogicalOpc,
1898 sf: Register.IntegerSize,1699 sf: Register.GeneralSize,
1899 };1700 };
19001701
1901 /// C6.2.12 AND (immediate)1702 /// C6.2.12 AND (immediate)
...@@ -1905,7 +1706,7 @@ pub const Instruction = packed union {...@@ -1905,7 +1706,7 @@ pub const Instruction = packed union {
1905 imm: Bitmask,1706 imm: Bitmask,
1906 decoded23: u6 = 0b100100,1707 decoded23: u6 = 0b100100,
1907 opc: LogicalOpc = .@"and",1708 opc: LogicalOpc = .@"and",
1908 sf: Register.IntegerSize,1709 sf: Register.GeneralSize,
1909 };1710 };
19101711
1911 /// C6.2.240 ORR (immediate)1712 /// C6.2.240 ORR (immediate)
...@@ -1915,7 +1716,7 @@ pub const Instruction = packed union {...@@ -1915,7 +1716,7 @@ pub const Instruction = packed union {
1915 imm: Bitmask,1716 imm: Bitmask,
1916 decoded23: u6 = 0b100100,1717 decoded23: u6 = 0b100100,
1917 opc: LogicalOpc = .orr,1718 opc: LogicalOpc = .orr,
1918 sf: Register.IntegerSize,1719 sf: Register.GeneralSize,
1919 };1720 };
19201721
1921 /// C6.2.119 EOR (immediate)1722 /// C6.2.119 EOR (immediate)
...@@ -1925,7 +1726,7 @@ pub const Instruction = packed union {...@@ -1925,7 +1726,7 @@ pub const Instruction = packed union {
1925 imm: Bitmask,1726 imm: Bitmask,
1926 decoded23: u6 = 0b100100,1727 decoded23: u6 = 0b100100,
1927 opc: LogicalOpc = .eor,1728 opc: LogicalOpc = .eor,
1928 sf: Register.IntegerSize,1729 sf: Register.GeneralSize,
1929 };1730 };
19301731
1931 /// C6.2.14 ANDS (immediate)1732 /// C6.2.14 ANDS (immediate)
...@@ -1935,7 +1736,7 @@ pub const Instruction = packed union {...@@ -1935,7 +1736,7 @@ pub const Instruction = packed union {
1935 imm: Bitmask,1736 imm: Bitmask,
1936 decoded23: u6 = 0b100100,1737 decoded23: u6 = 0b100100,
1937 opc: LogicalOpc = .ands,1738 opc: LogicalOpc = .ands,
1938 sf: Register.IntegerSize,1739 sf: Register.GeneralSize,
1939 };1740 };
19401741
1941 pub const Decoded = union(enum) {1742 pub const Decoded = union(enum) {
...@@ -1970,7 +1771,7 @@ pub const Instruction = packed union {...@@ -1970,7 +1771,7 @@ pub const Instruction = packed union {
1970 hw: Hw,1771 hw: Hw,
1971 decoded23: u6 = 0b100101,1772 decoded23: u6 = 0b100101,
1972 opc: Opc,1773 opc: Opc,
1973 sf: Register.IntegerSize,1774 sf: Register.GeneralSize,
1974 };1775 };
19751776
1976 /// C6.2.226 MOVN1777 /// C6.2.226 MOVN
...@@ -1980,7 +1781,7 @@ pub const Instruction = packed union {...@@ -1980,7 +1781,7 @@ pub const Instruction = packed union {
1980 hw: Hw,1781 hw: Hw,
1981 decoded23: u6 = 0b100101,1782 decoded23: u6 = 0b100101,
1982 opc: Opc = .movn,1783 opc: Opc = .movn,
1983 sf: Register.IntegerSize,1784 sf: Register.GeneralSize,
1984 };1785 };
19851786
1986 /// C6.2.227 MOVZ1787 /// C6.2.227 MOVZ
...@@ -1990,7 +1791,7 @@ pub const Instruction = packed union {...@@ -1990,7 +1791,7 @@ pub const Instruction = packed union {
1990 hw: Hw,1791 hw: Hw,
1991 decoded23: u6 = 0b100101,1792 decoded23: u6 = 0b100101,
1992 opc: Opc = .movz,1793 opc: Opc = .movz,
1993 sf: Register.IntegerSize,1794 sf: Register.GeneralSize,
1994 };1795 };
19951796
1996 /// C6.2.225 MOVK1797 /// C6.2.225 MOVK
...@@ -2000,7 +1801,7 @@ pub const Instruction = packed union {...@@ -2000,7 +1801,7 @@ pub const Instruction = packed union {
2000 hw: Hw,1801 hw: Hw,
2001 decoded23: u6 = 0b100101,1802 decoded23: u6 = 0b100101,
2002 opc: Opc = .movk,1803 opc: Opc = .movk,
2003 sf: Register.IntegerSize,1804 sf: Register.GeneralSize,
2004 };1805 };
20051806
2006 pub const Hw = enum(u2) {1807 pub const Hw = enum(u2) {
...@@ -2018,7 +1819,7 @@ pub const Instruction = packed union {...@@ -2018,7 +1819,7 @@ pub const Instruction = packed union {
2018 };1819 };
2019 }1820 }
20201821
2021 pub fn sf(hw: Hw) Register.IntegerSize {1822 pub fn sf(hw: Hw) Register.GeneralSize {
2022 return switch (hw) {1823 return switch (hw) {
2023 .@"0", .@"16" => .word,1824 .@"0", .@"16" => .word,
2024 .@"32", .@"48" => .doubleword,1825 .@"32", .@"48" => .doubleword,
...@@ -2064,7 +1865,7 @@ pub const Instruction = packed union {...@@ -2064,7 +1865,7 @@ pub const Instruction = packed union {
2064 imm: Bitmask,1865 imm: Bitmask,
2065 decoded23: u6 = 0b100110,1866 decoded23: u6 = 0b100110,
2066 opc: Opc,1867 opc: Opc,
2067 sf: Register.IntegerSize,1868 sf: Register.GeneralSize,
2068 };1869 };
20691870
2070 pub const Sbfm = packed struct {1871 pub const Sbfm = packed struct {
...@@ -2073,7 +1874,7 @@ pub const Instruction = packed union {...@@ -2073,7 +1874,7 @@ pub const Instruction = packed union {
2073 imm: Bitmask,1874 imm: Bitmask,
2074 decoded23: u6 = 0b100110,1875 decoded23: u6 = 0b100110,
2075 opc: Opc = .sbfm,1876 opc: Opc = .sbfm,
2076 sf: Register.IntegerSize,1877 sf: Register.GeneralSize,
2077 };1878 };
20781879
2079 pub const Bfm = packed struct {1880 pub const Bfm = packed struct {
...@@ -2082,7 +1883,7 @@ pub const Instruction = packed union {...@@ -2082,7 +1883,7 @@ pub const Instruction = packed union {
2082 imm: Bitmask,1883 imm: Bitmask,
2083 decoded23: u6 = 0b100110,1884 decoded23: u6 = 0b100110,
2084 opc: Opc = .bfm,1885 opc: Opc = .bfm,
2085 sf: Register.IntegerSize,1886 sf: Register.GeneralSize,
2086 };1887 };
20871888
2088 pub const Ubfm = packed struct {1889 pub const Ubfm = packed struct {
...@@ -2091,7 +1892,7 @@ pub const Instruction = packed union {...@@ -2091,7 +1892,7 @@ pub const Instruction = packed union {
2091 imm: Bitmask,1892 imm: Bitmask,
2092 decoded23: u6 = 0b100110,1893 decoded23: u6 = 0b100110,
2093 opc: Opc = .ubfm,1894 opc: Opc = .ubfm,
2094 sf: Register.IntegerSize,1895 sf: Register.GeneralSize,
2095 };1896 };
20961897
2097 pub const Opc = enum(u2) {1898 pub const Opc = enum(u2) {
...@@ -2130,10 +1931,10 @@ pub const Instruction = packed union {...@@ -2130,10 +1931,10 @@ pub const Instruction = packed union {
2130 imms: u6,1931 imms: u6,
2131 Rm: Register.Encoded,1932 Rm: Register.Encoded,
2132 o0: u1,1933 o0: u1,
2133 N: Register.IntegerSize,1934 N: Register.GeneralSize,
2134 decoded23: u6 = 0b100111,1935 decoded23: u6 = 0b100111,
2135 op21: u2,1936 op21: u2,
2136 sf: Register.IntegerSize,1937 sf: Register.GeneralSize,
2137 };1938 };
21381939
2139 pub const Extr = packed struct {1940 pub const Extr = packed struct {
...@@ -2142,10 +1943,10 @@ pub const Instruction = packed union {...@@ -2142,10 +1943,10 @@ pub const Instruction = packed union {
2142 imms: u6,1943 imms: u6,
2143 Rm: Register.Encoded,1944 Rm: Register.Encoded,
2144 o0: u1 = 0b0,1945 o0: u1 = 0b0,
2145 N: Register.IntegerSize,1946 N: Register.GeneralSize,
2146 decoded23: u6 = 0b100111,1947 decoded23: u6 = 0b100111,
2147 op21: u2 = 0b00,1948 op21: u2 = 0b00,
2148 sf: Register.IntegerSize,1949 sf: Register.GeneralSize,
2149 };1950 };
21501951
2151 pub const Decoded = union(enum) {1952 pub const Decoded = union(enum) {
...@@ -2170,22 +1971,22 @@ pub const Instruction = packed union {...@@ -2170,22 +1971,22 @@ pub const Instruction = packed union {
2170 pub const Bitmask = packed struct {1971 pub const Bitmask = packed struct {
2171 imms: u6,1972 imms: u6,
2172 immr: u6,1973 immr: u6,
2173 N: Register.IntegerSize,1974 N: Register.GeneralSize,
21741975
2175 fn lenHsb(bitmask: Bitmask) u7 {1976 fn lenHsb(bitmask: Bitmask) u7 {
2176 return @bitCast(packed struct {1977 return @bitCast(packed struct {
2177 not_imms: u6,1978 not_imms: u6,
2178 N: Register.IntegerSize,1979 N: Register.GeneralSize,
2179 }{ .not_imms = ~bitmask.imms, .N = bitmask.N });1980 }{ .not_imms = ~bitmask.imms, .N = bitmask.N });
2180 }1981 }
21811982
2182 fn validImmediate(bitmask: Bitmask, sf: Register.IntegerSize) bool {1983 fn validImmediate(bitmask: Bitmask, sf: Register.GeneralSize) bool {
2183 if (sf == .word and bitmask.N == .doubleword) return false;1984 if (sf == .word and bitmask.N == .doubleword) return false;
2184 const len_hsb = bitmask.lenHsb();1985 const len_hsb = bitmask.lenHsb();
2185 return (len_hsb -% 1) & len_hsb != 0b0_000000;1986 return (len_hsb -% 1) & len_hsb != 0b0_000000;
2186 }1987 }
21871988
2188 fn validBitfield(bitmask: Bitmask, sf: Register.IntegerSize) bool {1989 fn validBitfield(bitmask: Bitmask, sf: Register.GeneralSize) bool {
2189 if (sf != bitmask.N) return false;1990 if (sf != bitmask.N) return false;
2190 if (sf == .word and (@as(u1, @truncate(bitmask.immr >> 5)) != 0b0 or1991 if (sf == .word and (@as(u1, @truncate(bitmask.immr >> 5)) != 0b0 or
2191 @as(u1, @truncate(bitmask.imms >> 5)) != 0b0)) return false;1992 @as(u1, @truncate(bitmask.imms >> 5)) != 0b0)) return false;
...@@ -2193,7 +1994,7 @@ pub const Instruction = packed union {...@@ -2193,7 +1994,7 @@ pub const Instruction = packed union {
2193 return len_hsb >= 0b0_000010;1994 return len_hsb >= 0b0_000010;
2194 }1995 }
21951996
2196 fn decode(bitmask: Bitmask, sf: Register.IntegerSize) struct { u64, u64 } {1997 fn decode(bitmask: Bitmask, sf: Register.GeneralSize) struct { u64, u64 } {
2197 const esize = @as(u7, 1 << 6) >> @clz(bitmask.lenHsb());1998 const esize = @as(u7, 1 << 6) >> @clz(bitmask.lenHsb());
2198 const levels: u6 = @intCast(esize - 1);1999 const levels: u6 = @intCast(esize - 1);
2199 const s = bitmask.imms & levels;2000 const s = bitmask.imms & levels;
...@@ -2211,18 +2012,18 @@ pub const Instruction = packed union {...@@ -2211,18 +2012,18 @@ pub const Instruction = packed union {
2211 };2012 };
2212 }2013 }
22132014
2214 pub fn decodeImmediate(bitmask: Bitmask, sf: Register.IntegerSize) u64 {2015 pub fn decodeImmediate(bitmask: Bitmask, sf: Register.GeneralSize) u64 {
2215 assert(bitmask.validImmediate(sf));2016 assert(bitmask.validImmediate(sf));
2216 const imm, _ = bitmask.decode(sf);2017 const imm, _ = bitmask.decode(sf);
2217 return imm;2018 return imm;
2218 }2019 }
22192020
2220 pub fn decodeBitfield(bitmask: Bitmask, sf: Register.IntegerSize) struct { u64, u64 } {2021 pub fn decodeBitfield(bitmask: Bitmask, sf: Register.GeneralSize) struct { u64, u64 } {
2221 assert(bitmask.validBitfield(sf));2022 assert(bitmask.validBitfield(sf));
2222 return bitmask.decode(sf);2023 return bitmask.decode(sf);
2223 }2024 }
22242025
2225 pub fn moveWidePreferred(bitmask: Bitmask, sf: Register.IntegerSize) bool {2026 pub fn moveWidePreferred(bitmask: Bitmask, sf: Register.GeneralSize) bool {
2226 const s = bitmask.imms;2027 const s = bitmask.imms;
2227 const r = bitmask.immr;2028 const r = bitmask.immr;
2228 const width: u7 = switch (sf) {2029 const width: u7 = switch (sf) {
...@@ -2646,7 +2447,7 @@ pub const Instruction = packed union {...@@ -2646,7 +2447,7 @@ pub const Instruction = packed union {
26462447
2647 /// C6.2.56 CLREX2448 /// C6.2.56 CLREX
2648 pub const Clrex = packed struct {2449 pub const Clrex = packed struct {
2649 Rt: Register.Encoded = @enumFromInt(0b11111),2450 Rt: Register.Encoded = no_reg,
2650 op2: u3 = 0b010,2451 op2: u3 = 0b010,
2651 CRm: u4,2452 CRm: u4,
2652 decoded12: u4 = 0b0011,2453 decoded12: u4 = 0b0011,
...@@ -2658,7 +2459,7 @@ pub const Instruction = packed union {...@@ -2658,7 +2459,7 @@ pub const Instruction = packed union {
26582459
2659 /// C6.2.116 DSB2460 /// C6.2.116 DSB
2660 pub const Dsb = packed struct {2461 pub const Dsb = packed struct {
2661 Rt: Register.Encoded = @enumFromInt(0b11111),2462 Rt: Register.Encoded = no_reg,
2662 opc: u2 = 0b00,2463 opc: u2 = 0b00,
2663 decoded7: u1 = 0b1,2464 decoded7: u1 = 0b1,
2664 CRm: Option,2465 CRm: Option,
...@@ -2671,7 +2472,7 @@ pub const Instruction = packed union {...@@ -2671,7 +2472,7 @@ pub const Instruction = packed union {
26712472
2672 /// C6.2.114 DMB2473 /// C6.2.114 DMB
2673 pub const Dmb = packed struct {2474 pub const Dmb = packed struct {
2674 Rt: Register.Encoded = @enumFromInt(0b11111),2475 Rt: Register.Encoded = no_reg,
2675 opc: u2 = 0b01,2476 opc: u2 = 0b01,
2676 decoded7: u1 = 0b1,2477 decoded7: u1 = 0b1,
2677 CRm: Option,2478 CRm: Option,
...@@ -2684,7 +2485,7 @@ pub const Instruction = packed union {...@@ -2684,7 +2485,7 @@ pub const Instruction = packed union {
26842485
2685 /// C6.2.131 ISB2486 /// C6.2.131 ISB
2686 pub const Isb = packed struct {2487 pub const Isb = packed struct {
2687 Rt: Register.Encoded = @enumFromInt(0b11111),2488 Rt: Register.Encoded = no_reg,
2688 opc: u2 = 0b10,2489 opc: u2 = 0b10,
2689 decoded7: u1 = 0b1,2490 decoded7: u1 = 0b1,
2690 CRm: Option,2491 CRm: Option,
...@@ -2697,7 +2498,7 @@ pub const Instruction = packed union {...@@ -2697,7 +2498,7 @@ pub const Instruction = packed union {
26972498
2698 /// C6.2.264 SB2499 /// C6.2.264 SB
2699 pub const Sb = packed struct {2500 pub const Sb = packed struct {
2700 Rt: Register.Encoded = @enumFromInt(0b11111),2501 Rt: Register.Encoded = no_reg,
2701 opc: u2 = 0b11,2502 opc: u2 = 0b11,
2702 decoded7: u1 = 0b1,2503 decoded7: u1 = 0b1,
2703 CRm: u4 = 0b0000,2504 CRm: u4 = 0b0000,
...@@ -2723,16 +2524,115 @@ pub const Instruction = packed union {...@@ -2723,16 +2524,115 @@ pub const Instruction = packed union {
2723 sy = 0b1111,2524 sy = 0b1111,
2724 _,2525 _,
2725 };2526 };
2527
2528 pub const Decoded = union(enum) {
2529 unallocated,
2530 clrex: Clrex,
2531 dsb: Dsb,
2532 dmb: Dmb,
2533 isb: Isb,
2534 sb: Sb,
2535 };
2536 pub fn decode(inst: @This()) @This().Decoded {
2537 return switch (inst.group.op2) {
2538 0b000, 0b001 => .unallocated,
2539 0b010 => switch (inst.group.Rt) {
2540 no_reg => .{ .clrex = inst.clrex },
2541 else => .unallocated,
2542 },
2543 0b100 => switch (inst.group.Rt) {
2544 no_reg => .{ .dsb = inst.dsb },
2545 else => .unallocated,
2546 },
2547 0b101 => switch (inst.group.Rt) {
2548 no_reg => .{ .dmb = inst.dmb },
2549 else => .unallocated,
2550 },
2551 0b110 => switch (inst.group.Rt) {
2552 no_reg => .{ .isb = inst.isb },
2553 else => .unallocated,
2554 },
2555 0b111 => switch (inst.group.Rt) {
2556 no_reg => .{ .sb = inst.sb },
2557 else => .unallocated,
2558 },
2559 };
2560 }
2726 };2561 };
27272562
2728 /// PSTATE2563 /// PSTATE
2729 pub const Pstate = packed struct {2564 pub const Pstate = packed union {
2730 Rt: Register.Encoded,2565 group: @This().Group,
2731 op2: u3,2566
2732 CRm: u4,2567 pub const Group = packed struct {
2733 decoded12: u4 = 0b0100,2568 Rt: Register.Encoded,
2734 op1: u3,2569 op2: u3,
2735 decoded19: u13 = 0b1101010100000,2570 CRm: u4,
2571 decoded12: u4 = 0b0100,
2572 op1: u3,
2573 decoded19: u13 = 0b1101010100000,
2574 };
2575
2576 /// C6.2.229 MSR (immediate)
2577 pub const Msr = packed struct {
2578 Rt: Register.Encoded = no_reg,
2579 op2: u3,
2580 CRm: u4,
2581 decoded12: u4 = 0b0100,
2582 op1: u3,
2583 decoded19: u13 = 0b1101010100000,
2584 };
2585
2586 /// C6.2.52 CFINV
2587 pub const Cfinv = packed struct {
2588 Rt: Register.Encoded = no_reg,
2589 op2: u3 = 0b000,
2590 CRm: u4 = 0b0000,
2591 decoded12: u4 = 0b0100,
2592 op1: u3 = 0b000,
2593 decoded19: u13 = 0b1101010100000,
2594 };
2595
2596 /// C6.2.400 XAFLAG
2597 pub const Xaflag = packed struct {
2598 Rt: Register.Encoded = no_reg,
2599 op2: u3 = 0b001,
2600 CRm: u4 = 0b0000,
2601 decoded12: u4 = 0b0100,
2602 op1: u3 = 0b000,
2603 decoded19: u13 = 0b1101010100000,
2604 };
2605
2606 /// C6.2.24 AXFLAG
2607 pub const Axflag = packed struct {
2608 Rt: Register.Encoded = no_reg,
2609 op2: u3 = 0b010,
2610 CRm: u4 = 0b0000,
2611 decoded12: u4 = 0b0100,
2612 op1: u3 = 0b000,
2613 decoded19: u13 = 0b1101010100000,
2614 };
2615
2616 pub const Decoded = union(enum) {
2617 unallocated,
2618 cfinv: Cfinv,
2619 xaflag: Xaflag,
2620 axflag: Axflag,
2621 };
2622 pub fn decode(inst: @This()) @This().Decoded {
2623 return switch (inst.group.Rt) {
2624 else => .unallocated,
2625 no_reg => switch (inst.group.op1) {
2626 else => .{ .msr = inst.msr },
2627 0b000 => switch (inst.group.op2) {
2628 else => .{ .msr = inst.msr },
2629 0b000 => .{ .cfinv = inst.cfinv },
2630 0b001 => .{ .xaflag = inst.xaflag },
2631 0b010 => .{ .axflag = inst.axflag },
2632 },
2633 },
2634 };
2635 }
2736 };2636 };
27372637
2738 /// System with result2638 /// System with result
...@@ -2965,6 +2865,17 @@ pub const Instruction = packed union {...@@ -2965,6 +2865,17 @@ pub const Instruction = packed union {
2965 b = 0b0,2865 b = 0b0,
2966 bl = 0b1,2866 bl = 0b1,
2967 };2867 };
2868
2869 pub const Decoded = union(enum) {
2870 b: B,
2871 bl: Bl,
2872 };
2873 pub fn decode(inst: @This()) @This().Decoded {
2874 return switch (inst.group.op) {
2875 .b => .{ .b = inst.b },
2876 .bl => .{ .bl = inst.bl },
2877 };
2878 }
2968 };2879 };
29692880
2970 /// Compare and branch (immediate)2881 /// Compare and branch (immediate)
...@@ -2978,7 +2889,7 @@ pub const Instruction = packed union {...@@ -2978,7 +2889,7 @@ pub const Instruction = packed union {
2978 imm19: i19,2889 imm19: i19,
2979 op: Op,2890 op: Op,
2980 decoded25: u6 = 0b011010,2891 decoded25: u6 = 0b011010,
2981 sf: Register.IntegerSize,2892 sf: Register.GeneralSize,
2982 };2893 };
29832894
2984 /// C6.2.47 CBZ2895 /// C6.2.47 CBZ
...@@ -2987,7 +2898,7 @@ pub const Instruction = packed union {...@@ -2987,7 +2898,7 @@ pub const Instruction = packed union {
2987 imm19: i19,2898 imm19: i19,
2988 op: Op = .cbz,2899 op: Op = .cbz,
2989 decoded25: u6 = 0b011010,2900 decoded25: u6 = 0b011010,
2990 sf: Register.IntegerSize,2901 sf: Register.GeneralSize,
2991 };2902 };
29922903
2993 /// C6.2.46 CBNZ2904 /// C6.2.46 CBNZ
...@@ -2996,13 +2907,24 @@ pub const Instruction = packed union {...@@ -2996,13 +2907,24 @@ pub const Instruction = packed union {
2996 imm19: i19,2907 imm19: i19,
2997 op: Op = .cbnz,2908 op: Op = .cbnz,
2998 decoded25: u6 = 0b011010,2909 decoded25: u6 = 0b011010,
2999 sf: Register.IntegerSize,2910 sf: Register.GeneralSize,
3000 };2911 };
30012912
3002 pub const Op = enum(u1) {2913 pub const Op = enum(u1) {
3003 cbz = 0b0,2914 cbz = 0b0,
3004 cbnz = 0b1,2915 cbnz = 0b1,
3005 };2916 };
2917
2918 pub const Decoded = union(enum) {
2919 cbz: Cbz,
2920 cbnz: Cbnz,
2921 };
2922 pub fn decode(inst: @This()) @This().Decoded {
2923 return switch (inst.group.op) {
2924 .cbz => .{ .cbz = inst.cbz },
2925 .cbnz => .{ .cbnz = inst.cbnz },
2926 };
2927 }
3006 };2928 };
30072929
3008 /// Test and branch (immediate)2930 /// Test and branch (immediate)
...@@ -3044,8 +2966,21 @@ pub const Instruction = packed union {...@@ -3044,8 +2966,21 @@ pub const Instruction = packed union {
3044 tbz = 0b0,2966 tbz = 0b0,
3045 tbnz = 0b1,2967 tbnz = 0b1,
3046 };2968 };
2969
2970 pub const Decoded = union(enum) {
2971 tbz: Tbz,
2972 tbnz: Tbnz,
2973 };
2974 pub fn decode(inst: @This()) @This().Decoded {
2975 return switch (inst.group.op) {
2976 .tbz => .{ .tbz = inst.tbz },
2977 .tbnz => .{ .tbnz = inst.tbnz },
2978 };
2979 }
3047 };2980 };
30482981
2982 pub const no_reg: Register.Encoded = Register.Alias.zr.encode(.{});
2983
3049 pub const Decoded = union(enum) {2984 pub const Decoded = union(enum) {
3050 unallocated,2985 unallocated,
3051 conditional_branch_immediate: ConditionalBranchImmediate,2986 conditional_branch_immediate: ConditionalBranchImmediate,
...@@ -3168,7 +3103,7 @@ pub const Instruction = packed union {...@@ -3168,7 +3103,7 @@ pub const Instruction = packed union {
3168 decoded24: u2 = 0b00,3103 decoded24: u2 = 0b00,
3169 V: bool = false,3104 V: bool = false,
3170 decoded27: u3 = 0b011,3105 decoded27: u3 = 0b011,
3171 sf: Register.IntegerSize,3106 sf: Register.GeneralSize,
3172 opc1: u1 = 0b0,3107 opc1: u1 = 0b0,
3173 };3108 };
31743109
...@@ -3241,7 +3176,7 @@ pub const Instruction = packed union {...@@ -3241,7 +3176,7 @@ pub const Instruction = packed union {
3241 decoded24: u2 = 0b01,3176 decoded24: u2 = 0b01,
3242 o0: u1,3177 o0: u1,
3243 decoded27: u3 = 0b011,3178 decoded27: u3 = 0b011,
3244 size: IntegerSize,3179 size: Size,
3245 };3180 };
32463181
3247 /// Load/store no-allocate pair (offset)3182 /// Load/store no-allocate pair (offset)
...@@ -3304,7 +3239,7 @@ pub const Instruction = packed union {...@@ -3304,7 +3239,7 @@ pub const Instruction = packed union {
3304 V: bool = false,3239 V: bool = false,
3305 decoded27: u3 = 0b101,3240 decoded27: u3 = 0b101,
3306 opc0: u1 = 0b0,3241 opc0: u1 = 0b0,
3307 sf: Register.IntegerSize,3242 sf: Register.GeneralSize,
3308 };3243 };
33093244
3310 /// C6.2.164 LDP3245 /// C6.2.164 LDP
...@@ -3318,7 +3253,7 @@ pub const Instruction = packed union {...@@ -3318,7 +3253,7 @@ pub const Instruction = packed union {
3318 V: bool = false,3253 V: bool = false,
3319 decoded27: u3 = 0b101,3254 decoded27: u3 = 0b101,
3320 opc0: u1 = 0b0,3255 opc0: u1 = 0b0,
3321 sf: Register.IntegerSize,3256 sf: Register.GeneralSize,
3322 };3257 };
33233258
3324 /// C6.2.165 LDPSW3259 /// C6.2.165 LDPSW
...@@ -3473,7 +3408,7 @@ pub const Instruction = packed union {...@@ -3473,7 +3408,7 @@ pub const Instruction = packed union {
3473 V: bool = false,3408 V: bool = false,
3474 decoded27: u3 = 0b101,3409 decoded27: u3 = 0b101,
3475 opc0: u1 = 0b0,3410 opc0: u1 = 0b0,
3476 sf: Register.IntegerSize,3411 sf: Register.GeneralSize,
3477 };3412 };
34783413
3479 /// C6.2.164 LDP3414 /// C6.2.164 LDP
...@@ -3487,7 +3422,7 @@ pub const Instruction = packed union {...@@ -3487,7 +3422,7 @@ pub const Instruction = packed union {
3487 V: bool = false,3422 V: bool = false,
3488 decoded27: u3 = 0b101,3423 decoded27: u3 = 0b101,
3489 opc0: u1 = 0b0,3424 opc0: u1 = 0b0,
3490 sf: Register.IntegerSize,3425 sf: Register.GeneralSize,
3491 };3426 };
34923427
3493 /// C6.2.165 LDPSW3428 /// C6.2.165 LDPSW
...@@ -3642,7 +3577,7 @@ pub const Instruction = packed union {...@@ -3642,7 +3577,7 @@ pub const Instruction = packed union {
3642 V: bool = false,3577 V: bool = false,
3643 decoded27: u3 = 0b101,3578 decoded27: u3 = 0b101,
3644 opc0: u1 = 0b0,3579 opc0: u1 = 0b0,
3645 sf: Register.IntegerSize,3580 sf: Register.GeneralSize,
3646 };3581 };
36473582
3648 /// C6.2.164 LDP3583 /// C6.2.164 LDP
...@@ -3656,7 +3591,7 @@ pub const Instruction = packed union {...@@ -3656,7 +3591,7 @@ pub const Instruction = packed union {
3656 V: bool = false,3591 V: bool = false,
3657 decoded27: u3 = 0b101,3592 decoded27: u3 = 0b101,
3658 opc0: u1 = 0b0,3593 opc0: u1 = 0b0,
3659 sf: Register.IntegerSize,3594 sf: Register.GeneralSize,
3660 };3595 };
36613596
3662 /// C6.2.165 LDPSW3597 /// C6.2.165 LDPSW
...@@ -3806,7 +3741,7 @@ pub const Instruction = packed union {...@@ -3806,7 +3741,7 @@ pub const Instruction = packed union {
3806 decoded24: u2 = 0b00,3741 decoded24: u2 = 0b00,
3807 V: bool = false,3742 V: bool = false,
3808 decoded27: u3 = 0b111,3743 decoded27: u3 = 0b111,
3809 size: IntegerSize,3744 size: Size,
3810 };3745 };
38113746
3812 /// C6.2.347 STURB3747 /// C6.2.347 STURB
...@@ -3820,7 +3755,7 @@ pub const Instruction = packed union {...@@ -3820,7 +3755,7 @@ pub const Instruction = packed union {
3820 decoded24: u2 = 0b00,3755 decoded24: u2 = 0b00,
3821 V: bool = false,3756 V: bool = false,
3822 decoded27: u3 = 0b111,3757 decoded27: u3 = 0b111,
3823 size: IntegerSize = .byte,3758 size: Size = .byte,
3824 };3759 };
38253760
3826 /// C6.2.203 LDURB3761 /// C6.2.203 LDURB
...@@ -3834,7 +3769,7 @@ pub const Instruction = packed union {...@@ -3834,7 +3769,7 @@ pub const Instruction = packed union {
3834 decoded24: u2 = 0b00,3769 decoded24: u2 = 0b00,
3835 V: bool = false,3770 V: bool = false,
3836 decoded27: u3 = 0b111,3771 decoded27: u3 = 0b111,
3837 size: IntegerSize = .byte,3772 size: Size = .byte,
3838 };3773 };
38393774
3840 /// C6.2.205 LDURSB3775 /// C6.2.205 LDURSB
...@@ -3849,7 +3784,7 @@ pub const Instruction = packed union {...@@ -3849,7 +3784,7 @@ pub const Instruction = packed union {
3849 decoded24: u2 = 0b00,3784 decoded24: u2 = 0b00,
3850 V: bool = false,3785 V: bool = false,
3851 decoded27: u3 = 0b111,3786 decoded27: u3 = 0b111,
3852 size: IntegerSize = .byte,3787 size: Size = .byte,
3853 };3788 };
38543789
3855 /// C6.2.348 STURH3790 /// C6.2.348 STURH
...@@ -3863,7 +3798,7 @@ pub const Instruction = packed union {...@@ -3863,7 +3798,7 @@ pub const Instruction = packed union {
3863 decoded24: u2 = 0b00,3798 decoded24: u2 = 0b00,
3864 V: bool = false,3799 V: bool = false,
3865 decoded27: u3 = 0b111,3800 decoded27: u3 = 0b111,
3866 size: IntegerSize = .halfword,3801 size: Size = .halfword,
3867 };3802 };
38683803
3869 /// C6.2.204 LDURH3804 /// C6.2.204 LDURH
...@@ -3877,7 +3812,7 @@ pub const Instruction = packed union {...@@ -3877,7 +3812,7 @@ pub const Instruction = packed union {
3877 decoded24: u2 = 0b00,3812 decoded24: u2 = 0b00,
3878 V: bool = false,3813 V: bool = false,
3879 decoded27: u3 = 0b111,3814 decoded27: u3 = 0b111,
3880 size: IntegerSize = .halfword,3815 size: Size = .halfword,
3881 };3816 };
38823817
3883 /// C6.2.206 LDURSH3818 /// C6.2.206 LDURSH
...@@ -3892,7 +3827,7 @@ pub const Instruction = packed union {...@@ -3892,7 +3827,7 @@ pub const Instruction = packed union {
3892 decoded24: u2 = 0b00,3827 decoded24: u2 = 0b00,
3893 V: bool = false,3828 V: bool = false,
3894 decoded27: u3 = 0b111,3829 decoded27: u3 = 0b111,
3895 size: IntegerSize = .halfword,3830 size: Size = .halfword,
3896 };3831 };
38973832
3898 /// C6.2.346 STUR3833 /// C6.2.346 STUR
...@@ -3906,7 +3841,7 @@ pub const Instruction = packed union {...@@ -3906,7 +3841,7 @@ pub const Instruction = packed union {
3906 decoded24: u2 = 0b00,3841 decoded24: u2 = 0b00,
3907 V: bool = false,3842 V: bool = false,
3908 decoded27: u3 = 0b111,3843 decoded27: u3 = 0b111,
3909 sf: Register.IntegerSize,3844 sf: Register.GeneralSize,
3910 size1: u1 = 0b1,3845 size1: u1 = 0b1,
3911 };3846 };
39123847
...@@ -3921,7 +3856,7 @@ pub const Instruction = packed union {...@@ -3921,7 +3856,7 @@ pub const Instruction = packed union {
3921 decoded24: u2 = 0b00,3856 decoded24: u2 = 0b00,
3922 V: bool = false,3857 V: bool = false,
3923 decoded27: u3 = 0b111,3858 decoded27: u3 = 0b111,
3924 sf: Register.IntegerSize,3859 sf: Register.GeneralSize,
3925 size1: u1 = 0b1,3860 size1: u1 = 0b1,
3926 };3861 };
39273862
...@@ -3936,7 +3871,7 @@ pub const Instruction = packed union {...@@ -3936,7 +3871,7 @@ pub const Instruction = packed union {
3936 decoded24: u2 = 0b00,3871 decoded24: u2 = 0b00,
3937 V: bool = false,3872 V: bool = false,
3938 decoded27: u3 = 0b111,3873 decoded27: u3 = 0b111,
3939 size: IntegerSize = .word,3874 size: Size = .word,
3940 };3875 };
39413876
3942 /// C6.2.250 PRFUM3877 /// C6.2.250 PRFUM
...@@ -3950,7 +3885,7 @@ pub const Instruction = packed union {...@@ -3950,7 +3885,7 @@ pub const Instruction = packed union {
3950 decoded24: u2 = 0b00,3885 decoded24: u2 = 0b00,
3951 V: bool = false,3886 V: bool = false,
3952 decoded27: u3 = 0b111,3887 decoded27: u3 = 0b111,
3953 size: IntegerSize = .doubleword,3888 size: Size = .doubleword,
3954 };3889 };
39553890
3956 pub const Decoded = union(enum) {3891 pub const Decoded = union(enum) {
...@@ -4022,7 +3957,7 @@ pub const Instruction = packed union {...@@ -4022,7 +3957,7 @@ pub const Instruction = packed union {
4022 decoded24: u2 = 0b00,3957 decoded24: u2 = 0b00,
4023 V: bool = true,3958 V: bool = true,
4024 decoded27: u3 = 0b111,3959 decoded27: u3 = 0b111,
4025 size: Size,3960 size: Vector.Size,
4026 };3961 };
40273962
4028 /// C7.2.333 STUR (SIMD&FP)3963 /// C7.2.333 STUR (SIMD&FP)
...@@ -4037,7 +3972,7 @@ pub const Instruction = packed union {...@@ -4037,7 +3972,7 @@ pub const Instruction = packed union {
4037 decoded24: u2 = 0b00,3972 decoded24: u2 = 0b00,
4038 V: bool = true,3973 V: bool = true,
4039 decoded27: u3 = 0b111,3974 decoded27: u3 = 0b111,
4040 size: Size,3975 size: Vector.Size,
4041 };3976 };
40423977
4043 /// C7.2.194 LDUR (SIMD&FP)3978 /// C7.2.194 LDUR (SIMD&FP)
...@@ -4052,21 +3987,20 @@ pub const Instruction = packed union {...@@ -4052,21 +3987,20 @@ pub const Instruction = packed union {
4052 decoded24: u2 = 0b00,3987 decoded24: u2 = 0b00,
4053 V: bool = true,3988 V: bool = true,
4054 decoded27: u3 = 0b111,3989 decoded27: u3 = 0b111,
4055 size: Size,3990 size: Vector.Size,
4056 };3991 };
40573992
4058 pub const Opc1 = packed struct {3993 pub const Opc1 = packed struct {
4059 encoded: u1,3994 encoded: u1,
40603995
4061 pub fn encode(vs: Register.VectorSize) Opc1 {3996 pub fn encode(ss: Register.ScalarSize) Opc1 {
4062 return .{ .encoded = switch (vs) {3997 return .{ .encoded = switch (ss) {
4063 .byte, .half, .single, .double => 0b0,3998 .byte, .half, .single, .double => 0b0,
4064 .quad => 0b1,3999 .quad => 0b1,
4065 else => unreachable,
4066 } };4000 } };
4067 }4001 }
40684002
4069 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {4003 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
4070 return switch (enc_size.encoded) {4004 return switch (enc_size.encoded) {
4071 0b00 => switch (enc_opc1.encoded) {4005 0b00 => switch (enc_opc1.encoded) {
4072 0b0 => .byte,4006 0b0 => .byte,
...@@ -4091,13 +4025,12 @@ pub const Instruction = packed union {...@@ -4091,13 +4025,12 @@ pub const Instruction = packed union {
4091 pub const Size = packed struct {4025 pub const Size = packed struct {
4092 encoded: u2,4026 encoded: u2,
40934027
4094 pub fn encode(vs: Register.VectorSize) Size {4028 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4095 return .{ .encoded = switch (vs) {4029 return .{ .encoded = switch (ss) {
4096 .byte, .quad => 0b00,4030 .byte, .quad => 0b00,
4097 .half => 0b01,4031 .half => 0b01,
4098 .single => 0b10,4032 .single => 0b10,
4099 .double => 0b11,4033 .double => 0b11,
4100 else => unreachable,
4101 } };4034 } };
4102 }4035 }
4103 };4036 };
...@@ -4177,7 +4110,7 @@ pub const Instruction = packed union {...@@ -4177,7 +4110,7 @@ pub const Instruction = packed union {
4177 decoded24: u2 = 0b00,4110 decoded24: u2 = 0b00,
4178 V: bool = false,4111 V: bool = false,
4179 decoded27: u3 = 0b111,4112 decoded27: u3 = 0b111,
4180 size: IntegerSize,4113 size: Size,
4181 };4114 };
41824115
4183 /// C6.2.324 STRB (immediate)4116 /// C6.2.324 STRB (immediate)
...@@ -4191,7 +4124,7 @@ pub const Instruction = packed union {...@@ -4191,7 +4124,7 @@ pub const Instruction = packed union {
4191 decoded24: u2 = 0b00,4124 decoded24: u2 = 0b00,
4192 V: bool = false,4125 V: bool = false,
4193 decoded27: u3 = 0b111,4126 decoded27: u3 = 0b111,
4194 size: IntegerSize = .byte,4127 size: Size = .byte,
4195 };4128 };
41964129
4197 /// C6.2.170 LDRB (immediate)4130 /// C6.2.170 LDRB (immediate)
...@@ -4205,7 +4138,7 @@ pub const Instruction = packed union {...@@ -4205,7 +4138,7 @@ pub const Instruction = packed union {
4205 decoded24: u2 = 0b00,4138 decoded24: u2 = 0b00,
4206 V: bool = false,4139 V: bool = false,
4207 decoded27: u3 = 0b111,4140 decoded27: u3 = 0b111,
4208 size: IntegerSize = .byte,4141 size: Size = .byte,
4209 };4142 };
42104143
4211 /// C6.2.174 LDRSB (immediate)4144 /// C6.2.174 LDRSB (immediate)
...@@ -4220,7 +4153,7 @@ pub const Instruction = packed union {...@@ -4220,7 +4153,7 @@ pub const Instruction = packed union {
4220 decoded24: u2 = 0b00,4153 decoded24: u2 = 0b00,
4221 V: bool = false,4154 V: bool = false,
4222 decoded27: u3 = 0b111,4155 decoded27: u3 = 0b111,
4223 size: IntegerSize = .byte,4156 size: Size = .byte,
4224 };4157 };
42254158
4226 /// C6.2.326 STRH (immediate)4159 /// C6.2.326 STRH (immediate)
...@@ -4234,7 +4167,7 @@ pub const Instruction = packed union {...@@ -4234,7 +4167,7 @@ pub const Instruction = packed union {
4234 decoded24: u2 = 0b00,4167 decoded24: u2 = 0b00,
4235 V: bool = false,4168 V: bool = false,
4236 decoded27: u3 = 0b111,4169 decoded27: u3 = 0b111,
4237 size: IntegerSize = .halfword,4170 size: Size = .halfword,
4238 };4171 };
42394172
4240 /// C6.2.172 LDRH (immediate)4173 /// C6.2.172 LDRH (immediate)
...@@ -4248,7 +4181,7 @@ pub const Instruction = packed union {...@@ -4248,7 +4181,7 @@ pub const Instruction = packed union {
4248 decoded24: u2 = 0b00,4181 decoded24: u2 = 0b00,
4249 V: bool = false,4182 V: bool = false,
4250 decoded27: u3 = 0b111,4183 decoded27: u3 = 0b111,
4251 size: IntegerSize = .halfword,4184 size: Size = .halfword,
4252 };4185 };
42534186
4254 /// C6.2.176 LDRSH (immediate)4187 /// C6.2.176 LDRSH (immediate)
...@@ -4263,7 +4196,7 @@ pub const Instruction = packed union {...@@ -4263,7 +4196,7 @@ pub const Instruction = packed union {
4263 decoded24: u2 = 0b00,4196 decoded24: u2 = 0b00,
4264 V: bool = false,4197 V: bool = false,
4265 decoded27: u3 = 0b111,4198 decoded27: u3 = 0b111,
4266 size: IntegerSize = .halfword,4199 size: Size = .halfword,
4267 };4200 };
42684201
4269 /// C6.2.322 STR (immediate)4202 /// C6.2.322 STR (immediate)
...@@ -4277,7 +4210,7 @@ pub const Instruction = packed union {...@@ -4277,7 +4210,7 @@ pub const Instruction = packed union {
4277 decoded24: u2 = 0b00,4210 decoded24: u2 = 0b00,
4278 V: bool = false,4211 V: bool = false,
4279 decoded27: u3 = 0b111,4212 decoded27: u3 = 0b111,
4280 sf: Register.IntegerSize,4213 sf: Register.GeneralSize,
4281 size1: u1 = 0b1,4214 size1: u1 = 0b1,
4282 };4215 };
42834216
...@@ -4292,7 +4225,7 @@ pub const Instruction = packed union {...@@ -4292,7 +4225,7 @@ pub const Instruction = packed union {
4292 decoded24: u2 = 0b00,4225 decoded24: u2 = 0b00,
4293 V: bool = false,4226 V: bool = false,
4294 decoded27: u3 = 0b111,4227 decoded27: u3 = 0b111,
4295 sf: Register.IntegerSize,4228 sf: Register.GeneralSize,
4296 size1: u1 = 0b1,4229 size1: u1 = 0b1,
4297 };4230 };
42984231
...@@ -4307,7 +4240,7 @@ pub const Instruction = packed union {...@@ -4307,7 +4240,7 @@ pub const Instruction = packed union {
4307 decoded24: u2 = 0b00,4240 decoded24: u2 = 0b00,
4308 V: bool = false,4241 V: bool = false,
4309 decoded27: u3 = 0b111,4242 decoded27: u3 = 0b111,
4310 size: IntegerSize = .word,4243 size: Size = .word,
4311 };4244 };
43124245
4313 pub const Decoded = union(enum) {4246 pub const Decoded = union(enum) {
...@@ -4377,7 +4310,7 @@ pub const Instruction = packed union {...@@ -4377,7 +4310,7 @@ pub const Instruction = packed union {
4377 decoded24: u2 = 0b00,4310 decoded24: u2 = 0b00,
4378 V: bool = true,4311 V: bool = true,
4379 decoded27: u3 = 0b111,4312 decoded27: u3 = 0b111,
4380 size: Size,4313 size: Vector.Size,
4381 };4314 };
43824315
4383 /// C7.2.331 STR (immediate, SIMD&FP)4316 /// C7.2.331 STR (immediate, SIMD&FP)
...@@ -4392,7 +4325,7 @@ pub const Instruction = packed union {...@@ -4392,7 +4325,7 @@ pub const Instruction = packed union {
4392 decoded24: u2 = 0b00,4325 decoded24: u2 = 0b00,
4393 V: bool = true,4326 V: bool = true,
4394 decoded27: u3 = 0b111,4327 decoded27: u3 = 0b111,
4395 size: Size,4328 size: Vector.Size,
4396 };4329 };
43974330
4398 /// C7.2.191 LDR (immediate, SIMD&FP)4331 /// C7.2.191 LDR (immediate, SIMD&FP)
...@@ -4407,21 +4340,20 @@ pub const Instruction = packed union {...@@ -4407,21 +4340,20 @@ pub const Instruction = packed union {
4407 decoded24: u2 = 0b00,4340 decoded24: u2 = 0b00,
4408 V: bool = true,4341 V: bool = true,
4409 decoded27: u3 = 0b111,4342 decoded27: u3 = 0b111,
4410 size: Size,4343 size: Vector.Size,
4411 };4344 };
44124345
4413 pub const Opc1 = packed struct {4346 pub const Opc1 = packed struct {
4414 encoded: u1,4347 encoded: u1,
44154348
4416 pub fn encode(vs: Register.VectorSize) Opc1 {4349 pub fn encode(ss: Register.ScalarSize) Opc1 {
4417 return .{ .encoded = switch (vs) {4350 return .{ .encoded = switch (ss) {
4418 .byte, .half, .single, .double => 0b0,4351 .byte, .half, .single, .double => 0b0,
4419 .quad => 0b1,4352 .quad => 0b1,
4420 else => unreachable,
4421 } };4353 } };
4422 }4354 }
44234355
4424 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {4356 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
4425 return switch (enc_size.encoded) {4357 return switch (enc_size.encoded) {
4426 0b00 => switch (enc_opc1.encoded) {4358 0b00 => switch (enc_opc1.encoded) {
4427 0b0 => .byte,4359 0b0 => .byte,
...@@ -4446,13 +4378,12 @@ pub const Instruction = packed union {...@@ -4446,13 +4378,12 @@ pub const Instruction = packed union {
4446 pub const Size = packed struct {4378 pub const Size = packed struct {
4447 encoded: u2,4379 encoded: u2,
44484380
4449 pub fn encode(vs: Register.VectorSize) Size {4381 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4450 return .{ .encoded = switch (vs) {4382 return .{ .encoded = switch (ss) {
4451 .byte, .quad => 0b00,4383 .byte, .quad => 0b00,
4452 .half => 0b01,4384 .half => 0b01,
4453 .single => 0b10,4385 .single => 0b10,
4454 .double => 0b11,4386 .double => 0b11,
4455 else => unreachable,
4456 } };4387 } };
4457 }4388 }
4458 };4389 };
...@@ -4502,7 +4433,7 @@ pub const Instruction = packed union {...@@ -4502,7 +4433,7 @@ pub const Instruction = packed union {
4502 decoded24: u2 = 0b00,4433 decoded24: u2 = 0b00,
4503 V: bool,4434 V: bool,
4504 decoded27: u3 = 0b111,4435 decoded27: u3 = 0b111,
4505 size: IntegerSize,4436 size: Size,
4506 };4437 };
45074438
4508 /// Load/store register (immediate pre-indexed)4439 /// Load/store register (immediate pre-indexed)
...@@ -4546,7 +4477,7 @@ pub const Instruction = packed union {...@@ -4546,7 +4477,7 @@ pub const Instruction = packed union {
4546 decoded24: u2 = 0b00,4477 decoded24: u2 = 0b00,
4547 V: bool = false,4478 V: bool = false,
4548 decoded27: u3 = 0b111,4479 decoded27: u3 = 0b111,
4549 size: IntegerSize,4480 size: Size,
4550 };4481 };
45514482
4552 /// C6.2.324 STRB (immediate)4483 /// C6.2.324 STRB (immediate)
...@@ -4560,7 +4491,7 @@ pub const Instruction = packed union {...@@ -4560,7 +4491,7 @@ pub const Instruction = packed union {
4560 decoded24: u2 = 0b00,4491 decoded24: u2 = 0b00,
4561 V: bool = false,4492 V: bool = false,
4562 decoded27: u3 = 0b111,4493 decoded27: u3 = 0b111,
4563 size: IntegerSize = .byte,4494 size: Size = .byte,
4564 };4495 };
45654496
4566 /// C6.2.170 LDRB (immediate)4497 /// C6.2.170 LDRB (immediate)
...@@ -4574,7 +4505,7 @@ pub const Instruction = packed union {...@@ -4574,7 +4505,7 @@ pub const Instruction = packed union {
4574 decoded24: u2 = 0b00,4505 decoded24: u2 = 0b00,
4575 V: bool = false,4506 V: bool = false,
4576 decoded27: u3 = 0b111,4507 decoded27: u3 = 0b111,
4577 size: IntegerSize = .byte,4508 size: Size = .byte,
4578 };4509 };
45794510
4580 /// C6.2.174 LDRSB (immediate)4511 /// C6.2.174 LDRSB (immediate)
...@@ -4589,7 +4520,7 @@ pub const Instruction = packed union {...@@ -4589,7 +4520,7 @@ pub const Instruction = packed union {
4589 decoded24: u2 = 0b00,4520 decoded24: u2 = 0b00,
4590 V: bool = false,4521 V: bool = false,
4591 decoded27: u3 = 0b111,4522 decoded27: u3 = 0b111,
4592 size: IntegerSize = .byte,4523 size: Size = .byte,
4593 };4524 };
45944525
4595 /// C6.2.326 STRH (immediate)4526 /// C6.2.326 STRH (immediate)
...@@ -4603,7 +4534,7 @@ pub const Instruction = packed union {...@@ -4603,7 +4534,7 @@ pub const Instruction = packed union {
4603 decoded24: u2 = 0b00,4534 decoded24: u2 = 0b00,
4604 V: bool = false,4535 V: bool = false,
4605 decoded27: u3 = 0b111,4536 decoded27: u3 = 0b111,
4606 size: IntegerSize = .halfword,4537 size: Size = .halfword,
4607 };4538 };
46084539
4609 /// C6.2.172 LDRH (immediate)4540 /// C6.2.172 LDRH (immediate)
...@@ -4617,7 +4548,7 @@ pub const Instruction = packed union {...@@ -4617,7 +4548,7 @@ pub const Instruction = packed union {
4617 decoded24: u2 = 0b00,4548 decoded24: u2 = 0b00,
4618 V: bool = false,4549 V: bool = false,
4619 decoded27: u3 = 0b111,4550 decoded27: u3 = 0b111,
4620 size: IntegerSize = .halfword,4551 size: Size = .halfword,
4621 };4552 };
46224553
4623 /// C6.2.176 LDRSH (immediate)4554 /// C6.2.176 LDRSH (immediate)
...@@ -4632,7 +4563,7 @@ pub const Instruction = packed union {...@@ -4632,7 +4563,7 @@ pub const Instruction = packed union {
4632 decoded24: u2 = 0b00,4563 decoded24: u2 = 0b00,
4633 V: bool = false,4564 V: bool = false,
4634 decoded27: u3 = 0b111,4565 decoded27: u3 = 0b111,
4635 size: IntegerSize = .halfword,4566 size: Size = .halfword,
4636 };4567 };
46374568
4638 /// C6.2.322 STR (immediate)4569 /// C6.2.322 STR (immediate)
...@@ -4646,7 +4577,7 @@ pub const Instruction = packed union {...@@ -4646,7 +4577,7 @@ pub const Instruction = packed union {
4646 decoded24: u2 = 0b00,4577 decoded24: u2 = 0b00,
4647 V: bool = false,4578 V: bool = false,
4648 decoded27: u3 = 0b111,4579 decoded27: u3 = 0b111,
4649 sf: Register.IntegerSize,4580 sf: Register.GeneralSize,
4650 size1: u1 = 0b1,4581 size1: u1 = 0b1,
4651 };4582 };
46524583
...@@ -4661,7 +4592,7 @@ pub const Instruction = packed union {...@@ -4661,7 +4592,7 @@ pub const Instruction = packed union {
4661 decoded24: u2 = 0b00,4592 decoded24: u2 = 0b00,
4662 V: bool = false,4593 V: bool = false,
4663 decoded27: u3 = 0b111,4594 decoded27: u3 = 0b111,
4664 sf: Register.IntegerSize,4595 sf: Register.GeneralSize,
4665 size1: u1 = 0b1,4596 size1: u1 = 0b1,
4666 };4597 };
46674598
...@@ -4676,7 +4607,7 @@ pub const Instruction = packed union {...@@ -4676,7 +4607,7 @@ pub const Instruction = packed union {
4676 decoded24: u2 = 0b00,4607 decoded24: u2 = 0b00,
4677 V: bool = false,4608 V: bool = false,
4678 decoded27: u3 = 0b111,4609 decoded27: u3 = 0b111,
4679 size: IntegerSize = .word,4610 size: Size = .word,
4680 };4611 };
46814612
4682 pub const Decoded = union(enum) {4613 pub const Decoded = union(enum) {
...@@ -4734,7 +4665,7 @@ pub const Instruction = packed union {...@@ -4734,7 +4665,7 @@ pub const Instruction = packed union {
4734 decoded24: u2 = 0b00,4665 decoded24: u2 = 0b00,
4735 V: bool = true,4666 V: bool = true,
4736 decoded27: u3 = 0b111,4667 decoded27: u3 = 0b111,
4737 size: Size,4668 size: Vector.Size,
4738 };4669 };
47394670
4740 /// C7.2.331 STR (immediate, SIMD&FP)4671 /// C7.2.331 STR (immediate, SIMD&FP)
...@@ -4749,7 +4680,7 @@ pub const Instruction = packed union {...@@ -4749,7 +4680,7 @@ pub const Instruction = packed union {
4749 decoded24: u2 = 0b00,4680 decoded24: u2 = 0b00,
4750 V: bool = true,4681 V: bool = true,
4751 decoded27: u3 = 0b111,4682 decoded27: u3 = 0b111,
4752 size: Size,4683 size: Vector.Size,
4753 };4684 };
47544685
4755 /// C7.2.191 LDR (immediate, SIMD&FP)4686 /// C7.2.191 LDR (immediate, SIMD&FP)
...@@ -4764,21 +4695,20 @@ pub const Instruction = packed union {...@@ -4764,21 +4695,20 @@ pub const Instruction = packed union {
4764 decoded24: u2 = 0b00,4695 decoded24: u2 = 0b00,
4765 V: bool = true,4696 V: bool = true,
4766 decoded27: u3 = 0b111,4697 decoded27: u3 = 0b111,
4767 size: Size,4698 size: Vector.Size,
4768 };4699 };
47694700
4770 pub const Opc1 = packed struct {4701 pub const Opc1 = packed struct {
4771 encoded: u1,4702 encoded: u1,
47724703
4773 pub fn encode(vs: Register.VectorSize) Opc1 {4704 pub fn encode(ss: Register.ScalarSize) Opc1 {
4774 return .{ .encoded = switch (vs) {4705 return .{ .encoded = switch (ss) {
4775 .byte, .half, .single, .double => 0b0,4706 .byte, .half, .single, .double => 0b0,
4776 .quad => 0b1,4707 .quad => 0b1,
4777 else => unreachable,
4778 } };4708 } };
4779 }4709 }
47804710
4781 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {4711 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
4782 return switch (enc_size.encoded) {4712 return switch (enc_size.encoded) {
4783 0b00 => switch (enc_opc1.encoded) {4713 0b00 => switch (enc_opc1.encoded) {
4784 0b0 => .byte,4714 0b0 => .byte,
...@@ -4803,13 +4733,12 @@ pub const Instruction = packed union {...@@ -4803,13 +4733,12 @@ pub const Instruction = packed union {
4803 pub const Size = packed struct {4733 pub const Size = packed struct {
4804 encoded: u2,4734 encoded: u2,
48054735
4806 pub fn encode(vs: Register.VectorSize) Size {4736 pub fn encode(ss: Register.ScalarSize) Vector.Size {
4807 return .{ .encoded = switch (vs) {4737 return .{ .encoded = switch (ss) {
4808 .byte, .quad => 0b00,4738 .byte, .quad => 0b00,
4809 .half => 0b01,4739 .half => 0b01,
4810 .single => 0b10,4740 .single => 0b10,
4811 .double => 0b11,4741 .double => 0b11,
4812 else => unreachable,
4813 } };4742 } };
4814 }4743 }
4815 };4744 };
...@@ -4894,7 +4823,7 @@ pub const Instruction = packed union {...@@ -4894,7 +4823,7 @@ pub const Instruction = packed union {
4894 decoded24: u2 = 0b00,4823 decoded24: u2 = 0b00,
4895 V: bool = false,4824 V: bool = false,
4896 decoded27: u3 = 0b111,4825 decoded27: u3 = 0b111,
4897 size: IntegerSize,4826 size: Size,
4898 };4827 };
48994828
4900 /// C6.2.325 STRB (register)4829 /// C6.2.325 STRB (register)
...@@ -4910,7 +4839,7 @@ pub const Instruction = packed union {...@@ -4910,7 +4839,7 @@ pub const Instruction = packed union {
4910 decoded24: u2 = 0b00,4839 decoded24: u2 = 0b00,
4911 V: bool = false,4840 V: bool = false,
4912 decoded27: u3 = 0b111,4841 decoded27: u3 = 0b111,
4913 size: IntegerSize = .byte,4842 size: Size = .byte,
4914 };4843 };
49154844
4916 /// C6.2.171 LDRB (register)4845 /// C6.2.171 LDRB (register)
...@@ -4926,7 +4855,7 @@ pub const Instruction = packed union {...@@ -4926,7 +4855,7 @@ pub const Instruction = packed union {
4926 decoded24: u2 = 0b00,4855 decoded24: u2 = 0b00,
4927 V: bool = false,4856 V: bool = false,
4928 decoded27: u3 = 0b111,4857 decoded27: u3 = 0b111,
4929 size: IntegerSize = .byte,4858 size: Size = .byte,
4930 };4859 };
49314860
4932 /// C6.2.175 LDRSB (register)4861 /// C6.2.175 LDRSB (register)
...@@ -4943,7 +4872,7 @@ pub const Instruction = packed union {...@@ -4943,7 +4872,7 @@ pub const Instruction = packed union {
4943 decoded24: u2 = 0b00,4872 decoded24: u2 = 0b00,
4944 V: bool = false,4873 V: bool = false,
4945 decoded27: u3 = 0b111,4874 decoded27: u3 = 0b111,
4946 size: IntegerSize = .byte,4875 size: Size = .byte,
4947 };4876 };
49484877
4949 /// C6.2.327 STRH (register)4878 /// C6.2.327 STRH (register)
...@@ -4959,7 +4888,7 @@ pub const Instruction = packed union {...@@ -4959,7 +4888,7 @@ pub const Instruction = packed union {
4959 decoded24: u2 = 0b00,4888 decoded24: u2 = 0b00,
4960 V: bool = false,4889 V: bool = false,
4961 decoded27: u3 = 0b111,4890 decoded27: u3 = 0b111,
4962 size: IntegerSize = .halfword,4891 size: Size = .halfword,
4963 };4892 };
49644893
4965 /// C6.2.173 LDRH (register)4894 /// C6.2.173 LDRH (register)
...@@ -4975,7 +4904,7 @@ pub const Instruction = packed union {...@@ -4975,7 +4904,7 @@ pub const Instruction = packed union {
4975 decoded24: u2 = 0b00,4904 decoded24: u2 = 0b00,
4976 V: bool = false,4905 V: bool = false,
4977 decoded27: u3 = 0b111,4906 decoded27: u3 = 0b111,
4978 size: IntegerSize = .halfword,4907 size: Size = .halfword,
4979 };4908 };
49804909
4981 /// C6.2.177 LDRSH (register)4910 /// C6.2.177 LDRSH (register)
...@@ -4992,7 +4921,7 @@ pub const Instruction = packed union {...@@ -4992,7 +4921,7 @@ pub const Instruction = packed union {
4992 decoded24: u2 = 0b00,4921 decoded24: u2 = 0b00,
4993 V: bool = false,4922 V: bool = false,
4994 decoded27: u3 = 0b111,4923 decoded27: u3 = 0b111,
4995 size: IntegerSize = .halfword,4924 size: Size = .halfword,
4996 };4925 };
49974926
4998 /// C6.2.323 STR (register)4927 /// C6.2.323 STR (register)
...@@ -5008,7 +4937,7 @@ pub const Instruction = packed union {...@@ -5008,7 +4937,7 @@ pub const Instruction = packed union {
5008 decoded24: u2 = 0b00,4937 decoded24: u2 = 0b00,
5009 V: bool = false,4938 V: bool = false,
5010 decoded27: u3 = 0b111,4939 decoded27: u3 = 0b111,
5011 sf: Register.IntegerSize,4940 sf: Register.GeneralSize,
5012 size1: u1 = 0b1,4941 size1: u1 = 0b1,
5013 };4942 };
50144943
...@@ -5025,7 +4954,7 @@ pub const Instruction = packed union {...@@ -5025,7 +4954,7 @@ pub const Instruction = packed union {
5025 decoded24: u2 = 0b00,4954 decoded24: u2 = 0b00,
5026 V: bool = false,4955 V: bool = false,
5027 decoded27: u3 = 0b111,4956 decoded27: u3 = 0b111,
5028 sf: Register.IntegerSize,4957 sf: Register.GeneralSize,
5029 size1: u1 = 0b1,4958 size1: u1 = 0b1,
5030 };4959 };
50314960
...@@ -5042,7 +4971,7 @@ pub const Instruction = packed union {...@@ -5042,7 +4971,7 @@ pub const Instruction = packed union {
5042 decoded24: u2 = 0b00,4971 decoded24: u2 = 0b00,
5043 V: bool = false,4972 V: bool = false,
5044 decoded27: u3 = 0b111,4973 decoded27: u3 = 0b111,
5045 size: IntegerSize = .word,4974 size: Size = .word,
5046 };4975 };
50474976
5048 /// C6.2.249 PRFM (register)4977 /// C6.2.249 PRFM (register)
...@@ -5058,7 +4987,7 @@ pub const Instruction = packed union {...@@ -5058,7 +4987,7 @@ pub const Instruction = packed union {
5058 decoded24: u2 = 0b00,4987 decoded24: u2 = 0b00,
5059 V: bool = false,4988 V: bool = false,
5060 decoded27: u3 = 0b111,4989 decoded27: u3 = 0b111,
5061 size: IntegerSize = .doubleword,4990 size: Size = .doubleword,
5062 };4991 };
50634992
5064 pub const Decoded = union(enum) {4993 pub const Decoded = union(enum) {
...@@ -5131,7 +5060,7 @@ pub const Instruction = packed union {...@@ -5131,7 +5060,7 @@ pub const Instruction = packed union {
5131 decoded24: u2 = 0b00,5060 decoded24: u2 = 0b00,
5132 V: bool = true,5061 V: bool = true,
5133 decoded27: u3 = 0b111,5062 decoded27: u3 = 0b111,
5134 size: Size,5063 size: Vector.Size,
5135 };5064 };
51365065
5137 /// C7.2.332 STR (register, SIMD&FP)5066 /// C7.2.332 STR (register, SIMD&FP)
...@@ -5148,7 +5077,7 @@ pub const Instruction = packed union {...@@ -5148,7 +5077,7 @@ pub const Instruction = packed union {
5148 decoded24: u2 = 0b00,5077 decoded24: u2 = 0b00,
5149 V: bool = true,5078 V: bool = true,
5150 decoded27: u3 = 0b111,5079 decoded27: u3 = 0b111,
5151 size: Size,5080 size: Vector.Size,
5152 };5081 };
51535082
5154 /// C7.2.193 LDR (register, SIMD&FP)5083 /// C7.2.193 LDR (register, SIMD&FP)
...@@ -5165,21 +5094,20 @@ pub const Instruction = packed union {...@@ -5165,21 +5094,20 @@ pub const Instruction = packed union {
5165 decoded24: u2 = 0b00,5094 decoded24: u2 = 0b00,
5166 V: bool = true,5095 V: bool = true,
5167 decoded27: u3 = 0b111,5096 decoded27: u3 = 0b111,
5168 size: Size,5097 size: Vector.Size,
5169 };5098 };
51705099
5171 pub const Opc1 = packed struct {5100 pub const Opc1 = packed struct {
5172 encoded: u1,5101 encoded: u1,
51735102
5174 pub fn encode(vs: Register.VectorSize) Opc1 {5103 pub fn encode(ss: Register.ScalarSize) Opc1 {
5175 return .{ .encoded = switch (vs) {5104 return .{ .encoded = switch (ss) {
5176 .byte, .half, .single, .double => 0b0,5105 .byte, .half, .single, .double => 0b0,
5177 .quad => 0b1,5106 .quad => 0b1,
5178 else => unreachable,
5179 } };5107 } };
5180 }5108 }
51815109
5182 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {5110 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
5183 return switch (enc_size.encoded) {5111 return switch (enc_size.encoded) {
5184 0b00 => switch (enc_opc1.encoded) {5112 0b00 => switch (enc_opc1.encoded) {
5185 0b0 => .byte,5113 0b0 => .byte,
...@@ -5204,13 +5132,12 @@ pub const Instruction = packed union {...@@ -5204,13 +5132,12 @@ pub const Instruction = packed union {
5204 pub const Size = packed struct {5132 pub const Size = packed struct {
5205 encoded: u2,5133 encoded: u2,
52065134
5207 pub fn encode(vs: Register.VectorSize) Size {5135 pub fn encode(ss: Register.ScalarSize) Vector.Size {
5208 return .{ .encoded = switch (vs) {5136 return .{ .encoded = switch (ss) {
5209 .byte, .quad => 0b00,5137 .byte, .quad => 0b00,
5210 .half => 0b01,5138 .half => 0b01,
5211 .single => 0b10,5139 .single => 0b10,
5212 .double => 0b11,5140 .double => 0b11,
5213 else => unreachable,
5214 } };5141 } };
5215 }5142 }
5216 };5143 };
...@@ -5223,7 +5150,7 @@ pub const Instruction = packed union {...@@ -5223,7 +5150,7 @@ pub const Instruction = packed union {
5223 sxtx = 0b111,5150 sxtx = 0b111,
5224 _,5151 _,
52255152
5226 pub fn sf(option: Option) Register.IntegerSize {5153 pub fn sf(option: Option) Register.GeneralSize {
5227 return switch (option) {5154 return switch (option) {
5228 .uxtw, .sxtw => .word,5155 .uxtw, .sxtw => .word,
5229 .lsl, .sxtx => .doubleword,5156 .lsl, .sxtx => .doubleword,
...@@ -5291,7 +5218,7 @@ pub const Instruction = packed union {...@@ -5291,7 +5218,7 @@ pub const Instruction = packed union {
5291 decoded24: u2 = 0b01,5218 decoded24: u2 = 0b01,
5292 V: bool = false,5219 V: bool = false,
5293 decoded27: u3 = 0b111,5220 decoded27: u3 = 0b111,
5294 size: IntegerSize,5221 size: Size,
5295 };5222 };
52965223
5297 /// C6.2.324 STRB (immediate)5224 /// C6.2.324 STRB (immediate)
...@@ -5303,7 +5230,7 @@ pub const Instruction = packed union {...@@ -5303,7 +5230,7 @@ pub const Instruction = packed union {
5303 decoded24: u2 = 0b01,5230 decoded24: u2 = 0b01,
5304 V: bool = false,5231 V: bool = false,
5305 decoded27: u3 = 0b111,5232 decoded27: u3 = 0b111,
5306 size: IntegerSize = .byte,5233 size: Size = .byte,
5307 };5234 };
53085235
5309 /// C6.2.170 LDRB (immediate)5236 /// C6.2.170 LDRB (immediate)
...@@ -5315,7 +5242,7 @@ pub const Instruction = packed union {...@@ -5315,7 +5242,7 @@ pub const Instruction = packed union {
5315 decoded24: u2 = 0b01,5242 decoded24: u2 = 0b01,
5316 V: bool = false,5243 V: bool = false,
5317 decoded27: u3 = 0b111,5244 decoded27: u3 = 0b111,
5318 size: IntegerSize = .byte,5245 size: Size = .byte,
5319 };5246 };
53205247
5321 /// C6.2.174 LDRSB (immediate)5248 /// C6.2.174 LDRSB (immediate)
...@@ -5328,7 +5255,7 @@ pub const Instruction = packed union {...@@ -5328,7 +5255,7 @@ pub const Instruction = packed union {
5328 decoded24: u2 = 0b01,5255 decoded24: u2 = 0b01,
5329 V: bool = false,5256 V: bool = false,
5330 decoded27: u3 = 0b111,5257 decoded27: u3 = 0b111,
5331 size: IntegerSize = .byte,5258 size: Size = .byte,
5332 };5259 };
53335260
5334 /// C6.2.326 STRH (immediate)5261 /// C6.2.326 STRH (immediate)
...@@ -5340,7 +5267,7 @@ pub const Instruction = packed union {...@@ -5340,7 +5267,7 @@ pub const Instruction = packed union {
5340 decoded24: u2 = 0b01,5267 decoded24: u2 = 0b01,
5341 V: bool = false,5268 V: bool = false,
5342 decoded27: u3 = 0b111,5269 decoded27: u3 = 0b111,
5343 size: IntegerSize = .halfword,5270 size: Size = .halfword,
5344 };5271 };
53455272
5346 /// C6.2.172 LDRH (immediate)5273 /// C6.2.172 LDRH (immediate)
...@@ -5352,7 +5279,7 @@ pub const Instruction = packed union {...@@ -5352,7 +5279,7 @@ pub const Instruction = packed union {
5352 decoded24: u2 = 0b01,5279 decoded24: u2 = 0b01,
5353 V: bool = false,5280 V: bool = false,
5354 decoded27: u3 = 0b111,5281 decoded27: u3 = 0b111,
5355 size: IntegerSize = .halfword,5282 size: Size = .halfword,
5356 };5283 };
53575284
5358 /// C6.2.176 LDRSH (immediate)5285 /// C6.2.176 LDRSH (immediate)
...@@ -5365,7 +5292,7 @@ pub const Instruction = packed union {...@@ -5365,7 +5292,7 @@ pub const Instruction = packed union {
5365 decoded24: u2 = 0b01,5292 decoded24: u2 = 0b01,
5366 V: bool = false,5293 V: bool = false,
5367 decoded27: u3 = 0b111,5294 decoded27: u3 = 0b111,
5368 size: IntegerSize = .halfword,5295 size: Size = .halfword,
5369 };5296 };
53705297
5371 /// C6.2.322 STR (immediate)5298 /// C6.2.322 STR (immediate)
...@@ -5377,7 +5304,7 @@ pub const Instruction = packed union {...@@ -5377,7 +5304,7 @@ pub const Instruction = packed union {
5377 decoded24: u2 = 0b01,5304 decoded24: u2 = 0b01,
5378 V: bool = false,5305 V: bool = false,
5379 decoded27: u3 = 0b111,5306 decoded27: u3 = 0b111,
5380 sf: Register.IntegerSize,5307 sf: Register.GeneralSize,
5381 size1: u1 = 0b1,5308 size1: u1 = 0b1,
5382 };5309 };
53835310
...@@ -5390,7 +5317,7 @@ pub const Instruction = packed union {...@@ -5390,7 +5317,7 @@ pub const Instruction = packed union {
5390 decoded24: u2 = 0b01,5317 decoded24: u2 = 0b01,
5391 V: bool = false,5318 V: bool = false,
5392 decoded27: u3 = 0b111,5319 decoded27: u3 = 0b111,
5393 sf: Register.IntegerSize,5320 sf: Register.GeneralSize,
5394 size1: u1 = 0b1,5321 size1: u1 = 0b1,
5395 };5322 };
53965323
...@@ -5403,7 +5330,7 @@ pub const Instruction = packed union {...@@ -5403,7 +5330,7 @@ pub const Instruction = packed union {
5403 decoded24: u2 = 0b01,5330 decoded24: u2 = 0b01,
5404 V: bool = false,5331 V: bool = false,
5405 decoded27: u3 = 0b111,5332 decoded27: u3 = 0b111,
5406 size: IntegerSize = .word,5333 size: Size = .word,
5407 };5334 };
54085335
5409 /// C6.2.247 PRFM (immediate)5336 /// C6.2.247 PRFM (immediate)
...@@ -5415,7 +5342,7 @@ pub const Instruction = packed union {...@@ -5415,7 +5342,7 @@ pub const Instruction = packed union {
5415 decoded24: u2 = 0b01,5342 decoded24: u2 = 0b01,
5416 V: bool = false,5343 V: bool = false,
5417 decoded27: u3 = 0b111,5344 decoded27: u3 = 0b111,
5418 size: IntegerSize = .doubleword,5345 size: Size = .doubleword,
5419 };5346 };
54205347
5421 pub const Decoded = union(enum) {5348 pub const Decoded = union(enum) {
...@@ -5485,7 +5412,7 @@ pub const Instruction = packed union {...@@ -5485,7 +5412,7 @@ pub const Instruction = packed union {
5485 decoded24: u2 = 0b01,5412 decoded24: u2 = 0b01,
5486 V: bool = true,5413 V: bool = true,
5487 decoded27: u3 = 0b111,5414 decoded27: u3 = 0b111,
5488 size: Size,5415 size: Vector.Size,
5489 };5416 };
54905417
5491 /// C7.2.331 STR (immediate, SIMD&FP)5418 /// C7.2.331 STR (immediate, SIMD&FP)
...@@ -5498,7 +5425,7 @@ pub const Instruction = packed union {...@@ -5498,7 +5425,7 @@ pub const Instruction = packed union {
5498 decoded24: u2 = 0b01,5425 decoded24: u2 = 0b01,
5499 V: bool = true,5426 V: bool = true,
5500 decoded27: u3 = 0b111,5427 decoded27: u3 = 0b111,
5501 size: Size,5428 size: Vector.Size,
5502 };5429 };
55035430
5504 /// C7.2.191 LDR (immediate, SIMD&FP)5431 /// C7.2.191 LDR (immediate, SIMD&FP)
...@@ -5511,21 +5438,20 @@ pub const Instruction = packed union {...@@ -5511,21 +5438,20 @@ pub const Instruction = packed union {
5511 decoded24: u2 = 0b01,5438 decoded24: u2 = 0b01,
5512 V: bool = true,5439 V: bool = true,
5513 decoded27: u3 = 0b111,5440 decoded27: u3 = 0b111,
5514 size: Size,5441 size: Vector.Size,
5515 };5442 };
55165443
5517 pub const Opc1 = packed struct {5444 pub const Opc1 = packed struct {
5518 encoded: u1,5445 encoded: u1,
55195446
5520 pub fn encode(vs: Register.VectorSize) Opc1 {5447 pub fn encode(ss: Register.ScalarSize) Opc1 {
5521 return .{ .encoded = switch (vs) {5448 return .{ .encoded = switch (ss) {
5522 .byte, .half, .single, .double => 0b0,5449 .byte, .half, .single, .double => 0b0,
5523 .quad => 0b1,5450 .quad => 0b1,
5524 else => unreachable,
5525 } };5451 } };
5526 }5452 }
55275453
5528 pub fn decode(enc_opc1: Opc1, enc_size: Size) Register.VectorSize {5454 pub fn decode(enc_opc1: Opc1, enc_size: Vector.Size) Register.ScalarSize {
5529 return switch (enc_size.encoded) {5455 return switch (enc_size.encoded) {
5530 0b00 => switch (enc_opc1.encoded) {5456 0b00 => switch (enc_opc1.encoded) {
5531 0b0 => .byte,5457 0b0 => .byte,
...@@ -5550,13 +5476,12 @@ pub const Instruction = packed union {...@@ -5550,13 +5476,12 @@ pub const Instruction = packed union {
5550 pub const Size = packed struct {5476 pub const Size = packed struct {
5551 encoded: u2,5477 encoded: u2,
55525478
5553 pub fn encode(vs: Register.VectorSize) Size {5479 pub fn encode(ss: Register.ScalarSize) Vector.Size {
5554 return .{ .encoded = switch (vs) {5480 return .{ .encoded = switch (ss) {
5555 .byte, .quad => 0b00,5481 .byte, .quad => 0b00,
5556 .half => 0b01,5482 .half => 0b01,
5557 .single => 0b10,5483 .single => 0b10,
5558 .double => 0b11,5484 .double => 0b11,
5559 else => unreachable,
5560 } };5485 } };
5561 }5486 }
5562 };5487 };
...@@ -5600,7 +5525,7 @@ pub const Instruction = packed union {...@@ -5600,7 +5525,7 @@ pub const Instruction = packed union {
5600 load = 0b1,5525 load = 0b1,
5601 };5526 };
56025527
5603 pub const IntegerSize = enum(u2) {5528 pub const Size = enum(u2) {
5604 byte = 0b00,5529 byte = 0b00,
5605 halfword = 0b01,5530 halfword = 0b01,
5606 word = 0b10,5531 word = 0b10,
...@@ -5613,7 +5538,7 @@ pub const Instruction = packed union {...@@ -5613,7 +5538,7 @@ pub const Instruction = packed union {
5613 quad = 0b10,5538 quad = 0b10,
5614 _,5539 _,
56155540
5616 pub fn decode(vs: VectorSize) Register.VectorSize {5541 pub fn decode(vs: VectorSize) Register.ScalarSize {
5617 return switch (vs) {5542 return switch (vs) {
5618 .single => .single,5543 .single => .single,
5619 .double => .double,5544 .double => .double,
...@@ -5622,8 +5547,8 @@ pub const Instruction = packed union {...@@ -5622,8 +5547,8 @@ pub const Instruction = packed union {
5622 };5547 };
5623 }5548 }
56245549
5625 pub fn encode(vs: Register.VectorSize) VectorSize {5550 pub fn encode(ss: Register.ScalarSize) VectorSize {
5626 return switch (vs) {5551 return switch (ss) {
5627 else => unreachable,5552 else => unreachable,
5628 .single => .single,5553 .single => .single,
5629 .double => .double,5554 .double => .double,
...@@ -5767,7 +5692,7 @@ pub const Instruction = packed union {...@@ -5767,7 +5692,7 @@ pub const Instruction = packed union {
5767 decoded21: u8 = 0b11010110,5692 decoded21: u8 = 0b11010110,
5768 S: bool,5693 S: bool,
5769 decoded30: u1 = 0b0,5694 decoded30: u1 = 0b0,
5770 sf: Register.IntegerSize,5695 sf: Register.GeneralSize,
5771 };5696 };
57725697
5773 /// C6.2.388 UDIV5698 /// C6.2.388 UDIV
...@@ -5780,7 +5705,7 @@ pub const Instruction = packed union {...@@ -5780,7 +5705,7 @@ pub const Instruction = packed union {
5780 decoded21: u8 = 0b11010110,5705 decoded21: u8 = 0b11010110,
5781 S: bool = false,5706 S: bool = false,
5782 decoded30: u1 = 0b0,5707 decoded30: u1 = 0b0,
5783 sf: Register.IntegerSize,5708 sf: Register.GeneralSize,
5784 };5709 };
57855710
5786 /// C6.2.270 SDIV5711 /// C6.2.270 SDIV
...@@ -5793,7 +5718,7 @@ pub const Instruction = packed union {...@@ -5793,7 +5718,7 @@ pub const Instruction = packed union {
5793 decoded21: u8 = 0b11010110,5718 decoded21: u8 = 0b11010110,
5794 S: bool = false,5719 S: bool = false,
5795 decoded30: u1 = 0b0,5720 decoded30: u1 = 0b0,
5796 sf: Register.IntegerSize,5721 sf: Register.GeneralSize,
5797 };5722 };
57985723
5799 /// C6.2.214 LSLV5724 /// C6.2.214 LSLV
...@@ -5806,7 +5731,7 @@ pub const Instruction = packed union {...@@ -5806,7 +5731,7 @@ pub const Instruction = packed union {
5806 decoded21: u8 = 0b11010110,5731 decoded21: u8 = 0b11010110,
5807 S: bool = false,5732 S: bool = false,
5808 decoded30: u1 = 0b0,5733 decoded30: u1 = 0b0,
5809 sf: Register.IntegerSize,5734 sf: Register.GeneralSize,
5810 };5735 };
58115736
5812 /// C6.2.217 LSRV5737 /// C6.2.217 LSRV
...@@ -5819,7 +5744,7 @@ pub const Instruction = packed union {...@@ -5819,7 +5744,7 @@ pub const Instruction = packed union {
5819 decoded21: u8 = 0b11010110,5744 decoded21: u8 = 0b11010110,
5820 S: bool = false,5745 S: bool = false,
5821 decoded30: u1 = 0b0,5746 decoded30: u1 = 0b0,
5822 sf: Register.IntegerSize,5747 sf: Register.GeneralSize,
5823 };5748 };
58245749
5825 /// C6.2.18 ASRV5750 /// C6.2.18 ASRV
...@@ -5832,7 +5757,7 @@ pub const Instruction = packed union {...@@ -5832,7 +5757,7 @@ pub const Instruction = packed union {
5832 decoded21: u8 = 0b11010110,5757 decoded21: u8 = 0b11010110,
5833 S: bool = false,5758 S: bool = false,
5834 decoded30: u1 = 0b0,5759 decoded30: u1 = 0b0,
5835 sf: Register.IntegerSize,5760 sf: Register.GeneralSize,
5836 };5761 };
58375762
5838 /// C6.2.263 RORV5763 /// C6.2.263 RORV
...@@ -5845,7 +5770,7 @@ pub const Instruction = packed union {...@@ -5845,7 +5770,7 @@ pub const Instruction = packed union {
5845 decoded21: u8 = 0b11010110,5770 decoded21: u8 = 0b11010110,
5846 S: bool = false,5771 S: bool = false,
5847 decoded30: u1 = 0b0,5772 decoded30: u1 = 0b0,
5848 sf: Register.IntegerSize,5773 sf: Register.GeneralSize,
5849 };5774 };
58505775
5851 pub const DivOp = enum(u1) {5776 pub const DivOp = enum(u1) {
...@@ -5903,7 +5828,7 @@ pub const Instruction = packed union {...@@ -5903,7 +5828,7 @@ pub const Instruction = packed union {
5903 decoded21: u8 = 0b11010110,5828 decoded21: u8 = 0b11010110,
5904 S: bool,5829 S: bool,
5905 decoded30: u1 = 0b1,5830 decoded30: u1 = 0b1,
5906 sf: Register.IntegerSize,5831 sf: Register.GeneralSize,
5907 };5832 };
59085833
5909 /// C6.2.253 RBIT5834 /// C6.2.253 RBIT
...@@ -5916,7 +5841,7 @@ pub const Instruction = packed union {...@@ -5916,7 +5841,7 @@ pub const Instruction = packed union {
5916 decoded21: u8 = 0b11010110,5841 decoded21: u8 = 0b11010110,
5917 S: bool = false,5842 S: bool = false,
5918 decoded30: u1 = 0b1,5843 decoded30: u1 = 0b1,
5919 sf: Register.IntegerSize,5844 sf: Register.GeneralSize,
5920 };5845 };
59215846
5922 /// C6.2.257 REV165847 /// C6.2.257 REV16
...@@ -5929,7 +5854,7 @@ pub const Instruction = packed union {...@@ -5929,7 +5854,7 @@ pub const Instruction = packed union {
5929 decoded21: u8 = 0b11010110,5854 decoded21: u8 = 0b11010110,
5930 S: bool = false,5855 S: bool = false,
5931 decoded30: u1 = 0b1,5856 decoded30: u1 = 0b1,
5932 sf: Register.IntegerSize,5857 sf: Register.GeneralSize,
5933 };5858 };
59345859
5935 /// C6.2.258 REV325860 /// C6.2.258 REV32
...@@ -5942,21 +5867,21 @@ pub const Instruction = packed union {...@@ -5942,21 +5867,21 @@ pub const Instruction = packed union {
5942 decoded21: u8 = 0b11010110,5867 decoded21: u8 = 0b11010110,
5943 S: bool = false,5868 S: bool = false,
5944 decoded30: u1 = 0b1,5869 decoded30: u1 = 0b1,
5945 sf: Register.IntegerSize = .doubleword,5870 sf: Register.GeneralSize = .doubleword,
5946 };5871 };
59475872
5948 /// C6.2.256 REV5873 /// C6.2.256 REV
5949 pub const Rev = packed struct {5874 pub const Rev = packed struct {
5950 Rd: Register.Encoded,5875 Rd: Register.Encoded,
5951 Rn: Register.Encoded,5876 Rn: Register.Encoded,
5952 opc0: Register.IntegerSize,5877 opc0: Register.GeneralSize,
5953 opc1: u1 = 0b1,5878 opc1: u1 = 0b1,
5954 decoded12: u4 = 0b0000,5879 decoded12: u4 = 0b0000,
5955 decoded16: u5 = 0b00000,5880 decoded16: u5 = 0b00000,
5956 decoded21: u8 = 0b11010110,5881 decoded21: u8 = 0b11010110,
5957 S: bool = false,5882 S: bool = false,
5958 decoded30: u1 = 0b1,5883 decoded30: u1 = 0b1,
5959 sf: Register.IntegerSize,5884 sf: Register.GeneralSize,
5960 };5885 };
59615886
5962 /// C6.2.58 CLZ5887 /// C6.2.58 CLZ
...@@ -5969,7 +5894,7 @@ pub const Instruction = packed union {...@@ -5969,7 +5894,7 @@ pub const Instruction = packed union {
5969 decoded21: u8 = 0b11010110,5894 decoded21: u8 = 0b11010110,
5970 S: bool = false,5895 S: bool = false,
5971 decoded30: u1 = 0b1,5896 decoded30: u1 = 0b1,
5972 sf: Register.IntegerSize,5897 sf: Register.GeneralSize,
5973 };5898 };
59745899
5975 /// C6.2.57 CLS5900 /// C6.2.57 CLS
...@@ -5982,7 +5907,7 @@ pub const Instruction = packed union {...@@ -5982,7 +5907,7 @@ pub const Instruction = packed union {
5982 decoded21: u8 = 0b11010110,5907 decoded21: u8 = 0b11010110,
5983 S: bool = false,5908 S: bool = false,
5984 decoded30: u1 = 0b1,5909 decoded30: u1 = 0b1,
5985 sf: Register.IntegerSize,5910 sf: Register.GeneralSize,
5986 };5911 };
59875912
5988 pub const Decoded = union(enum) {5913 pub const Decoded = union(enum) {
...@@ -6040,7 +5965,7 @@ pub const Instruction = packed union {...@@ -6040,7 +5965,7 @@ pub const Instruction = packed union {
6040 shift: Shift.Op,5965 shift: Shift.Op,
6041 decoded24: u5 = 0b01010,5966 decoded24: u5 = 0b01010,
6042 opc: LogicalOpc,5967 opc: LogicalOpc,
6043 sf: Register.IntegerSize,5968 sf: Register.GeneralSize,
6044 };5969 };
60455970
6046 /// C6.2.13 AND (shifted register)5971 /// C6.2.13 AND (shifted register)
...@@ -6053,7 +5978,7 @@ pub const Instruction = packed union {...@@ -6053,7 +5978,7 @@ pub const Instruction = packed union {
6053 shift: Shift.Op,5978 shift: Shift.Op,
6054 decoded24: u5 = 0b01010,5979 decoded24: u5 = 0b01010,
6055 opc: LogicalOpc = .@"and",5980 opc: LogicalOpc = .@"and",
6056 sf: Register.IntegerSize,5981 sf: Register.GeneralSize,
6057 };5982 };
60585983
6059 /// C6.2.32 BIC (shifted register)5984 /// C6.2.32 BIC (shifted register)
...@@ -6066,7 +5991,7 @@ pub const Instruction = packed union {...@@ -6066,7 +5991,7 @@ pub const Instruction = packed union {
6066 shift: Shift.Op,5991 shift: Shift.Op,
6067 decoded24: u5 = 0b01010,5992 decoded24: u5 = 0b01010,
6068 opc: LogicalOpc = .@"and",5993 opc: LogicalOpc = .@"and",
6069 sf: Register.IntegerSize,5994 sf: Register.GeneralSize,
6070 };5995 };
60715996
6072 /// C6.2.241 ORR (shifted register)5997 /// C6.2.241 ORR (shifted register)
...@@ -6079,7 +6004,7 @@ pub const Instruction = packed union {...@@ -6079,7 +6004,7 @@ pub const Instruction = packed union {
6079 shift: Shift.Op,6004 shift: Shift.Op,
6080 decoded24: u5 = 0b01010,6005 decoded24: u5 = 0b01010,
6081 opc: LogicalOpc = .orr,6006 opc: LogicalOpc = .orr,
6082 sf: Register.IntegerSize,6007 sf: Register.GeneralSize,
6083 };6008 };
60846009
6085 /// C6.2.239 ORN (shifted register)6010 /// C6.2.239 ORN (shifted register)
...@@ -6092,7 +6017,7 @@ pub const Instruction = packed union {...@@ -6092,7 +6017,7 @@ pub const Instruction = packed union {
6092 shift: Shift.Op,6017 shift: Shift.Op,
6093 decoded24: u5 = 0b01010,6018 decoded24: u5 = 0b01010,
6094 opc: LogicalOpc = .orr,6019 opc: LogicalOpc = .orr,
6095 sf: Register.IntegerSize,6020 sf: Register.GeneralSize,
6096 };6021 };
60976022
6098 /// C6.2.120 EOR (shifted register)6023 /// C6.2.120 EOR (shifted register)
...@@ -6105,7 +6030,7 @@ pub const Instruction = packed union {...@@ -6105,7 +6030,7 @@ pub const Instruction = packed union {
6105 shift: Shift.Op,6030 shift: Shift.Op,
6106 decoded24: u5 = 0b01010,6031 decoded24: u5 = 0b01010,
6107 opc: LogicalOpc = .eor,6032 opc: LogicalOpc = .eor,
6108 sf: Register.IntegerSize,6033 sf: Register.GeneralSize,
6109 };6034 };
61106035
6111 /// C6.2.118 EON (shifted register)6036 /// C6.2.118 EON (shifted register)
...@@ -6118,7 +6043,7 @@ pub const Instruction = packed union {...@@ -6118,7 +6043,7 @@ pub const Instruction = packed union {
6118 shift: Shift.Op,6043 shift: Shift.Op,
6119 decoded24: u5 = 0b01010,6044 decoded24: u5 = 0b01010,
6120 opc: LogicalOpc = .eor,6045 opc: LogicalOpc = .eor,
6121 sf: Register.IntegerSize,6046 sf: Register.GeneralSize,
6122 };6047 };
61236048
6124 /// C6.2.15 ANDS (shifted register)6049 /// C6.2.15 ANDS (shifted register)
...@@ -6131,7 +6056,7 @@ pub const Instruction = packed union {...@@ -6131,7 +6056,7 @@ pub const Instruction = packed union {
6131 shift: Shift.Op,6056 shift: Shift.Op,
6132 decoded24: u5 = 0b01010,6057 decoded24: u5 = 0b01010,
6133 opc: LogicalOpc = .ands,6058 opc: LogicalOpc = .ands,
6134 sf: Register.IntegerSize,6059 sf: Register.GeneralSize,
6135 };6060 };
61366061
6137 /// C6.2.33 BICS (shifted register)6062 /// C6.2.33 BICS (shifted register)
...@@ -6144,7 +6069,7 @@ pub const Instruction = packed union {...@@ -6144,7 +6069,7 @@ pub const Instruction = packed union {
6144 shift: Shift.Op,6069 shift: Shift.Op,
6145 decoded24: u5 = 0b01010,6070 decoded24: u5 = 0b01010,
6146 opc: LogicalOpc = .ands,6071 opc: LogicalOpc = .ands,
6147 sf: Register.IntegerSize,6072 sf: Register.GeneralSize,
6148 };6073 };
61496074
6150 pub const Decoded = union(enum) {6075 pub const Decoded = union(enum) {
...@@ -6200,7 +6125,7 @@ pub const Instruction = packed union {...@@ -6200,7 +6125,7 @@ pub const Instruction = packed union {
6200 decoded24: u5 = 0b01011,6125 decoded24: u5 = 0b01011,
6201 S: bool,6126 S: bool,
6202 op: AddSubtractOp,6127 op: AddSubtractOp,
6203 sf: Register.IntegerSize,6128 sf: Register.GeneralSize,
6204 };6129 };
62056130
6206 /// C6.2.5 ADD (shifted register)6131 /// C6.2.5 ADD (shifted register)
...@@ -6214,7 +6139,7 @@ pub const Instruction = packed union {...@@ -6214,7 +6139,7 @@ pub const Instruction = packed union {
6214 decoded24: u5 = 0b01011,6139 decoded24: u5 = 0b01011,
6215 S: bool = false,6140 S: bool = false,
6216 op: AddSubtractOp = .add,6141 op: AddSubtractOp = .add,
6217 sf: Register.IntegerSize,6142 sf: Register.GeneralSize,
6218 };6143 };
62196144
6220 /// C6.2.9 ADDS (shifted register)6145 /// C6.2.9 ADDS (shifted register)
...@@ -6228,7 +6153,7 @@ pub const Instruction = packed union {...@@ -6228,7 +6153,7 @@ pub const Instruction = packed union {
6228 decoded24: u5 = 0b01011,6153 decoded24: u5 = 0b01011,
6229 S: bool = true,6154 S: bool = true,
6230 op: AddSubtractOp = .add,6155 op: AddSubtractOp = .add,
6231 sf: Register.IntegerSize,6156 sf: Register.GeneralSize,
6232 };6157 };
62336158
6234 /// C6.2.5 SUB (shifted register)6159 /// C6.2.5 SUB (shifted register)
...@@ -6242,7 +6167,7 @@ pub const Instruction = packed union {...@@ -6242,7 +6167,7 @@ pub const Instruction = packed union {
6242 decoded24: u5 = 0b01011,6167 decoded24: u5 = 0b01011,
6243 S: bool = false,6168 S: bool = false,
6244 op: AddSubtractOp = .sub,6169 op: AddSubtractOp = .sub,
6245 sf: Register.IntegerSize,6170 sf: Register.GeneralSize,
6246 };6171 };
62476172
6248 /// C6.2.9 SUBS (shifted register)6173 /// C6.2.9 SUBS (shifted register)
...@@ -6256,7 +6181,7 @@ pub const Instruction = packed union {...@@ -6256,7 +6181,7 @@ pub const Instruction = packed union {
6256 decoded24: u5 = 0b01011,6181 decoded24: u5 = 0b01011,
6257 S: bool = true,6182 S: bool = true,
6258 op: AddSubtractOp = .sub,6183 op: AddSubtractOp = .sub,
6259 sf: Register.IntegerSize,6184 sf: Register.GeneralSize,
6260 };6185 };
62616186
6262 pub const Decoded = union(enum) {6187 pub const Decoded = union(enum) {
...@@ -6304,7 +6229,7 @@ pub const Instruction = packed union {...@@ -6304,7 +6229,7 @@ pub const Instruction = packed union {
6304 decoded24: u5 = 0b01011,6229 decoded24: u5 = 0b01011,
6305 S: bool,6230 S: bool,
6306 op: AddSubtractOp,6231 op: AddSubtractOp,
6307 sf: Register.IntegerSize,6232 sf: Register.GeneralSize,
6308 };6233 };
63096234
6310 /// C6.2.3 ADD (extended register)6235 /// C6.2.3 ADD (extended register)
...@@ -6319,7 +6244,7 @@ pub const Instruction = packed union {...@@ -6319,7 +6244,7 @@ pub const Instruction = packed union {
6319 decoded24: u5 = 0b01011,6244 decoded24: u5 = 0b01011,
6320 S: bool = false,6245 S: bool = false,
6321 op: AddSubtractOp = .add,6246 op: AddSubtractOp = .add,
6322 sf: Register.IntegerSize,6247 sf: Register.GeneralSize,
6323 };6248 };
63246249
6325 /// C6.2.7 ADDS (extended register)6250 /// C6.2.7 ADDS (extended register)
...@@ -6334,7 +6259,7 @@ pub const Instruction = packed union {...@@ -6334,7 +6259,7 @@ pub const Instruction = packed union {
6334 decoded24: u5 = 0b01011,6259 decoded24: u5 = 0b01011,
6335 S: bool = true,6260 S: bool = true,
6336 op: AddSubtractOp = .add,6261 op: AddSubtractOp = .add,
6337 sf: Register.IntegerSize,6262 sf: Register.GeneralSize,
6338 };6263 };
63396264
6340 /// C6.2.356 SUB (extended register)6265 /// C6.2.356 SUB (extended register)
...@@ -6349,7 +6274,7 @@ pub const Instruction = packed union {...@@ -6349,7 +6274,7 @@ pub const Instruction = packed union {
6349 decoded24: u5 = 0b01011,6274 decoded24: u5 = 0b01011,
6350 S: bool = false,6275 S: bool = false,
6351 op: AddSubtractOp = .sub,6276 op: AddSubtractOp = .sub,
6352 sf: Register.IntegerSize,6277 sf: Register.GeneralSize,
6353 };6278 };
63546279
6355 /// C6.2.362 SUBS (extended register)6280 /// C6.2.362 SUBS (extended register)
...@@ -6364,7 +6289,7 @@ pub const Instruction = packed union {...@@ -6364,7 +6289,7 @@ pub const Instruction = packed union {
6364 decoded24: u5 = 0b01011,6289 decoded24: u5 = 0b01011,
6365 S: bool = true,6290 S: bool = true,
6366 op: AddSubtractOp = .sub,6291 op: AddSubtractOp = .sub,
6367 sf: Register.IntegerSize,6292 sf: Register.GeneralSize,
6368 };6293 };
63696294
6370 pub const Option = enum(u3) {6295 pub const Option = enum(u3) {
...@@ -6377,7 +6302,7 @@ pub const Instruction = packed union {...@@ -6377,7 +6302,7 @@ pub const Instruction = packed union {
6377 sxtw = 0b110,6302 sxtw = 0b110,
6378 sxtx = 0b111,6303 sxtx = 0b111,
63796304
6380 pub fn sf(option: Option) Register.IntegerSize {6305 pub fn sf(option: Option) Register.GeneralSize {
6381 return switch (option) {6306 return switch (option) {
6382 .uxtb, .uxth, .uxtw, .sxtb, .sxth, .sxtw => .word,6307 .uxtb, .uxth, .uxtw, .sxtb, .sxth, .sxtw => .word,
6383 .uxtx, .sxtx => .doubleword,6308 .uxtx, .sxtx => .doubleword,
...@@ -6443,7 +6368,7 @@ pub const Instruction = packed union {...@@ -6443,7 +6368,7 @@ pub const Instruction = packed union {
6443 decoded21: u8 = 0b11010000,6368 decoded21: u8 = 0b11010000,
6444 S: bool,6369 S: bool,
6445 op: Op,6370 op: Op,
6446 sf: Register.IntegerSize,6371 sf: Register.GeneralSize,
6447 };6372 };
64486373
6449 /// C6.2.1 ADC6374 /// C6.2.1 ADC
...@@ -6455,7 +6380,7 @@ pub const Instruction = packed union {...@@ -6455,7 +6380,7 @@ pub const Instruction = packed union {
6455 decoded21: u8 = 0b11010000,6380 decoded21: u8 = 0b11010000,
6456 S: bool = false,6381 S: bool = false,
6457 op: Op = .adc,6382 op: Op = .adc,
6458 sf: Register.IntegerSize,6383 sf: Register.GeneralSize,
6459 };6384 };
64606385
6461 /// C6.2.2 ADCS6386 /// C6.2.2 ADCS
...@@ -6467,7 +6392,7 @@ pub const Instruction = packed union {...@@ -6467,7 +6392,7 @@ pub const Instruction = packed union {
6467 decoded21: u8 = 0b11010000,6392 decoded21: u8 = 0b11010000,
6468 S: bool = true,6393 S: bool = true,
6469 op: Op = .adc,6394 op: Op = .adc,
6470 sf: Register.IntegerSize,6395 sf: Register.GeneralSize,
6471 };6396 };
64726397
6473 /// C6.2.265 SBC6398 /// C6.2.265 SBC
...@@ -6479,7 +6404,7 @@ pub const Instruction = packed union {...@@ -6479,7 +6404,7 @@ pub const Instruction = packed union {
6479 decoded21: u8 = 0b11010000,6404 decoded21: u8 = 0b11010000,
6480 S: bool = false,6405 S: bool = false,
6481 op: Op = .sbc,6406 op: Op = .sbc,
6482 sf: Register.IntegerSize,6407 sf: Register.GeneralSize,
6483 };6408 };
64846409
6485 /// C6.2.266 SBCS6410 /// C6.2.266 SBCS
...@@ -6491,7 +6416,7 @@ pub const Instruction = packed union {...@@ -6491,7 +6416,7 @@ pub const Instruction = packed union {
6491 decoded21: u8 = 0b11010000,6416 decoded21: u8 = 0b11010000,
6492 S: bool = true,6417 S: bool = true,
6493 op: Op = .sbc,6418 op: Op = .sbc,
6494 sf: Register.IntegerSize,6419 sf: Register.GeneralSize,
6495 };6420 };
64966421
6497 pub const Op = enum(u1) {6422 pub const Op = enum(u1) {
...@@ -6532,7 +6457,7 @@ pub const Instruction = packed union {...@@ -6532,7 +6457,7 @@ pub const Instruction = packed union {
6532 decoded21: u8 = 0b11010000,6457 decoded21: u8 = 0b11010000,
6533 S: bool,6458 S: bool,
6534 op: u1,6459 op: u1,
6535 sf: Register.IntegerSize,6460 sf: Register.GeneralSize,
6536 };6461 };
6537 };6462 };
65386463
...@@ -6553,7 +6478,7 @@ pub const Instruction = packed union {...@@ -6553,7 +6478,7 @@ pub const Instruction = packed union {
6553 decoded21: u8 = 0b11010000,6478 decoded21: u8 = 0b11010000,
6554 S: bool,6479 S: bool,
6555 op: u1,6480 op: u1,
6556 sf: Register.IntegerSize,6481 sf: Register.GeneralSize,
6557 };6482 };
6558 };6483 };
65596484
...@@ -6574,7 +6499,7 @@ pub const Instruction = packed union {...@@ -6574,7 +6499,7 @@ pub const Instruction = packed union {
6574 decoded21: u8 = 0b11010010,6499 decoded21: u8 = 0b11010010,
6575 S: bool,6500 S: bool,
6576 op: Op,6501 op: Op,
6577 sf: Register.IntegerSize,6502 sf: Register.GeneralSize,
6578 };6503 };
65796504
6580 /// C6.2.49 CCMN (register)6505 /// C6.2.49 CCMN (register)
...@@ -6589,7 +6514,7 @@ pub const Instruction = packed union {...@@ -6589,7 +6514,7 @@ pub const Instruction = packed union {
6589 decoded21: u8 = 0b11010010,6514 decoded21: u8 = 0b11010010,
6590 S: bool = true,6515 S: bool = true,
6591 op: Op = .ccmn,6516 op: Op = .ccmn,
6592 sf: Register.IntegerSize,6517 sf: Register.GeneralSize,
6593 };6518 };
65946519
6595 /// C6.2.51 CCMP (register)6520 /// C6.2.51 CCMP (register)
...@@ -6604,7 +6529,7 @@ pub const Instruction = packed union {...@@ -6604,7 +6529,7 @@ pub const Instruction = packed union {
6604 decoded21: u8 = 0b11010010,6529 decoded21: u8 = 0b11010010,
6605 S: bool = true,6530 S: bool = true,
6606 op: Op = .ccmp,6531 op: Op = .ccmp,
6607 sf: Register.IntegerSize,6532 sf: Register.GeneralSize,
6608 };6533 };
66096534
6610 pub const Op = enum(u1) {6535 pub const Op = enum(u1) {
...@@ -6630,7 +6555,7 @@ pub const Instruction = packed union {...@@ -6630,7 +6555,7 @@ pub const Instruction = packed union {
6630 decoded21: u8 = 0b11010010,6555 decoded21: u8 = 0b11010010,
6631 S: bool,6556 S: bool,
6632 op: Op,6557 op: Op,
6633 sf: Register.IntegerSize,6558 sf: Register.GeneralSize,
6634 };6559 };
66356560
6636 /// C6.2.48 CCMN (immediate)6561 /// C6.2.48 CCMN (immediate)
...@@ -6645,7 +6570,7 @@ pub const Instruction = packed union {...@@ -6645,7 +6570,7 @@ pub const Instruction = packed union {
6645 decoded21: u8 = 0b11010010,6570 decoded21: u8 = 0b11010010,
6646 S: bool = true,6571 S: bool = true,
6647 op: Op = .ccmn,6572 op: Op = .ccmn,
6648 sf: Register.IntegerSize,6573 sf: Register.GeneralSize,
6649 };6574 };
66506575
6651 /// C6.2.50 CCMP (immediate)6576 /// C6.2.50 CCMP (immediate)
...@@ -6660,7 +6585,7 @@ pub const Instruction = packed union {...@@ -6660,7 +6585,7 @@ pub const Instruction = packed union {
6660 decoded21: u8 = 0b11010010,6585 decoded21: u8 = 0b11010010,
6661 S: bool = true,6586 S: bool = true,
6662 op: Op = .ccmp,6587 op: Op = .ccmp,
6663 sf: Register.IntegerSize,6588 sf: Register.GeneralSize,
6664 };6589 };
66656590
6666 pub const Op = enum(u1) {6591 pub const Op = enum(u1) {
...@@ -6686,7 +6611,7 @@ pub const Instruction = packed union {...@@ -6686,7 +6611,7 @@ pub const Instruction = packed union {
6686 decoded21: u8 = 0b11010100,6611 decoded21: u8 = 0b11010100,
6687 S: bool,6612 S: bool,
6688 op: u1,6613 op: u1,
6689 sf: Register.IntegerSize,6614 sf: Register.GeneralSize,
6690 };6615 };
66916616
6692 /// C6.2.103 CSEL6617 /// C6.2.103 CSEL
...@@ -6699,7 +6624,7 @@ pub const Instruction = packed union {...@@ -6699,7 +6624,7 @@ pub const Instruction = packed union {
6699 decoded21: u8 = 0b11010100,6624 decoded21: u8 = 0b11010100,
6700 S: bool = false,6625 S: bool = false,
6701 op: u1 = 0b0,6626 op: u1 = 0b0,
6702 sf: Register.IntegerSize,6627 sf: Register.GeneralSize,
6703 };6628 };
67046629
6705 /// C6.2.106 CSINC6630 /// C6.2.106 CSINC
...@@ -6712,7 +6637,7 @@ pub const Instruction = packed union {...@@ -6712,7 +6637,7 @@ pub const Instruction = packed union {
6712 decoded21: u8 = 0b11010100,6637 decoded21: u8 = 0b11010100,
6713 S: bool = false,6638 S: bool = false,
6714 op: u1 = 0b0,6639 op: u1 = 0b0,
6715 sf: Register.IntegerSize,6640 sf: Register.GeneralSize,
6716 };6641 };
67176642
6718 /// C6.2.107 CSINV6643 /// C6.2.107 CSINV
...@@ -6725,7 +6650,7 @@ pub const Instruction = packed union {...@@ -6725,7 +6650,7 @@ pub const Instruction = packed union {
6725 decoded21: u8 = 0b11010100,6650 decoded21: u8 = 0b11010100,
6726 S: bool = false,6651 S: bool = false,
6727 op: u1 = 0b1,6652 op: u1 = 0b1,
6728 sf: Register.IntegerSize,6653 sf: Register.GeneralSize,
6729 };6654 };
67306655
6731 /// C6.2.108 CSNEG6656 /// C6.2.108 CSNEG
...@@ -6738,7 +6663,7 @@ pub const Instruction = packed union {...@@ -6738,7 +6663,7 @@ pub const Instruction = packed union {
6738 decoded21: u8 = 0b11010100,6663 decoded21: u8 = 0b11010100,
6739 S: bool = false,6664 S: bool = false,
6740 op: u1 = 0b1,6665 op: u1 = 0b1,
6741 sf: Register.IntegerSize,6666 sf: Register.GeneralSize,
6742 };6667 };
67436668
6744 pub const Decoded = union(enum) {6669 pub const Decoded = union(enum) {
...@@ -6788,7 +6713,7 @@ pub const Instruction = packed union {...@@ -6788,7 +6713,7 @@ pub const Instruction = packed union {
6788 op31: u3,6713 op31: u3,
6789 decoded24: u5 = 0b11011,6714 decoded24: u5 = 0b11011,
6790 op54: u2,6715 op54: u2,
6791 sf: Register.IntegerSize,6716 sf: Register.GeneralSize,
6792 };6717 };
67936718
6794 /// C6.2.218 MADD6719 /// C6.2.218 MADD
...@@ -6801,7 +6726,7 @@ pub const Instruction = packed union {...@@ -6801,7 +6726,7 @@ pub const Instruction = packed union {
6801 op31: u3 = 0b000,6726 op31: u3 = 0b000,
6802 decoded24: u5 = 0b11011,6727 decoded24: u5 = 0b11011,
6803 op54: u2 = 0b00,6728 op54: u2 = 0b00,
6804 sf: Register.IntegerSize,6729 sf: Register.GeneralSize,
6805 };6730 };
68066731
6807 /// C6.2.231 MSUB6732 /// C6.2.231 MSUB
...@@ -6814,7 +6739,7 @@ pub const Instruction = packed union {...@@ -6814,7 +6739,7 @@ pub const Instruction = packed union {
6814 op31: u3 = 0b000,6739 op31: u3 = 0b000,
6815 decoded24: u5 = 0b11011,6740 decoded24: u5 = 0b11011,
6816 op54: u2 = 0b00,6741 op54: u2 = 0b00,
6817 sf: Register.IntegerSize,6742 sf: Register.GeneralSize,
6818 };6743 };
68196744
6820 /// C6.2.282 SMADDL6745 /// C6.2.282 SMADDL
...@@ -6828,7 +6753,7 @@ pub const Instruction = packed union {...@@ -6828,7 +6753,7 @@ pub const Instruction = packed union {
6828 U: std.builtin.Signedness = .signed,6753 U: std.builtin.Signedness = .signed,
6829 decoded24: u5 = 0b11011,6754 decoded24: u5 = 0b11011,
6830 op54: u2 = 0b00,6755 op54: u2 = 0b00,
6831 sf: Register.IntegerSize = .doubleword,6756 sf: Register.GeneralSize = .doubleword,
6832 };6757 };
68336758
6834 /// C6.2.287 SMSUBL6759 /// C6.2.287 SMSUBL
...@@ -6842,21 +6767,21 @@ pub const Instruction = packed union {...@@ -6842,21 +6767,21 @@ pub const Instruction = packed union {
6842 U: std.builtin.Signedness = .signed,6767 U: std.builtin.Signedness = .signed,
6843 decoded24: u5 = 0b11011,6768 decoded24: u5 = 0b11011,
6844 op54: u2 = 0b00,6769 op54: u2 = 0b00,
6845 sf: Register.IntegerSize = .doubleword,6770 sf: Register.GeneralSize = .doubleword,
6846 };6771 };
68476772
6848 /// C6.2.288 SMULH6773 /// C6.2.288 SMULH
6849 pub const Smulh = packed struct {6774 pub const Smulh = packed struct {
6850 Rd: Register.Encoded,6775 Rd: Register.Encoded,
6851 Rn: Register.Encoded,6776 Rn: Register.Encoded,
6852 Ra: Register.Encoded = @enumFromInt(0b11111),6777 Ra: Register.Encoded = Register.Alias.zr.encode(.{}),
6853 o0: AddSubtractOp = .add,6778 o0: AddSubtractOp = .add,
6854 Rm: Register.Encoded,6779 Rm: Register.Encoded,
6855 op21: u2 = 0b10,6780 op21: u2 = 0b10,
6856 U: std.builtin.Signedness = .signed,6781 U: std.builtin.Signedness = .signed,
6857 decoded24: u5 = 0b11011,6782 decoded24: u5 = 0b11011,
6858 op54: u2 = 0b00,6783 op54: u2 = 0b00,
6859 sf: Register.IntegerSize = .doubleword,6784 sf: Register.GeneralSize = .doubleword,
6860 };6785 };
68616786
6862 /// C6.2.389 UMADDL6787 /// C6.2.389 UMADDL
...@@ -6870,7 +6795,7 @@ pub const Instruction = packed union {...@@ -6870,7 +6795,7 @@ pub const Instruction = packed union {
6870 U: std.builtin.Signedness = .unsigned,6795 U: std.builtin.Signedness = .unsigned,
6871 decoded24: u5 = 0b11011,6796 decoded24: u5 = 0b11011,
6872 op54: u2 = 0b00,6797 op54: u2 = 0b00,
6873 sf: Register.IntegerSize = .doubleword,6798 sf: Register.GeneralSize = .doubleword,
6874 };6799 };
68756800
6876 /// C6.2.391 UMSUBL6801 /// C6.2.391 UMSUBL
...@@ -6884,21 +6809,21 @@ pub const Instruction = packed union {...@@ -6884,21 +6809,21 @@ pub const Instruction = packed union {
6884 U: std.builtin.Signedness = .unsigned,6809 U: std.builtin.Signedness = .unsigned,
6885 decoded24: u5 = 0b11011,6810 decoded24: u5 = 0b11011,
6886 op54: u2 = 0b00,6811 op54: u2 = 0b00,
6887 sf: Register.IntegerSize = .doubleword,6812 sf: Register.GeneralSize = .doubleword,
6888 };6813 };
68896814
6890 /// C6.2.392 UMULH6815 /// C6.2.392 UMULH
6891 pub const Umulh = packed struct {6816 pub const Umulh = packed struct {
6892 Rd: Register.Encoded,6817 Rd: Register.Encoded,
6893 Rn: Register.Encoded,6818 Rn: Register.Encoded,
6894 Ra: Register.Encoded = @enumFromInt(0b11111),6819 Ra: Register.Encoded = Register.Alias.zr.encode(.{}),
6895 o0: AddSubtractOp = .add,6820 o0: AddSubtractOp = .add,
6896 Rm: Register.Encoded,6821 Rm: Register.Encoded,
6897 op21: u2 = 0b10,6822 op21: u2 = 0b10,
6898 U: std.builtin.Signedness = .unsigned,6823 U: std.builtin.Signedness = .unsigned,
6899 decoded24: u5 = 0b11011,6824 decoded24: u5 = 0b11011,
6900 op54: u2 = 0b00,6825 op54: u2 = 0b00,
6901 sf: Register.IntegerSize = .doubleword,6826 sf: Register.GeneralSize = .doubleword,
6902 };6827 };
69036828
6904 pub const Decoded = union(enum) {6829 pub const Decoded = union(enum) {
...@@ -6965,8 +6890,6 @@ pub const Instruction = packed union {...@@ -6965,8 +6890,6 @@ pub const Instruction = packed union {
6965 pub const none: Shift = .{ .lsl = 0 };6890 pub const none: Shift = .{ .lsl = 0 };
6966 };6891 };
69676892
6968 pub const Nzcv = packed struct { v: bool, c: bool, z: bool, n: bool };
6969
6970 pub const Decoded = union(enum) {6893 pub const Decoded = union(enum) {
6971 unallocated,6894 unallocated,
6972 data_processing_two_source: DataProcessingTwoSource,6895 data_processing_two_source: DataProcessingTwoSource,
...@@ -7027,10 +6950,12 @@ pub const Instruction = packed union {...@@ -7027,10 +6950,12 @@ pub const Instruction = packed union {
7027 simd_across_lanes: SimdAcrossLanes,6950 simd_across_lanes: SimdAcrossLanes,
7028 simd_three_same: SimdThreeSame,6951 simd_three_same: SimdThreeSame,
7029 simd_modified_immediate: SimdModifiedImmediate,6952 simd_modified_immediate: SimdModifiedImmediate,
6953 convert_float_fixed: ConvertFloatFixed,
7030 convert_float_integer: ConvertFloatInteger,6954 convert_float_integer: ConvertFloatInteger,
7031 float_data_processing_one_source: FloatDataProcessingOneSource,6955 float_data_processing_one_source: FloatDataProcessingOneSource,
7032 float_compare: FloatCompare,6956 float_compare: FloatCompare,
7033 float_immediate: FloatImmediate,6957 float_immediate: FloatImmediate,
6958 float_conditional_compare: FloatConditionalCompare,
7034 float_data_processing_two_source: FloatDataProcessingTwoSource,6959 float_data_processing_two_source: FloatDataProcessingTwoSource,
7035 float_conditional_select: FloatConditionalSelect,6960 float_conditional_select: FloatConditionalSelect,
7036 float_data_processing_three_source: FloatDataProcessingThreeSource,6961 float_data_processing_three_source: FloatDataProcessingThreeSource,
...@@ -7385,22 +7310,86 @@ pub const Instruction = packed union {...@@ -7385,22 +7310,86 @@ pub const Instruction = packed union {
7385 U: std.builtin.Signedness = .unsigned,7310 U: std.builtin.Signedness = .unsigned,
7386 decoded30: u2 = 0b01,7311 decoded30: u2 = 0b01,
7387 };7312 };
7388 };
73897313
7390 /// Advanced SIMD scalar two-register miscellaneous7314 pub const Decoded = union(enum) {
7391 pub const SimdScalarTwoRegisterMiscellaneous = packed union {7315 unallocated,
7392 group: @This().Group,7316 fcvtns: Fcvtns,
7393 suqadd: Suqadd,7317 fcvtms: Fcvtms,
7394 sqabs: Sqabs,7318 fcvtas: Fcvtas,
7395 cmgt: Cmgt,7319 scvtf: Scvtf,
7396 cmeq: Cmeq,7320 fcmgt: Fcmgt,
7397 cmlt: Cmlt,7321 fcmeq: Fcmeq,
7398 abs: Abs,7322 fcmlt: Fcmlt,
7399 sqxtn: Sqxtn,7323 fcvtps: Fcvtps,
7400 fcvtns: Fcvtns,7324 fcvtzs: Fcvtzs,
7401 fcvtms: Fcvtms,7325 frecpe: Frecpe,
7402 fcvtas: Fcvtas,7326 frecpx: Frecpx,
7403 scvtf: Scvtf,7327 fcvtnu: Fcvtnu,
7328 fcvtmu: Fcvtmu,
7329 fcvtau: Fcvtau,
7330 ucvtf: Ucvtf,
7331 fcmge: Fcmge,
7332 fcmle: Fcmle,
7333 fcvtpu: Fcvtpu,
7334 fcvtzu: Fcvtzu,
7335 frsqrte: Frsqrte,
7336 };
7337 pub fn decode(inst: @This()) @This().Decoded {
7338 return switch (inst.group.U) {
7339 .signed => switch (inst.group.a) {
7340 0b0 => switch (inst.group.opcode) {
7341 else => .unallocated,
7342 0b11010 => .{ .fcvtns = inst.fcvtns },
7343 0b11011 => .{ .fcvtms = inst.fcvtms },
7344 0b11100 => .{ .fcvtas = inst.fcvtas },
7345 0b11101 => .{ .scvtf = inst.scvtf },
7346 },
7347 0b1 => switch (inst.group.opcode) {
7348 else => .unallocated,
7349 0b01100 => .{ .fcmgt = inst.fcmgt },
7350 0b01101 => .{ .fcmeq = inst.fcmeq },
7351 0b01110 => .{ .fcmlt = inst.fcmlt },
7352 0b11010 => .{ .fcvtps = inst.fcvtps },
7353 0b11011 => .{ .fcvtzs = inst.fcvtzs },
7354 0b11101 => .{ .frecpe = inst.frecpe },
7355 0b11111 => .{ .frecpx = inst.frecpx },
7356 },
7357 },
7358 .unsigned => switch (inst.group.a) {
7359 0b0 => switch (inst.group.opcode) {
7360 else => .unallocated,
7361 0b11010 => .{ .fcvtnu = inst.fcvtnu },
7362 0b11011 => .{ .fcvtmu = inst.fcvtmu },
7363 0b11100 => .{ .fcvtau = inst.fcvtau },
7364 0b11101 => .{ .ucvtf = inst.ucvtf },
7365 },
7366 0b1 => switch (inst.group.opcode) {
7367 else => .unallocated,
7368 0b01100 => .{ .fcmge = inst.fcmge },
7369 0b01101 => .{ .fcmle = inst.fcmle },
7370 0b11010 => .{ .fcvtpu = inst.fcvtpu },
7371 0b11011 => .{ .fcvtzu = inst.fcvtzu },
7372 0b11101 => .{ .frsqrte = inst.frsqrte },
7373 },
7374 },
7375 };
7376 }
7377 };
7378
7379 /// Advanced SIMD scalar two-register miscellaneous
7380 pub const SimdScalarTwoRegisterMiscellaneous = packed union {
7381 group: @This().Group,
7382 suqadd: Suqadd,
7383 sqabs: Sqabs,
7384 cmgt: Cmgt,
7385 cmeq: Cmeq,
7386 cmlt: Cmlt,
7387 abs: Abs,
7388 sqxtn: Sqxtn,
7389 fcvtns: Fcvtns,
7390 fcvtms: Fcvtms,
7391 fcvtas: Fcvtas,
7392 scvtf: Scvtf,
7404 fcmgt: Fcmgt,7393 fcmgt: Fcmgt,
7405 fcmeq: Fcmeq,7394 fcmeq: Fcmeq,
7406 fcmlt: Fcmlt,7395 fcmlt: Fcmlt,
...@@ -7913,6 +7902,129 @@ pub const Instruction = packed union {...@@ -7913,6 +7902,129 @@ pub const Instruction = packed union {
7913 U: std.builtin.Signedness = .unsigned,7902 U: std.builtin.Signedness = .unsigned,
7914 decoded30: u2 = 0b01,7903 decoded30: u2 = 0b01,
7915 };7904 };
7905
7906 pub const Decoded = union(enum) {
7907 unallocated,
7908 suqadd: Suqadd,
7909 sqabs: Sqabs,
7910 cmgt: Cmgt,
7911 cmeq: Cmeq,
7912 cmlt: Cmlt,
7913 abs: Abs,
7914 sqxtn: Sqxtn,
7915 fcvtns: Fcvtns,
7916 fcvtms: Fcvtms,
7917 fcvtas: Fcvtas,
7918 scvtf: Scvtf,
7919 fcmgt: Fcmgt,
7920 fcmeq: Fcmeq,
7921 fcmlt: Fcmlt,
7922 fcvtps: Fcvtps,
7923 fcvtzs: Fcvtzs,
7924 frecpe: Frecpe,
7925 frecpx: Frecpx,
7926 usqadd: Usqadd,
7927 sqneg: Sqneg,
7928 cmge: Cmge,
7929 cmle: Cmle,
7930 neg: Neg,
7931 sqxtun: Sqxtun,
7932 uqxtn: Uqxtn,
7933 fcvtxn: Fcvtxn,
7934 fcvtnu: Fcvtnu,
7935 fcvtmu: Fcvtmu,
7936 fcvtau: Fcvtau,
7937 ucvtf: Ucvtf,
7938 fcmge: Fcmge,
7939 fcmle: Fcmle,
7940 fcvtpu: Fcvtpu,
7941 fcvtzu: Fcvtzu,
7942 frsqrte: Frsqrte,
7943 };
7944 pub fn decode(inst: @This()) @This().Decoded {
7945 return switch (inst.group.U) {
7946 .signed => switch (inst.group.opcode) {
7947 else => .unallocated,
7948 0b00011 => .{ .suqadd = inst.suqadd },
7949 0b00111 => .{ .sqabs = inst.sqabs },
7950 0b01000 => .{ .cmgt = inst.cmgt },
7951 0b01001 => .{ .cmeq = inst.cmeq },
7952 0b01010 => .{ .cmlt = inst.cmlt },
7953 0b01011 => .{ .abs = inst.abs },
7954 0b10100 => .{ .sqxtn = inst.sqxtn },
7955 0b11010 => switch (inst.group.size) {
7956 .byte, .half => .{ .fcvtns = inst.fcvtns },
7957 .single, .double => .{ .fcvtps = inst.fcvtps },
7958 },
7959 0b11011 => switch (inst.group.size) {
7960 .byte, .half => .{ .fcvtms = inst.fcvtms },
7961 .single, .double => .{ .fcvtzs = inst.fcvtzs },
7962 },
7963 0b11100 => switch (inst.group.size) {
7964 .byte, .half => .{ .fcvtas = inst.fcvtas },
7965 .single, .double => .unallocated,
7966 },
7967 0b11101 => switch (inst.group.size) {
7968 .byte, .half => .{ .scvtf = inst.scvtf },
7969 .single, .double => .{ .frecpe = inst.frecpe },
7970 },
7971 0b01100 => switch (inst.group.size) {
7972 .byte, .half => .unallocated,
7973 .single, .double => .{ .fcmgt = inst.fcmgt },
7974 },
7975 0b01101 => switch (inst.group.size) {
7976 .byte, .half => .unallocated,
7977 .single, .double => .{ .fcmeq = inst.fcmeq },
7978 },
7979 0b01110 => switch (inst.group.size) {
7980 .byte, .half => .unallocated,
7981 .single, .double => .{ .fcmlt = inst.fcmlt },
7982 },
7983 0b11111 => switch (inst.group.size) {
7984 .byte, .half => .unallocated,
7985 .single, .double => .{ .frecpx = inst.frecpx },
7986 },
7987 },
7988 .unsigned => switch (inst.group.opcode) {
7989 else => .unallocated,
7990 0b00011 => .{ .usqadd = inst.usqadd },
7991 0b00111 => .{ .sqneg = inst.sqneg },
7992 0b01000 => .{ .cmge = inst.cmge },
7993 0b01001 => .{ .cmle = inst.cmle },
7994 0b01011 => .{ .neg = inst.neg },
7995 0b10010 => .{ .sqxtun = inst.sqxtun },
7996 0b10100 => .{ .uqxtn = inst.uqxtn },
7997 0b10110 => switch (inst.group.size) {
7998 .byte, .half => .{ .fcvtxn = inst.fcvtxn },
7999 .single, .double => .unallocated,
8000 },
8001 0b11010 => switch (inst.group.size) {
8002 .byte, .half => .{ .fcvtnu = inst.fcvtnu },
8003 .single, .double => .{ .fcvtpu = inst.fcvtpu },
8004 },
8005 0b11011 => switch (inst.group.size) {
8006 .byte, .half => .{ .fcvtmu = inst.fcvtmu },
8007 .single, .double => .{ .fcvtzu = inst.fcvtzu },
8008 },
8009 0b11100 => switch (inst.group.size) {
8010 .byte, .half => .{ .fcvtau = inst.fcvtau },
8011 .single, .double => .unallocated,
8012 },
8013 0b11101 => switch (inst.group.size) {
8014 .byte, .half => .{ .ucvtf = inst.ucvtf },
8015 .single, .double => .{ .frsqrte = inst.frsqrte },
8016 },
8017 0b01100 => switch (inst.group.size) {
8018 .byte, .half => .unallocated,
8019 .single, .double => .{ .fcmge = inst.fcmge },
8020 },
8021 0b01101 => switch (inst.group.size) {
8022 .byte, .half => .unallocated,
8023 .single, .double => .{ .fcmle = inst.fcmle },
8024 },
8025 },
8026 };
8027 }
7916 };8028 };
79178029
7918 /// Advanced SIMD scalar pairwise8030 /// Advanced SIMD scalar pairwise
...@@ -7944,6 +8056,20 @@ pub const Instruction = packed union {...@@ -7944,6 +8056,20 @@ pub const Instruction = packed union {
7944 U: std.builtin.Signedness = .signed,8056 U: std.builtin.Signedness = .signed,
7945 decoded30: u2 = 0b01,8057 decoded30: u2 = 0b01,
7946 };8058 };
8059
8060 pub const Decoded = union(enum) {
8061 unallocated,
8062 addp: Addp,
8063 };
8064 pub fn decode(inst: @This()) @This().Decoded {
8065 return switch (inst.group.U) {
8066 .signed => switch (inst.group.opcode) {
8067 else => .unallocated,
8068 0b11011 => .{ .addp = inst.addp },
8069 },
8070 .unsigned => .unallocated,
8071 };
8072 }
7947 };8073 };
79488074
7949 /// Advanced SIMD copy8075 /// Advanced SIMD copy
...@@ -7998,7 +8124,7 @@ pub const Instruction = packed union {...@@ -7998,7 +8124,7 @@ pub const Instruction = packed union {
7998 imm5: u5,8124 imm5: u5,
7999 decoded21: u8 = 0b01110000,8125 decoded21: u8 = 0b01110000,
8000 op: u1 = 0b0,8126 op: u1 = 0b0,
8001 Q: Register.IntegerSize,8127 Q: Register.GeneralSize,
8002 decoded31: u1 = 0b0,8128 decoded31: u1 = 0b0,
8003 };8129 };
80048130
...@@ -8012,7 +8138,7 @@ pub const Instruction = packed union {...@@ -8012,7 +8138,7 @@ pub const Instruction = packed union {
8012 imm5: u5,8138 imm5: u5,
8013 decoded21: u8 = 0b01110000,8139 decoded21: u8 = 0b01110000,
8014 op: u1 = 0b0,8140 op: u1 = 0b0,
8015 Q: Register.IntegerSize,8141 Q: Register.GeneralSize,
8016 decoded31: u1 = 0b0,8142 decoded31: u1 = 0b0,
8017 };8143 };
80188144
...@@ -8031,8 +8157,8 @@ pub const Instruction = packed union {...@@ -8031,8 +8157,8 @@ pub const Instruction = packed union {
8031 decoded31: u1 = 0b0,8157 decoded31: u1 = 0b0,
80328158
8033 pub const Imm4 = packed union {8159 pub const Imm4 = packed union {
8034 general: General,
8035 element: u4,8160 element: u4,
8161 general: General,
80368162
8037 pub const General = enum(u4) {8163 pub const General = enum(u4) {
8038 general = 0b0011,8164 general = 0b0011,
...@@ -8077,6 +8203,10 @@ pub const Instruction = packed union {...@@ -8077,6 +8203,10 @@ pub const Instruction = packed union {
8077 },8203 },
8078 else => .unallocated,8204 else => .unallocated,
8079 },8205 },
8206 0b0011 => switch (inst.group.Q) {
8207 0b0 => .unallocated,
8208 0b1 => .{ .ins = inst.ins },
8209 },
8080 },8210 },
8081 0b1 => switch (inst.group.Q) {8211 0b1 => switch (inst.group.Q) {
8082 0b0 => .unallocated,8212 0b0 => .unallocated,
...@@ -8537,6 +8667,88 @@ pub const Instruction = packed union {...@@ -8537,6 +8667,88 @@ pub const Instruction = packed union {
8537 Q: Q,8667 Q: Q,
8538 decoded31: u1 = 0b0,8668 decoded31: u1 = 0b0,
8539 };8669 };
8670
8671 pub const Decoded = union(enum) {
8672 unallocated,
8673 frintn: Frintn,
8674 frintm: Frintm,
8675 fcvtns: Fcvtns,
8676 fcvtms: Fcvtms,
8677 fcvtas: Fcvtas,
8678 scvtf: Scvtf,
8679 fcmgt: Fcmgt,
8680 fcmeq: Fcmeq,
8681 fcmlt: Fcmlt,
8682 fabs: Fabs,
8683 frintp: Frintp,
8684 frintz: Frintz,
8685 fcvtps: Fcvtps,
8686 fcvtzs: Fcvtzs,
8687 frecpe: Frecpe,
8688 frinta: Frinta,
8689 frintx: Frintx,
8690 fcvtnu: Fcvtnu,
8691 fcvtmu: Fcvtmu,
8692 fcvtau: Fcvtau,
8693 ucvtf: Ucvtf,
8694 fcmge: Fcmge,
8695 fcmle: Fcmle,
8696 fneg: Fneg,
8697 frinti: Frinti,
8698 fcvtpu: Fcvtpu,
8699 fcvtzu: Fcvtzu,
8700 frsqrte: Frsqrte,
8701 fsqrt: Fsqrt,
8702 };
8703 pub fn decode(inst: @This()) @This().Decoded {
8704 return switch (inst.group.U) {
8705 .signed => switch (inst.group.a) {
8706 0b0 => switch (inst.group.opcode) {
8707 else => .unallocated,
8708 0b11000 => .{ .frintn = inst.frintn },
8709 0b11001 => .{ .frintm = inst.frintm },
8710 0b11010 => .{ .fcvtns = inst.fcvtns },
8711 0b11011 => .{ .fcvtms = inst.fcvtms },
8712 0b11100 => .{ .fcvtas = inst.fcvtas },
8713 0b11101 => .{ .scvtf = inst.scvtf },
8714 },
8715 0b1 => switch (inst.group.opcode) {
8716 else => .unallocated,
8717 0b01100 => .{ .fcmgt = inst.fcmgt },
8718 0b01101 => .{ .fcmeq = inst.fcmeq },
8719 0b01110 => .{ .fcmlt = inst.fcmlt },
8720 0b01111 => .{ .fabs = inst.fabs },
8721 0b11000 => .{ .frintp = inst.frintp },
8722 0b11001 => .{ .frintz = inst.frintz },
8723 0b11010 => .{ .fcvtps = inst.fcvtps },
8724 0b11011 => .{ .fcvtzs = inst.fcvtzs },
8725 0b11101 => .{ .frecpe = inst.frecpe },
8726 },
8727 },
8728 .unsigned => switch (inst.group.a) {
8729 0b0 => switch (inst.group.opcode) {
8730 else => .unallocated,
8731 0b11000 => .{ .frinta = inst.frinta },
8732 0b11001 => .{ .frintx = inst.frintx },
8733 0b11010 => .{ .fcvtnu = inst.fcvtnu },
8734 0b11011 => .{ .fcvtmu = inst.fcvtmu },
8735 0b11100 => .{ .fcvtau = inst.fcvtau },
8736 0b11101 => .{ .ucvtf = inst.ucvtf },
8737 },
8738 0b1 => switch (inst.group.opcode) {
8739 else => .unallocated,
8740 0b01100 => .{ .fcmge = inst.fcmge },
8741 0b01101 => .{ .fcmle = inst.fcmle },
8742 0b01111 => .{ .fneg = inst.fneg },
8743 0b11001 => .{ .frinti = inst.frinti },
8744 0b11010 => .{ .fcvtpu = inst.fcvtpu },
8745 0b11011 => .{ .fcvtzu = inst.fcvtzu },
8746 0b11101 => .{ .frsqrte = inst.frsqrte },
8747 0b11111 => .{ .fsqrt = inst.fsqrt },
8748 },
8749 },
8750 };
8751 }
8540 };8752 };
85418753
8542 /// Advanced SIMD two-register miscellaneous8754 /// Advanced SIMD two-register miscellaneous
...@@ -8700,7 +8912,7 @@ pub const Instruction = packed union {...@@ -8700,7 +8912,7 @@ pub const Instruction = packed union {
8700 decoded31: u1 = 0b0,8912 decoded31: u1 = 0b0,
8701 };8913 };
87028914
8703 /// C7.2.308 SQXTN8915 /// C7.2.308 SQXTN, SQXTN2
8704 pub const Sqxtn = packed struct {8916 pub const Sqxtn = packed struct {
8705 Rd: Register.Encoded,8917 Rd: Register.Encoded,
8706 Rn: Register.Encoded,8918 Rn: Register.Encoded,
...@@ -9275,6 +9487,169 @@ pub const Instruction = packed union {...@@ -9275,6 +9487,169 @@ pub const Instruction = packed union {
9275 Q: Q,9487 Q: Q,
9276 decoded31: u1 = 0b0,9488 decoded31: u1 = 0b0,
9277 };9489 };
9490
9491 pub const Decoded = union(enum) {
9492 unallocated,
9493 suqadd: Suqadd,
9494 cnt: Cnt,
9495 sqabs: Sqabs,
9496 cmgt: Cmgt,
9497 cmeq: Cmeq,
9498 cmlt: Cmlt,
9499 abs: Abs,
9500 sqxtn: Sqxtn,
9501 frintn: Frintn,
9502 frintm: Frintm,
9503 fcvtns: Fcvtns,
9504 fcvtms: Fcvtms,
9505 fcvtas: Fcvtas,
9506 scvtf: Scvtf,
9507 fcmgt: Fcmgt,
9508 fcmeq: Fcmeq,
9509 fcmlt: Fcmlt,
9510 fabs: Fabs,
9511 frintp: Frintp,
9512 frintz: Frintz,
9513 fcvtps: Fcvtps,
9514 fcvtzs: Fcvtzs,
9515 frecpe: Frecpe,
9516 usqadd: Usqadd,
9517 sqneg: Sqneg,
9518 cmge: Cmge,
9519 cmle: Cmle,
9520 neg: Neg,
9521 sqxtun: Sqxtun,
9522 uqxtn: Uqxtn,
9523 fcvtxn: Fcvtxn,
9524 frinta: Frinta,
9525 frintx: Frintx,
9526 fcvtnu: Fcvtnu,
9527 fcvtmu: Fcvtmu,
9528 fcvtau: Fcvtau,
9529 ucvtf: Ucvtf,
9530 not: Not,
9531 fcmge: Fcmge,
9532 fcmle: Fcmle,
9533 fneg: Fneg,
9534 frinti: Frinti,
9535 fcvtpu: Fcvtpu,
9536 fcvtzu: Fcvtzu,
9537 frsqrte: Frsqrte,
9538 fsqrt: Fsqrt,
9539 };
9540 pub fn decode(inst: @This()) @This().Decoded {
9541 return switch (inst.group.U) {
9542 .signed => switch (inst.group.opcode) {
9543 else => .unallocated,
9544 0b00011 => .{ .suqadd = inst.suqadd },
9545 0b00101 => .{ .cnt = inst.cnt },
9546 0b00111 => .{ .sqabs = inst.sqabs },
9547 0b01000 => .{ .cmgt = inst.cmgt },
9548 0b01001 => .{ .cmeq = inst.cmeq },
9549 0b01010 => .{ .cmlt = inst.cmlt },
9550 0b01011 => .{ .abs = inst.abs },
9551 0b10100 => .{ .sqxtn = inst.sqxtn },
9552 0b11000 => switch (inst.group.size) {
9553 .byte, .half => .{ .frintn = inst.frintn },
9554 .single, .double => .{ .frintp = inst.frintp },
9555 },
9556 0b11001 => switch (inst.group.size) {
9557 .byte, .half => .{ .frintm = inst.frintm },
9558 .single, .double => .{ .frintz = inst.frintz },
9559 },
9560 0b11010 => switch (inst.group.size) {
9561 .byte, .half => .{ .fcvtns = inst.fcvtns },
9562 .single, .double => .{ .fcvtps = inst.fcvtps },
9563 },
9564 0b11011 => switch (inst.group.size) {
9565 .byte, .half => .{ .fcvtms = inst.fcvtms },
9566 .single, .double => .{ .fcvtzs = inst.fcvtzs },
9567 },
9568 0b11100 => switch (inst.group.size) {
9569 .byte, .half => .{ .fcvtas = inst.fcvtas },
9570 .single, .double => .unallocated,
9571 },
9572 0b11101 => switch (inst.group.size) {
9573 .byte, .half => .{ .scvtf = inst.scvtf },
9574 .single, .double => .{ .frecpe = inst.frecpe },
9575 },
9576 0b01100 => switch (inst.group.size) {
9577 .byte, .half => .unallocated,
9578 .single, .double => .{ .fcmgt = inst.fcmgt },
9579 },
9580 0b01101 => switch (inst.group.size) {
9581 .byte, .half => .unallocated,
9582 .single, .double => .{ .fcmeq = inst.fcmeq },
9583 },
9584 0b01110 => switch (inst.group.size) {
9585 .byte, .half => .unallocated,
9586 .single, .double => .{ .fcmlt = inst.fcmlt },
9587 },
9588 0b01111 => switch (inst.group.size) {
9589 .byte, .half => .unallocated,
9590 .single, .double => .{ .fabs = inst.fabs },
9591 },
9592 },
9593 .unsigned => switch (inst.group.opcode) {
9594 else => .unallocated,
9595 0b00011 => .{ .usqadd = inst.usqadd },
9596 0b00111 => .{ .sqneg = inst.sqneg },
9597 0b01000 => .{ .cmge = inst.cmge },
9598 0b01001 => .{ .cmle = inst.cmle },
9599 0b01011 => .{ .neg = inst.neg },
9600 0b10010 => .{ .sqxtun = inst.sqxtun },
9601 0b10100 => .{ .uqxtn = inst.uqxtn },
9602 0b10110 => switch (inst.group.size) {
9603 .byte, .half => .{ .fcvtxn = inst.fcvtxn },
9604 .single, .double => .unallocated,
9605 },
9606 0b11000 => switch (inst.group.size) {
9607 .byte, .half => .{ .frinta = inst.frinta },
9608 .single, .double => .unallocated,
9609 },
9610 0b11001 => switch (inst.group.size) {
9611 .byte, .half => .{ .frintx = inst.frintx },
9612 .single, .double => .{ .frinti = inst.frinti },
9613 },
9614 0b11010 => switch (inst.group.size) {
9615 .byte, .half => .{ .fcvtnu = inst.fcvtnu },
9616 .single, .double => .{ .fcvtpu = inst.fcvtpu },
9617 },
9618 0b11011 => switch (inst.group.size) {
9619 .byte, .half => .{ .fcvtmu = inst.fcvtmu },
9620 .single, .double => .{ .fcvtzu = inst.fcvtzu },
9621 },
9622 0b11100 => switch (inst.group.size) {
9623 .byte, .half => .{ .fcvtau = inst.fcvtau },
9624 .single, .double => .unallocated,
9625 },
9626 0b11101 => switch (inst.group.size) {
9627 .byte, .half => .{ .ucvtf = inst.ucvtf },
9628 .single, .double => .{ .frsqrte = inst.frsqrte },
9629 },
9630 0b00101 => switch (inst.group.size) {
9631 .byte => .{ .not = inst.not },
9632 .half, .single, .double => .unallocated,
9633 },
9634 0b01100 => switch (inst.group.size) {
9635 .byte, .half => .unallocated,
9636 .single, .double => .{ .fcmge = inst.fcmge },
9637 },
9638 0b01101 => switch (inst.group.size) {
9639 .byte, .half => .unallocated,
9640 .single, .double => .{ .fcmle = inst.fcmle },
9641 },
9642 0b01111 => switch (inst.group.size) {
9643 .byte, .half => .unallocated,
9644 .single, .double => .{ .fneg = inst.fneg },
9645 },
9646 0b11111 => switch (inst.group.size) {
9647 .byte, .half => .unallocated,
9648 .single, .double => .{ .fsqrt = inst.fsqrt },
9649 },
9650 },
9651 };
9652 }
9278 };9653 };
92799654
9280 /// Advanced SIMD across lanes9655 /// Advanced SIMD across lanes
...@@ -9308,6 +9683,20 @@ pub const Instruction = packed union {...@@ -9308,6 +9683,20 @@ pub const Instruction = packed union {
9308 Q: Q,9683 Q: Q,
9309 decoded31: u1 = 0b0,9684 decoded31: u1 = 0b0,
9310 };9685 };
9686
9687 pub const Decoded = union(enum) {
9688 unallocated,
9689 addv: Addv,
9690 };
9691 pub fn decode(inst: @This()) @This().Decoded {
9692 return switch (inst.group.U) {
9693 .signed => switch (inst.group.opcode) {
9694 else => .unallocated,
9695 0b11011 => .{ .addv = inst.addv },
9696 },
9697 .unsigned => .unallocated,
9698 };
9699 }
9311 };9700 };
93129701
9313 /// Advanced SIMD three same9702 /// Advanced SIMD three same
...@@ -9471,6 +9860,42 @@ pub const Instruction = packed union {...@@ -9471,6 +9860,42 @@ pub const Instruction = packed union {
9471 Q: Q,9860 Q: Q,
9472 decoded31: u1 = 0b0,9861 decoded31: u1 = 0b0,
9473 };9862 };
9863
9864 pub const Decoded = union(enum) {
9865 unallocated,
9866 addp: Addp,
9867 @"and": And,
9868 bic: Bic,
9869 orr: Orr,
9870 orn: Orn,
9871 eor: Eor,
9872 bsl: Bsl,
9873 bit: Bit,
9874 bif: Bif,
9875 };
9876 pub fn decode(inst: @This()) @This().Decoded {
9877 return switch (inst.group.U) {
9878 .signed => switch (inst.group.opcode) {
9879 else => .unallocated,
9880 0b10111 => .{ .addp = inst.addp },
9881 0b00011 => switch (inst.group.size) {
9882 .byte => .{ .@"and" = inst.@"and" },
9883 .half => .{ .bic = inst.bic },
9884 .single => .{ .orr = inst.orr },
9885 .double => .{ .orn = inst.orn },
9886 },
9887 },
9888 .unsigned => switch (inst.group.opcode) {
9889 else => .unallocated,
9890 0b00011 => switch (inst.group.size) {
9891 .byte => .{ .eor = inst.eor },
9892 .half => .{ .bsl = inst.bsl },
9893 .single => .{ .bit = inst.bit },
9894 .double => .{ .bif = inst.bif },
9895 },
9896 },
9897 };
9898 }
9474 };9899 };
94759900
9476 /// Advanced SIMD modified immediate9901 /// Advanced SIMD modified immediate
...@@ -9529,11 +9954,11 @@ pub const Instruction = packed union {...@@ -9529,11 +9954,11 @@ pub const Instruction = packed union {
9529 Rd: Register.Encoded,9954 Rd: Register.Encoded,
9530 imm5: u5,9955 imm5: u5,
9531 decoded10: u1 = 0b1,9956 decoded10: u1 = 0b1,
9532 o2: u1 = 0b1,9957 o2: u1,
9533 cmode: u4 = 0b1111,9958 cmode: u4 = 0b1111,
9534 imm3: u3,9959 imm3: u3,
9535 decoded19: u10 = 0b0111100000,9960 decoded19: u10 = 0b0111100000,
9536 op: u1 = 0b0,9961 op: u1,
9537 Q: Q,9962 Q: Q,
9538 decoded31: u1 = 0b0,9963 decoded31: u1 = 0b0,
9539 };9964 };
...@@ -9566,6 +9991,45 @@ pub const Instruction = packed union {...@@ -9566,6 +9991,45 @@ pub const Instruction = packed union {
9566 Q: Q,9991 Q: Q,
9567 decoded31: u1 = 0b0,9992 decoded31: u1 = 0b0,
9568 };9993 };
9994
9995 pub const Decoded = union(enum) {
9996 unallocated,
9997 fmov: Fmov,
9998 };
9999 pub fn decode(inst: @This()) @This().Decoded {
10000 return switch (inst.group.cmode) {
10001 else => .unallocated,
10002 0b1111 => switch (inst.group.op) {
10003 0b0 => .{ .fmov = inst.fmov },
10004 0b1 => switch (inst.group.Q) {
10005 .double => .unallocated,
10006 .quad => switch (inst.group.o2) {
10007 0b1 => .unallocated,
10008 0b0 => .{ .fmov = inst.fmov },
10009 },
10010 },
10011 },
10012 };
10013 }
10014 };
10015
10016 /// Conversion between floating-point and fixed-point
10017 pub const ConvertFloatFixed = packed union {
10018 group: @This().Group,
10019
10020 pub const Group = packed struct {
10021 Rd: Register.Encoded,
10022 Rn: Register.Encoded,
10023 scale: u6,
10024 opcode: u3,
10025 rmode: u2,
10026 decoded21: u1 = 0b0,
10027 ptype: Ftype,
10028 decoded24: u5 = 0b11110,
10029 S: bool,
10030 decoded30: u1 = 0b0,
10031 sf: Register.GeneralSize,
10032 };
9569 };10033 };
957010034
9571 /// Conversion between floating-point and integer10035 /// Conversion between floating-point and integer
...@@ -9597,7 +10061,7 @@ pub const Instruction = packed union {...@@ -9597,7 +10061,7 @@ pub const Instruction = packed union {
9597 decoded24: u5 = 0b11110,10061 decoded24: u5 = 0b11110,
9598 S: bool,10062 S: bool,
9599 decoded30: u1 = 0b0,10063 decoded30: u1 = 0b0,
9600 sf: Register.IntegerSize,10064 sf: Register.GeneralSize,
9601 };10065 };
960210066
9603 /// C7.2.81 FCVTNS (scalar)10067 /// C7.2.81 FCVTNS (scalar)
...@@ -9612,7 +10076,7 @@ pub const Instruction = packed union {...@@ -9612,7 +10076,7 @@ pub const Instruction = packed union {
9612 decoded24: u5 = 0b11110,10076 decoded24: u5 = 0b11110,
9613 S: bool = false,10077 S: bool = false,
9614 decoded30: u1 = 0b0,10078 decoded30: u1 = 0b0,
9615 sf: Register.IntegerSize,10079 sf: Register.GeneralSize,
9616 };10080 };
961710081
9618 /// C7.2.83 FCVTNU (scalar)10082 /// C7.2.83 FCVTNU (scalar)
...@@ -9627,7 +10091,7 @@ pub const Instruction = packed union {...@@ -9627,7 +10091,7 @@ pub const Instruction = packed union {
9627 decoded24: u5 = 0b11110,10091 decoded24: u5 = 0b11110,
9628 S: bool = false,10092 S: bool = false,
9629 decoded30: u1 = 0b0,10093 decoded30: u1 = 0b0,
9630 sf: Register.IntegerSize,10094 sf: Register.GeneralSize,
9631 };10095 };
963210096
9633 /// C7.2.236 SCVTF (scalar, integer)10097 /// C7.2.236 SCVTF (scalar, integer)
...@@ -9642,7 +10106,7 @@ pub const Instruction = packed union {...@@ -9642,7 +10106,7 @@ pub const Instruction = packed union {
9642 decoded24: u5 = 0b11110,10106 decoded24: u5 = 0b11110,
9643 S: bool = false,10107 S: bool = false,
9644 decoded30: u1 = 0b0,10108 decoded30: u1 = 0b0,
9645 sf: Register.IntegerSize,10109 sf: Register.GeneralSize,
9646 };10110 };
964710111
9648 /// C7.2.355 UCVTF (scalar, integer)10112 /// C7.2.355 UCVTF (scalar, integer)
...@@ -9657,7 +10121,7 @@ pub const Instruction = packed union {...@@ -9657,7 +10121,7 @@ pub const Instruction = packed union {
9657 decoded24: u5 = 0b11110,10121 decoded24: u5 = 0b11110,
9658 S: bool = false,10122 S: bool = false,
9659 decoded30: u1 = 0b0,10123 decoded30: u1 = 0b0,
9660 sf: Register.IntegerSize,10124 sf: Register.GeneralSize,
9661 };10125 };
966210126
9663 /// C7.2.71 FCVTAS (scalar)10127 /// C7.2.71 FCVTAS (scalar)
...@@ -9672,7 +10136,7 @@ pub const Instruction = packed union {...@@ -9672,7 +10136,7 @@ pub const Instruction = packed union {
9672 decoded24: u5 = 0b11110,10136 decoded24: u5 = 0b11110,
9673 S: bool = false,10137 S: bool = false,
9674 decoded30: u1 = 0b0,10138 decoded30: u1 = 0b0,
9675 sf: Register.IntegerSize,10139 sf: Register.GeneralSize,
9676 };10140 };
967710141
9678 /// C7.2.73 FCVTAU (scalar)10142 /// C7.2.73 FCVTAU (scalar)
...@@ -9687,7 +10151,7 @@ pub const Instruction = packed union {...@@ -9687,7 +10151,7 @@ pub const Instruction = packed union {
9687 decoded24: u5 = 0b11110,10151 decoded24: u5 = 0b11110,
9688 S: bool = false,10152 S: bool = false,
9689 decoded30: u1 = 0b0,10153 decoded30: u1 = 0b0,
9690 sf: Register.IntegerSize,10154 sf: Register.GeneralSize,
9691 };10155 };
969210156
9693 /// C7.2.131 FMOV (general)10157 /// C7.2.131 FMOV (general)
...@@ -9702,7 +10166,7 @@ pub const Instruction = packed union {...@@ -9702,7 +10166,7 @@ pub const Instruction = packed union {
9702 decoded24: u5 = 0b11110,10166 decoded24: u5 = 0b11110,
9703 S: bool = false,10167 S: bool = false,
9704 decoded30: u1 = 0b0,10168 decoded30: u1 = 0b0,
9705 sf: Register.IntegerSize,10169 sf: Register.GeneralSize,
970610170
9707 pub const Opcode = enum(u3) {10171 pub const Opcode = enum(u3) {
9708 float_to_integer = 0b110,10172 float_to_integer = 0b110,
...@@ -9729,7 +10193,7 @@ pub const Instruction = packed union {...@@ -9729,7 +10193,7 @@ pub const Instruction = packed union {
9729 decoded24: u5 = 0b11110,10193 decoded24: u5 = 0b11110,
9730 S: bool = false,10194 S: bool = false,
9731 decoded30: u1 = 0b0,10195 decoded30: u1 = 0b0,
9732 sf: Register.IntegerSize,10196 sf: Register.GeneralSize,
9733 };10197 };
973410198
9735 /// C7.2.87 FCVTPU (scalar)10199 /// C7.2.87 FCVTPU (scalar)
...@@ -9744,7 +10208,7 @@ pub const Instruction = packed union {...@@ -9744,7 +10208,7 @@ pub const Instruction = packed union {
9744 decoded24: u5 = 0b11110,10208 decoded24: u5 = 0b11110,
9745 S: bool = false,10209 S: bool = false,
9746 decoded30: u1 = 0b0,10210 decoded30: u1 = 0b0,
9747 sf: Register.IntegerSize,10211 sf: Register.GeneralSize,
9748 };10212 };
974910213
9750 /// C7.2.76 FCVTMS (scalar)10214 /// C7.2.76 FCVTMS (scalar)
...@@ -9759,7 +10223,7 @@ pub const Instruction = packed union {...@@ -9759,7 +10223,7 @@ pub const Instruction = packed union {
9759 decoded24: u5 = 0b11110,10223 decoded24: u5 = 0b11110,
9760 S: bool = false,10224 S: bool = false,
9761 decoded30: u1 = 0b0,10225 decoded30: u1 = 0b0,
9762 sf: Register.IntegerSize,10226 sf: Register.GeneralSize,
9763 };10227 };
976410228
9765 /// C7.2.78 FCVTMU (scalar)10229 /// C7.2.78 FCVTMU (scalar)
...@@ -9774,7 +10238,7 @@ pub const Instruction = packed union {...@@ -9774,7 +10238,7 @@ pub const Instruction = packed union {
9774 decoded24: u5 = 0b11110,10238 decoded24: u5 = 0b11110,
9775 S: bool = false,10239 S: bool = false,
9776 decoded30: u1 = 0b0,10240 decoded30: u1 = 0b0,
9777 sf: Register.IntegerSize,10241 sf: Register.GeneralSize,
9778 };10242 };
977910243
9780 /// C7.2.92 FCVTZS (scalar, integer)10244 /// C7.2.92 FCVTZS (scalar, integer)
...@@ -9789,7 +10253,7 @@ pub const Instruction = packed union {...@@ -9789,7 +10253,7 @@ pub const Instruction = packed union {
9789 decoded24: u5 = 0b11110,10253 decoded24: u5 = 0b11110,
9790 S: bool = false,10254 S: bool = false,
9791 decoded30: u1 = 0b0,10255 decoded30: u1 = 0b0,
9792 sf: Register.IntegerSize,10256 sf: Register.GeneralSize,
9793 };10257 };
979410258
9795 /// C7.2.96 FCVTZU (scalar, integer)10259 /// C7.2.96 FCVTZU (scalar, integer)
...@@ -9804,7 +10268,7 @@ pub const Instruction = packed union {...@@ -9804,7 +10268,7 @@ pub const Instruction = packed union {
9804 decoded24: u5 = 0b11110,10268 decoded24: u5 = 0b11110,
9805 S: bool = false,10269 S: bool = false,
9806 decoded30: u1 = 0b0,10270 decoded30: u1 = 0b0,
9807 sf: Register.IntegerSize,10271 sf: Register.GeneralSize,
9808 };10272 };
980910273
9810 /// C7.2.99 FJCVTZS10274 /// C7.2.99 FJCVTZS
...@@ -9819,7 +10283,7 @@ pub const Instruction = packed union {...@@ -9819,7 +10283,7 @@ pub const Instruction = packed union {
9819 decoded24: u5 = 0b11110,10283 decoded24: u5 = 0b11110,
9820 S: bool = false,10284 S: bool = false,
9821 decoded30: u1 = 0b0,10285 decoded30: u1 = 0b0,
9822 sf: Register.IntegerSize = .word,10286 sf: Register.GeneralSize = .word,
9823 };10287 };
982410288
9825 pub const Rmode = enum(u2) {10289 pub const Rmode = enum(u2) {
...@@ -9832,6 +10296,84 @@ pub const Instruction = packed union {...@@ -9832,6 +10296,84 @@ pub const Instruction = packed union {
9832 /// toward zero10296 /// toward zero
9833 z = 0b11,10297 z = 0b11,
9834 };10298 };
10299
10300 pub const Decoded = union(enum) {
10301 unallocated,
10302 fcvtns: Fcvtns,
10303 fcvtnu: Fcvtnu,
10304 scvtf: Scvtf,
10305 ucvtf: Ucvtf,
10306 fcvtas: Fcvtas,
10307 fcvtau: Fcvtau,
10308 fmov: Fmov,
10309 fcvtps: Fcvtps,
10310 fcvtpu: Fcvtpu,
10311 fcvtms: Fcvtms,
10312 fcvtmu: Fcvtmu,
10313 fcvtzs: Fcvtzs,
10314 fcvtzu: Fcvtzu,
10315 fjcvtzs: Fjcvtzs,
10316 };
10317 pub fn decode(inst: @This()) @This().Decoded {
10318 return switch (inst.group.S) {
10319 true => .unallocated,
10320 false => switch (inst.group.ptype) {
10321 .single, .double, .half => switch (inst.group.opcode) {
10322 0b000 => switch (inst.group.rmode) {
10323 0b00 => .{ .fcvtns = inst.fcvtns },
10324 0b01 => .{ .fcvtps = inst.fcvtps },
10325 0b10 => .{ .fcvtms = inst.fcvtms },
10326 0b11 => .{ .fcvtzs = inst.fcvtzs },
10327 },
10328 0b001 => switch (inst.group.rmode) {
10329 0b00 => .{ .fcvtnu = inst.fcvtnu },
10330 0b01 => .{ .fcvtpu = inst.fcvtpu },
10331 0b10 => .{ .fcvtmu = inst.fcvtmu },
10332 0b11 => .{ .fcvtzu = inst.fcvtzu },
10333 },
10334 0b010 => switch (inst.group.rmode) {
10335 else => .unallocated,
10336 0b00 => .{ .scvtf = inst.scvtf },
10337 },
10338 0b011 => switch (inst.group.rmode) {
10339 else => .unallocated,
10340 0b00 => .{ .ucvtf = inst.ucvtf },
10341 },
10342 0b100 => switch (inst.group.rmode) {
10343 else => .unallocated,
10344 0b00 => .{ .fcvtas = inst.fcvtas },
10345 },
10346 0b101 => switch (inst.group.rmode) {
10347 else => .unallocated,
10348 0b00 => .{ .fcvtau = inst.fcvtau },
10349 },
10350 0b110 => switch (inst.group.rmode) {
10351 else => .unallocated,
10352 0b00 => .{ .fmov = inst.fmov },
10353 0b11 => switch (inst.group.ptype) {
10354 .single, .double => .unallocated,
10355 .quad => unreachable,
10356 .half => .{ .fjcvtzs = inst.fjcvtzs },
10357 },
10358 },
10359 0b111 => switch (inst.group.rmode) {
10360 else => .unallocated,
10361 0b00 => .{ .fmov = inst.fmov },
10362 },
10363 },
10364 .quad => switch (inst.group.opcode) {
10365 else => .unallocated,
10366 0b110, 0b111 => switch (inst.group.rmode) {
10367 else => .unallocated,
10368 0b01 => switch (inst.group.sf) {
10369 .word => .unallocated,
10370 .doubleword => .{ .fmov = inst.fmov },
10371 },
10372 },
10373 },
10374 },
10375 };
10376 }
9835 };10377 };
983610378
9837 /// Floating-point data-processing (1 source)10379 /// Floating-point data-processing (1 source)
...@@ -10060,6 +10602,48 @@ pub const Instruction = packed union {...@@ -10060,6 +10602,48 @@ pub const Instruction = packed union {
10060 i = 0b111,10602 i = 0b111,
10061 _,10603 _,
10062 };10604 };
10605
10606 pub const Decoded = union(enum) {
10607 unallocated,
10608 fmov: Fmov,
10609 fabs: Fabs,
10610 fneg: Fneg,
10611 fsqrt: Fsqrt,
10612 fcvt: Fcvt,
10613 frintn: Frintn,
10614 frintp: Frintp,
10615 frintm: Frintm,
10616 frintz: Frintz,
10617 frinta: Frinta,
10618 frintx: Frintx,
10619 frinti: Frinti,
10620 };
10621 pub fn decode(inst: @This()) @This().Decoded {
10622 return switch (inst.group.M) {
10623 0b0 => switch (inst.group.S) {
10624 true => .unallocated,
10625 false => switch (inst.group.ptype) {
10626 .single, .double, .half => switch (inst.group.opcode) {
10627 else => .unallocated,
10628 0b000000 => .{ .fmov = inst.fmov },
10629 0b000001 => .{ .fabs = inst.fabs },
10630 0b000010 => .{ .fneg = inst.fneg },
10631 0b000011 => .{ .fsqrt = inst.fsqrt },
10632 0b000101, 0b000111 => .{ .fcvt = inst.fcvt },
10633 0b001000 => .{ .frintn = inst.frintn },
10634 0b001001 => .{ .frintp = inst.frintp },
10635 0b001010 => .{ .frintm = inst.frintm },
10636 0b001011 => .{ .frintz = inst.frintz },
10637 0b001100 => .{ .frinta = inst.frinta },
10638 0b001110 => .{ .frintx = inst.frintx },
10639 0b001111 => .{ .frinti = inst.frinti },
10640 },
10641 .quad => .unallocated,
10642 },
10643 },
10644 0b1 => .unallocated,
10645 };
10646 }
10063 };10647 };
1006410648
10065 /// Floating-point compare10649 /// Floating-point compare
...@@ -10145,13 +10729,77 @@ pub const Instruction = packed union {...@@ -10145,13 +10729,77 @@ pub const Instruction = packed union {
10145 Rd: Register.Encoded,10729 Rd: Register.Encoded,
10146 imm5: u5 = 0b00000,10730 imm5: u5 = 0b00000,
10147 decoded10: u3 = 0b100,10731 decoded10: u3 = 0b100,
10148 imm8: u8,10732 imm8: Imm8,
10149 decoded21: u1 = 0b1,10733 decoded21: u1 = 0b1,
10150 ftype: Ftype,10734 ftype: Ftype,
10151 decoded24: u5 = 0b11110,10735 decoded24: u5 = 0b11110,
10152 S: bool = false,10736 S: bool = false,
10153 decoded30: u1 = 0b0,10737 decoded30: u1 = 0b0,
10154 M: u1 = 0b0,10738 M: u1 = 0b0,
10739
10740 pub const Imm8 = packed struct(u8) {
10741 mantissa: u4,
10742 exponent: i3,
10743 sign: std.math.Sign,
10744
10745 pub const Modified = packed struct(u8) { imm5: u5, imm3: u3 };
10746
10747 pub fn fromModified(mod: Modified) Imm8 {
10748 return @bitCast(mod);
10749 }
10750
10751 pub fn toModified(imm8: Imm8) Modified {
10752 return @bitCast(imm8);
10753 }
10754
10755 pub fn decode(imm8: Imm8) f16 {
10756 const Normalized = std.math.FloatRepr(f16).Normalized;
10757 return Normalized.reconstruct(.{
10758 .fraction = @as(Normalized.Fraction, imm8.mantissa) << 6,
10759 .exponent = @as(Normalized.Exponent, imm8.exponent) + 1,
10760 }, imm8.sign);
10761 }
10762 };
10763 };
10764
10765 pub const Decoded = union(enum) {
10766 unallocated,
10767 fmov: Fmov,
10768 };
10769 pub fn decode(inst: @This()) @This().Decoded {
10770 return switch (inst.group.M) {
10771 0b0 => switch (inst.group.S) {
10772 true => .unallocated,
10773 false => switch (inst.group.imm5) {
10774 else => .unallocated,
10775 0b00000 => switch (inst.group.ptype) {
10776 .quad => .unallocated,
10777 .single, .double, .half => .{ .fmov = inst.fmov },
10778 },
10779 },
10780 },
10781 0b1 => .unallocated,
10782 };
10783 }
10784 };
10785
10786 /// Floating-point conditional compare
10787 pub const FloatConditionalCompare = packed union {
10788 group: @This().Group,
10789
10790 pub const Group = packed struct {
10791 nzcv: Nzcv,
10792 op: u1,
10793 Rn: Register.Encoded,
10794 decoded10: u2 = 0b01,
10795 cond: ConditionCode,
10796 Rm: Register.Encoded,
10797 decoded21: u1 = 0b1,
10798 ptype: Ftype,
10799 decoded24: u5 = 0b11110,
10800 S: bool,
10801 decoded30: u1 = 0b0,
10802 M: u1,
10155 };10803 };
10156 };10804 };
1015710805
...@@ -10477,7 +11125,15 @@ pub const Instruction = packed union {...@@ -10477,7 +11125,15 @@ pub const Instruction = packed union {
10477 single = 0b10,11125 single = 0b10,
10478 double = 0b11,11126 double = 0b11,
1047911127
10480 pub fn toVectorSize(s: Size) Register.VectorSize {11128 pub fn n(s: Size) Size {
11129 return @enumFromInt(@intFromEnum(s) - 1);
11130 }
11131
11132 pub fn w(s: Size) Size {
11133 return @enumFromInt(@intFromEnum(s) + 1);
11134 }
11135
11136 pub fn toScalarSize(s: Size) Register.ScalarSize {
10481 return switch (s) {11137 return switch (s) {
10482 .byte => .byte,11138 .byte => .byte,
10483 .half => .half,11139 .half => .half,
...@@ -10486,8 +11142,8 @@ pub const Instruction = packed union {...@@ -10486,8 +11142,8 @@ pub const Instruction = packed union {
10486 };11142 };
10487 }11143 }
1048811144
10489 pub fn fromVectorSize(vs: Register.VectorSize) Size {11145 pub fn fromScalarSize(ss: Register.ScalarSize) Size {
10490 return switch (vs) {11146 return switch (ss) {
10491 else => unreachable,11147 else => unreachable,
10492 .byte => .byte,11148 .byte => .byte,
10493 .half => .half,11149 .half => .half,
...@@ -10495,26 +11151,41 @@ pub const Instruction = packed union {...@@ -10495,26 +11151,41 @@ pub const Instruction = packed union {
10495 .double => .double,11151 .double => .double,
10496 };11152 };
10497 }11153 }
11154
11155 pub fn toSz(s: Size) Sz {
11156 return switch (s) {
11157 else => unreachable,
11158 .single => .single,
11159 .double => .double,
11160 };
11161 }
10498 };11162 };
1049911163
10500 pub const Sz = enum(u1) {11164 pub const Sz = enum(u1) {
10501 single = 0b0,11165 single = 0b0,
10502 double = 0b1,11166 double = 0b1,
1050311167
10504 pub fn toVectorSize(sz: Sz) Register.VectorSize {11168 pub fn toScalarSize(sz: Sz) Register.ScalarSize {
10505 return switch (sz) {11169 return switch (sz) {
10506 .single => .single,11170 .single => .single,
10507 .double => .double,11171 .double => .double,
10508 };11172 };
10509 }11173 }
1051011174
10511 pub fn fromVectorSize(vs: Register.VectorSize) Sz {11175 pub fn fromScalarSize(ss: Register.ScalarSize) Sz {
10512 return switch (vs) {11176 return switch (ss) {
10513 else => unreachable,11177 else => unreachable,
10514 .single => .single,11178 .single => .single,
10515 .double => .double,11179 .double => .double,
10516 };11180 };
10517 }11181 }
11182
11183 pub fn toSize(sz: Sz) Size {
11184 return switch (sz) {
11185 .single => .single,
11186 .double => .double,
11187 };
11188 }
10518 };11189 };
1051911190
10520 pub const Q = enum(u1) {11191 pub const Q = enum(u1) {
...@@ -10528,24 +11199,104 @@ pub const Instruction = packed union {...@@ -10528,24 +11199,104 @@ pub const Instruction = packed union {
10528 quad = 0b10,11199 quad = 0b10,
10529 half = 0b11,11200 half = 0b11,
1053011201
10531 pub fn toVectorSize(ftype: Ftype) Register.VectorSize {11202 pub fn toScalarSize(ftype: Ftype) Register.ScalarSize {
10532 return switch (ftype) {11203 return switch (ftype) {
10533 _ => unreachable,
10534 .single => .single,11204 .single => .single,
10535 .double => .double,11205 .double => .double,
11206 .quad => .quad,
10536 .half => .half,11207 .half => .half,
10537 };11208 };
10538 }11209 }
1053911210
10540 pub fn fromVectorSize(vs: Register.VectorSize) Ftype {11211 pub fn fromScalarSize(ss: Register.ScalarSize) Ftype {
10541 return switch (vs) {11212 return switch (ss) {
10542 else => unreachable,11213 else => unreachable,
10543 .single => .single,11214 .single => .single,
10544 .double => .double,11215 .double => .double,
11216 .quad => .quad,
10545 .half => .half,11217 .half => .half,
10546 };11218 };
10547 }11219 }
10548 };11220 };
11221
11222 pub const Decoded = union(enum) {
11223 unallocated,
11224 simd_scalar_copy: SimdScalarCopy,
11225 simd_scalar_two_register_miscellaneous_fp16: SimdScalarTwoRegisterMiscellaneousFp16,
11226 simd_scalar_two_register_miscellaneous: SimdScalarTwoRegisterMiscellaneous,
11227 simd_scalar_pairwise: SimdScalarPairwise,
11228 simd_copy: SimdCopy,
11229 simd_two_register_miscellaneous_fp16: SimdTwoRegisterMiscellaneousFp16,
11230 simd_two_register_miscellaneous: SimdTwoRegisterMiscellaneous,
11231 simd_across_lanes: SimdAcrossLanes,
11232 simd_three_same: SimdThreeSame,
11233 simd_modified_immediate: SimdModifiedImmediate,
11234 convert_float_fixed: ConvertFloatFixed,
11235 convert_float_integer: ConvertFloatInteger,
11236 float_data_processing_one_source: FloatDataProcessingOneSource,
11237 float_compare: FloatCompare,
11238 float_immediate: FloatImmediate,
11239 float_conditional_compare: FloatConditionalCompare,
11240 float_data_processing_two_source: FloatDataProcessingTwoSource,
11241 float_conditional_select: FloatConditionalSelect,
11242 float_data_processing_three_source: FloatDataProcessingThreeSource,
11243 };
11244 pub fn decode(inst: @This()) @This().Decoded {
11245 return switch (inst.group.op0) {
11246 else => .unallocated,
11247 0b0101, 0b0111 => switch (inst.group.op1) {
11248 0b00...0b01 => if (inst.group.op3 & 0b000100001 == 0b000000001)
11249 if (inst.group.op1 == 0b00 and inst.group.op2 & 0b1100 == 0b0000)
11250 .{ .simd_scalar_copy = inst.simd_scalar_copy }
11251 else
11252 .unallocated
11253 else if (inst.group.op3 & 0b110000011 == 0b000000010) switch (inst.group.op2) {
11254 else => .unallocated,
11255 0b1111 => .{ .simd_scalar_two_register_miscellaneous_fp16 = inst.simd_scalar_two_register_miscellaneous_fp16 },
11256 0b0100, 0b1100 => .{ .simd_scalar_two_register_miscellaneous = inst.simd_scalar_two_register_miscellaneous },
11257 0b0110, 0b1110 => .{ .simd_scalar_pairwise = inst.simd_scalar_pairwise },
11258 } else .unallocated,
11259 0b10, 0b11 => switch (@as(u1, @truncate(inst.group.op3 >> 0))) {
11260 0b1 => switch (inst.group.op1) {
11261 0b10 => .unallocated,
11262 else => .unallocated,
11263 },
11264 0b0 => .unallocated,
11265 },
11266 },
11267 0b0000, 0b0010, 0b0100, 0b0110 => if (inst.group.op1 == 0b00 and inst.group.op2 & 0b1100 == 0b0000 and inst.group.op3 & 0b000100001 == 0b0000000001)
11268 .{ .simd_copy = inst.simd_copy }
11269 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 == 0b1111 and inst.group.op3 & 0b110000011 == 0b000000010)
11270 .{ .simd_two_register_miscellaneous_fp16 = inst.simd_two_register_miscellaneous_fp16 }
11271 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0111 == 0b0100 and inst.group.op3 & 0b110000011 == 0b000000010)
11272 .{ .simd_two_register_miscellaneous = inst.simd_two_register_miscellaneous }
11273 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0111 == 0b0110 and inst.group.op3 & 0b110000011 == 0b000000010)
11274 .{ .simd_across_lanes = inst.simd_across_lanes }
11275 else if (inst.group.op1 & 0b10 == 0b00 and inst.group.op2 & 0b0100 == 0b0100 and inst.group.op3 & 0b000000001 == 0b000000001)
11276 .{ .simd_three_same = inst.simd_three_same }
11277 else if (inst.group.op1 == 0b10 and inst.group.op2 == 0b0000 and inst.group.op3 & 0b000000001 == 0b000000001)
11278 .{ .simd_modified_immediate = inst.simd_modified_immediate }
11279 else
11280 .unallocated,
11281 0b0001, 0b0011, 0b1001, 0b1011 => switch (@as(u1, @truncate(inst.group.op1 >> 1))) {
11282 0b0 => switch (@as(u1, @truncate(inst.group.op2 >> 2))) {
11283 0b0 => .{ .convert_float_fixed = inst.convert_float_fixed },
11284 0b1 => switch (@ctz(inst.group.op3)) {
11285 else => .{ .convert_float_integer = inst.convert_float_integer },
11286 4 => .{ .float_data_processing_one_source = inst.float_data_processing_one_source },
11287 3 => .{ .float_compare = inst.float_compare },
11288 2 => .{ .float_immediate = inst.float_immediate },
11289 1 => .{ .float_data_processing_two_source = inst.float_data_processing_two_source },
11290 0 => switch (@as(u1, @truncate(inst.group.op3 >> 1))) {
11291 0b0 => .unallocated,
11292 0b1 => .{ .float_conditional_select = inst.float_conditional_select },
11293 },
11294 },
11295 },
11296 0b1 => .unallocated,
11297 },
11298 };
11299 }
10549 };11300 };
1055011301
10551 pub const AddSubtractOp = enum(u1) {11302 pub const AddSubtractOp = enum(u1) {
...@@ -10560,6 +11311,8 @@ pub const Instruction = packed union {...@@ -10560,6 +11311,8 @@ pub const Instruction = packed union {
10560 ands = 0b11,11311 ands = 0b11,
10561 };11312 };
1056211313
11314 pub const Nzcv = packed struct { v: bool, c: bool, z: bool, n: bool };
11315
10563 pub const Decoded = union(enum) {11316 pub const Decoded = union(enum) {
10564 unallocated,11317 unallocated,
10565 reserved: Reserved,11318 reserved: Reserved,
...@@ -10588,7 +11341,7 @@ pub const Instruction = packed union {...@@ -10588,7 +11341,7 @@ pub const Instruction = packed union {
10588 };11341 };
10589 }11342 }
1059011343
10591 /// C7.2.1 ABS (zero)11344 /// C7.2.1 ABS
10592 pub fn abs(d: Register, n: Register) Instruction {11345 pub fn abs(d: Register, n: Register) Instruction {
10593 switch (d.format) {11346 switch (d.format) {
10594 else => unreachable,11347 else => unreachable,
...@@ -10598,7 +11351,7 @@ pub const Instruction = packed union {...@@ -10598,7 +11351,7 @@ pub const Instruction = packed union {
10598 .abs = .{11351 .abs = .{
10599 .Rd = d.alias.encode(.{ .V = true }),11352 .Rd = d.alias.encode(.{ .V = true }),
10600 .Rn = n.alias.encode(.{ .V = true }),11353 .Rn = n.alias.encode(.{ .V = true }),
10601 .size = .fromVectorSize(elem_size),11354 .size = .fromScalarSize(elem_size),
10602 },11355 },
10603 } } };11356 } } };
10604 },11357 },
...@@ -10617,8 +11370,8 @@ pub const Instruction = packed union {...@@ -10617,8 +11370,8 @@ pub const Instruction = packed union {
10617 }11370 }
10618 /// C6.2.1 ADC11371 /// C6.2.1 ADC
10619 pub fn adc(d: Register, n: Register, m: Register) Instruction {11372 pub fn adc(d: Register, n: Register, m: Register) Instruction {
10620 const sf = d.format.integer;11373 const sf = d.format.general;
10621 assert(n.format.integer == sf and m.format.integer == sf);11374 assert(n.format.general == sf and m.format.general == sf);
10622 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{11375 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
10623 .adc = .{11376 .adc = .{
10624 .Rd = d.alias.encode(.{}),11377 .Rd = d.alias.encode(.{}),
...@@ -10630,8 +11383,8 @@ pub const Instruction = packed union {...@@ -10630,8 +11383,8 @@ pub const Instruction = packed union {
10630 }11383 }
10631 /// C6.2.2 ADCS11384 /// C6.2.2 ADCS
10632 pub fn adcs(d: Register, n: Register, m: Register) Instruction {11385 pub fn adcs(d: Register, n: Register, m: Register) Instruction {
10633 const sf = d.format.integer;11386 const sf = d.format.general;
10634 assert(n.format.integer == sf and m.format.integer == sf);11387 assert(n.format.general == sf and m.format.general == sf);
10635 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{11388 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
10636 .adcs = .{11389 .adcs = .{
10637 .Rd = d.alias.encode(.{}),11390 .Rd = d.alias.encode(.{}),
...@@ -10657,11 +11410,11 @@ pub const Instruction = packed union {...@@ -10657,11 +11410,11 @@ pub const Instruction = packed union {
10657 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },11410 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
10658 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },11411 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
10659 }) Instruction {11412 }) Instruction {
10660 const sf = d.format.integer;11413 const sf = d.format.general;
10661 assert(n.format.integer == sf);11414 assert(n.format.general == sf);
10662 form: switch (form) {11415 form: switch (form) {
10663 .extended_register_explicit => |extended_register_explicit| {11416 .extended_register_explicit => |extended_register_explicit| {
10664 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());11417 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
10665 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{11418 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
10666 .add = .{11419 .add = .{
10667 .Rd = d.alias.encode(.{ .sp = true }),11420 .Rd = d.alias.encode(.{ .sp = true }),
...@@ -10703,7 +11456,7 @@ pub const Instruction = packed union {...@@ -10703,7 +11456,7 @@ pub const Instruction = packed union {
10703 else11456 else
10704 .{ .shifted_register = .{ .register = register } },11457 .{ .shifted_register = .{ .register = register } },
10705 .shifted_register_explicit => |shifted_register_explicit| {11458 .shifted_register_explicit => |shifted_register_explicit| {
10706 assert(shifted_register_explicit.register.format.integer == sf);11459 assert(shifted_register_explicit.register.format.general == sf);
10707 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{11460 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
10708 .add = .{11461 .add = .{
10709 .Rd = d.alias.encode(.{}),11462 .Rd = d.alias.encode(.{}),
...@@ -10779,11 +11532,11 @@ pub const Instruction = packed union {...@@ -10779,11 +11532,11 @@ pub const Instruction = packed union {
10779 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },11532 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
10780 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },11533 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
10781 }) Instruction {11534 }) Instruction {
10782 const sf = d.format.integer;11535 const sf = d.format.general;
10783 assert(n.format.integer == sf);11536 assert(n.format.general == sf);
10784 form: switch (form) {11537 form: switch (form) {
10785 .extended_register_explicit => |extended_register_explicit| {11538 .extended_register_explicit => |extended_register_explicit| {
10786 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());11539 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
10787 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{11540 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
10788 .adds = .{11541 .adds = .{
10789 .Rd = d.alias.encode(.{}),11542 .Rd = d.alias.encode(.{}),
...@@ -10825,7 +11578,7 @@ pub const Instruction = packed union {...@@ -10825,7 +11578,7 @@ pub const Instruction = packed union {
10825 else11578 else
10826 .{ .shifted_register = .{ .register = register } },11579 .{ .shifted_register = .{ .register = register } },
10827 .shifted_register_explicit => |shifted_register_explicit| {11580 .shifted_register_explicit => |shifted_register_explicit| {
10828 assert(shifted_register_explicit.register.format.integer == sf);11581 assert(shifted_register_explicit.register.format.general == sf);
10829 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{11582 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
10830 .adds = .{11583 .adds = .{
10831 .Rd = d.alias.encode(.{}),11584 .Rd = d.alias.encode(.{}),
...@@ -10856,7 +11609,7 @@ pub const Instruction = packed union {...@@ -10856,7 +11609,7 @@ pub const Instruction = packed union {
10856 /// C7.2.6 ADDV11609 /// C7.2.6 ADDV
10857 pub fn addv(d: Register, n: Register) Instruction {11610 pub fn addv(d: Register, n: Register) Instruction {
10858 const arrangement = n.format.vector;11611 const arrangement = n.format.vector;
10859 assert(arrangement.len() > 2 and d.format.scalar == arrangement.elemSize().toVectorSize());11612 assert(arrangement.len() > 2 and d.format.scalar == arrangement.elemSize().toScalarSize());
10860 return .{ .data_processing_vector = .{ .simd_across_lanes = .{11613 return .{ .data_processing_vector = .{ .simd_across_lanes = .{
10861 .addv = .{11614 .addv = .{
10862 .Rd = d.alias.encode(.{ .V = true }),11615 .Rd = d.alias.encode(.{ .V = true }),
...@@ -10868,7 +11621,7 @@ pub const Instruction = packed union {...@@ -10868,7 +11621,7 @@ pub const Instruction = packed union {
10868 }11621 }
10869 /// C6.2.10 ADR11622 /// C6.2.10 ADR
10870 pub fn adr(d: Register, label: i21) Instruction {11623 pub fn adr(d: Register, label: i21) Instruction {
10871 assert(d.format.integer == .doubleword);11624 assert(d.format.general == .doubleword);
10872 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{11625 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{
10873 .adr = .{11626 .adr = .{
10874 .Rd = d.alias.encode(.{}),11627 .Rd = d.alias.encode(.{}),
...@@ -10879,7 +11632,7 @@ pub const Instruction = packed union {...@@ -10879,7 +11632,7 @@ pub const Instruction = packed union {
10879 }11632 }
10880 /// C6.2.11 ADRP11633 /// C6.2.11 ADRP
10881 pub fn adrp(d: Register, label: i33) Instruction {11634 pub fn adrp(d: Register, label: i33) Instruction {
10882 assert(d.format.integer == .doubleword);11635 assert(d.format.general == .doubleword);
10883 const imm: i21 = @intCast(@shrExact(label, 12));11636 const imm: i21 = @intCast(@shrExact(label, 12));
10884 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{11637 return .{ .data_processing_immediate = .{ .pc_relative_addressing = .{
10885 .adrp = .{11638 .adrp = .{
...@@ -10900,8 +11653,8 @@ pub const Instruction = packed union {...@@ -10900,8 +11653,8 @@ pub const Instruction = packed union {
10900 }) Instruction {11653 }) Instruction {
10901 switch (d.format) {11654 switch (d.format) {
10902 else => unreachable,11655 else => unreachable,
10903 .integer => |sf| {11656 .general => |sf| {
10904 assert(n.format.integer == sf);11657 assert(n.format.general == sf);
10905 form: switch (form) {11658 form: switch (form) {
10906 .immediate => |bitmask| {11659 .immediate => |bitmask| {
10907 assert(bitmask.validImmediate(sf));11660 assert(bitmask.validImmediate(sf));
...@@ -10916,7 +11669,7 @@ pub const Instruction = packed union {...@@ -10916,7 +11669,7 @@ pub const Instruction = packed union {
10916 },11669 },
10917 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },11670 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
10918 .shifted_register_explicit => |shifted_register_explicit| {11671 .shifted_register_explicit => |shifted_register_explicit| {
10919 assert(shifted_register_explicit.register.format.integer == sf);11672 assert(shifted_register_explicit.register.format.general == sf);
10920 return .{ .data_processing_register = .{ .logical_shifted_register = .{11673 return .{ .data_processing_register = .{ .logical_shifted_register = .{
10921 .@"and" = .{11674 .@"and" = .{
10922 .Rd = d.alias.encode(.{}),11675 .Rd = d.alias.encode(.{}),
...@@ -10962,8 +11715,8 @@ pub const Instruction = packed union {...@@ -10962,8 +11715,8 @@ pub const Instruction = packed union {
10962 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },11715 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
10963 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },11716 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
10964 }) Instruction {11717 }) Instruction {
10965 const sf = d.format.integer;11718 const sf = d.format.general;
10966 assert(n.format.integer == sf);11719 assert(n.format.general == sf);
10967 form: switch (form) {11720 form: switch (form) {
10968 .immediate => |bitmask| {11721 .immediate => |bitmask| {
10969 assert(bitmask.validImmediate(sf));11722 assert(bitmask.validImmediate(sf));
...@@ -10978,7 +11731,7 @@ pub const Instruction = packed union {...@@ -10978,7 +11731,7 @@ pub const Instruction = packed union {
10978 },11731 },
10979 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },11732 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
10980 .shifted_register_explicit => |shifted_register_explicit| {11733 .shifted_register_explicit => |shifted_register_explicit| {
10981 assert(shifted_register_explicit.register.format.integer == sf);11734 assert(shifted_register_explicit.register.format.general == sf);
10982 return .{ .data_processing_register = .{ .logical_shifted_register = .{11735 return .{ .data_processing_register = .{ .logical_shifted_register = .{
10983 .ands = .{11736 .ands = .{
10984 .Rd = d.alias.encode(.{}),11737 .Rd = d.alias.encode(.{}),
...@@ -11004,8 +11757,8 @@ pub const Instruction = packed union {...@@ -11004,8 +11757,8 @@ pub const Instruction = packed union {
11004 }11757 }
11005 /// C6.2.18 ASRV11758 /// C6.2.18 ASRV
11006 pub fn asrv(d: Register, n: Register, m: Register) Instruction {11759 pub fn asrv(d: Register, n: Register, m: Register) Instruction {
11007 const sf = d.format.integer;11760 const sf = d.format.general;
11008 assert(n.format.integer == sf and m.format.integer == sf);11761 assert(n.format.general == sf and m.format.general == sf);
11009 return .{ .data_processing_register = .{ .data_processing_two_source = .{11762 return .{ .data_processing_register = .{ .data_processing_two_source = .{
11010 .asrv = .{11763 .asrv = .{
11011 .Rd = d.alias.encode(.{}),11764 .Rd = d.alias.encode(.{}),
...@@ -11041,8 +11794,8 @@ pub const Instruction = packed union {...@@ -11041,8 +11794,8 @@ pub const Instruction = packed union {
11041 }11794 }
11042 /// C6.2.30 BFM11795 /// C6.2.30 BFM
11043 pub fn bfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {11796 pub fn bfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
11044 const sf = d.format.integer;11797 const sf = d.format.general;
11045 assert(n.format.integer == sf and bitmask.validBitfield(sf));11798 assert(n.format.general == sf and bitmask.validBitfield(sf));
11046 return .{ .data_processing_immediate = .{ .bitfield = .{11799 return .{ .data_processing_immediate = .{ .bitfield = .{
11047 .bfm = .{11800 .bfm = .{
11048 .Rd = d.alias.encode(.{}),11801 .Rd = d.alias.encode(.{}),
...@@ -11063,13 +11816,13 @@ pub const Instruction = packed union {...@@ -11063,13 +11816,13 @@ pub const Instruction = packed union {
11063 }) Instruction {11816 }) Instruction {
11064 switch (d.format) {11817 switch (d.format) {
11065 else => unreachable,11818 else => unreachable,
11066 .integer => |sf| {11819 .general => |sf| {
11067 assert(n.format.integer == sf);11820 assert(n.format.general == sf);
11068 form: switch (form) {11821 form: switch (form) {
11069 else => unreachable,11822 else => unreachable,
11070 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },11823 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
11071 .shifted_register_explicit => |shifted_register_explicit| {11824 .shifted_register_explicit => |shifted_register_explicit| {
11072 assert(shifted_register_explicit.register.format.integer == sf);11825 assert(shifted_register_explicit.register.format.general == sf);
11073 return .{ .data_processing_register = .{ .logical_shifted_register = .{11826 return .{ .data_processing_register = .{ .logical_shifted_register = .{
11074 .bic = .{11827 .bic = .{
11075 .Rd = d.alias.encode(.{}),11828 .Rd = d.alias.encode(.{}),
...@@ -11133,12 +11886,12 @@ pub const Instruction = packed union {...@@ -11133,12 +11886,12 @@ pub const Instruction = packed union {
11133 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },11886 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
11134 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },11887 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
11135 }) Instruction {11888 }) Instruction {
11136 const sf = d.format.integer;11889 const sf = d.format.general;
11137 assert(n.format.integer == sf);11890 assert(n.format.general == sf);
11138 form: switch (form) {11891 form: switch (form) {
11139 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },11892 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
11140 .shifted_register_explicit => |shifted_register_explicit| {11893 .shifted_register_explicit => |shifted_register_explicit| {
11141 assert(shifted_register_explicit.register.format.integer == sf);11894 assert(shifted_register_explicit.register.format.general == sf);
11142 return .{ .data_processing_register = .{ .logical_shifted_register = .{11895 return .{ .data_processing_register = .{ .logical_shifted_register = .{
11143 .bics = .{11896 .bics = .{
11144 .Rd = d.alias.encode(.{}),11897 .Rd = d.alias.encode(.{}),
...@@ -11209,14 +11962,14 @@ pub const Instruction = packed union {...@@ -11209,14 +11962,14 @@ pub const Instruction = packed union {
11209 }11962 }
11210 /// C6.2.35 BLR11963 /// C6.2.35 BLR
11211 pub fn blr(n: Register) Instruction {11964 pub fn blr(n: Register) Instruction {
11212 assert(n.format.integer == .doubleword);11965 assert(n.format.general == .doubleword);
11213 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{11966 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
11214 .blr = .{ .Rn = n.alias.encode(.{}) },11967 .blr = .{ .Rn = n.alias.encode(.{}) },
11215 } } };11968 } } };
11216 }11969 }
11217 /// C6.2.37 BR11970 /// C6.2.37 BR
11218 pub fn br(n: Register) Instruction {11971 pub fn br(n: Register) Instruction {
11219 assert(n.format.integer == .doubleword);11972 assert(n.format.general == .doubleword);
11220 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{11973 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
11221 .br = .{ .Rn = n.alias.encode(.{}) },11974 .br = .{ .Rn = n.alias.encode(.{}) },
11222 } } };11975 } } };
...@@ -11233,7 +11986,7 @@ pub const Instruction = packed union {...@@ -11233,7 +11986,7 @@ pub const Instruction = packed union {
11233 .cbnz = .{11986 .cbnz = .{
11234 .Rt = t.alias.encode(.{}),11987 .Rt = t.alias.encode(.{}),
11235 .imm19 = @intCast(@shrExact(label, 2)),11988 .imm19 = @intCast(@shrExact(label, 2)),
11236 .sf = t.format.integer,11989 .sf = t.format.general,
11237 },11990 },
11238 } } };11991 } } };
11239 }11992 }
...@@ -11243,7 +11996,7 @@ pub const Instruction = packed union {...@@ -11243,7 +11996,7 @@ pub const Instruction = packed union {
11243 .cbz = .{11996 .cbz = .{
11244 .Rt = t.alias.encode(.{}),11997 .Rt = t.alias.encode(.{}),
11245 .imm19 = @intCast(@shrExact(label, 2)),11998 .imm19 = @intCast(@shrExact(label, 2)),
11246 .sf = t.format.integer,11999 .sf = t.format.general,
11247 },12000 },
11248 } } };12001 } } };
11249 }12002 }
...@@ -11252,13 +12005,13 @@ pub const Instruction = packed union {...@@ -11252,13 +12005,13 @@ pub const Instruction = packed union {
11252 pub fn ccmn(12005 pub fn ccmn(
11253 n: Register,12006 n: Register,
11254 form: union(enum) { register: Register, immediate: u5 },12007 form: union(enum) { register: Register, immediate: u5 },
11255 nzcv: DataProcessingRegister.Nzcv,12008 nzcv: Nzcv,
11256 cond: ConditionCode,12009 cond: ConditionCode,
11257 ) Instruction {12010 ) Instruction {
11258 const sf = n.format.integer;12011 const sf = n.format.general;
11259 switch (form) {12012 switch (form) {
11260 .register => |m| {12013 .register => |m| {
11261 assert(m.format.integer == sf);12014 assert(m.format.general == sf);
11262 return .{ .data_processing_register = .{ .conditional_compare_register = .{12015 return .{ .data_processing_register = .{ .conditional_compare_register = .{
11263 .ccmn = .{12016 .ccmn = .{
11264 .nzcv = nzcv,12017 .nzcv = nzcv,
...@@ -11285,13 +12038,13 @@ pub const Instruction = packed union {...@@ -11285,13 +12038,13 @@ pub const Instruction = packed union {
11285 pub fn ccmp(12038 pub fn ccmp(
11286 n: Register,12039 n: Register,
11287 form: union(enum) { register: Register, immediate: u5 },12040 form: union(enum) { register: Register, immediate: u5 },
11288 nzcv: DataProcessingRegister.Nzcv,12041 nzcv: Nzcv,
11289 cond: ConditionCode,12042 cond: ConditionCode,
11290 ) Instruction {12043 ) Instruction {
11291 const sf = n.format.integer;12044 const sf = n.format.general;
11292 switch (form) {12045 switch (form) {
11293 .register => |m| {12046 .register => |m| {
11294 assert(m.format.integer == sf);12047 assert(m.format.general == sf);
11295 return .{ .data_processing_register = .{ .conditional_compare_register = .{12048 return .{ .data_processing_register = .{ .conditional_compare_register = .{
11296 .ccmp = .{12049 .ccmp = .{
11297 .nzcv = nzcv,12050 .nzcv = nzcv,
...@@ -11321,10 +12074,22 @@ pub const Instruction = packed union {...@@ -11321,10 +12074,22 @@ pub const Instruction = packed union {
11321 },12074 },
11322 } } };12075 } } };
11323 }12076 }
12077 /// C6.2.57 CLS
12078 pub fn cls(d: Register, n: Register) Instruction {
12079 const sf = d.format.general;
12080 assert(n.format.general == sf);
12081 return .{ .data_processing_register = .{ .data_processing_one_source = .{
12082 .cls = .{
12083 .Rd = d.alias.encode(.{}),
12084 .Rn = n.alias.encode(.{}),
12085 .sf = sf,
12086 },
12087 } } };
12088 }
11324 /// C6.2.58 CLZ12089 /// C6.2.58 CLZ
11325 pub fn clz(d: Register, n: Register) Instruction {12090 pub fn clz(d: Register, n: Register) Instruction {
11326 const sf = d.format.integer;12091 const sf = d.format.general;
11327 assert(n.format.integer == sf);12092 assert(n.format.general == sf);
11328 return .{ .data_processing_register = .{ .data_processing_one_source = .{12093 return .{ .data_processing_register = .{ .data_processing_one_source = .{
11329 .clz = .{12094 .clz = .{
11330 .Rd = d.alias.encode(.{}),12095 .Rd = d.alias.encode(.{}),
...@@ -11344,7 +12109,7 @@ pub const Instruction = packed union {...@@ -11344,7 +12109,7 @@ pub const Instruction = packed union {
11344 .cmeq = .{12109 .cmeq = .{
11345 .Rd = d.alias.encode(.{ .V = true }),12110 .Rd = d.alias.encode(.{ .V = true }),
11346 .Rn = n.alias.encode(.{ .V = true }),12111 .Rn = n.alias.encode(.{ .V = true }),
11347 .size = .fromVectorSize(elem_size),12112 .size = .fromScalarSize(elem_size),
11348 },12113 },
11349 } } };12114 } } };
11350 },12115 },
...@@ -11373,7 +12138,7 @@ pub const Instruction = packed union {...@@ -11373,7 +12138,7 @@ pub const Instruction = packed union {
11373 .cmge = .{12138 .cmge = .{
11374 .Rd = d.alias.encode(.{ .V = true }),12139 .Rd = d.alias.encode(.{ .V = true }),
11375 .Rn = n.alias.encode(.{ .V = true }),12140 .Rn = n.alias.encode(.{ .V = true }),
11376 .size = .fromVectorSize(elem_size),12141 .size = .fromScalarSize(elem_size),
11377 },12142 },
11378 } } };12143 } } };
11379 },12144 },
...@@ -11402,7 +12167,7 @@ pub const Instruction = packed union {...@@ -11402,7 +12167,7 @@ pub const Instruction = packed union {
11402 .cmgt = .{12167 .cmgt = .{
11403 .Rd = d.alias.encode(.{ .V = true }),12168 .Rd = d.alias.encode(.{ .V = true }),
11404 .Rn = n.alias.encode(.{ .V = true }),12169 .Rn = n.alias.encode(.{ .V = true }),
11405 .size = .fromVectorSize(elem_size),12170 .size = .fromScalarSize(elem_size),
11406 },12171 },
11407 } } };12172 } } };
11408 },12173 },
...@@ -11431,7 +12196,7 @@ pub const Instruction = packed union {...@@ -11431,7 +12196,7 @@ pub const Instruction = packed union {
11431 .cmle = .{12196 .cmle = .{
11432 .Rd = d.alias.encode(.{ .V = true }),12197 .Rd = d.alias.encode(.{ .V = true }),
11433 .Rn = n.alias.encode(.{ .V = true }),12198 .Rn = n.alias.encode(.{ .V = true }),
11434 .size = .fromVectorSize(elem_size),12199 .size = .fromScalarSize(elem_size),
11435 },12200 },
11436 } } };12201 } } };
11437 },12202 },
...@@ -11460,7 +12225,7 @@ pub const Instruction = packed union {...@@ -11460,7 +12225,7 @@ pub const Instruction = packed union {
11460 .cmlt = .{12225 .cmlt = .{
11461 .Rd = d.alias.encode(.{ .V = true }),12226 .Rd = d.alias.encode(.{ .V = true }),
11462 .Rn = n.alias.encode(.{ .V = true }),12227 .Rn = n.alias.encode(.{ .V = true }),
11463 .size = .fromVectorSize(elem_size),12228 .size = .fromScalarSize(elem_size),
11464 },12229 },
11465 } } };12230 } } };
11466 },12231 },
...@@ -11493,8 +12258,8 @@ pub const Instruction = packed union {...@@ -11493,8 +12258,8 @@ pub const Instruction = packed union {
11493 }12258 }
11494 /// C6.2.103 CSEL12259 /// C6.2.103 CSEL
11495 pub fn csel(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {12260 pub fn csel(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11496 const sf = d.format.integer;12261 const sf = d.format.general;
11497 assert(n.format.integer == sf and m.format.integer == sf);12262 assert(n.format.general == sf and m.format.general == sf);
11498 return .{ .data_processing_register = .{ .conditional_select = .{12263 return .{ .data_processing_register = .{ .conditional_select = .{
11499 .csel = .{12264 .csel = .{
11500 .Rd = d.alias.encode(.{}),12265 .Rd = d.alias.encode(.{}),
...@@ -11507,8 +12272,8 @@ pub const Instruction = packed union {...@@ -11507,8 +12272,8 @@ pub const Instruction = packed union {
11507 }12272 }
11508 /// C6.2.106 CSINC12273 /// C6.2.106 CSINC
11509 pub fn csinc(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {12274 pub fn csinc(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11510 const sf = d.format.integer;12275 const sf = d.format.general;
11511 assert(n.format.integer == sf and m.format.integer == sf);12276 assert(n.format.general == sf and m.format.general == sf);
11512 return .{ .data_processing_register = .{ .conditional_select = .{12277 return .{ .data_processing_register = .{ .conditional_select = .{
11513 .csinc = .{12278 .csinc = .{
11514 .Rd = d.alias.encode(.{}),12279 .Rd = d.alias.encode(.{}),
...@@ -11521,8 +12286,8 @@ pub const Instruction = packed union {...@@ -11521,8 +12286,8 @@ pub const Instruction = packed union {
11521 }12286 }
11522 /// C6.2.107 CSINV12287 /// C6.2.107 CSINV
11523 pub fn csinv(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {12288 pub fn csinv(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11524 const sf = d.format.integer;12289 const sf = d.format.general;
11525 assert(n.format.integer == sf and m.format.integer == sf);12290 assert(n.format.general == sf and m.format.general == sf);
11526 return .{ .data_processing_register = .{ .conditional_select = .{12291 return .{ .data_processing_register = .{ .conditional_select = .{
11527 .csinv = .{12292 .csinv = .{
11528 .Rd = d.alias.encode(.{}),12293 .Rd = d.alias.encode(.{}),
...@@ -11535,8 +12300,8 @@ pub const Instruction = packed union {...@@ -11535,8 +12300,8 @@ pub const Instruction = packed union {
11535 }12300 }
11536 /// C6.2.108 CSNEG12301 /// C6.2.108 CSNEG
11537 pub fn csneg(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {12302 pub fn csneg(d: Register, n: Register, m: Register, cond: ConditionCode) Instruction {
11538 const sf = d.format.integer;12303 const sf = d.format.general;
11539 assert(n.format.integer == sf and m.format.integer == sf);12304 assert(n.format.general == sf and m.format.general == sf);
11540 return .{ .data_processing_register = .{ .conditional_select = .{12305 return .{ .data_processing_register = .{ .conditional_select = .{
11541 .csneg = .{12306 .csneg = .{
11542 .Rd = d.alias.encode(.{}),12307 .Rd = d.alias.encode(.{}),
...@@ -11579,7 +12344,7 @@ pub const Instruction = packed union {...@@ -11579,7 +12344,7 @@ pub const Instruction = packed union {
11579 switch (d.format) {12344 switch (d.format) {
11580 else => unreachable,12345 else => unreachable,
11581 .scalar => |elem_size| {12346 .scalar => |elem_size| {
11582 assert(@intFromEnum(elem_size) <= @intFromEnum(Register.VectorSize.double) and elem_size == n.format.element.size);12347 assert(@intFromEnum(elem_size) <= @intFromEnum(Register.ScalarSize.double) and elem_size == n.format.element.size);
11583 return .{ .data_processing_vector = .{ .simd_scalar_copy = .{12348 return .{ .data_processing_vector = .{ .simd_scalar_copy = .{
11584 .dup = .{12349 .dup = .{
11585 .Rd = d.alias.encode(.{ .V = true }),12350 .Rd = d.alias.encode(.{ .V = true }),
...@@ -11594,7 +12359,7 @@ pub const Instruction = packed union {...@@ -11594,7 +12359,7 @@ pub const Instruction = packed union {
11594 switch (n.format) {12359 switch (n.format) {
11595 else => unreachable,12360 else => unreachable,
11596 .element => |element| {12361 .element => |element| {
11597 assert(elem_size.toVectorSize() == element.size);12362 assert(elem_size.toScalarSize() == element.size);
11598 return .{ .data_processing_vector = .{ .simd_copy = .{12363 return .{ .data_processing_vector = .{ .simd_copy = .{
11599 .dup = .{12364 .dup = .{
11600 .Rd = d.alias.encode(.{ .V = true }),12365 .Rd = d.alias.encode(.{ .V = true }),
...@@ -11605,8 +12370,8 @@ pub const Instruction = packed union {...@@ -11605,8 +12370,8 @@ pub const Instruction = packed union {
11605 },12370 },
11606 } } };12371 } } };
11607 },12372 },
11608 .integer => |sf| {12373 .general => |sf| {
11609 assert(sf == @as(Register.IntegerSize, switch (elem_size) {12374 assert(sf == @as(Register.GeneralSize, switch (elem_size) {
11610 .byte, .half, .single => .word,12375 .byte, .half, .single => .word,
11611 .double => .doubleword,12376 .double => .doubleword,
11612 }));12377 }));
...@@ -11630,12 +12395,12 @@ pub const Instruction = packed union {...@@ -11630,12 +12395,12 @@ pub const Instruction = packed union {
11630 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },12395 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
11631 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },12396 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
11632 }) Instruction {12397 }) Instruction {
11633 const sf = d.format.integer;12398 const sf = d.format.general;
11634 assert(n.format.integer == sf);12399 assert(n.format.general == sf);
11635 form: switch (form) {12400 form: switch (form) {
11636 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },12401 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
11637 .shifted_register_explicit => |shifted_register_explicit| {12402 .shifted_register_explicit => |shifted_register_explicit| {
11638 assert(shifted_register_explicit.register.format.integer == sf);12403 assert(shifted_register_explicit.register.format.general == sf);
11639 return .{ .data_processing_register = .{ .logical_shifted_register = .{12404 return .{ .data_processing_register = .{ .logical_shifted_register = .{
11640 .eon = .{12405 .eon = .{
11641 .Rd = d.alias.encode(.{}),12406 .Rd = d.alias.encode(.{}),
...@@ -11670,8 +12435,8 @@ pub const Instruction = packed union {...@@ -11670,8 +12435,8 @@ pub const Instruction = packed union {
11670 }) Instruction {12435 }) Instruction {
11671 switch (d.format) {12436 switch (d.format) {
11672 else => unreachable,12437 else => unreachable,
11673 .integer => |sf| {12438 .general => |sf| {
11674 assert(n.format.integer == sf);12439 assert(n.format.general == sf);
11675 form: switch (form) {12440 form: switch (form) {
11676 .immediate => |bitmask| {12441 .immediate => |bitmask| {
11677 assert(bitmask.validImmediate(sf));12442 assert(bitmask.validImmediate(sf));
...@@ -11686,7 +12451,7 @@ pub const Instruction = packed union {...@@ -11686,7 +12451,7 @@ pub const Instruction = packed union {
11686 },12451 },
11687 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },12452 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
11688 .shifted_register_explicit => |shifted_register_explicit| {12453 .shifted_register_explicit => |shifted_register_explicit| {
11689 assert(shifted_register_explicit.register.format.integer == sf);12454 assert(shifted_register_explicit.register.format.general == sf);
11690 return .{ .data_processing_register = .{ .logical_shifted_register = .{12455 return .{ .data_processing_register = .{ .logical_shifted_register = .{
11691 .eor = .{12456 .eor = .{
11692 .Rd = d.alias.encode(.{}),12457 .Rd = d.alias.encode(.{}),
...@@ -11726,8 +12491,8 @@ pub const Instruction = packed union {...@@ -11726,8 +12491,8 @@ pub const Instruction = packed union {
11726 }12491 }
11727 /// C6.2.124 EXTR12492 /// C6.2.124 EXTR
11728 pub fn extr(d: Register, n: Register, m: Register, lsb: u6) Instruction {12493 pub fn extr(d: Register, n: Register, m: Register, lsb: u6) Instruction {
11729 const sf = d.format.integer;12494 const sf = d.format.general;
11730 assert(n.format.integer == sf and m.format.integer == sf);12495 assert(n.format.general == sf and m.format.general == sf);
11731 return .{ .data_processing_immediate = .{ .extract = .{12496 return .{ .data_processing_immediate = .{ .extract = .{
11732 .extr = .{12497 .extr = .{
11733 .Rd = d.alias.encode(.{}),12498 .Rd = d.alias.encode(.{}),
...@@ -11774,7 +12539,7 @@ pub const Instruction = packed union {...@@ -11774,7 +12539,7 @@ pub const Instruction = packed union {
11774 .fabs = .{12539 .fabs = .{
11775 .Rd = d.alias.encode(.{ .V = true }),12540 .Rd = d.alias.encode(.{ .V = true }),
11776 .Rn = n.alias.encode(.{ .V = true }),12541 .Rn = n.alias.encode(.{ .V = true }),
11777 .ftype = .fromVectorSize(ftype),12542 .ftype = .fromScalarSize(ftype),
11778 },12543 },
11779 } } };12544 } } };
11780 },12545 },
...@@ -11789,7 +12554,7 @@ pub const Instruction = packed union {...@@ -11789,7 +12554,7 @@ pub const Instruction = packed union {
11789 .Rd = d.alias.encode(.{ .V = true }),12554 .Rd = d.alias.encode(.{ .V = true }),
11790 .Rn = n.alias.encode(.{ .V = true }),12555 .Rn = n.alias.encode(.{ .V = true }),
11791 .Rm = m.alias.encode(.{ .V = true }),12556 .Rm = m.alias.encode(.{ .V = true }),
11792 .ftype = .fromVectorSize(ftype),12557 .ftype = .fromScalarSize(ftype),
11793 },12558 },
11794 } } };12559 } } };
11795 }12560 }
...@@ -11814,7 +12579,7 @@ pub const Instruction = packed union {...@@ -11814,7 +12579,7 @@ pub const Instruction = packed union {
11814 .fcmeq = .{12579 .fcmeq = .{
11815 .Rd = d.alias.encode(.{ .V = true }),12580 .Rd = d.alias.encode(.{ .V = true }),
11816 .Rn = n.alias.encode(.{ .V = true }),12581 .Rn = n.alias.encode(.{ .V = true }),
11817 .sz = .fromVectorSize(ftype),12582 .sz = .fromScalarSize(ftype),
11818 },12583 },
11819 } } },12584 } } },
11820 }12585 }
...@@ -11865,7 +12630,7 @@ pub const Instruction = packed union {...@@ -11865,7 +12630,7 @@ pub const Instruction = packed union {
11865 .fcmge = .{12630 .fcmge = .{
11866 .Rd = d.alias.encode(.{ .V = true }),12631 .Rd = d.alias.encode(.{ .V = true }),
11867 .Rn = n.alias.encode(.{ .V = true }),12632 .Rn = n.alias.encode(.{ .V = true }),
11868 .sz = .fromVectorSize(ftype),12633 .sz = .fromScalarSize(ftype),
11869 },12634 },
11870 } } },12635 } } },
11871 }12636 }
...@@ -11916,7 +12681,7 @@ pub const Instruction = packed union {...@@ -11916,7 +12681,7 @@ pub const Instruction = packed union {
11916 .fcmgt = .{12681 .fcmgt = .{
11917 .Rd = d.alias.encode(.{ .V = true }),12682 .Rd = d.alias.encode(.{ .V = true }),
11918 .Rn = n.alias.encode(.{ .V = true }),12683 .Rn = n.alias.encode(.{ .V = true }),
11919 .sz = .fromVectorSize(ftype),12684 .sz = .fromScalarSize(ftype),
11920 },12685 },
11921 } } },12686 } } },
11922 }12687 }
...@@ -11967,7 +12732,7 @@ pub const Instruction = packed union {...@@ -11967,7 +12732,7 @@ pub const Instruction = packed union {
11967 .fcmle = .{12732 .fcmle = .{
11968 .Rd = d.alias.encode(.{ .V = true }),12733 .Rd = d.alias.encode(.{ .V = true }),
11969 .Rn = n.alias.encode(.{ .V = true }),12734 .Rn = n.alias.encode(.{ .V = true }),
11970 .sz = .fromVectorSize(ftype),12735 .sz = .fromScalarSize(ftype),
11971 },12736 },
11972 } } },12737 } } },
11973 }12738 }
...@@ -12018,7 +12783,7 @@ pub const Instruction = packed union {...@@ -12018,7 +12783,7 @@ pub const Instruction = packed union {
12018 .fcmlt = .{12783 .fcmlt = .{
12019 .Rd = d.alias.encode(.{ .V = true }),12784 .Rd = d.alias.encode(.{ .V = true }),
12020 .Rn = n.alias.encode(.{ .V = true }),12785 .Rn = n.alias.encode(.{ .V = true }),
12021 .sz = .fromVectorSize(ftype),12786 .sz = .fromScalarSize(ftype),
12022 },12787 },
12023 } } },12788 } } },
12024 }12789 }
...@@ -12059,7 +12824,7 @@ pub const Instruction = packed union {...@@ -12059,7 +12824,7 @@ pub const Instruction = packed union {
12059 .opc0 = .register,12824 .opc0 = .register,
12060 .Rn = n.alias.encode(.{ .V = true }),12825 .Rn = n.alias.encode(.{ .V = true }),
12061 .Rm = m.alias.encode(.{ .V = true }),12826 .Rm = m.alias.encode(.{ .V = true }),
12062 .ftype = .fromVectorSize(ftype),12827 .ftype = .fromScalarSize(ftype),
12063 },12828 },
12064 } } };12829 } } };
12065 },12830 },
...@@ -12068,7 +12833,7 @@ pub const Instruction = packed union {...@@ -12068,7 +12833,7 @@ pub const Instruction = packed union {
12068 .opc0 = .register,12833 .opc0 = .register,
12069 .Rn = n.alias.encode(.{ .V = true }),12834 .Rn = n.alias.encode(.{ .V = true }),
12070 .Rm = @enumFromInt(0b00000),12835 .Rm = @enumFromInt(0b00000),
12071 .ftype = .fromVectorSize(ftype),12836 .ftype = .fromScalarSize(ftype),
12072 },12837 },
12073 } } },12838 } } },
12074 }12839 }
...@@ -12084,7 +12849,7 @@ pub const Instruction = packed union {...@@ -12084,7 +12849,7 @@ pub const Instruction = packed union {
12084 .opc0 = .zero,12849 .opc0 = .zero,
12085 .Rn = n.alias.encode(.{ .V = true }),12850 .Rn = n.alias.encode(.{ .V = true }),
12086 .Rm = m.alias.encode(.{ .V = true }),12851 .Rm = m.alias.encode(.{ .V = true }),
12087 .ftype = .fromVectorSize(ftype),12852 .ftype = .fromScalarSize(ftype),
12088 },12853 },
12089 } } };12854 } } };
12090 },12855 },
...@@ -12093,7 +12858,7 @@ pub const Instruction = packed union {...@@ -12093,7 +12858,7 @@ pub const Instruction = packed union {
12093 .opc0 = .zero,12858 .opc0 = .zero,
12094 .Rn = n.alias.encode(.{ .V = true }),12859 .Rn = n.alias.encode(.{ .V = true }),
12095 .Rm = @enumFromInt(0b00000),12860 .Rm = @enumFromInt(0b00000),
12096 .ftype = .fromVectorSize(ftype),12861 .ftype = .fromScalarSize(ftype),
12097 },12862 },
12098 } } },12863 } } },
12099 }12864 }
...@@ -12108,7 +12873,7 @@ pub const Instruction = packed union {...@@ -12108,7 +12873,7 @@ pub const Instruction = packed union {
12108 .Rn = n.alias.encode(.{ .V = true }),12873 .Rn = n.alias.encode(.{ .V = true }),
12109 .cond = cond,12874 .cond = cond,
12110 .Rm = m.alias.encode(.{ .V = true }),12875 .Rm = m.alias.encode(.{ .V = true }),
12111 .ftype = .fromVectorSize(ftype),12876 .ftype = .fromScalarSize(ftype),
12112 },12877 },
12113 } } };12878 } } };
12114 }12879 }
...@@ -12125,7 +12890,7 @@ pub const Instruction = packed union {...@@ -12125,7 +12890,7 @@ pub const Instruction = packed union {
12125 .double => .double,12890 .double => .double,
12126 .half => .half,12891 .half => .half,
12127 },12892 },
12128 .ftype = .fromVectorSize(n.format.scalar),12893 .ftype = .fromScalarSize(n.format.scalar),
12129 },12894 },
12130 } } };12895 } } };
12131 }12896 }
...@@ -12134,11 +12899,11 @@ pub const Instruction = packed union {...@@ -12134,11 +12899,11 @@ pub const Instruction = packed union {
12134 pub fn fcvtas(d: Register, n: Register) Instruction {12899 pub fn fcvtas(d: Register, n: Register) Instruction {
12135 switch (d.format) {12900 switch (d.format) {
12136 else => unreachable,12901 else => unreachable,
12137 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{12902 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12138 .fcvtas = .{12903 .fcvtas = .{
12139 .Rd = d.alias.encode(.{}),12904 .Rd = d.alias.encode(.{}),
12140 .Rn = n.alias.encode(.{ .V = true }),12905 .Rn = n.alias.encode(.{ .V = true }),
12141 .ftype = .fromVectorSize(n.format.scalar),12906 .ftype = .fromScalarSize(n.format.scalar),
12142 .sf = sf,12907 .sf = sf,
12143 },12908 },
12144 } } },12909 } } },
...@@ -12158,7 +12923,7 @@ pub const Instruction = packed union {...@@ -12158,7 +12923,7 @@ pub const Instruction = packed union {
12158 .fcvtas = .{12923 .fcvtas = .{
12159 .Rd = d.alias.encode(.{ .V = true }),12924 .Rd = d.alias.encode(.{ .V = true }),
12160 .Rn = n.alias.encode(.{ .V = true }),12925 .Rn = n.alias.encode(.{ .V = true }),
12161 .sz = .fromVectorSize(elem_size),12926 .sz = .fromScalarSize(elem_size),
12162 },12927 },
12163 } } },12928 } } },
12164 }12929 }
...@@ -12192,11 +12957,11 @@ pub const Instruction = packed union {...@@ -12192,11 +12957,11 @@ pub const Instruction = packed union {
12192 pub fn fcvtau(d: Register, n: Register) Instruction {12957 pub fn fcvtau(d: Register, n: Register) Instruction {
12193 switch (d.format) {12958 switch (d.format) {
12194 else => unreachable,12959 else => unreachable,
12195 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{12960 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12196 .fcvtau = .{12961 .fcvtau = .{
12197 .Rd = d.alias.encode(.{}),12962 .Rd = d.alias.encode(.{}),
12198 .Rn = n.alias.encode(.{ .V = true }),12963 .Rn = n.alias.encode(.{ .V = true }),
12199 .ftype = .fromVectorSize(n.format.scalar),12964 .ftype = .fromScalarSize(n.format.scalar),
12200 .sf = sf,12965 .sf = sf,
12201 },12966 },
12202 } } },12967 } } },
...@@ -12216,7 +12981,7 @@ pub const Instruction = packed union {...@@ -12216,7 +12981,7 @@ pub const Instruction = packed union {
12216 .fcvtau = .{12981 .fcvtau = .{
12217 .Rd = d.alias.encode(.{ .V = true }),12982 .Rd = d.alias.encode(.{ .V = true }),
12218 .Rn = n.alias.encode(.{ .V = true }),12983 .Rn = n.alias.encode(.{ .V = true }),
12219 .sz = .fromVectorSize(elem_size),12984 .sz = .fromScalarSize(elem_size),
12220 },12985 },
12221 } } },12986 } } },
12222 }12987 }
...@@ -12250,11 +13015,11 @@ pub const Instruction = packed union {...@@ -12250,11 +13015,11 @@ pub const Instruction = packed union {
12250 pub fn fcvtms(d: Register, n: Register) Instruction {13015 pub fn fcvtms(d: Register, n: Register) Instruction {
12251 switch (d.format) {13016 switch (d.format) {
12252 else => unreachable,13017 else => unreachable,
12253 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13018 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12254 .fcvtms = .{13019 .fcvtms = .{
12255 .Rd = d.alias.encode(.{}),13020 .Rd = d.alias.encode(.{}),
12256 .Rn = n.alias.encode(.{ .V = true }),13021 .Rn = n.alias.encode(.{ .V = true }),
12257 .ftype = .fromVectorSize(n.format.scalar),13022 .ftype = .fromScalarSize(n.format.scalar),
12258 .sf = sf,13023 .sf = sf,
12259 },13024 },
12260 } } },13025 } } },
...@@ -12274,7 +13039,7 @@ pub const Instruction = packed union {...@@ -12274,7 +13039,7 @@ pub const Instruction = packed union {
12274 .fcvtms = .{13039 .fcvtms = .{
12275 .Rd = d.alias.encode(.{ .V = true }),13040 .Rd = d.alias.encode(.{ .V = true }),
12276 .Rn = n.alias.encode(.{ .V = true }),13041 .Rn = n.alias.encode(.{ .V = true }),
12277 .sz = .fromVectorSize(elem_size),13042 .sz = .fromScalarSize(elem_size),
12278 },13043 },
12279 } } },13044 } } },
12280 }13045 }
...@@ -12308,11 +13073,11 @@ pub const Instruction = packed union {...@@ -12308,11 +13073,11 @@ pub const Instruction = packed union {
12308 pub fn fcvtmu(d: Register, n: Register) Instruction {13073 pub fn fcvtmu(d: Register, n: Register) Instruction {
12309 switch (d.format) {13074 switch (d.format) {
12310 else => unreachable,13075 else => unreachable,
12311 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13076 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12312 .fcvtmu = .{13077 .fcvtmu = .{
12313 .Rd = d.alias.encode(.{}),13078 .Rd = d.alias.encode(.{}),
12314 .Rn = n.alias.encode(.{ .V = true }),13079 .Rn = n.alias.encode(.{ .V = true }),
12315 .ftype = .fromVectorSize(n.format.scalar),13080 .ftype = .fromScalarSize(n.format.scalar),
12316 .sf = sf,13081 .sf = sf,
12317 },13082 },
12318 } } },13083 } } },
...@@ -12332,7 +13097,7 @@ pub const Instruction = packed union {...@@ -12332,7 +13097,7 @@ pub const Instruction = packed union {
12332 .fcvtmu = .{13097 .fcvtmu = .{
12333 .Rd = d.alias.encode(.{ .V = true }),13098 .Rd = d.alias.encode(.{ .V = true }),
12334 .Rn = n.alias.encode(.{ .V = true }),13099 .Rn = n.alias.encode(.{ .V = true }),
12335 .sz = .fromVectorSize(elem_size),13100 .sz = .fromScalarSize(elem_size),
12336 },13101 },
12337 } } },13102 } } },
12338 }13103 }
...@@ -12366,11 +13131,11 @@ pub const Instruction = packed union {...@@ -12366,11 +13131,11 @@ pub const Instruction = packed union {
12366 pub fn fcvtns(d: Register, n: Register) Instruction {13131 pub fn fcvtns(d: Register, n: Register) Instruction {
12367 switch (d.format) {13132 switch (d.format) {
12368 else => unreachable,13133 else => unreachable,
12369 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13134 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12370 .fcvtns = .{13135 .fcvtns = .{
12371 .Rd = d.alias.encode(.{}),13136 .Rd = d.alias.encode(.{}),
12372 .Rn = n.alias.encode(.{ .V = true }),13137 .Rn = n.alias.encode(.{ .V = true }),
12373 .ftype = .fromVectorSize(n.format.scalar),13138 .ftype = .fromScalarSize(n.format.scalar),
12374 .sf = sf,13139 .sf = sf,
12375 },13140 },
12376 } } },13141 } } },
...@@ -12390,7 +13155,7 @@ pub const Instruction = packed union {...@@ -12390,7 +13155,7 @@ pub const Instruction = packed union {
12390 .fcvtns = .{13155 .fcvtns = .{
12391 .Rd = d.alias.encode(.{ .V = true }),13156 .Rd = d.alias.encode(.{ .V = true }),
12392 .Rn = n.alias.encode(.{ .V = true }),13157 .Rn = n.alias.encode(.{ .V = true }),
12393 .sz = .fromVectorSize(elem_size),13158 .sz = .fromScalarSize(elem_size),
12394 },13159 },
12395 } } },13160 } } },
12396 }13161 }
...@@ -12424,11 +13189,11 @@ pub const Instruction = packed union {...@@ -12424,11 +13189,11 @@ pub const Instruction = packed union {
12424 pub fn fcvtnu(d: Register, n: Register) Instruction {13189 pub fn fcvtnu(d: Register, n: Register) Instruction {
12425 switch (d.format) {13190 switch (d.format) {
12426 else => unreachable,13191 else => unreachable,
12427 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13192 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12428 .fcvtnu = .{13193 .fcvtnu = .{
12429 .Rd = d.alias.encode(.{}),13194 .Rd = d.alias.encode(.{}),
12430 .Rn = n.alias.encode(.{ .V = true }),13195 .Rn = n.alias.encode(.{ .V = true }),
12431 .ftype = .fromVectorSize(n.format.scalar),13196 .ftype = .fromScalarSize(n.format.scalar),
12432 .sf = sf,13197 .sf = sf,
12433 },13198 },
12434 } } },13199 } } },
...@@ -12448,7 +13213,7 @@ pub const Instruction = packed union {...@@ -12448,7 +13213,7 @@ pub const Instruction = packed union {
12448 .fcvtnu = .{13213 .fcvtnu = .{
12449 .Rd = d.alias.encode(.{ .V = true }),13214 .Rd = d.alias.encode(.{ .V = true }),
12450 .Rn = n.alias.encode(.{ .V = true }),13215 .Rn = n.alias.encode(.{ .V = true }),
12451 .sz = .fromVectorSize(elem_size),13216 .sz = .fromScalarSize(elem_size),
12452 },13217 },
12453 } } },13218 } } },
12454 }13219 }
...@@ -12482,11 +13247,11 @@ pub const Instruction = packed union {...@@ -12482,11 +13247,11 @@ pub const Instruction = packed union {
12482 pub fn fcvtps(d: Register, n: Register) Instruction {13247 pub fn fcvtps(d: Register, n: Register) Instruction {
12483 switch (d.format) {13248 switch (d.format) {
12484 else => unreachable,13249 else => unreachable,
12485 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13250 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12486 .fcvtps = .{13251 .fcvtps = .{
12487 .Rd = d.alias.encode(.{}),13252 .Rd = d.alias.encode(.{}),
12488 .Rn = n.alias.encode(.{ .V = true }),13253 .Rn = n.alias.encode(.{ .V = true }),
12489 .ftype = .fromVectorSize(n.format.scalar),13254 .ftype = .fromScalarSize(n.format.scalar),
12490 .sf = sf,13255 .sf = sf,
12491 },13256 },
12492 } } },13257 } } },
...@@ -12506,7 +13271,7 @@ pub const Instruction = packed union {...@@ -12506,7 +13271,7 @@ pub const Instruction = packed union {
12506 .fcvtps = .{13271 .fcvtps = .{
12507 .Rd = d.alias.encode(.{ .V = true }),13272 .Rd = d.alias.encode(.{ .V = true }),
12508 .Rn = n.alias.encode(.{ .V = true }),13273 .Rn = n.alias.encode(.{ .V = true }),
12509 .sz = .fromVectorSize(elem_size),13274 .sz = .fromScalarSize(elem_size),
12510 },13275 },
12511 } } },13276 } } },
12512 }13277 }
...@@ -12540,11 +13305,11 @@ pub const Instruction = packed union {...@@ -12540,11 +13305,11 @@ pub const Instruction = packed union {
12540 pub fn fcvtpu(d: Register, n: Register) Instruction {13305 pub fn fcvtpu(d: Register, n: Register) Instruction {
12541 switch (d.format) {13306 switch (d.format) {
12542 else => unreachable,13307 else => unreachable,
12543 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13308 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12544 .fcvtpu = .{13309 .fcvtpu = .{
12545 .Rd = d.alias.encode(.{}),13310 .Rd = d.alias.encode(.{}),
12546 .Rn = n.alias.encode(.{ .V = true }),13311 .Rn = n.alias.encode(.{ .V = true }),
12547 .ftype = .fromVectorSize(n.format.scalar),13312 .ftype = .fromScalarSize(n.format.scalar),
12548 .sf = sf,13313 .sf = sf,
12549 },13314 },
12550 } } },13315 } } },
...@@ -12564,7 +13329,7 @@ pub const Instruction = packed union {...@@ -12564,7 +13329,7 @@ pub const Instruction = packed union {
12564 .fcvtpu = .{13329 .fcvtpu = .{
12565 .Rd = d.alias.encode(.{ .V = true }),13330 .Rd = d.alias.encode(.{ .V = true }),
12566 .Rn = n.alias.encode(.{ .V = true }),13331 .Rn = n.alias.encode(.{ .V = true }),
12567 .sz = .fromVectorSize(elem_size),13332 .sz = .fromScalarSize(elem_size),
12568 },13333 },
12569 } } },13334 } } },
12570 }13335 }
...@@ -12598,11 +13363,11 @@ pub const Instruction = packed union {...@@ -12598,11 +13363,11 @@ pub const Instruction = packed union {
12598 pub fn fcvtzs(d: Register, n: Register) Instruction {13363 pub fn fcvtzs(d: Register, n: Register) Instruction {
12599 switch (d.format) {13364 switch (d.format) {
12600 else => unreachable,13365 else => unreachable,
12601 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13366 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12602 .fcvtzs = .{13367 .fcvtzs = .{
12603 .Rd = d.alias.encode(.{}),13368 .Rd = d.alias.encode(.{}),
12604 .Rn = n.alias.encode(.{ .V = true }),13369 .Rn = n.alias.encode(.{ .V = true }),
12605 .ftype = .fromVectorSize(n.format.scalar),13370 .ftype = .fromScalarSize(n.format.scalar),
12606 .sf = sf,13371 .sf = sf,
12607 },13372 },
12608 } } },13373 } } },
...@@ -12622,7 +13387,7 @@ pub const Instruction = packed union {...@@ -12622,7 +13387,7 @@ pub const Instruction = packed union {
12622 .fcvtzs = .{13387 .fcvtzs = .{
12623 .Rd = d.alias.encode(.{ .V = true }),13388 .Rd = d.alias.encode(.{ .V = true }),
12624 .Rn = n.alias.encode(.{ .V = true }),13389 .Rn = n.alias.encode(.{ .V = true }),
12625 .sz = .fromVectorSize(elem_size),13390 .sz = .fromScalarSize(elem_size),
12626 },13391 },
12627 } } },13392 } } },
12628 }13393 }
...@@ -12656,11 +13421,11 @@ pub const Instruction = packed union {...@@ -12656,11 +13421,11 @@ pub const Instruction = packed union {
12656 pub fn fcvtzu(d: Register, n: Register) Instruction {13421 pub fn fcvtzu(d: Register, n: Register) Instruction {
12657 switch (d.format) {13422 switch (d.format) {
12658 else => unreachable,13423 else => unreachable,
12659 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13424 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12660 .fcvtzu = .{13425 .fcvtzu = .{
12661 .Rd = d.alias.encode(.{}),13426 .Rd = d.alias.encode(.{}),
12662 .Rn = n.alias.encode(.{ .V = true }),13427 .Rn = n.alias.encode(.{ .V = true }),
12663 .ftype = .fromVectorSize(n.format.scalar),13428 .ftype = .fromScalarSize(n.format.scalar),
12664 .sf = sf,13429 .sf = sf,
12665 },13430 },
12666 } } },13431 } } },
...@@ -12680,7 +13445,7 @@ pub const Instruction = packed union {...@@ -12680,7 +13445,7 @@ pub const Instruction = packed union {
12680 .fcvtzu = .{13445 .fcvtzu = .{
12681 .Rd = d.alias.encode(.{ .V = true }),13446 .Rd = d.alias.encode(.{ .V = true }),
12682 .Rn = n.alias.encode(.{ .V = true }),13447 .Rn = n.alias.encode(.{ .V = true }),
12683 .sz = .fromVectorSize(elem_size),13448 .sz = .fromScalarSize(elem_size),
12684 },13449 },
12685 } } },13450 } } },
12686 }13451 }
...@@ -12718,13 +13483,13 @@ pub const Instruction = packed union {...@@ -12718,13 +13483,13 @@ pub const Instruction = packed union {
12718 .Rd = d.alias.encode(.{ .V = true }),13483 .Rd = d.alias.encode(.{ .V = true }),
12719 .Rn = n.alias.encode(.{ .V = true }),13484 .Rn = n.alias.encode(.{ .V = true }),
12720 .Rm = m.alias.encode(.{ .V = true }),13485 .Rm = m.alias.encode(.{ .V = true }),
12721 .ftype = .fromVectorSize(ftype),13486 .ftype = .fromScalarSize(ftype),
12722 },13487 },
12723 } } };13488 } } };
12724 }13489 }
12725 /// C7.2.99 FJCVTZS13490 /// C7.2.99 FJCVTZS
12726 pub fn fjcvtzs(d: Register, n: Register) Instruction {13491 pub fn fjcvtzs(d: Register, n: Register) Instruction {
12727 assert(d.format.integer == .word);13492 assert(d.format.general == .word);
12728 assert(n.format.scalar == .double);13493 assert(n.format.scalar == .double);
12729 return .{ .data_processing_vector = .{ .convert_float_integer = .{13494 return .{ .data_processing_vector = .{ .convert_float_integer = .{
12730 .fjcvtzs = .{13495 .fjcvtzs = .{
...@@ -12743,7 +13508,7 @@ pub const Instruction = packed union {...@@ -12743,7 +13508,7 @@ pub const Instruction = packed union {
12743 .Rn = n.alias.encode(.{ .V = true }),13508 .Rn = n.alias.encode(.{ .V = true }),
12744 .Rm = m.alias.encode(.{ .V = true }),13509 .Rm = m.alias.encode(.{ .V = true }),
12745 .Ra = a.alias.encode(.{ .V = true }),13510 .Ra = a.alias.encode(.{ .V = true }),
12746 .ftype = .fromVectorSize(ftype),13511 .ftype = .fromScalarSize(ftype),
12747 },13512 },
12748 } } };13513 } } };
12749 }13514 }
...@@ -12756,7 +13521,7 @@ pub const Instruction = packed union {...@@ -12756,7 +13521,7 @@ pub const Instruction = packed union {
12756 .Rd = d.alias.encode(.{ .V = true }),13521 .Rd = d.alias.encode(.{ .V = true }),
12757 .Rn = n.alias.encode(.{ .V = true }),13522 .Rn = n.alias.encode(.{ .V = true }),
12758 .Rm = m.alias.encode(.{ .V = true }),13523 .Rm = m.alias.encode(.{ .V = true }),
12759 .ftype = .fromVectorSize(ftype),13524 .ftype = .fromScalarSize(ftype),
12760 },13525 },
12761 } } };13526 } } };
12762 }13527 }
...@@ -12769,7 +13534,7 @@ pub const Instruction = packed union {...@@ -12769,7 +13534,7 @@ pub const Instruction = packed union {
12769 .Rd = d.alias.encode(.{ .V = true }),13534 .Rd = d.alias.encode(.{ .V = true }),
12770 .Rn = n.alias.encode(.{ .V = true }),13535 .Rn = n.alias.encode(.{ .V = true }),
12771 .Rm = m.alias.encode(.{ .V = true }),13536 .Rm = m.alias.encode(.{ .V = true }),
12772 .ftype = .fromVectorSize(ftype),13537 .ftype = .fromScalarSize(ftype),
12773 },13538 },
12774 } } };13539 } } };
12775 }13540 }
...@@ -12782,7 +13547,7 @@ pub const Instruction = packed union {...@@ -12782,7 +13547,7 @@ pub const Instruction = packed union {
12782 .Rd = d.alias.encode(.{ .V = true }),13547 .Rd = d.alias.encode(.{ .V = true }),
12783 .Rn = n.alias.encode(.{ .V = true }),13548 .Rn = n.alias.encode(.{ .V = true }),
12784 .Rm = m.alias.encode(.{ .V = true }),13549 .Rm = m.alias.encode(.{ .V = true }),
12785 .ftype = .fromVectorSize(ftype),13550 .ftype = .fromScalarSize(ftype),
12786 },13551 },
12787 } } };13552 } } };
12788 }13553 }
...@@ -12795,7 +13560,7 @@ pub const Instruction = packed union {...@@ -12795,7 +13560,7 @@ pub const Instruction = packed union {
12795 .Rd = d.alias.encode(.{ .V = true }),13560 .Rd = d.alias.encode(.{ .V = true }),
12796 .Rn = n.alias.encode(.{ .V = true }),13561 .Rn = n.alias.encode(.{ .V = true }),
12797 .Rm = m.alias.encode(.{ .V = true }),13562 .Rm = m.alias.encode(.{ .V = true }),
12798 .ftype = .fromVectorSize(ftype),13563 .ftype = .fromScalarSize(ftype),
12799 },13564 },
12800 } } };13565 } } };
12801 }13566 }
...@@ -12807,31 +13572,39 @@ pub const Instruction = packed union {...@@ -12807,31 +13572,39 @@ pub const Instruction = packed union {
12807 switch (form) {13572 switch (form) {
12808 .immediate => |immediate| {13573 .immediate => |immediate| {
12809 const repr: std.math.FloatRepr(f16) = @bitCast(immediate);13574 const repr: std.math.FloatRepr(f16) = @bitCast(immediate);
12810 const imm: u8 = @bitCast(@as(packed struct(u8) {13575 const imm: DataProcessingVector.FloatImmediate.Fmov.Imm8 = .{
12811 mantissa: u4,
12812 exponent: i3,
12813 sign: std.math.Sign,
12814 }, .{
12815 .mantissa = @intCast(@shrExact(repr.mantissa, 6)),13576 .mantissa = @intCast(@shrExact(repr.mantissa, 6)),
12816 .exponent = @intCast(repr.exponent.unbias() - 1),13577 .exponent = @intCast(repr.exponent.unbias() - 1),
12817 .sign = repr.sign,13578 .sign = repr.sign,
12818 }));13579 };
12819 switch (d.format) {13580 switch (d.format) {
12820 else => unreachable,13581 else => unreachable,
12821 .scalar => |ftype| return .{ .data_processing_vector = .{ .float_immediate = .{13582 .scalar => |ftype| return .{ .data_processing_vector = .{ .float_immediate = .{
12822 .fmov = .{13583 .fmov = .{
12823 .Rd = d.alias.encode(.{ .V = true }),13584 .Rd = d.alias.encode(.{ .V = true }),
12824 .imm8 = imm,13585 .imm8 = imm,
12825 .ftype = .fromVectorSize(ftype),13586 .ftype = .fromScalarSize(ftype),
12826 },13587 },
12827 } } },13588 } } },
12828 .vector => |arrangement| {13589 .vector => |arrangement| {
12829 assert(arrangement.len() > 1 and arrangement.elemSize() != .byte);13590 const elem_size = arrangement.elemSize();
13591 assert(arrangement.len() > 1);
13592 const mod_imm = imm.toModified();
12830 return .{ .data_processing_vector = .{ .simd_modified_immediate = .{13593 return .{ .data_processing_vector = .{ .simd_modified_immediate = .{
12831 .fmov = .{13594 .fmov = .{
12832 .Rd = d.alias.encode(.{ .V = true }),13595 .Rd = d.alias.encode(.{ .V = true }),
12833 .imm5 = @truncate(imm >> 0),13596 .imm5 = mod_imm.imm5,
12834 .imm3 = @intCast(imm >> 5),13597 .o2 = switch (elem_size) {
13598 .byte => unreachable,
13599 .half => 0b1,
13600 .single, .double => 0b0,
13601 },
13602 .imm3 = mod_imm.imm3,
13603 .op = switch (elem_size) {
13604 .byte => unreachable,
13605 .half, .single => 0b0,
13606 .double => 0b1,
13607 },
12835 .Q = arrangement.size(),13608 .Q = arrangement.size(),
12836 },13609 },
12837 } } };13610 } } };
...@@ -12840,7 +13613,7 @@ pub const Instruction = packed union {...@@ -12840,7 +13613,7 @@ pub const Instruction = packed union {
12840 },13613 },
12841 .register => |n| switch (d.format) {13614 .register => |n| switch (d.format) {
12842 else => unreachable,13615 else => unreachable,
12843 .integer => |sf| switch (n.format) {13616 .general => |sf| switch (n.format) {
12844 else => unreachable,13617 else => unreachable,
12845 .scalar => |ftype| {13618 .scalar => |ftype| {
12846 switch (ftype) {13619 switch (ftype) {
...@@ -12855,7 +13628,7 @@ pub const Instruction = packed union {...@@ -12855,7 +13628,7 @@ pub const Instruction = packed union {
12855 .Rn = n.alias.encode(.{ .V = true }),13628 .Rn = n.alias.encode(.{ .V = true }),
12856 .opcode = .float_to_integer,13629 .opcode = .float_to_integer,
12857 .rmode = .@"0",13630 .rmode = .@"0",
12858 .ftype = .fromVectorSize(ftype),13631 .ftype = .fromScalarSize(ftype),
12859 .sf = sf,13632 .sf = sf,
12860 },13633 },
12861 } } };13634 } } };
...@@ -12879,8 +13652,7 @@ pub const Instruction = packed union {...@@ -12879,8 +13652,7 @@ pub const Instruction = packed union {
12879 },13652 },
12880 .scalar => |ftype| switch (n.format) {13653 .scalar => |ftype| switch (n.format) {
12881 else => unreachable,13654 else => unreachable,
12882 .integer => {13655 .general => |sf| {
12883 const sf = n.format.integer;
12884 switch (ftype) {13656 switch (ftype) {
12885 else => unreachable,13657 else => unreachable,
12886 .half => {},13658 .half => {},
...@@ -12893,7 +13665,7 @@ pub const Instruction = packed union {...@@ -12893,7 +13665,7 @@ pub const Instruction = packed union {
12893 .Rn = n.alias.encode(.{}),13665 .Rn = n.alias.encode(.{}),
12894 .opcode = .integer_to_float,13666 .opcode = .integer_to_float,
12895 .rmode = .@"0",13667 .rmode = .@"0",
12896 .ftype = .fromVectorSize(ftype),13668 .ftype = .fromScalarSize(ftype),
12897 .sf = sf,13669 .sf = sf,
12898 },13670 },
12899 } } };13671 } } };
...@@ -12904,14 +13676,14 @@ pub const Instruction = packed union {...@@ -12904,14 +13676,14 @@ pub const Instruction = packed union {
12904 .fmov = .{13676 .fmov = .{
12905 .Rd = d.alias.encode(.{ .V = true }),13677 .Rd = d.alias.encode(.{ .V = true }),
12906 .Rn = n.alias.encode(.{ .V = true }),13678 .Rn = n.alias.encode(.{ .V = true }),
12907 .ftype = .fromVectorSize(ftype),13679 .ftype = .fromScalarSize(ftype),
12908 },13680 },
12909 } } };13681 } } };
12910 },13682 },
12911 },13683 },
12912 .element => |element| switch (n.format) {13684 .element => |element| switch (n.format) {
12913 else => unreachable,13685 else => unreachable,
12914 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{13686 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
12915 .fmov = .{13687 .fmov = .{
12916 .Rd = d.alias.encode(.{ .V = true }),13688 .Rd = d.alias.encode(.{ .V = true }),
12917 .Rn = n.alias.encode(.{}),13689 .Rn = n.alias.encode(.{}),
...@@ -12941,7 +13713,7 @@ pub const Instruction = packed union {...@@ -12941,7 +13713,7 @@ pub const Instruction = packed union {
12941 .Rn = n.alias.encode(.{ .V = true }),13713 .Rn = n.alias.encode(.{ .V = true }),
12942 .Rm = m.alias.encode(.{ .V = true }),13714 .Rm = m.alias.encode(.{ .V = true }),
12943 .Ra = a.alias.encode(.{ .V = true }),13715 .Ra = a.alias.encode(.{ .V = true }),
12944 .ftype = .fromVectorSize(ftype),13716 .ftype = .fromScalarSize(ftype),
12945 },13717 },
12946 } } };13718 } } };
12947 }13719 }
...@@ -12954,7 +13726,7 @@ pub const Instruction = packed union {...@@ -12954,7 +13726,7 @@ pub const Instruction = packed union {
12954 .Rd = d.alias.encode(.{ .V = true }),13726 .Rd = d.alias.encode(.{ .V = true }),
12955 .Rn = n.alias.encode(.{ .V = true }),13727 .Rn = n.alias.encode(.{ .V = true }),
12956 .Rm = m.alias.encode(.{ .V = true }),13728 .Rm = m.alias.encode(.{ .V = true }),
12957 .ftype = .fromVectorSize(ftype),13729 .ftype = .fromScalarSize(ftype),
12958 },13730 },
12959 } } };13731 } } };
12960 }13732 }
...@@ -12990,7 +13762,7 @@ pub const Instruction = packed union {...@@ -12990,7 +13762,7 @@ pub const Instruction = packed union {
12990 .fneg = .{13762 .fneg = .{
12991 .Rd = d.alias.encode(.{ .V = true }),13763 .Rd = d.alias.encode(.{ .V = true }),
12992 .Rn = n.alias.encode(.{ .V = true }),13764 .Rn = n.alias.encode(.{ .V = true }),
12993 .ftype = .fromVectorSize(ftype),13765 .ftype = .fromScalarSize(ftype),
12994 },13766 },
12995 } } };13767 } } };
12996 },13768 },
...@@ -13006,7 +13778,7 @@ pub const Instruction = packed union {...@@ -13006,7 +13778,7 @@ pub const Instruction = packed union {
13006 .Rn = n.alias.encode(.{ .V = true }),13778 .Rn = n.alias.encode(.{ .V = true }),
13007 .Rm = m.alias.encode(.{ .V = true }),13779 .Rm = m.alias.encode(.{ .V = true }),
13008 .Ra = a.alias.encode(.{ .V = true }),13780 .Ra = a.alias.encode(.{ .V = true }),
13009 .ftype = .fromVectorSize(ftype),13781 .ftype = .fromScalarSize(ftype),
13010 },13782 },
13011 } } };13783 } } };
13012 }13784 }
...@@ -13020,7 +13792,7 @@ pub const Instruction = packed union {...@@ -13020,7 +13792,7 @@ pub const Instruction = packed union {
13020 .Rn = n.alias.encode(.{ .V = true }),13792 .Rn = n.alias.encode(.{ .V = true }),
13021 .Rm = m.alias.encode(.{ .V = true }),13793 .Rm = m.alias.encode(.{ .V = true }),
13022 .Ra = a.alias.encode(.{ .V = true }),13794 .Ra = a.alias.encode(.{ .V = true }),
13023 .ftype = .fromVectorSize(ftype),13795 .ftype = .fromScalarSize(ftype),
13024 },13796 },
13025 } } };13797 } } };
13026 }13798 }
...@@ -13033,7 +13805,7 @@ pub const Instruction = packed union {...@@ -13033,7 +13805,7 @@ pub const Instruction = packed union {
13033 .Rd = d.alias.encode(.{ .V = true }),13805 .Rd = d.alias.encode(.{ .V = true }),
13034 .Rn = n.alias.encode(.{ .V = true }),13806 .Rn = n.alias.encode(.{ .V = true }),
13035 .Rm = m.alias.encode(.{ .V = true }),13807 .Rm = m.alias.encode(.{ .V = true }),
13036 .ftype = .fromVectorSize(ftype),13808 .ftype = .fromScalarSize(ftype),
13037 },13809 },
13038 } } };13810 } } };
13039 }13811 }
...@@ -13069,7 +13841,7 @@ pub const Instruction = packed union {...@@ -13069,7 +13841,7 @@ pub const Instruction = packed union {
13069 .frinta = .{13841 .frinta = .{
13070 .Rd = d.alias.encode(.{ .V = true }),13842 .Rd = d.alias.encode(.{ .V = true }),
13071 .Rn = n.alias.encode(.{ .V = true }),13843 .Rn = n.alias.encode(.{ .V = true }),
13072 .ftype = .fromVectorSize(ftype),13844 .ftype = .fromScalarSize(ftype),
13073 },13845 },
13074 } } };13846 } } };
13075 },13847 },
...@@ -13107,7 +13879,7 @@ pub const Instruction = packed union {...@@ -13107,7 +13879,7 @@ pub const Instruction = packed union {
13107 .frinti = .{13879 .frinti = .{
13108 .Rd = d.alias.encode(.{ .V = true }),13880 .Rd = d.alias.encode(.{ .V = true }),
13109 .Rn = n.alias.encode(.{ .V = true }),13881 .Rn = n.alias.encode(.{ .V = true }),
13110 .ftype = .fromVectorSize(ftype),13882 .ftype = .fromScalarSize(ftype),
13111 },13883 },
13112 } } };13884 } } };
13113 },13885 },
...@@ -13145,7 +13917,7 @@ pub const Instruction = packed union {...@@ -13145,7 +13917,7 @@ pub const Instruction = packed union {
13145 .frintm = .{13917 .frintm = .{
13146 .Rd = d.alias.encode(.{ .V = true }),13918 .Rd = d.alias.encode(.{ .V = true }),
13147 .Rn = n.alias.encode(.{ .V = true }),13919 .Rn = n.alias.encode(.{ .V = true }),
13148 .ftype = .fromVectorSize(ftype),13920 .ftype = .fromScalarSize(ftype),
13149 },13921 },
13150 } } };13922 } } };
13151 },13923 },
...@@ -13183,7 +13955,7 @@ pub const Instruction = packed union {...@@ -13183,7 +13955,7 @@ pub const Instruction = packed union {
13183 .frintn = .{13955 .frintn = .{
13184 .Rd = d.alias.encode(.{ .V = true }),13956 .Rd = d.alias.encode(.{ .V = true }),
13185 .Rn = n.alias.encode(.{ .V = true }),13957 .Rn = n.alias.encode(.{ .V = true }),
13186 .ftype = .fromVectorSize(ftype),13958 .ftype = .fromScalarSize(ftype),
13187 },13959 },
13188 } } };13960 } } };
13189 },13961 },
...@@ -13221,7 +13993,7 @@ pub const Instruction = packed union {...@@ -13221,7 +13993,7 @@ pub const Instruction = packed union {
13221 .frintp = .{13993 .frintp = .{
13222 .Rd = d.alias.encode(.{ .V = true }),13994 .Rd = d.alias.encode(.{ .V = true }),
13223 .Rn = n.alias.encode(.{ .V = true }),13995 .Rn = n.alias.encode(.{ .V = true }),
13224 .ftype = .fromVectorSize(ftype),13996 .ftype = .fromScalarSize(ftype),
13225 },13997 },
13226 } } };13998 } } };
13227 },13999 },
...@@ -13259,7 +14031,7 @@ pub const Instruction = packed union {...@@ -13259,7 +14031,7 @@ pub const Instruction = packed union {
13259 .frintx = .{14031 .frintx = .{
13260 .Rd = d.alias.encode(.{ .V = true }),14032 .Rd = d.alias.encode(.{ .V = true }),
13261 .Rn = n.alias.encode(.{ .V = true }),14033 .Rn = n.alias.encode(.{ .V = true }),
13262 .ftype = .fromVectorSize(ftype),14034 .ftype = .fromScalarSize(ftype),
13263 },14035 },
13264 } } };14036 } } };
13265 },14037 },
...@@ -13297,7 +14069,7 @@ pub const Instruction = packed union {...@@ -13297,7 +14069,7 @@ pub const Instruction = packed union {
13297 .frintz = .{14069 .frintz = .{
13298 .Rd = d.alias.encode(.{ .V = true }),14070 .Rd = d.alias.encode(.{ .V = true }),
13299 .Rn = n.alias.encode(.{ .V = true }),14071 .Rn = n.alias.encode(.{ .V = true }),
13300 .ftype = .fromVectorSize(ftype),14072 .ftype = .fromScalarSize(ftype),
13301 },14073 },
13302 } } };14074 } } };
13303 },14075 },
...@@ -13335,7 +14107,7 @@ pub const Instruction = packed union {...@@ -13335,7 +14107,7 @@ pub const Instruction = packed union {
13335 .fsqrt = .{14107 .fsqrt = .{
13336 .Rd = d.alias.encode(.{ .V = true }),14108 .Rd = d.alias.encode(.{ .V = true }),
13337 .Rn = n.alias.encode(.{ .V = true }),14109 .Rn = n.alias.encode(.{ .V = true }),
13338 .ftype = .fromVectorSize(ftype),14110 .ftype = .fromScalarSize(ftype),
13339 },14111 },
13340 } } };14112 } } };
13341 },14113 },
...@@ -13350,7 +14122,7 @@ pub const Instruction = packed union {...@@ -13350,7 +14122,7 @@ pub const Instruction = packed union {
13350 .Rd = d.alias.encode(.{ .V = true }),14122 .Rd = d.alias.encode(.{ .V = true }),
13351 .Rn = n.alias.encode(.{ .V = true }),14123 .Rn = n.alias.encode(.{ .V = true }),
13352 .Rm = m.alias.encode(.{ .V = true }),14124 .Rm = m.alias.encode(.{ .V = true }),
13353 .ftype = .fromVectorSize(ftype),14125 .ftype = .fromScalarSize(ftype),
13354 },14126 },
13355 } } };14127 } } };
13356 }14128 }
...@@ -13375,6 +14147,42 @@ pub const Instruction = packed union {...@@ -13375,6 +14147,42 @@ pub const Instruction = packed union {
13375 .hvc = .{ .imm16 = imm },14147 .hvc = .{ .imm16 = imm },
13376 } } };14148 } } };
13377 }14149 }
14150 /// C7.2.175 INS (element)
14151 /// C7.2.176 INS (general)
14152 pub fn ins(d: Register, n: Register) Instruction {
14153 const elem_size = d.format.element.size;
14154 switch (n.format) {
14155 else => unreachable,
14156 .element => |element| {
14157 assert(elem_size == element.size);
14158 return .{ .data_processing_vector = .{ .simd_copy = .{
14159 .ins = .{
14160 .Rd = d.alias.encode(.{ .V = true }),
14161 .Rn = n.alias.encode(.{ .V = true }),
14162 .imm4 = .{ .element = element.index << @intCast(@intFromEnum(elem_size)) },
14163 .imm5 = (@as(u5, d.format.element.index) << 1 | @as(u5, 0b1) << 0) << @intFromEnum(elem_size),
14164 .op = .element,
14165 },
14166 } } };
14167 },
14168 .general => |general| {
14169 assert(general == @as(Register.GeneralSize, switch (elem_size) {
14170 else => unreachable,
14171 .byte, .half, .single => .word,
14172 .double => .doubleword,
14173 }));
14174 return .{ .data_processing_vector = .{ .simd_copy = .{
14175 .ins = .{
14176 .Rd = d.alias.encode(.{ .V = true }),
14177 .Rn = n.alias.encode(.{}),
14178 .imm4 = .{ .general = .general },
14179 .imm5 = (@as(u5, d.format.element.index) << 1 | @as(u5, 0b1) << 0) << @intFromEnum(elem_size),
14180 .op = .general,
14181 },
14182 } } };
14183 },
14184 }
14185 }
13378 /// C6.2.131 ISB14186 /// C6.2.131 ISB
13379 pub fn isb(option: BranchExceptionGeneratingSystem.Barriers.Option) Instruction {14187 pub fn isb(option: BranchExceptionGeneratingSystem.Barriers.Option) Instruction {
13380 return .{ .branch_exception_generating_system = .{ .barriers = .{14188 return .{ .branch_exception_generating_system = .{ .barriers = .{
...@@ -13393,11 +14201,11 @@ pub const Instruction = packed union {...@@ -13393,11 +14201,11 @@ pub const Instruction = packed union {
13393 }) Instruction {14201 }) Instruction {
13394 switch (t1.format) {14202 switch (t1.format) {
13395 else => unreachable,14203 else => unreachable,
13396 .integer => |sf| {14204 .general => |sf| {
13397 assert(t2.format.integer == sf);14205 assert(t2.format.general == sf);
13398 form: switch (form) {14206 form: switch (form) {
13399 .post_index => |post_index| {14207 .post_index => |post_index| {
13400 assert(post_index.base.format.integer == .doubleword);14208 assert(post_index.base.format.general == .doubleword);
13401 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{14209 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{
13402 .ldp = .{14210 .ldp = .{
13403 .Rt = t1.alias.encode(.{}),14211 .Rt = t1.alias.encode(.{}),
...@@ -13409,7 +14217,7 @@ pub const Instruction = packed union {...@@ -13409,7 +14217,7 @@ pub const Instruction = packed union {
13409 } } } };14217 } } } };
13410 },14218 },
13411 .pre_index => |pre_index| {14219 .pre_index => |pre_index| {
13412 assert(pre_index.base.format.integer == .doubleword);14220 assert(pre_index.base.format.general == .doubleword);
13413 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{14221 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{
13414 .ldp = .{14222 .ldp = .{
13415 .Rt = t1.alias.encode(.{}),14223 .Rt = t1.alias.encode(.{}),
...@@ -13421,7 +14229,7 @@ pub const Instruction = packed union {...@@ -13421,7 +14229,7 @@ pub const Instruction = packed union {
13421 } } } };14229 } } } };
13422 },14230 },
13423 .signed_offset => |signed_offset| {14231 .signed_offset => |signed_offset| {
13424 assert(signed_offset.base.format.integer == .doubleword);14232 assert(signed_offset.base.format.general == .doubleword);
13425 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{14233 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{
13426 .ldp = .{14234 .ldp = .{
13427 .Rt = t1.alias.encode(.{}),14235 .Rt = t1.alias.encode(.{}),
...@@ -13439,7 +14247,7 @@ pub const Instruction = packed union {...@@ -13439,7 +14247,7 @@ pub const Instruction = packed union {
13439 assert(t2.format.scalar == vs);14247 assert(t2.format.scalar == vs);
13440 form: switch (form) {14248 form: switch (form) {
13441 .post_index => |post_index| {14249 .post_index => |post_index| {
13442 assert(post_index.base.format.integer == .doubleword);14250 assert(post_index.base.format.general == .doubleword);
13443 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{14251 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{
13444 .ldp = .{14252 .ldp = .{
13445 .Rt = t1.alias.encode(.{ .V = true }),14253 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -13451,7 +14259,7 @@ pub const Instruction = packed union {...@@ -13451,7 +14259,7 @@ pub const Instruction = packed union {
13451 } } } };14259 } } } };
13452 },14260 },
13453 .signed_offset => |signed_offset| {14261 .signed_offset => |signed_offset| {
13454 assert(signed_offset.base.format.integer == .doubleword);14262 assert(signed_offset.base.format.general == .doubleword);
13455 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{14263 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{
13456 .ldp = .{14264 .ldp = .{
13457 .Rt = t1.alias.encode(.{ .V = true }),14265 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -13463,7 +14271,7 @@ pub const Instruction = packed union {...@@ -13463,7 +14271,7 @@ pub const Instruction = packed union {
13463 } } } };14271 } } } };
13464 },14272 },
13465 .pre_index => |pre_index| {14273 .pre_index => |pre_index| {
13466 assert(pre_index.base.format.integer == .doubleword);14274 assert(pre_index.base.format.general == .doubleword);
13467 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{14275 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{
13468 .ldp = .{14276 .ldp = .{
13469 .Rt = t1.alias.encode(.{ .V = true }),14277 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -13505,9 +14313,9 @@ pub const Instruction = packed union {...@@ -13505,9 +14313,9 @@ pub const Instruction = packed union {
13505 }) Instruction {14313 }) Instruction {
13506 switch (t.format) {14314 switch (t.format) {
13507 else => unreachable,14315 else => unreachable,
13508 .integer => |sf| form: switch (form) {14316 .general => |sf| form: switch (form) {
13509 .post_index => |post_index| {14317 .post_index => |post_index| {
13510 assert(post_index.base.format.integer == .doubleword);14318 assert(post_index.base.format.general == .doubleword);
13511 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{14319 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
13512 .ldr = .{14320 .ldr = .{
13513 .Rt = t.alias.encode(.{}),14321 .Rt = t.alias.encode(.{}),
...@@ -13518,7 +14326,7 @@ pub const Instruction = packed union {...@@ -13518,7 +14326,7 @@ pub const Instruction = packed union {
13518 } } } };14326 } } } };
13519 },14327 },
13520 .pre_index => |pre_index| {14328 .pre_index => |pre_index| {
13521 assert(pre_index.base.format.integer == .doubleword);14329 assert(pre_index.base.format.general == .doubleword);
13522 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14330 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
13523 .ldr = .{14331 .ldr = .{
13524 .Rt = t.alias.encode(.{}),14332 .Rt = t.alias.encode(.{}),
...@@ -13529,7 +14337,7 @@ pub const Instruction = packed union {...@@ -13529,7 +14337,7 @@ pub const Instruction = packed union {
13529 } } } };14337 } } } };
13530 },14338 },
13531 .unsigned_offset => |unsigned_offset| {14339 .unsigned_offset => |unsigned_offset| {
13532 assert(unsigned_offset.base.format.integer == .doubleword);14340 assert(unsigned_offset.base.format.general == .doubleword);
13533 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{14341 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
13534 .ldr = .{14342 .ldr = .{
13535 .Rt = t.alias.encode(.{}),14343 .Rt = t.alias.encode(.{}),
...@@ -13548,8 +14356,8 @@ pub const Instruction = packed union {...@@ -13548,8 +14356,8 @@ pub const Instruction = packed union {
13548 },14356 },
13549 } } } },14357 } } } },
13550 .extended_register_explicit => |extended_register_explicit| {14358 .extended_register_explicit => |extended_register_explicit| {
13551 assert(extended_register_explicit.base.format.integer == .doubleword and14359 assert(extended_register_explicit.base.format.general == .doubleword and
13552 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14360 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13553 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14361 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
13554 .ldr = .{14362 .ldr = .{
13555 .Rt = t.alias.encode(.{}),14363 .Rt = t.alias.encode(.{}),
...@@ -13583,7 +14391,7 @@ pub const Instruction = packed union {...@@ -13583,7 +14391,7 @@ pub const Instruction = packed union {
13583 },14391 },
13584 .scalar => |vs| form: switch (form) {14392 .scalar => |vs| form: switch (form) {
13585 .post_index => |post_index| {14393 .post_index => |post_index| {
13586 assert(post_index.base.format.integer == .doubleword);14394 assert(post_index.base.format.general == .doubleword);
13587 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{14395 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{
13588 .ldr = .{14396 .ldr = .{
13589 .Rt = t.alias.encode(.{ .V = true }),14397 .Rt = t.alias.encode(.{ .V = true }),
...@@ -13595,7 +14403,7 @@ pub const Instruction = packed union {...@@ -13595,7 +14403,7 @@ pub const Instruction = packed union {
13595 } } } };14403 } } } };
13596 },14404 },
13597 .pre_index => |pre_index| {14405 .pre_index => |pre_index| {
13598 assert(pre_index.base.format.integer == .doubleword);14406 assert(pre_index.base.format.general == .doubleword);
13599 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{14407 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{
13600 .ldr = .{14408 .ldr = .{
13601 .Rt = t.alias.encode(.{ .V = true }),14409 .Rt = t.alias.encode(.{ .V = true }),
...@@ -13607,7 +14415,7 @@ pub const Instruction = packed union {...@@ -13607,7 +14415,7 @@ pub const Instruction = packed union {
13607 } } } };14415 } } } };
13608 },14416 },
13609 .unsigned_offset => |unsigned_offset| {14417 .unsigned_offset => |unsigned_offset| {
13610 assert(unsigned_offset.base.format.integer == .doubleword);14418 assert(unsigned_offset.base.format.general == .doubleword);
13611 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{14419 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{
13612 .ldr = .{14420 .ldr = .{
13613 .Rt = t.alias.encode(.{ .V = true }),14421 .Rt = t.alias.encode(.{ .V = true }),
...@@ -13627,14 +14435,13 @@ pub const Instruction = packed union {...@@ -13627,14 +14435,13 @@ pub const Instruction = packed union {
13627 },14435 },
13628 } } } },14436 } } } },
13629 .extended_register_explicit => |extended_register_explicit| {14437 .extended_register_explicit => |extended_register_explicit| {
13630 assert(extended_register_explicit.base.format.integer == .doubleword and14438 assert(extended_register_explicit.base.format.general == .doubleword and
13631 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14439 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13632 return .{ .load_store = .{ .register_register_offset = .{ .vector = .{14440 return .{ .load_store = .{ .register_register_offset = .{ .vector = .{
13633 .ldr = .{14441 .ldr = .{
13634 .Rt = t.alias.encode(.{ .V = true }),14442 .Rt = t.alias.encode(.{ .V = true }),
13635 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),14443 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),
13636 .S = switch (vs) {14444 .S = switch (vs) {
13637 else => unreachable,
13638 .byte => switch (extended_register_explicit.amount) {14445 .byte => switch (extended_register_explicit.amount) {
13639 0 => false,14446 0 => false,
13640 else => unreachable,14447 else => unreachable,
...@@ -13697,10 +14504,10 @@ pub const Instruction = packed union {...@@ -13697,10 +14504,10 @@ pub const Instruction = packed union {
13697 extend: LoadStore.RegisterRegisterOffset.Extend,14504 extend: LoadStore.RegisterRegisterOffset.Extend,
13698 },14505 },
13699 }) Instruction {14506 }) Instruction {
13700 assert(t.format.integer == .word);14507 assert(t.format.general == .word);
13701 form: switch (form) {14508 form: switch (form) {
13702 .post_index => |post_index| {14509 .post_index => |post_index| {
13703 assert(post_index.base.format.integer == .doubleword);14510 assert(post_index.base.format.general == .doubleword);
13704 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{14511 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
13705 .ldrb = .{14512 .ldrb = .{
13706 .Rt = t.alias.encode(.{}),14513 .Rt = t.alias.encode(.{}),
...@@ -13710,7 +14517,7 @@ pub const Instruction = packed union {...@@ -13710,7 +14517,7 @@ pub const Instruction = packed union {
13710 } } } };14517 } } } };
13711 },14518 },
13712 .pre_index => |pre_index| {14519 .pre_index => |pre_index| {
13713 assert(pre_index.base.format.integer == .doubleword);14520 assert(pre_index.base.format.general == .doubleword);
13714 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14521 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
13715 .ldrb = .{14522 .ldrb = .{
13716 .Rt = t.alias.encode(.{}),14523 .Rt = t.alias.encode(.{}),
...@@ -13720,7 +14527,7 @@ pub const Instruction = packed union {...@@ -13720,7 +14527,7 @@ pub const Instruction = packed union {
13720 } } } };14527 } } } };
13721 },14528 },
13722 .unsigned_offset => |unsigned_offset| {14529 .unsigned_offset => |unsigned_offset| {
13723 assert(unsigned_offset.base.format.integer == .doubleword);14530 assert(unsigned_offset.base.format.general == .doubleword);
13724 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{14531 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
13725 .ldrb = .{14532 .ldrb = .{
13726 .Rt = t.alias.encode(.{}),14533 .Rt = t.alias.encode(.{}),
...@@ -13731,8 +14538,8 @@ pub const Instruction = packed union {...@@ -13731,8 +14538,8 @@ pub const Instruction = packed union {
13731 },14538 },
13732 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },14539 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
13733 .extended_register_explicit => |extended_register_explicit| {14540 .extended_register_explicit => |extended_register_explicit| {
13734 assert(extended_register_explicit.base.format.integer == .doubleword and14541 assert(extended_register_explicit.base.format.general == .doubleword and
13735 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14542 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13736 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14543 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
13737 .ldrb = .{14544 .ldrb = .{
13738 .Rt = t.alias.encode(.{}),14545 .Rt = t.alias.encode(.{}),
...@@ -13775,10 +14582,10 @@ pub const Instruction = packed union {...@@ -13775,10 +14582,10 @@ pub const Instruction = packed union {
13775 extend: LoadStore.RegisterRegisterOffset.Extend,14582 extend: LoadStore.RegisterRegisterOffset.Extend,
13776 },14583 },
13777 }) Instruction {14584 }) Instruction {
13778 assert(t.format.integer == .word);14585 assert(t.format.general == .word);
13779 form: switch (form) {14586 form: switch (form) {
13780 .post_index => |post_index| {14587 .post_index => |post_index| {
13781 assert(post_index.base.format.integer == .doubleword);14588 assert(post_index.base.format.general == .doubleword);
13782 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{14589 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
13783 .ldrh = .{14590 .ldrh = .{
13784 .Rt = t.alias.encode(.{}),14591 .Rt = t.alias.encode(.{}),
...@@ -13788,7 +14595,7 @@ pub const Instruction = packed union {...@@ -13788,7 +14595,7 @@ pub const Instruction = packed union {
13788 } } } };14595 } } } };
13789 },14596 },
13790 .pre_index => |pre_index| {14597 .pre_index => |pre_index| {
13791 assert(pre_index.base.format.integer == .doubleword);14598 assert(pre_index.base.format.general == .doubleword);
13792 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14599 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
13793 .ldrh = .{14600 .ldrh = .{
13794 .Rt = t.alias.encode(.{}),14601 .Rt = t.alias.encode(.{}),
...@@ -13798,7 +14605,7 @@ pub const Instruction = packed union {...@@ -13798,7 +14605,7 @@ pub const Instruction = packed union {
13798 } } } };14605 } } } };
13799 },14606 },
13800 .unsigned_offset => |unsigned_offset| {14607 .unsigned_offset => |unsigned_offset| {
13801 assert(unsigned_offset.base.format.integer == .doubleword);14608 assert(unsigned_offset.base.format.general == .doubleword);
13802 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{14609 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
13803 .ldrh = .{14610 .ldrh = .{
13804 .Rt = t.alias.encode(.{}),14611 .Rt = t.alias.encode(.{}),
...@@ -13809,8 +14616,8 @@ pub const Instruction = packed union {...@@ -13809,8 +14616,8 @@ pub const Instruction = packed union {
13809 },14616 },
13810 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },14617 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
13811 .extended_register_explicit => |extended_register_explicit| {14618 .extended_register_explicit => |extended_register_explicit| {
13812 assert(extended_register_explicit.base.format.integer == .doubleword and14619 assert(extended_register_explicit.base.format.general == .doubleword and
13813 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14620 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13814 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14621 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
13815 .ldrh = .{14622 .ldrh = .{
13816 .Rt = t.alias.encode(.{}),14623 .Rt = t.alias.encode(.{}),
...@@ -13854,10 +14661,10 @@ pub const Instruction = packed union {...@@ -13854,10 +14661,10 @@ pub const Instruction = packed union {
13854 extend: LoadStore.RegisterRegisterOffset.Extend,14661 extend: LoadStore.RegisterRegisterOffset.Extend,
13855 },14662 },
13856 }) Instruction {14663 }) Instruction {
13857 const sf = t.format.integer;14664 const sf = t.format.general;
13858 form: switch (form) {14665 form: switch (form) {
13859 .post_index => |post_index| {14666 .post_index => |post_index| {
13860 assert(post_index.base.format.integer == .doubleword);14667 assert(post_index.base.format.general == .doubleword);
13861 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{14668 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
13862 .ldrsb = .{14669 .ldrsb = .{
13863 .Rt = t.alias.encode(.{}),14670 .Rt = t.alias.encode(.{}),
...@@ -13868,7 +14675,7 @@ pub const Instruction = packed union {...@@ -13868,7 +14675,7 @@ pub const Instruction = packed union {
13868 } } } };14675 } } } };
13869 },14676 },
13870 .pre_index => |pre_index| {14677 .pre_index => |pre_index| {
13871 assert(pre_index.base.format.integer == .doubleword);14678 assert(pre_index.base.format.general == .doubleword);
13872 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14679 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
13873 .ldrsb = .{14680 .ldrsb = .{
13874 .Rt = t.alias.encode(.{}),14681 .Rt = t.alias.encode(.{}),
...@@ -13879,7 +14686,7 @@ pub const Instruction = packed union {...@@ -13879,7 +14686,7 @@ pub const Instruction = packed union {
13879 } } } };14686 } } } };
13880 },14687 },
13881 .unsigned_offset => |unsigned_offset| {14688 .unsigned_offset => |unsigned_offset| {
13882 assert(unsigned_offset.base.format.integer == .doubleword);14689 assert(unsigned_offset.base.format.general == .doubleword);
13883 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{14690 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
13884 .ldrsb = .{14691 .ldrsb = .{
13885 .Rt = t.alias.encode(.{}),14692 .Rt = t.alias.encode(.{}),
...@@ -13891,8 +14698,8 @@ pub const Instruction = packed union {...@@ -13891,8 +14698,8 @@ pub const Instruction = packed union {
13891 },14698 },
13892 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },14699 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
13893 .extended_register_explicit => |extended_register_explicit| {14700 .extended_register_explicit => |extended_register_explicit| {
13894 assert(extended_register_explicit.base.format.integer == .doubleword and14701 assert(extended_register_explicit.base.format.general == .doubleword and
13895 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14702 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13896 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14703 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
13897 .ldrsb = .{14704 .ldrsb = .{
13898 .Rt = t.alias.encode(.{}),14705 .Rt = t.alias.encode(.{}),
...@@ -13936,10 +14743,10 @@ pub const Instruction = packed union {...@@ -13936,10 +14743,10 @@ pub const Instruction = packed union {
13936 extend: LoadStore.RegisterRegisterOffset.Extend,14743 extend: LoadStore.RegisterRegisterOffset.Extend,
13937 },14744 },
13938 }) Instruction {14745 }) Instruction {
13939 const sf = t.format.integer;14746 const sf = t.format.general;
13940 form: switch (form) {14747 form: switch (form) {
13941 .post_index => |post_index| {14748 .post_index => |post_index| {
13942 assert(post_index.base.format.integer == .doubleword);14749 assert(post_index.base.format.general == .doubleword);
13943 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{14750 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
13944 .ldrsh = .{14751 .ldrsh = .{
13945 .Rt = t.alias.encode(.{}),14752 .Rt = t.alias.encode(.{}),
...@@ -13950,7 +14757,7 @@ pub const Instruction = packed union {...@@ -13950,7 +14757,7 @@ pub const Instruction = packed union {
13950 } } } };14757 } } } };
13951 },14758 },
13952 .pre_index => |pre_index| {14759 .pre_index => |pre_index| {
13953 assert(pre_index.base.format.integer == .doubleword);14760 assert(pre_index.base.format.general == .doubleword);
13954 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14761 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
13955 .ldrsh = .{14762 .ldrsh = .{
13956 .Rt = t.alias.encode(.{}),14763 .Rt = t.alias.encode(.{}),
...@@ -13961,7 +14768,7 @@ pub const Instruction = packed union {...@@ -13961,7 +14768,7 @@ pub const Instruction = packed union {
13961 } } } };14768 } } } };
13962 },14769 },
13963 .unsigned_offset => |unsigned_offset| {14770 .unsigned_offset => |unsigned_offset| {
13964 assert(unsigned_offset.base.format.integer == .doubleword);14771 assert(unsigned_offset.base.format.general == .doubleword);
13965 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{14772 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
13966 .ldrsh = .{14773 .ldrsh = .{
13967 .Rt = t.alias.encode(.{}),14774 .Rt = t.alias.encode(.{}),
...@@ -13973,8 +14780,8 @@ pub const Instruction = packed union {...@@ -13973,8 +14780,8 @@ pub const Instruction = packed union {
13973 },14780 },
13974 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },14781 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
13975 .extended_register_explicit => |extended_register_explicit| {14782 .extended_register_explicit => |extended_register_explicit| {
13976 assert(extended_register_explicit.base.format.integer == .doubleword and14783 assert(extended_register_explicit.base.format.general == .doubleword and
13977 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14784 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
13978 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14785 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
13979 .ldrsh = .{14786 .ldrsh = .{
13980 .Rt = t.alias.encode(.{}),14787 .Rt = t.alias.encode(.{}),
...@@ -14012,29 +14819,29 @@ pub const Instruction = packed union {...@@ -14012,29 +14819,29 @@ pub const Instruction = packed union {
14012 extended_register_explicit: struct {14819 extended_register_explicit: struct {
14013 base: Register,14820 base: Register,
14014 index: Register,14821 index: Register,
14015 option: LoadStore.RegisterRegisterOffset.Integer.Option,14822 option: LoadStore.RegisterRegisterOffset.Option,
14016 amount: LoadStore.RegisterRegisterOffset.Integer.Extend.Amount,14823 amount: LoadStore.RegisterRegisterOffset.Extend.Amount,
14017 },14824 },
14018 extended_register: struct {14825 extended_register: struct {
14019 base: Register,14826 base: Register,
14020 index: Register,14827 index: Register,
14021 extend: LoadStore.RegisterRegisterOffset.Integer.Extend,14828 extend: LoadStore.RegisterRegisterOffset.Extend,
14022 },14829 },
14023 }) Instruction {14830 }) Instruction {
14024 assert(t.format.integer == .doubleword);14831 assert(t.format.general == .doubleword);
14025 form: switch (form) {14832 form: switch (form) {
14026 .post_index => |post_index| {14833 .post_index => |post_index| {
14027 assert(post_index.base.format.integer == .doubleword);14834 assert(post_index.base.format.general == .doubleword);
14028 return .{ .load_store = .{ .register_immediate_post_indexed = .{14835 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
14029 .ldrsw = .{14836 .ldrsw = .{
14030 .Rt = t.alias.encode(.{}),14837 .Rt = t.alias.encode(.{}),
14031 .Rn = post_index.base.alias.encode(.{ .sp = true }),14838 .Rn = post_index.base.alias.encode(.{ .sp = true }),
14032 .imm9 = post_index.index,14839 .imm9 = post_index.index,
14033 },14840 },
14034 } } };14841 } } } };
14035 },14842 },
14036 .pre_index => |pre_index| {14843 .pre_index => |pre_index| {
14037 assert(pre_index.base.format.integer == .doubleword);14844 assert(pre_index.base.format.general == .doubleword);
14038 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{14845 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
14039 .ldrsw = .{14846 .ldrsw = .{
14040 .Rt = t.alias.encode(.{}),14847 .Rt = t.alias.encode(.{}),
...@@ -14044,32 +14851,32 @@ pub const Instruction = packed union {...@@ -14044,32 +14851,32 @@ pub const Instruction = packed union {
14044 } } } };14851 } } } };
14045 },14852 },
14046 .unsigned_offset => |unsigned_offset| {14853 .unsigned_offset => |unsigned_offset| {
14047 assert(unsigned_offset.base.format.integer == .doubleword);14854 assert(unsigned_offset.base.format.general == .doubleword);
14048 return .{ .load_store = .{ .register_unsigned_immediate = .{14855 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
14049 .ldrsw = .{14856 .ldrsw = .{
14050 .Rt = t.alias.encode(.{}),14857 .Rt = t.alias.encode(.{}),
14051 .Rn = unsigned_offset.base.alias.encode(.{ .sp = true }),14858 .Rn = unsigned_offset.base.alias.encode(.{ .sp = true }),
14052 .imm12 = @intCast(@shrExact(unsigned_offset.offset, 2)),14859 .imm12 = @intCast(@shrExact(unsigned_offset.offset, 2)),
14053 },14860 },
14054 } } };14861 } } } };
14055 },14862 },
14056 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },14863 .base => |base| continue :form .{ .unsigned_offset = .{ .base = base } },
14057 .literal => |offset| return .{ .load_store = .{ .register_literal = .{14864 .literal => |offset| return .{ .load_store = .{ .register_literal = .{ .integer = .{
14058 .ldrsw = .{14865 .ldrsw = .{
14059 .Rt = t.alias.encode(.{}),14866 .Rt = t.alias.encode(.{}),
14060 .imm19 = @intCast(@shrExact(offset, 2)),14867 .imm19 = @intCast(@shrExact(offset, 2)),
14061 },14868 },
14062 } } },14869 } } } },
14063 .extended_register_explicit => |extended_register_explicit| {14870 .extended_register_explicit => |extended_register_explicit| {
14064 assert(extended_register_explicit.base.format.integer == .doubleword and14871 assert(extended_register_explicit.base.format.general == .doubleword and
14065 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());14872 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
14066 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{14873 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
14067 .ldrsw = .{14874 .ldrsw = .{
14068 .Rt = t.alias.encode(.{}),14875 .Rt = t.alias.encode(.{}),
14069 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),14876 .Rn = extended_register_explicit.base.alias.encode(.{ .sp = true }),
14070 .S = switch (extended_register_explicit.amount) {14877 .S = switch (extended_register_explicit.amount) {
14071 0 => 0b0,14878 0 => false,
14072 2 => 0b1,14879 2 => true,
14073 else => unreachable,14880 else => unreachable,
14074 },14881 },
14075 .option = extended_register_explicit.option,14882 .option = extended_register_explicit.option,
...@@ -14090,10 +14897,10 @@ pub const Instruction = packed union {...@@ -14090,10 +14897,10 @@ pub const Instruction = packed union {
14090 /// C6.2.202 LDUR14897 /// C6.2.202 LDUR
14091 /// C7.2.194 LDUR (SIMD&FP)14898 /// C7.2.194 LDUR (SIMD&FP)
14092 pub fn ldur(t: Register, n: Register, simm: i9) Instruction {14899 pub fn ldur(t: Register, n: Register, simm: i9) Instruction {
14093 assert(n.format.integer == .doubleword);14900 assert(n.format.general == .doubleword);
14094 switch (t.format) {14901 switch (t.format) {
14095 else => unreachable,14902 else => unreachable,
14096 .integer => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14903 .general => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14097 .ldur = .{14904 .ldur = .{
14098 .Rt = t.alias.encode(.{}),14905 .Rt = t.alias.encode(.{}),
14099 .Rn = n.alias.encode(.{ .sp = true }),14906 .Rn = n.alias.encode(.{ .sp = true }),
...@@ -14114,7 +14921,7 @@ pub const Instruction = packed union {...@@ -14114,7 +14921,7 @@ pub const Instruction = packed union {
14114 }14921 }
14115 /// C6.2.203 LDURB14922 /// C6.2.203 LDURB
14116 pub fn ldurb(t: Register, n: Register, simm: i9) Instruction {14923 pub fn ldurb(t: Register, n: Register, simm: i9) Instruction {
14117 assert(t.format.integer == .word and n.format.integer == .doubleword);14924 assert(t.format.general == .word and n.format.general == .doubleword);
14118 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14925 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14119 .ldurb = .{14926 .ldurb = .{
14120 .Rt = t.alias.encode(.{}),14927 .Rt = t.alias.encode(.{}),
...@@ -14125,7 +14932,7 @@ pub const Instruction = packed union {...@@ -14125,7 +14932,7 @@ pub const Instruction = packed union {
14125 }14932 }
14126 /// C6.2.204 LDURH14933 /// C6.2.204 LDURH
14127 pub fn ldurh(t: Register, n: Register, simm: i9) Instruction {14934 pub fn ldurh(t: Register, n: Register, simm: i9) Instruction {
14128 assert(t.format.integer == .word and n.format.integer == .doubleword);14935 assert(t.format.general == .word and n.format.general == .doubleword);
14129 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14936 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14130 .ldurh = .{14937 .ldurh = .{
14131 .Rt = t.alias.encode(.{}),14938 .Rt = t.alias.encode(.{}),
...@@ -14136,31 +14943,31 @@ pub const Instruction = packed union {...@@ -14136,31 +14943,31 @@ pub const Instruction = packed union {
14136 }14943 }
14137 /// C6.2.205 LDURSB14944 /// C6.2.205 LDURSB
14138 pub fn ldursb(t: Register, n: Register, simm: i9) Instruction {14945 pub fn ldursb(t: Register, n: Register, simm: i9) Instruction {
14139 assert(n.format.integer == .doubleword);14946 assert(n.format.general == .doubleword);
14140 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14947 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14141 .ldursb = .{14948 .ldursb = .{
14142 .Rt = t.alias.encode(.{}),14949 .Rt = t.alias.encode(.{}),
14143 .Rn = n.alias.encode(.{ .sp = true }),14950 .Rn = n.alias.encode(.{ .sp = true }),
14144 .imm9 = simm,14951 .imm9 = simm,
14145 .opc0 = ~@intFromEnum(t.format.integer),14952 .opc0 = ~@intFromEnum(t.format.general),
14146 },14953 },
14147 } } } };14954 } } } };
14148 }14955 }
14149 /// C6.2.206 LDURSH14956 /// C6.2.206 LDURSH
14150 pub fn ldursh(t: Register, n: Register, simm: i9) Instruction {14957 pub fn ldursh(t: Register, n: Register, simm: i9) Instruction {
14151 assert(n.format.integer == .doubleword);14958 assert(n.format.general == .doubleword);
14152 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14959 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14153 .ldursh = .{14960 .ldursh = .{
14154 .Rt = t.alias.encode(.{}),14961 .Rt = t.alias.encode(.{}),
14155 .Rn = n.alias.encode(.{ .sp = true }),14962 .Rn = n.alias.encode(.{ .sp = true }),
14156 .imm9 = simm,14963 .imm9 = simm,
14157 .opc0 = ~@intFromEnum(t.format.integer),14964 .opc0 = ~@intFromEnum(t.format.general),
14158 },14965 },
14159 } } } };14966 } } } };
14160 }14967 }
14161 /// C6.2.207 LDURSW14968 /// C6.2.207 LDURSW
14162 pub fn ldursw(t: Register, n: Register, simm: i9) Instruction {14969 pub fn ldursw(t: Register, n: Register, simm: i9) Instruction {
14163 assert(t.format.integer == .doubleword and n.format.integer == .doubleword);14970 assert(t.format.general == .doubleword and n.format.general == .doubleword);
14164 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{14971 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
14165 .ldursw = .{14972 .ldursw = .{
14166 .Rt = t.alias.encode(.{}),14973 .Rt = t.alias.encode(.{}),
...@@ -14171,8 +14978,8 @@ pub const Instruction = packed union {...@@ -14171,8 +14978,8 @@ pub const Instruction = packed union {
14171 }14978 }
14172 /// C6.2.214 LSLV14979 /// C6.2.214 LSLV
14173 pub fn lslv(d: Register, n: Register, m: Register) Instruction {14980 pub fn lslv(d: Register, n: Register, m: Register) Instruction {
14174 const sf = d.format.integer;14981 const sf = d.format.general;
14175 assert(n.format.integer == sf and m.format.integer == sf);14982 assert(n.format.general == sf and m.format.general == sf);
14176 return .{ .data_processing_register = .{ .data_processing_two_source = .{14983 return .{ .data_processing_register = .{ .data_processing_two_source = .{
14177 .lslv = .{14984 .lslv = .{
14178 .Rd = d.alias.encode(.{}),14985 .Rd = d.alias.encode(.{}),
...@@ -14184,8 +14991,8 @@ pub const Instruction = packed union {...@@ -14184,8 +14991,8 @@ pub const Instruction = packed union {
14184 }14991 }
14185 /// C6.2.217 LSRV14992 /// C6.2.217 LSRV
14186 pub fn lsrv(d: Register, n: Register, m: Register) Instruction {14993 pub fn lsrv(d: Register, n: Register, m: Register) Instruction {
14187 const sf = d.format.integer;14994 const sf = d.format.general;
14188 assert(n.format.integer == sf and m.format.integer == sf);14995 assert(n.format.general == sf and m.format.general == sf);
14189 return .{ .data_processing_register = .{ .data_processing_two_source = .{14996 return .{ .data_processing_register = .{ .data_processing_two_source = .{
14190 .lsrv = .{14997 .lsrv = .{
14191 .Rd = d.alias.encode(.{}),14998 .Rd = d.alias.encode(.{}),
...@@ -14197,8 +15004,8 @@ pub const Instruction = packed union {...@@ -14197,8 +15004,8 @@ pub const Instruction = packed union {
14197 }15004 }
14198 /// C6.2.218 MADD15005 /// C6.2.218 MADD
14199 pub fn madd(d: Register, n: Register, m: Register, a: Register) Instruction {15006 pub fn madd(d: Register, n: Register, m: Register, a: Register) Instruction {
14200 const sf = d.format.integer;15007 const sf = d.format.general;
14201 assert(n.format.integer == sf and m.format.integer == sf and a.format.integer == sf);15008 assert(n.format.general == sf and m.format.general == sf and a.format.general == sf);
14202 return .{ .data_processing_register = .{ .data_processing_three_source = .{15009 return .{ .data_processing_register = .{ .data_processing_three_source = .{
14203 .madd = .{15010 .madd = .{
14204 .Rd = d.alias.encode(.{}),15011 .Rd = d.alias.encode(.{}),
...@@ -14261,7 +15068,7 @@ pub const Instruction = packed union {...@@ -14261,7 +15068,7 @@ pub const Instruction = packed union {
14261 imm: u16,15068 imm: u16,
14262 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },15069 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
14263 ) Instruction {15070 ) Instruction {
14264 const sf = d.format.integer;15071 const sf = d.format.general;
14265 assert(sf == .doubleword or shift.lsl.sf() == .word);15072 assert(sf == .doubleword or shift.lsl.sf() == .word);
14266 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{15073 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
14267 .movk = .{15074 .movk = .{
...@@ -14278,7 +15085,7 @@ pub const Instruction = packed union {...@@ -14278,7 +15085,7 @@ pub const Instruction = packed union {
14278 imm: u16,15085 imm: u16,
14279 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },15086 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
14280 ) Instruction {15087 ) Instruction {
14281 const sf = d.format.integer;15088 const sf = d.format.general;
14282 assert(sf == .doubleword or shift.lsl.sf() == .word);15089 assert(sf == .doubleword or shift.lsl.sf() == .word);
14283 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{15090 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
14284 .movn = .{15091 .movn = .{
...@@ -14295,7 +15102,7 @@ pub const Instruction = packed union {...@@ -14295,7 +15102,7 @@ pub const Instruction = packed union {
14295 imm: u16,15102 imm: u16,
14296 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },15103 shift: struct { lsl: DataProcessingImmediate.MoveWideImmediate.Hw = .@"0" },
14297 ) Instruction {15104 ) Instruction {
14298 const sf = d.format.integer;15105 const sf = d.format.general;
14299 assert(sf == .doubleword or shift.lsl.sf() == .word);15106 assert(sf == .doubleword or shift.lsl.sf() == .word);
14300 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{15107 return .{ .data_processing_immediate = .{ .move_wide_immediate = .{
14301 .movz = .{15108 .movz = .{
...@@ -14308,7 +15115,7 @@ pub const Instruction = packed union {...@@ -14308,7 +15115,7 @@ pub const Instruction = packed union {
14308 }15115 }
14309 /// C6.2.228 MRS15116 /// C6.2.228 MRS
14310 pub fn mrs(t: Register, systemreg: Register.System) Instruction {15117 pub fn mrs(t: Register, systemreg: Register.System) Instruction {
14311 assert(t.format.integer == .doubleword and systemreg.op0 >= 0b10);15118 assert(t.format.general == .doubleword and systemreg.op0 >= 0b10);
14312 return .{ .branch_exception_generating_system = .{ .system_register_move = .{15119 return .{ .branch_exception_generating_system = .{ .system_register_move = .{
14313 .mrs = .{15120 .mrs = .{
14314 .Rt = t.alias.encode(.{}),15121 .Rt = t.alias.encode(.{}),
...@@ -14318,7 +15125,7 @@ pub const Instruction = packed union {...@@ -14318,7 +15125,7 @@ pub const Instruction = packed union {
14318 }15125 }
14319 /// C6.2.230 MSR (register)15126 /// C6.2.230 MSR (register)
14320 pub fn msr(systemreg: Register.System, t: Register) Instruction {15127 pub fn msr(systemreg: Register.System, t: Register) Instruction {
14321 assert(systemreg.op0 >= 0b10 and t.format.integer == .doubleword);15128 assert(systemreg.op0 >= 0b10 and t.format.general == .doubleword);
14322 return .{ .branch_exception_generating_system = .{ .system_register_move = .{15129 return .{ .branch_exception_generating_system = .{ .system_register_move = .{
14323 .msr = .{15130 .msr = .{
14324 .Rt = t.alias.encode(.{}),15131 .Rt = t.alias.encode(.{}),
...@@ -14328,8 +15135,8 @@ pub const Instruction = packed union {...@@ -14328,8 +15135,8 @@ pub const Instruction = packed union {
14328 }15135 }
14329 /// C6.2.231 MSUB15136 /// C6.2.231 MSUB
14330 pub fn msub(d: Register, n: Register, m: Register, a: Register) Instruction {15137 pub fn msub(d: Register, n: Register, m: Register, a: Register) Instruction {
14331 const sf = d.format.integer;15138 const sf = d.format.general;
14332 assert(n.format.integer == sf and m.format.integer == sf and a.format.integer == sf);15139 assert(n.format.general == sf and m.format.general == sf and a.format.general == sf);
14333 return .{ .data_processing_register = .{ .data_processing_three_source = .{15140 return .{ .data_processing_register = .{ .data_processing_three_source = .{
14334 .msub = .{15141 .msub = .{
14335 .Rd = d.alias.encode(.{}),15142 .Rd = d.alias.encode(.{}),
...@@ -14350,7 +15157,7 @@ pub const Instruction = packed union {...@@ -14350,7 +15157,7 @@ pub const Instruction = packed union {
14350 .neg = .{15157 .neg = .{
14351 .Rd = d.alias.encode(.{ .V = true }),15158 .Rd = d.alias.encode(.{ .V = true }),
14352 .Rn = n.alias.encode(.{ .V = true }),15159 .Rn = n.alias.encode(.{ .V = true }),
14353 .size = .fromVectorSize(elem_size),15160 .size = .fromScalarSize(elem_size),
14354 },15161 },
14355 } } };15162 } } };
14356 },15163 },
...@@ -14395,12 +15202,12 @@ pub const Instruction = packed union {...@@ -14395,12 +15202,12 @@ pub const Instruction = packed union {
14395 }) Instruction {15202 }) Instruction {
14396 switch (d.format) {15203 switch (d.format) {
14397 else => unreachable,15204 else => unreachable,
14398 .integer => |sf| {15205 .general => |sf| {
14399 assert(n.format.integer == sf);15206 assert(n.format.general == sf);
14400 form: switch (form) {15207 form: switch (form) {
14401 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },15208 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
14402 .shifted_register_explicit => |shifted_register_explicit| {15209 .shifted_register_explicit => |shifted_register_explicit| {
14403 assert(shifted_register_explicit.register.format.integer == sf);15210 assert(shifted_register_explicit.register.format.general == sf);
14404 return .{ .data_processing_register = .{ .logical_shifted_register = .{15211 return .{ .data_processing_register = .{ .logical_shifted_register = .{
14405 .orn = .{15212 .orn = .{
14406 .Rd = d.alias.encode(.{}),15213 .Rd = d.alias.encode(.{}),
...@@ -14451,8 +15258,8 @@ pub const Instruction = packed union {...@@ -14451,8 +15258,8 @@ pub const Instruction = packed union {
14451 }) Instruction {15258 }) Instruction {
14452 switch (d.format) {15259 switch (d.format) {
14453 else => unreachable,15260 else => unreachable,
14454 .integer => |sf| {15261 .general => |sf| {
14455 assert(n.format.integer == sf);15262 assert(n.format.general == sf);
14456 form: switch (form) {15263 form: switch (form) {
14457 .immediate => |bitmask| {15264 .immediate => |bitmask| {
14458 assert(bitmask.validImmediate(sf));15265 assert(bitmask.validImmediate(sf));
...@@ -14468,7 +15275,7 @@ pub const Instruction = packed union {...@@ -14468,7 +15275,7 @@ pub const Instruction = packed union {
14468 .shifted_immediate => unreachable,15275 .shifted_immediate => unreachable,
14469 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },15276 .register => |register| continue :form .{ .shifted_register = .{ .register = register } },
14470 .shifted_register_explicit => |shifted_register_explicit| {15277 .shifted_register_explicit => |shifted_register_explicit| {
14471 assert(shifted_register_explicit.register.format.integer == sf);15278 assert(shifted_register_explicit.register.format.general == sf);
14472 return .{ .data_processing_register = .{ .logical_shifted_register = .{15279 return .{ .data_processing_register = .{ .logical_shifted_register = .{
14473 .orr = .{15280 .orr = .{
14474 .Rd = d.alias.encode(.{}),15281 .Rd = d.alias.encode(.{}),
...@@ -14547,7 +15354,7 @@ pub const Instruction = packed union {...@@ -14547,7 +15354,7 @@ pub const Instruction = packed union {
14547 }) Instruction {15354 }) Instruction {
14548 form: switch (form) {15355 form: switch (form) {
14549 .unsigned_offset => |unsigned_offset| {15356 .unsigned_offset => |unsigned_offset| {
14550 assert(unsigned_offset.base.format.integer == .doubleword);15357 assert(unsigned_offset.base.format.general == .doubleword);
14551 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{15358 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
14552 .prfm = .{15359 .prfm = .{
14553 .prfop = prfop,15360 .prfop = prfop,
...@@ -14564,8 +15371,8 @@ pub const Instruction = packed union {...@@ -14564,8 +15371,8 @@ pub const Instruction = packed union {
14564 },15371 },
14565 } } } },15372 } } } },
14566 .extended_register_explicit => |extended_register_explicit| {15373 .extended_register_explicit => |extended_register_explicit| {
14567 assert(extended_register_explicit.base.format.integer == .doubleword and15374 assert(extended_register_explicit.base.format.general == .doubleword and
14568 extended_register_explicit.index.format.integer == extended_register_explicit.option.sf());15375 extended_register_explicit.index.format.general == extended_register_explicit.option.sf());
14569 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{15376 return .{ .load_store = .{ .register_register_offset = .{ .integer = .{
14570 .prfm = .{15377 .prfm = .{
14571 .prfop = prfop,15378 .prfop = prfop,
...@@ -14592,8 +15399,8 @@ pub const Instruction = packed union {...@@ -14592,8 +15399,8 @@ pub const Instruction = packed union {
14592 }15399 }
14593 /// C6.2.253 RBIT15400 /// C6.2.253 RBIT
14594 pub fn rbit(d: Register, n: Register) Instruction {15401 pub fn rbit(d: Register, n: Register) Instruction {
14595 const sf = d.format.integer;15402 const sf = d.format.general;
14596 assert(n.format.integer == sf);15403 assert(n.format.general == sf);
14597 return .{ .data_processing_register = .{ .data_processing_one_source = .{15404 return .{ .data_processing_register = .{ .data_processing_one_source = .{
14598 .rbit = .{15405 .rbit = .{
14599 .Rd = d.alias.encode(.{}),15406 .Rd = d.alias.encode(.{}),
...@@ -14604,15 +15411,15 @@ pub const Instruction = packed union {...@@ -14604,15 +15411,15 @@ pub const Instruction = packed union {
14604 }15411 }
14605 /// C6.2.254 RET15412 /// C6.2.254 RET
14606 pub fn ret(n: Register) Instruction {15413 pub fn ret(n: Register) Instruction {
14607 assert(n.format.integer == .doubleword);15414 assert(n.format.general == .doubleword);
14608 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{15415 return .{ .branch_exception_generating_system = .{ .unconditional_branch_register = .{
14609 .ret = .{ .Rn = n.alias.encode(.{}) },15416 .ret = .{ .Rn = n.alias.encode(.{}) },
14610 } } };15417 } } };
14611 }15418 }
14612 /// C6.2.256 REV15419 /// C6.2.256 REV
14613 pub fn rev(d: Register, n: Register) Instruction {15420 pub fn rev(d: Register, n: Register) Instruction {
14614 const sf = d.format.integer;15421 const sf = d.format.general;
14615 assert(n.format.integer == sf);15422 assert(n.format.general == sf);
14616 return .{ .data_processing_register = .{ .data_processing_one_source = .{15423 return .{ .data_processing_register = .{ .data_processing_one_source = .{
14617 .rev = .{15424 .rev = .{
14618 .Rd = d.alias.encode(.{}),15425 .Rd = d.alias.encode(.{}),
...@@ -14624,8 +15431,8 @@ pub const Instruction = packed union {...@@ -14624,8 +15431,8 @@ pub const Instruction = packed union {
14624 }15431 }
14625 /// C6.2.257 REV1615432 /// C6.2.257 REV16
14626 pub fn rev16(d: Register, n: Register) Instruction {15433 pub fn rev16(d: Register, n: Register) Instruction {
14627 const sf = d.format.integer;15434 const sf = d.format.general;
14628 assert(n.format.integer == sf);15435 assert(n.format.general == sf);
14629 return .{ .data_processing_register = .{ .data_processing_one_source = .{15436 return .{ .data_processing_register = .{ .data_processing_one_source = .{
14630 .rev16 = .{15437 .rev16 = .{
14631 .Rd = d.alias.encode(.{}),15438 .Rd = d.alias.encode(.{}),
...@@ -14636,7 +15443,7 @@ pub const Instruction = packed union {...@@ -14636,7 +15443,7 @@ pub const Instruction = packed union {
14636 }15443 }
14637 /// C6.2.258 REV3215444 /// C6.2.258 REV32
14638 pub fn rev32(d: Register, n: Register) Instruction {15445 pub fn rev32(d: Register, n: Register) Instruction {
14639 assert(d.format.integer == .doubleword and n.format.integer == .doubleword);15446 assert(d.format.general == .doubleword and n.format.general == .doubleword);
14640 return .{ .data_processing_register = .{ .data_processing_one_source = .{15447 return .{ .data_processing_register = .{ .data_processing_one_source = .{
14641 .rev32 = .{15448 .rev32 = .{
14642 .Rd = d.alias.encode(.{}),15449 .Rd = d.alias.encode(.{}),
...@@ -14646,8 +15453,8 @@ pub const Instruction = packed union {...@@ -14646,8 +15453,8 @@ pub const Instruction = packed union {
14646 }15453 }
14647 /// C6.2.263 RORV15454 /// C6.2.263 RORV
14648 pub fn rorv(d: Register, n: Register, m: Register) Instruction {15455 pub fn rorv(d: Register, n: Register, m: Register) Instruction {
14649 const sf = d.format.integer;15456 const sf = d.format.general;
14650 assert(n.format.integer == sf and m.format.integer == sf);15457 assert(n.format.general == sf and m.format.general == sf);
14651 return .{ .data_processing_register = .{ .data_processing_two_source = .{15458 return .{ .data_processing_register = .{ .data_processing_two_source = .{
14652 .rorv = .{15459 .rorv = .{
14653 .Rd = d.alias.encode(.{}),15460 .Rd = d.alias.encode(.{}),
...@@ -14665,8 +15472,8 @@ pub const Instruction = packed union {...@@ -14665,8 +15472,8 @@ pub const Instruction = packed union {
14665 }15472 }
14666 /// C6.2.265 SBC15473 /// C6.2.265 SBC
14667 pub fn sbc(d: Register, n: Register, m: Register) Instruction {15474 pub fn sbc(d: Register, n: Register, m: Register) Instruction {
14668 const sf = d.format.integer;15475 const sf = d.format.general;
14669 assert(n.format.integer == sf and m.format.integer == sf);15476 assert(n.format.general == sf and m.format.general == sf);
14670 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{15477 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
14671 .sbc = .{15478 .sbc = .{
14672 .Rd = d.alias.encode(.{}),15479 .Rd = d.alias.encode(.{}),
...@@ -14678,8 +15485,8 @@ pub const Instruction = packed union {...@@ -14678,8 +15485,8 @@ pub const Instruction = packed union {
14678 }15485 }
14679 /// C6.2.266 SBCS15486 /// C6.2.266 SBCS
14680 pub fn sbcs(d: Register, n: Register, m: Register) Instruction {15487 pub fn sbcs(d: Register, n: Register, m: Register) Instruction {
14681 const sf = d.format.integer;15488 const sf = d.format.general;
14682 assert(n.format.integer == sf and m.format.integer == sf);15489 assert(n.format.general == sf and m.format.general == sf);
14683 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{15490 return .{ .data_processing_register = .{ .add_subtract_with_carry = .{
14684 .sbcs = .{15491 .sbcs = .{
14685 .Rd = d.alias.encode(.{}),15492 .Rd = d.alias.encode(.{}),
...@@ -14691,8 +15498,8 @@ pub const Instruction = packed union {...@@ -14691,8 +15498,8 @@ pub const Instruction = packed union {
14691 }15498 }
14692 /// C6.2.268 SBFM15499 /// C6.2.268 SBFM
14693 pub fn sbfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {15500 pub fn sbfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
14694 const sf = d.format.integer;15501 const sf = d.format.general;
14695 assert(n.format.integer == sf and bitmask.validBitfield(sf));15502 assert(n.format.general == sf and bitmask.validBitfield(sf));
14696 return .{ .data_processing_immediate = .{ .bitfield = .{15503 return .{ .data_processing_immediate = .{ .bitfield = .{
14697 .sbfm = .{15504 .sbfm = .{
14698 .Rd = d.alias.encode(.{}),15505 .Rd = d.alias.encode(.{}),
...@@ -14723,16 +15530,16 @@ pub const Instruction = packed union {...@@ -14723,16 +15530,16 @@ pub const Instruction = packed union {
14723 .scvtf = .{15530 .scvtf = .{
14724 .Rd = d.alias.encode(.{ .V = true }),15531 .Rd = d.alias.encode(.{ .V = true }),
14725 .Rn = n.alias.encode(.{ .V = true }),15532 .Rn = n.alias.encode(.{ .V = true }),
14726 .sz = .fromVectorSize(ftype),15533 .sz = .fromScalarSize(ftype),
14727 },15534 },
14728 } } },15535 } } },
14729 }15536 }
14730 },15537 },
14731 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{15538 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
14732 .scvtf = .{15539 .scvtf = .{
14733 .Rd = d.alias.encode(.{ .V = true }),15540 .Rd = d.alias.encode(.{ .V = true }),
14734 .Rn = n.alias.encode(.{}),15541 .Rn = n.alias.encode(.{}),
14735 .ftype = .fromVectorSize(ftype),15542 .ftype = .fromScalarSize(ftype),
14736 .sf = sf,15543 .sf = sf,
14737 },15544 },
14738 } } },15545 } } },
...@@ -14762,8 +15569,8 @@ pub const Instruction = packed union {...@@ -14762,8 +15569,8 @@ pub const Instruction = packed union {
14762 }15569 }
14763 /// C6.2.270 SDIV15570 /// C6.2.270 SDIV
14764 pub fn sdiv(d: Register, n: Register, m: Register) Instruction {15571 pub fn sdiv(d: Register, n: Register, m: Register) Instruction {
14765 const sf = d.format.integer;15572 const sf = d.format.general;
14766 assert(n.format.integer == sf and m.format.integer == sf);15573 assert(n.format.general == sf and m.format.general == sf);
14767 return .{ .data_processing_register = .{ .data_processing_two_source = .{15574 return .{ .data_processing_register = .{ .data_processing_two_source = .{
14768 .sdiv = .{15575 .sdiv = .{
14769 .Rd = d.alias.encode(.{}),15576 .Rd = d.alias.encode(.{}),
...@@ -14787,7 +15594,7 @@ pub const Instruction = packed union {...@@ -14787,7 +15594,7 @@ pub const Instruction = packed union {
14787 }15594 }
14788 /// C6.2.282 SMADDL15595 /// C6.2.282 SMADDL
14789 pub fn smaddl(d: Register, n: Register, m: Register, a: Register) Instruction {15596 pub fn smaddl(d: Register, n: Register, m: Register, a: Register) Instruction {
14790 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);15597 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
14791 return .{ .data_processing_register = .{ .data_processing_three_source = .{15598 return .{ .data_processing_register = .{ .data_processing_three_source = .{
14792 .smaddl = .{15599 .smaddl = .{
14793 .Rd = d.alias.encode(.{}),15600 .Rd = d.alias.encode(.{}),
...@@ -14805,7 +15612,7 @@ pub const Instruction = packed union {...@@ -14805,7 +15612,7 @@ pub const Instruction = packed union {
14805 }15612 }
14806 /// C7.2.279 SMOV15613 /// C7.2.279 SMOV
14807 pub fn smov(d: Register, n: Register) Instruction {15614 pub fn smov(d: Register, n: Register) Instruction {
14808 const sf = d.format.integer;15615 const sf = d.format.general;
14809 const vs = n.format.element.size;15616 const vs = n.format.element.size;
14810 switch (vs) {15617 switch (vs) {
14811 else => unreachable,15618 else => unreachable,
...@@ -14828,7 +15635,7 @@ pub const Instruction = packed union {...@@ -14828,7 +15635,7 @@ pub const Instruction = packed union {
14828 }15635 }
14829 /// C6.2.287 SMSUBL15636 /// C6.2.287 SMSUBL
14830 pub fn smsubl(d: Register, n: Register, m: Register, a: Register) Instruction {15637 pub fn smsubl(d: Register, n: Register, m: Register, a: Register) Instruction {
14831 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);15638 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
14832 return .{ .data_processing_register = .{ .data_processing_three_source = .{15639 return .{ .data_processing_register = .{ .data_processing_three_source = .{
14833 .smsubl = .{15640 .smsubl = .{
14834 .Rd = d.alias.encode(.{}),15641 .Rd = d.alias.encode(.{}),
...@@ -14840,7 +15647,7 @@ pub const Instruction = packed union {...@@ -14840,7 +15647,7 @@ pub const Instruction = packed union {
14840 }15647 }
14841 /// C6.2.288 SMULH15648 /// C6.2.288 SMULH
14842 pub fn smulh(d: Register, n: Register, m: Register) Instruction {15649 pub fn smulh(d: Register, n: Register, m: Register) Instruction {
14843 assert(d.format.integer == .doubleword and n.format.integer == .doubleword and m.format.integer == .doubleword);15650 assert(d.format.general == .doubleword and n.format.general == .doubleword and m.format.general == .doubleword);
14844 return .{ .data_processing_register = .{ .data_processing_three_source = .{15651 return .{ .data_processing_register = .{ .data_processing_three_source = .{
14845 .smulh = .{15652 .smulh = .{
14846 .Rd = d.alias.encode(.{}),15653 .Rd = d.alias.encode(.{}),
...@@ -14859,7 +15666,7 @@ pub const Instruction = packed union {...@@ -14859,7 +15666,7 @@ pub const Instruction = packed union {
14859 .sqabs = .{15666 .sqabs = .{
14860 .Rd = d.alias.encode(.{ .V = true }),15667 .Rd = d.alias.encode(.{ .V = true }),
14861 .Rn = n.alias.encode(.{ .V = true }),15668 .Rn = n.alias.encode(.{ .V = true }),
14862 .size = .fromVectorSize(elem_size),15669 .size = .fromScalarSize(elem_size),
14863 },15670 },
14864 } } };15671 } } };
14865 },15672 },
...@@ -14881,17 +15688,17 @@ pub const Instruction = packed union {...@@ -14881,17 +15688,17 @@ pub const Instruction = packed union {
14881 switch (d.format) {15688 switch (d.format) {
14882 else => unreachable,15689 else => unreachable,
14883 .scalar => |elem_size| {15690 .scalar => |elem_size| {
14884 assert(elem_size == n.format.scalar);15691 assert(elem_size == n.format.scalar.n());
14885 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{15692 return .{ .data_processing_vector = .{ .simd_scalar_two_register_miscellaneous = .{
14886 .sqxtn = .{15693 .sqxtn = .{
14887 .Rd = d.alias.encode(.{ .V = true }),15694 .Rd = d.alias.encode(.{ .V = true }),
14888 .Rn = n.alias.encode(.{ .V = true }),15695 .Rn = n.alias.encode(.{ .V = true }),
14889 .size = .fromVectorSize(elem_size),15696 .size = .fromScalarSize(elem_size),
14890 },15697 },
14891 } } };15698 } } };
14892 },15699 },
14893 .vector => |arrangement| {15700 .vector => |arrangement| {
14894 assert(arrangement != .@"1d" and n.format.vector == arrangement);15701 assert(arrangement.len() == n.format.vector.len() and arrangement.elemSize() == n.format.vector.elemSize().n());
14895 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{15702 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
14896 .sqxtn = .{15703 .sqxtn = .{
14897 .Rd = d.alias.encode(.{ .V = true }),15704 .Rd = d.alias.encode(.{ .V = true }),
...@@ -14903,6 +15710,19 @@ pub const Instruction = packed union {...@@ -14903,6 +15710,19 @@ pub const Instruction = packed union {
14903 },15710 },
14904 }15711 }
14905 }15712 }
15713 /// C7.2.308 SQXTN2
15714 pub fn sqxtn2(d: Register, n: Register) Instruction {
15715 const arrangement = d.format.vector;
15716 assert(arrangement.len() == n.format.vector.len() * 2 and arrangement.elemSize() == n.format.vector.elemSize().n());
15717 return .{ .data_processing_vector = .{ .simd_two_register_miscellaneous = .{
15718 .sqxtn = .{
15719 .Rd = d.alias.encode(.{ .V = true }),
15720 .Rn = n.alias.encode(.{ .V = true }),
15721 .size = arrangement.elemSize(),
15722 .Q = arrangement.size(),
15723 },
15724 } } };
15725 }
14906 /// C6.2.321 STP15726 /// C6.2.321 STP
14907 /// C7.2.330 STP (SIMD&FP)15727 /// C7.2.330 STP (SIMD&FP)
14908 pub fn stp(t1: Register, t2: Register, form: union(enum) {15728 pub fn stp(t1: Register, t2: Register, form: union(enum) {
...@@ -14913,11 +15733,11 @@ pub const Instruction = packed union {...@@ -14913,11 +15733,11 @@ pub const Instruction = packed union {
14913 }) Instruction {15733 }) Instruction {
14914 switch (t1.format) {15734 switch (t1.format) {
14915 else => unreachable,15735 else => unreachable,
14916 .integer => |sf| {15736 .general => |sf| {
14917 assert(t2.format.integer == sf);15737 assert(t2.format.general == sf);
14918 form: switch (form) {15738 form: switch (form) {
14919 .post_index => |post_index| {15739 .post_index => |post_index| {
14920 assert(post_index.base.format.integer == .doubleword);15740 assert(post_index.base.format.general == .doubleword);
14921 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{15741 return .{ .load_store = .{ .register_pair_post_indexed = .{ .integer = .{
14922 .stp = .{15742 .stp = .{
14923 .Rt = t1.alias.encode(.{}),15743 .Rt = t1.alias.encode(.{}),
...@@ -14929,7 +15749,7 @@ pub const Instruction = packed union {...@@ -14929,7 +15749,7 @@ pub const Instruction = packed union {
14929 } } } };15749 } } } };
14930 },15750 },
14931 .pre_index => |pre_index| {15751 .pre_index => |pre_index| {
14932 assert(pre_index.base.format.integer == .doubleword);15752 assert(pre_index.base.format.general == .doubleword);
14933 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{15753 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .integer = .{
14934 .stp = .{15754 .stp = .{
14935 .Rt = t1.alias.encode(.{}),15755 .Rt = t1.alias.encode(.{}),
...@@ -14941,7 +15761,7 @@ pub const Instruction = packed union {...@@ -14941,7 +15761,7 @@ pub const Instruction = packed union {
14941 } } } };15761 } } } };
14942 },15762 },
14943 .signed_offset => |signed_offset| {15763 .signed_offset => |signed_offset| {
14944 assert(signed_offset.base.format.integer == .doubleword);15764 assert(signed_offset.base.format.general == .doubleword);
14945 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{15765 return .{ .load_store = .{ .register_pair_offset = .{ .integer = .{
14946 .stp = .{15766 .stp = .{
14947 .Rt = t1.alias.encode(.{}),15767 .Rt = t1.alias.encode(.{}),
...@@ -14959,7 +15779,7 @@ pub const Instruction = packed union {...@@ -14959,7 +15779,7 @@ pub const Instruction = packed union {
14959 assert(t2.format.scalar == vs);15779 assert(t2.format.scalar == vs);
14960 form: switch (form) {15780 form: switch (form) {
14961 .post_index => |post_index| {15781 .post_index => |post_index| {
14962 assert(post_index.base.format.integer == .doubleword);15782 assert(post_index.base.format.general == .doubleword);
14963 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{15783 return .{ .load_store = .{ .register_pair_post_indexed = .{ .vector = .{
14964 .stp = .{15784 .stp = .{
14965 .Rt = t1.alias.encode(.{ .V = true }),15785 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -14971,7 +15791,7 @@ pub const Instruction = packed union {...@@ -14971,7 +15791,7 @@ pub const Instruction = packed union {
14971 } } } };15791 } } } };
14972 },15792 },
14973 .signed_offset => |signed_offset| {15793 .signed_offset => |signed_offset| {
14974 assert(signed_offset.base.format.integer == .doubleword);15794 assert(signed_offset.base.format.general == .doubleword);
14975 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{15795 return .{ .load_store = .{ .register_pair_offset = .{ .vector = .{
14976 .stp = .{15796 .stp = .{
14977 .Rt = t1.alias.encode(.{ .V = true }),15797 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -14983,7 +15803,7 @@ pub const Instruction = packed union {...@@ -14983,7 +15803,7 @@ pub const Instruction = packed union {
14983 } } } };15803 } } } };
14984 },15804 },
14985 .pre_index => |pre_index| {15805 .pre_index => |pre_index| {
14986 assert(pre_index.base.format.integer == .doubleword);15806 assert(pre_index.base.format.general == .doubleword);
14987 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{15807 return .{ .load_store = .{ .register_pair_pre_indexed = .{ .vector = .{
14988 .stp = .{15808 .stp = .{
14989 .Rt = t1.alias.encode(.{ .V = true }),15809 .Rt = t1.alias.encode(.{ .V = true }),
...@@ -15009,9 +15829,9 @@ pub const Instruction = packed union {...@@ -15009,9 +15829,9 @@ pub const Instruction = packed union {
15009 }) Instruction {15829 }) Instruction {
15010 switch (t.format) {15830 switch (t.format) {
15011 else => unreachable,15831 else => unreachable,
15012 .integer => |sf| form: switch (form) {15832 .general => |sf| form: switch (form) {
15013 .post_index => |post_index| {15833 .post_index => |post_index| {
15014 assert(post_index.base.format.integer == .doubleword);15834 assert(post_index.base.format.general == .doubleword);
15015 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{15835 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
15016 .str = .{15836 .str = .{
15017 .Rt = t.alias.encode(.{}),15837 .Rt = t.alias.encode(.{}),
...@@ -15022,7 +15842,7 @@ pub const Instruction = packed union {...@@ -15022,7 +15842,7 @@ pub const Instruction = packed union {
15022 } } } };15842 } } } };
15023 },15843 },
15024 .pre_index => |pre_index| {15844 .pre_index => |pre_index| {
15025 assert(pre_index.base.format.integer == .doubleword);15845 assert(pre_index.base.format.general == .doubleword);
15026 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{15846 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
15027 .str = .{15847 .str = .{
15028 .Rt = t.alias.encode(.{}),15848 .Rt = t.alias.encode(.{}),
...@@ -15033,7 +15853,7 @@ pub const Instruction = packed union {...@@ -15033,7 +15853,7 @@ pub const Instruction = packed union {
15033 } } } };15853 } } } };
15034 },15854 },
15035 .unsigned_offset => |unsigned_offset| {15855 .unsigned_offset => |unsigned_offset| {
15036 assert(unsigned_offset.base.format.integer == .doubleword);15856 assert(unsigned_offset.base.format.general == .doubleword);
15037 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{15857 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
15038 .str = .{15858 .str = .{
15039 .Rt = t.alias.encode(.{}),15859 .Rt = t.alias.encode(.{}),
...@@ -15047,7 +15867,7 @@ pub const Instruction = packed union {...@@ -15047,7 +15867,7 @@ pub const Instruction = packed union {
15047 },15867 },
15048 .scalar => |vs| form: switch (form) {15868 .scalar => |vs| form: switch (form) {
15049 .post_index => |post_index| {15869 .post_index => |post_index| {
15050 assert(post_index.base.format.integer == .doubleword);15870 assert(post_index.base.format.general == .doubleword);
15051 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{15871 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .vector = .{
15052 .str = .{15872 .str = .{
15053 .Rt = t.alias.encode(.{ .V = true }),15873 .Rt = t.alias.encode(.{ .V = true }),
...@@ -15059,7 +15879,7 @@ pub const Instruction = packed union {...@@ -15059,7 +15879,7 @@ pub const Instruction = packed union {
15059 } } } };15879 } } } };
15060 },15880 },
15061 .pre_index => |pre_index| {15881 .pre_index => |pre_index| {
15062 assert(pre_index.base.format.integer == .doubleword);15882 assert(pre_index.base.format.general == .doubleword);
15063 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{15883 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .vector = .{
15064 .str = .{15884 .str = .{
15065 .Rt = t.alias.encode(.{ .V = true }),15885 .Rt = t.alias.encode(.{ .V = true }),
...@@ -15071,7 +15891,7 @@ pub const Instruction = packed union {...@@ -15071,7 +15891,7 @@ pub const Instruction = packed union {
15071 } } } };15891 } } } };
15072 },15892 },
15073 .unsigned_offset => |unsigned_offset| {15893 .unsigned_offset => |unsigned_offset| {
15074 assert(unsigned_offset.base.format.integer == .doubleword);15894 assert(unsigned_offset.base.format.general == .doubleword);
15075 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{15895 return .{ .load_store = .{ .register_unsigned_immediate = .{ .vector = .{
15076 .str = .{15896 .str = .{
15077 .Rt = t.alias.encode(.{ .V = true }),15897 .Rt = t.alias.encode(.{ .V = true }),
...@@ -15093,10 +15913,10 @@ pub const Instruction = packed union {...@@ -15093,10 +15913,10 @@ pub const Instruction = packed union {
15093 unsigned_offset: struct { base: Register, offset: u12 = 0 },15913 unsigned_offset: struct { base: Register, offset: u12 = 0 },
15094 base: Register,15914 base: Register,
15095 }) Instruction {15915 }) Instruction {
15096 assert(t.format.integer == .word);15916 assert(t.format.general == .word);
15097 form: switch (form) {15917 form: switch (form) {
15098 .post_index => |post_index| {15918 .post_index => |post_index| {
15099 assert(post_index.base.format.integer == .doubleword);15919 assert(post_index.base.format.general == .doubleword);
15100 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{15920 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
15101 .strb = .{15921 .strb = .{
15102 .Rt = t.alias.encode(.{}),15922 .Rt = t.alias.encode(.{}),
...@@ -15106,7 +15926,7 @@ pub const Instruction = packed union {...@@ -15106,7 +15926,7 @@ pub const Instruction = packed union {
15106 } } } };15926 } } } };
15107 },15927 },
15108 .pre_index => |pre_index| {15928 .pre_index => |pre_index| {
15109 assert(pre_index.base.format.integer == .doubleword);15929 assert(pre_index.base.format.general == .doubleword);
15110 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{15930 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
15111 .strb = .{15931 .strb = .{
15112 .Rt = t.alias.encode(.{}),15932 .Rt = t.alias.encode(.{}),
...@@ -15116,7 +15936,7 @@ pub const Instruction = packed union {...@@ -15116,7 +15936,7 @@ pub const Instruction = packed union {
15116 } } } };15936 } } } };
15117 },15937 },
15118 .unsigned_offset => |unsigned_offset| {15938 .unsigned_offset => |unsigned_offset| {
15119 assert(unsigned_offset.base.format.integer == .doubleword);15939 assert(unsigned_offset.base.format.general == .doubleword);
15120 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{15940 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
15121 .strb = .{15941 .strb = .{
15122 .Rt = t.alias.encode(.{}),15942 .Rt = t.alias.encode(.{}),
...@@ -15135,10 +15955,10 @@ pub const Instruction = packed union {...@@ -15135,10 +15955,10 @@ pub const Instruction = packed union {
15135 unsigned_offset: struct { base: Register, offset: u13 = 0 },15955 unsigned_offset: struct { base: Register, offset: u13 = 0 },
15136 base: Register,15956 base: Register,
15137 }) Instruction {15957 }) Instruction {
15138 assert(t.format.integer == .word);15958 assert(t.format.general == .word);
15139 form: switch (form) {15959 form: switch (form) {
15140 .post_index => |post_index| {15960 .post_index => |post_index| {
15141 assert(post_index.base.format.integer == .doubleword);15961 assert(post_index.base.format.general == .doubleword);
15142 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{15962 return .{ .load_store = .{ .register_immediate_post_indexed = .{ .integer = .{
15143 .strh = .{15963 .strh = .{
15144 .Rt = t.alias.encode(.{}),15964 .Rt = t.alias.encode(.{}),
...@@ -15148,7 +15968,7 @@ pub const Instruction = packed union {...@@ -15148,7 +15968,7 @@ pub const Instruction = packed union {
15148 } } } };15968 } } } };
15149 },15969 },
15150 .pre_index => |pre_index| {15970 .pre_index => |pre_index| {
15151 assert(pre_index.base.format.integer == .doubleword);15971 assert(pre_index.base.format.general == .doubleword);
15152 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{15972 return .{ .load_store = .{ .register_immediate_pre_indexed = .{ .integer = .{
15153 .strh = .{15973 .strh = .{
15154 .Rt = t.alias.encode(.{}),15974 .Rt = t.alias.encode(.{}),
...@@ -15158,7 +15978,7 @@ pub const Instruction = packed union {...@@ -15158,7 +15978,7 @@ pub const Instruction = packed union {
15158 } } } };15978 } } } };
15159 },15979 },
15160 .unsigned_offset => |unsigned_offset| {15980 .unsigned_offset => |unsigned_offset| {
15161 assert(unsigned_offset.base.format.integer == .doubleword);15981 assert(unsigned_offset.base.format.general == .doubleword);
15162 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{15982 return .{ .load_store = .{ .register_unsigned_immediate = .{ .integer = .{
15163 .strh = .{15983 .strh = .{
15164 .Rt = t.alias.encode(.{}),15984 .Rt = t.alias.encode(.{}),
...@@ -15173,10 +15993,10 @@ pub const Instruction = packed union {...@@ -15173,10 +15993,10 @@ pub const Instruction = packed union {
15173 /// C6.2.346 STUR15993 /// C6.2.346 STUR
15174 /// C7.2.333 STUR (SIMD&FP)15994 /// C7.2.333 STUR (SIMD&FP)
15175 pub fn stur(t: Register, n: Register, simm: i9) Instruction {15995 pub fn stur(t: Register, n: Register, simm: i9) Instruction {
15176 assert(n.format.integer == .doubleword);15996 assert(n.format.general == .doubleword);
15177 switch (t.format) {15997 switch (t.format) {
15178 else => unreachable,15998 else => unreachable,
15179 .integer => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{15999 .general => |sf| return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
15180 .stur = .{16000 .stur = .{
15181 .Rt = t.alias.encode(.{}),16001 .Rt = t.alias.encode(.{}),
15182 .Rn = n.alias.encode(.{ .sp = true }),16002 .Rn = n.alias.encode(.{ .sp = true }),
...@@ -15197,7 +16017,7 @@ pub const Instruction = packed union {...@@ -15197,7 +16017,7 @@ pub const Instruction = packed union {
15197 }16017 }
15198 /// C6.2.347 STURB16018 /// C6.2.347 STURB
15199 pub fn sturb(t: Register, n: Register, simm: i9) Instruction {16019 pub fn sturb(t: Register, n: Register, simm: i9) Instruction {
15200 assert(t.format.integer == .word and n.format.integer == .doubleword);16020 assert(t.format.general == .word and n.format.general == .doubleword);
15201 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{16021 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
15202 .sturb = .{16022 .sturb = .{
15203 .Rt = t.alias.encode(.{}),16023 .Rt = t.alias.encode(.{}),
...@@ -15208,7 +16028,7 @@ pub const Instruction = packed union {...@@ -15208,7 +16028,7 @@ pub const Instruction = packed union {
15208 }16028 }
15209 /// C6.2.348 STURH16029 /// C6.2.348 STURH
15210 pub fn sturh(t: Register, n: Register, simm: i9) Instruction {16030 pub fn sturh(t: Register, n: Register, simm: i9) Instruction {
15211 assert(t.format.integer == .word and n.format.integer == .doubleword);16031 assert(t.format.general == .word and n.format.general == .doubleword);
15212 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{16032 return .{ .load_store = .{ .register_unscaled_immediate = .{ .integer = .{
15213 .sturh = .{16033 .sturh = .{
15214 .Rt = t.alias.encode(.{}),16034 .Rt = t.alias.encode(.{}),
...@@ -15233,11 +16053,11 @@ pub const Instruction = packed union {...@@ -15233,11 +16053,11 @@ pub const Instruction = packed union {
15233 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },16053 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
15234 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },16054 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
15235 }) Instruction {16055 }) Instruction {
15236 const sf = d.format.integer;16056 const sf = d.format.general;
15237 assert(n.format.integer == sf);16057 assert(n.format.general == sf);
15238 form: switch (form) {16058 form: switch (form) {
15239 .extended_register_explicit => |extended_register_explicit| {16059 .extended_register_explicit => |extended_register_explicit| {
15240 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());16060 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
15241 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{16061 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
15242 .sub = .{16062 .sub = .{
15243 .Rd = d.alias.encode(.{ .sp = true }),16063 .Rd = d.alias.encode(.{ .sp = true }),
...@@ -15279,7 +16099,7 @@ pub const Instruction = packed union {...@@ -15279,7 +16099,7 @@ pub const Instruction = packed union {
15279 else16099 else
15280 .{ .shifted_register = .{ .register = register } },16100 .{ .shifted_register = .{ .register = register } },
15281 .shifted_register_explicit => |shifted_register_explicit| {16101 .shifted_register_explicit => |shifted_register_explicit| {
15282 assert(shifted_register_explicit.register.format.integer == sf);16102 assert(shifted_register_explicit.register.format.general == sf);
15283 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{16103 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
15284 .sub = .{16104 .sub = .{
15285 .Rd = d.alias.encode(.{}),16105 .Rd = d.alias.encode(.{}),
...@@ -15323,11 +16143,11 @@ pub const Instruction = packed union {...@@ -15323,11 +16143,11 @@ pub const Instruction = packed union {
15323 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },16143 shifted_register_explicit: struct { register: Register, shift: DataProcessingRegister.Shift.Op, amount: u6 },
15324 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },16144 shifted_register: struct { register: Register, shift: DataProcessingRegister.Shift = .none },
15325 }) Instruction {16145 }) Instruction {
15326 const sf = d.format.integer;16146 const sf = d.format.general;
15327 assert(n.format.integer == sf);16147 assert(n.format.general == sf);
15328 form: switch (form) {16148 form: switch (form) {
15329 .extended_register_explicit => |extended_register_explicit| {16149 .extended_register_explicit => |extended_register_explicit| {
15330 assert(extended_register_explicit.register.format.integer == extended_register_explicit.option.sf());16150 assert(extended_register_explicit.register.format.general == extended_register_explicit.option.sf());
15331 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{16151 return .{ .data_processing_register = .{ .add_subtract_extended_register = .{
15332 .subs = .{16152 .subs = .{
15333 .Rd = d.alias.encode(.{}),16153 .Rd = d.alias.encode(.{}),
...@@ -15369,7 +16189,7 @@ pub const Instruction = packed union {...@@ -15369,7 +16189,7 @@ pub const Instruction = packed union {
15369 else16189 else
15370 .{ .shifted_register = .{ .register = register } },16190 .{ .shifted_register = .{ .register = register } },
15371 .shifted_register_explicit => |shifted_register_explicit| {16191 .shifted_register_explicit => |shifted_register_explicit| {
15372 assert(shifted_register_explicit.register.format.integer == sf);16192 assert(shifted_register_explicit.register.format.general == sf);
15373 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{16193 return .{ .data_processing_register = .{ .add_subtract_shifted_register = .{
15374 .subs = .{16194 .subs = .{
15375 .Rd = d.alias.encode(.{}),16195 .Rd = d.alias.encode(.{}),
...@@ -15407,7 +16227,7 @@ pub const Instruction = packed union {...@@ -15407,7 +16227,7 @@ pub const Instruction = packed union {
15407 .suqadd = .{16227 .suqadd = .{
15408 .Rd = d.alias.encode(.{ .V = true }),16228 .Rd = d.alias.encode(.{ .V = true }),
15409 .Rn = n.alias.encode(.{ .V = true }),16229 .Rn = n.alias.encode(.{ .V = true }),
15410 .size = .fromVectorSize(elem_size),16230 .size = .fromScalarSize(elem_size),
15411 },16231 },
15412 } } };16232 } } };
15413 },16233 },
...@@ -15432,7 +16252,7 @@ pub const Instruction = packed union {...@@ -15432,7 +16252,7 @@ pub const Instruction = packed union {
15432 }16252 }
15433 /// C6.2.372 SYS16253 /// C6.2.372 SYS
15434 pub fn sys(op1: u3, n: u4, m: u4, op2: u3, t: Register) Instruction {16254 pub fn sys(op1: u3, n: u4, m: u4, op2: u3, t: Register) Instruction {
15435 assert(t.format.integer == .doubleword);16255 assert(t.format.general == .doubleword);
15436 return .{ .branch_exception_generating_system = .{ .system = .{16256 return .{ .branch_exception_generating_system = .{ .system = .{
15437 .sys = .{16257 .sys = .{
15438 .Rt = t.alias.encode(.{}),16258 .Rt = t.alias.encode(.{}),
...@@ -15445,7 +16265,7 @@ pub const Instruction = packed union {...@@ -15445,7 +16265,7 @@ pub const Instruction = packed union {
15445 }16265 }
15446 /// C6.2.373 SYSL16266 /// C6.2.373 SYSL
15447 pub fn sysl(t: Register, op1: u3, n: u4, m: u4, op2: u3) Instruction {16267 pub fn sysl(t: Register, op1: u3, n: u4, m: u4, op2: u3) Instruction {
15448 assert(t.format.integer == .doubleword);16268 assert(t.format.general == .doubleword);
15449 return .{ .branch_exception_generating_system = .{ .system = .{16269 return .{ .branch_exception_generating_system = .{ .system = .{
15450 .sysl = .{16270 .sysl = .{
15451 .Rt = t.alias.encode(.{}),16271 .Rt = t.alias.encode(.{}),
...@@ -15462,7 +16282,7 @@ pub const Instruction = packed union {...@@ -15462,7 +16282,7 @@ pub const Instruction = packed union {
15462 .tbnz = .{16282 .tbnz = .{
15463 .Rt = t.alias.encode(.{}),16283 .Rt = t.alias.encode(.{}),
15464 .imm14 = @intCast(@shrExact(label, 2)),16284 .imm14 = @intCast(@shrExact(label, 2)),
15465 .b40 = @truncate(switch (t.format.integer) {16285 .b40 = @truncate(switch (t.format.general) {
15466 .word => @as(u5, @intCast(imm)),16286 .word => @as(u5, @intCast(imm)),
15467 .doubleword => imm,16287 .doubleword => imm,
15468 }),16288 }),
...@@ -15476,7 +16296,7 @@ pub const Instruction = packed union {...@@ -15476,7 +16296,7 @@ pub const Instruction = packed union {
15476 .tbz = .{16296 .tbz = .{
15477 .Rt = t.alias.encode(.{}),16297 .Rt = t.alias.encode(.{}),
15478 .imm14 = @intCast(@shrExact(label, 2)),16298 .imm14 = @intCast(@shrExact(label, 2)),
15479 .b40 = @truncate(switch (t.format.integer) {16299 .b40 = @truncate(switch (t.format.general) {
15480 .word => @as(u5, @intCast(imm)),16300 .word => @as(u5, @intCast(imm)),
15481 .doubleword => imm,16301 .doubleword => imm,
15482 }),16302 }),
...@@ -15492,8 +16312,8 @@ pub const Instruction = packed union {...@@ -15492,8 +16312,8 @@ pub const Instruction = packed union {
15492 }16312 }
15493 /// C6.2.385 UBFM16313 /// C6.2.385 UBFM
15494 pub fn ubfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {16314 pub fn ubfm(d: Register, n: Register, bitmask: DataProcessingImmediate.Bitmask) Instruction {
15495 const sf = d.format.integer;16315 const sf = d.format.general;
15496 assert(n.format.integer == sf and bitmask.validBitfield(sf));16316 assert(n.format.general == sf and bitmask.validBitfield(sf));
15497 return .{ .data_processing_immediate = .{ .bitfield = .{16317 return .{ .data_processing_immediate = .{ .bitfield = .{
15498 .ubfm = .{16318 .ubfm = .{
15499 .Rd = d.alias.encode(.{}),16319 .Rd = d.alias.encode(.{}),
...@@ -15524,16 +16344,16 @@ pub const Instruction = packed union {...@@ -15524,16 +16344,16 @@ pub const Instruction = packed union {
15524 .ucvtf = .{16344 .ucvtf = .{
15525 .Rd = d.alias.encode(.{ .V = true }),16345 .Rd = d.alias.encode(.{ .V = true }),
15526 .Rn = n.alias.encode(.{ .V = true }),16346 .Rn = n.alias.encode(.{ .V = true }),
15527 .sz = .fromVectorSize(ftype),16347 .sz = .fromScalarSize(ftype),
15528 },16348 },
15529 } } },16349 } } },
15530 }16350 }
15531 },16351 },
15532 .integer => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{16352 .general => |sf| return .{ .data_processing_vector = .{ .convert_float_integer = .{
15533 .ucvtf = .{16353 .ucvtf = .{
15534 .Rd = d.alias.encode(.{ .V = true }),16354 .Rd = d.alias.encode(.{ .V = true }),
15535 .Rn = n.alias.encode(.{}),16355 .Rn = n.alias.encode(.{}),
15536 .ftype = .fromVectorSize(ftype),16356 .ftype = .fromScalarSize(ftype),
15537 .sf = sf,16357 .sf = sf,
15538 },16358 },
15539 } } },16359 } } },
...@@ -15569,8 +16389,8 @@ pub const Instruction = packed union {...@@ -15569,8 +16389,8 @@ pub const Instruction = packed union {
15569 }16389 }
15570 /// C6.2.388 UDIV16390 /// C6.2.388 UDIV
15571 pub fn udiv(d: Register, n: Register, m: Register) Instruction {16391 pub fn udiv(d: Register, n: Register, m: Register) Instruction {
15572 const sf = d.format.integer;16392 const sf = d.format.general;
15573 assert(n.format.integer == sf and m.format.integer == sf);16393 assert(n.format.general == sf and m.format.general == sf);
15574 return .{ .data_processing_register = .{ .data_processing_two_source = .{16394 return .{ .data_processing_register = .{ .data_processing_two_source = .{
15575 .udiv = .{16395 .udiv = .{
15576 .Rd = d.alias.encode(.{}),16396 .Rd = d.alias.encode(.{}),
...@@ -15582,7 +16402,7 @@ pub const Instruction = packed union {...@@ -15582,7 +16402,7 @@ pub const Instruction = packed union {
15582 }16402 }
15583 /// C6.2.389 UMADDL16403 /// C6.2.389 UMADDL
15584 pub fn umaddl(d: Register, n: Register, m: Register, a: Register) Instruction {16404 pub fn umaddl(d: Register, n: Register, m: Register, a: Register) Instruction {
15585 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);16405 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
15586 return .{ .data_processing_register = .{ .data_processing_three_source = .{16406 return .{ .data_processing_register = .{ .data_processing_three_source = .{
15587 .umaddl = .{16407 .umaddl = .{
15588 .Rd = d.alias.encode(.{}),16408 .Rd = d.alias.encode(.{}),
...@@ -15594,7 +16414,7 @@ pub const Instruction = packed union {...@@ -15594,7 +16414,7 @@ pub const Instruction = packed union {
15594 }16414 }
15595 /// C6.2.391 UMSUBL16415 /// C6.2.391 UMSUBL
15596 pub fn umsubl(d: Register, n: Register, m: Register, a: Register) Instruction {16416 pub fn umsubl(d: Register, n: Register, m: Register, a: Register) Instruction {
15597 assert(d.format.integer == .doubleword and n.format.integer == .word and m.format.integer == .word and a.format.integer == .doubleword);16417 assert(d.format.general == .doubleword and n.format.general == .word and m.format.general == .word and a.format.general == .doubleword);
15598 return .{ .data_processing_register = .{ .data_processing_three_source = .{16418 return .{ .data_processing_register = .{ .data_processing_three_source = .{
15599 .umsubl = .{16419 .umsubl = .{
15600 .Rd = d.alias.encode(.{}),16420 .Rd = d.alias.encode(.{}),
...@@ -15606,7 +16426,7 @@ pub const Instruction = packed union {...@@ -15606,7 +16426,7 @@ pub const Instruction = packed union {
15606 }16426 }
15607 /// C7.2.371 UMOV16427 /// C7.2.371 UMOV
15608 pub fn umov(d: Register, n: Register) Instruction {16428 pub fn umov(d: Register, n: Register) Instruction {
15609 const sf = d.format.integer;16429 const sf = d.format.general;
15610 const vs = n.format.element.size;16430 const vs = n.format.element.size;
15611 switch (vs) {16431 switch (vs) {
15612 else => unreachable,16432 else => unreachable,
...@@ -15630,7 +16450,7 @@ pub const Instruction = packed union {...@@ -15630,7 +16450,7 @@ pub const Instruction = packed union {
15630 }16450 }
15631 /// C6.2.392 UMULH16451 /// C6.2.392 UMULH
15632 pub fn umulh(d: Register, n: Register, m: Register) Instruction {16452 pub fn umulh(d: Register, n: Register, m: Register) Instruction {
15633 assert(d.format.integer == .doubleword and n.format.integer == .doubleword and m.format.integer == .doubleword);16453 assert(d.format.general == .doubleword and n.format.general == .doubleword and m.format.general == .doubleword);
15634 return .{ .data_processing_register = .{ .data_processing_three_source = .{16454 return .{ .data_processing_register = .{ .data_processing_three_source = .{
15635 .umulh = .{16455 .umulh = .{
15636 .Rd = d.alias.encode(.{}),16456 .Rd = d.alias.encode(.{}),
src/codegen/aarch64/instructions.zon+3965-354
...@@ -3,60 +3,72 @@...@@ -3,60 +3,72 @@
3 .{3 .{
4 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>",4 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>",
5 .symbols = .{5 .symbols = .{
6 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },6 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
7 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },7 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
8 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },8 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
9 },9 },
10 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },10 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },
11 },11 },
12 .{12 .{
13 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",13 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",
14 .symbols = .{14 .symbols = .{
15 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },15 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
16 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },16 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
17 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },17 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
18 .extend = .{ .extend = .{ .size = .word } },18 .extend = .{ .extend = .{ .size = .word } },
19 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },19 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
20 },20 },
21 .encode = .{ .add, .Wd, .Wn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },21 .encode = .{ .add, .Wd, .Wn, .{ .extended_register_explicit = .{
22 .register = .Wm,
23 .option = .extend,
24 .amount = .amount,
25 } } },
22 },26 },
23 .{27 .{
24 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>",28 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>",
25 .symbols = .{29 .symbols = .{
26 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },30 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
27 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },31 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
28 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },32 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
29 },33 },
30 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },34 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },
31 },35 },
32 .{36 .{
33 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",37 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",
34 .symbols = .{38 .symbols = .{
35 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },39 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
36 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },40 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
37 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },41 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
38 .extend = .{ .extend = .{ .size = .word } },42 .extend = .{ .extend = .{ .size = .word } },
39 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },43 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
40 },44 },
41 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },45 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{
46 .register = .Wm,
47 .option = .extend,
48 .amount = .amount,
49 } } },
42 },50 },
43 .{51 .{
44 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",52 .pattern = "ADD <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",
45 .symbols = .{53 .symbols = .{
46 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },54 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
47 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },55 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
48 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },56 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
49 .extend = .{ .extend = .{ .size = .doubleword } },57 .extend = .{ .extend = .{ .size = .doubleword } },
50 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },58 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
51 },59 },
52 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Xm, .option = .extend, .amount = .amount } } },60 .encode = .{ .add, .Xd, .Xn, .{ .extended_register_explicit = .{
61 .register = .Xm,
62 .option = .extend,
63 .amount = .amount,
64 } } },
53 },65 },
54 // C6.2.4 ADD (immediate)66 // C6.2.4 ADD (immediate)
55 .{67 .{
56 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>",68 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>",
57 .symbols = .{69 .symbols = .{
58 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },70 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
59 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },71 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
60 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },72 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
61 },73 },
62 .encode = .{ .add, .Wd, .Wn, .{ .immediate = .imm } },74 .encode = .{ .add, .Wd, .Wn, .{ .immediate = .imm } },
...@@ -64,8 +76,8 @@...@@ -64,8 +76,8 @@
64 .{76 .{
65 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",77 .pattern = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",
66 .symbols = .{78 .symbols = .{
67 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },79 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
68 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },80 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
69 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },81 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
70 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },82 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
71 },83 },
...@@ -74,8 +86,8 @@...@@ -74,8 +86,8 @@
74 .{86 .{
75 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>",87 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>",
76 .symbols = .{88 .symbols = .{
77 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },89 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
78 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },90 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
79 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },91 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
80 },92 },
81 .encode = .{ .add, .Xd, .Xn, .{ .immediate = .imm } },93 .encode = .{ .add, .Xd, .Xn, .{ .immediate = .imm } },
...@@ -83,8 +95,8 @@...@@ -83,8 +95,8 @@
83 .{95 .{
84 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",96 .pattern = "ADD <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",
85 .symbols = .{97 .symbols = .{
86 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },98 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
87 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },99 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
88 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },100 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
89 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },101 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
90 },102 },
...@@ -94,141 +106,165 @@...@@ -94,141 +106,165 @@
94 .{106 .{
95 .pattern = "ADD <Wd>, <Wn>, <Wm>",107 .pattern = "ADD <Wd>, <Wn>, <Wm>",
96 .symbols = .{108 .symbols = .{
97 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },109 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
98 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },110 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
99 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },111 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
100 },112 },
101 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },113 .encode = .{ .add, .Wd, .Wn, .{ .register = .Wm } },
102 },114 },
103 .{115 .{
104 .pattern = "ADD <Wd>, <Wn>, <Wm>, <shift> #<amount>",116 .pattern = "ADD <Wd>, <Wn>, <Wm>, <shift> #<amount>",
105 .symbols = .{117 .symbols = .{
106 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },118 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
107 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },119 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
108 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },120 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
109 .shift = .{ .shift = .{ .allow_ror = false } },121 .shift = .{ .shift = .{ .allow_ror = false } },
110 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },122 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
111 },123 },
112 .encode = .{ .add, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },124 .encode = .{ .add, .Wd, .Wn, .{ .shifted_register_explicit = .{
125 .register = .Wm,
126 .shift = .shift,
127 .amount = .amount,
128 } } },
113 },129 },
114 .{130 .{
115 .pattern = "ADD <Xd>, <Xn>, <Xm>",131 .pattern = "ADD <Xd>, <Xn>, <Xm>",
116 .symbols = .{132 .symbols = .{
117 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },133 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
118 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },134 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
119 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },135 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
120 },136 },
121 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },137 .encode = .{ .add, .Xd, .Xn, .{ .register = .Xm } },
122 },138 },
123 .{139 .{
124 .pattern = "ADD <Xd>, <Xn>, <Xm>, <shift> #<amount>",140 .pattern = "ADD <Xd>, <Xn>, <Xm>, <shift> #<amount>",
125 .symbols = .{141 .symbols = .{
126 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },142 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
127 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },143 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
128 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },144 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
129 .shift = .{ .shift = .{ .allow_ror = false } },145 .shift = .{ .shift = .{ .allow_ror = false } },
130 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },146 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
131 },147 },
132 .encode = .{ .add, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },148 .encode = .{ .add, .Xd, .Xn, .{ .shifted_register_explicit = .{
149 .register = .Xm,
150 .shift = .shift,
151 .amount = .amount,
152 } } },
133 },153 },
134 // C6.2.13 AND (shifted register)154 // C6.2.13 AND (shifted register)
135 .{155 .{
136 .pattern = "AND <Wd>, <Wn>, <Wm>",156 .pattern = "AND <Wd>, <Wn>, <Wm>",
137 .symbols = .{157 .symbols = .{
138 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },158 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
139 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },159 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
140 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },160 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
141 },161 },
142 .encode = .{ .@"and", .Wd, .Wn, .{ .register = .Wm } },162 .encode = .{ .@"and", .Wd, .Wn, .{ .register = .Wm } },
143 },163 },
144 .{164 .{
145 .pattern = "AND <Wd>, <Wn>, <Wm>, <shift> #<amount>",165 .pattern = "AND <Wd>, <Wn>, <Wm>, <shift> #<amount>",
146 .symbols = .{166 .symbols = .{
147 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
148 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },168 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
149 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },169 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
150 .shift = .{ .shift = .{} },170 .shift = .{ .shift = .{} },
151 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },171 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
152 },172 },
153 .encode = .{ .@"and", .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },173 .encode = .{ .@"and", .Wd, .Wn, .{ .shifted_register_explicit = .{
174 .register = .Wm,
175 .shift = .shift,
176 .amount = .amount,
177 } } },
154 },178 },
155 .{179 .{
156 .pattern = "AND <Xd>, <Xn>, <Xm>",180 .pattern = "AND <Xd>, <Xn>, <Xm>",
157 .symbols = .{181 .symbols = .{
158 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },182 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
159 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },183 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
160 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },184 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
161 },185 },
162 .encode = .{ .@"and", .Xd, .Xn, .{ .register = .Xm } },186 .encode = .{ .@"and", .Xd, .Xn, .{ .register = .Xm } },
163 },187 },
164 .{188 .{
165 .pattern = "AND <Xd>, <Xn>, <Xm>, <shift> #<amount>",189 .pattern = "AND <Xd>, <Xn>, <Xm>, <shift> #<amount>",
166 .symbols = .{190 .symbols = .{
167 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },191 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
168 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },192 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
169 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },193 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
170 .shift = .{ .shift = .{} },194 .shift = .{ .shift = .{} },
171 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },195 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
172 },196 },
173 .encode = .{ .@"and", .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },197 .encode = .{ .@"and", .Xd, .Xn, .{ .shifted_register_explicit = .{
198 .register = .Xm,
199 .shift = .shift,
200 .amount = .amount,
201 } } },
174 },202 },
175 // C6.2.15 ANDS (shifted register)203 // C6.2.15 ANDS (shifted register)
176 .{204 .{
177 .pattern = "ANDS <Wd>, <Wn>, <Wm>",205 .pattern = "ANDS <Wd>, <Wn>, <Wm>",
178 .symbols = .{206 .symbols = .{
179 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },207 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
180 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },208 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
181 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },209 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
182 },210 },
183 .encode = .{ .ands, .Wd, .Wn, .{ .register = .Wm } },211 .encode = .{ .ands, .Wd, .Wn, .{ .register = .Wm } },
184 },212 },
185 .{213 .{
186 .pattern = "ANDS <Wd>, <Wn>, <Wm>, <shift> #<amount>",214 .pattern = "ANDS <Wd>, <Wn>, <Wm>, <shift> #<amount>",
187 .symbols = .{215 .symbols = .{
188 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },216 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
189 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },217 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
190 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },218 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
191 .shift = .{ .shift = .{} },219 .shift = .{ .shift = .{} },
192 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },220 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
193 },221 },
194 .encode = .{ .ands, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },222 .encode = .{ .ands, .Wd, .Wn, .{ .shifted_register_explicit = .{
223 .register = .Wm,
224 .shift = .shift,
225 .amount = .amount,
226 } } },
195 },227 },
196 .{228 .{
197 .pattern = "ANDS <Xd>, <Xn>, <Xm>",229 .pattern = "ANDS <Xd>, <Xn>, <Xm>",
198 .symbols = .{230 .symbols = .{
199 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },231 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
200 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },232 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
201 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },233 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
202 },234 },
203 .encode = .{ .ands, .Xd, .Xn, .{ .register = .Xm } },235 .encode = .{ .ands, .Xd, .Xn, .{ .register = .Xm } },
204 },236 },
205 .{237 .{
206 .pattern = "ANDS <Xd>, <Xn>, <Xm>, <shift> #<amount>",238 .pattern = "ANDS <Xd>, <Xn>, <Xm>, <shift> #<amount>",
207 .symbols = .{239 .symbols = .{
208 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },240 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
209 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },241 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
210 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },242 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
211 .shift = .{ .shift = .{} },243 .shift = .{ .shift = .{} },
212 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },244 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
213 },245 },
214 .encode = .{ .ands, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },246 .encode = .{ .ands, .Xd, .Xn, .{ .shifted_register_explicit = .{
247 .register = .Xm,
248 .shift = .shift,
249 .amount = .amount,
250 } } },
215 },251 },
216 // C6.2.16 ASR (register)252 // C6.2.16 ASR (register)
217 .{253 .{
218 .pattern = "ASR <Wd>, <Wn>, <Wm>",254 .pattern = "ASR <Wd>, <Wn>, <Wm>",
219 .symbols = .{255 .symbols = .{
220 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },256 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
221 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },257 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
222 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },258 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
223 },259 },
224 .encode = .{ .asrv, .Wd, .Wn, .Wm },260 .encode = .{ .asrv, .Wd, .Wn, .Wm },
225 },261 },
226 .{262 .{
227 .pattern = "ASR <Xd>, <Xn>, <Xm>",263 .pattern = "ASR <Xd>, <Xn>, <Xm>",
228 .symbols = .{264 .symbols = .{
229 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },265 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
230 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },266 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
231 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },267 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
232 },268 },
233 .encode = .{ .asrv, .Xd, .Xn, .Xm },269 .encode = .{ .asrv, .Xd, .Xn, .Xm },
234 },270 },
...@@ -236,8 +272,8 @@...@@ -236,8 +272,8 @@
236 .{272 .{
237 .pattern = "ASR <Wd>, <Wn>, #<shift>",273 .pattern = "ASR <Wd>, <Wn>, #<shift>",
238 .symbols = .{274 .symbols = .{
239 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },275 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
240 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },276 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
241 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },277 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
242 },278 },
243 .encode = .{ .sbfm, .Wd, .Wn, .{ .N = .word, .immr = .shift, .imms = 31 } },279 .encode = .{ .sbfm, .Wd, .Wn, .{ .N = .word, .immr = .shift, .imms = 31 } },
...@@ -245,8 +281,8 @@...@@ -245,8 +281,8 @@
245 .{281 .{
246 .pattern = "ASR <Xd>, <Xn>, #<shift>",282 .pattern = "ASR <Xd>, <Xn>, #<shift>",
247 .symbols = .{283 .symbols = .{
248 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },284 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
249 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },285 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
250 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },286 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
251 },287 },
252 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .shift, .imms = 63 } },288 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .shift, .imms = 63 } },
...@@ -255,35 +291,27 @@...@@ -255,35 +291,27 @@
255 .{291 .{
256 .pattern = "ASRV <Wd>, <Wn>, <Wm>",292 .pattern = "ASRV <Wd>, <Wn>, <Wm>",
257 .symbols = .{293 .symbols = .{
258 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },294 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
259 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },295 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
260 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },296 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
261 },297 },
262 .encode = .{ .asrv, .Wd, .Wn, .Wm },298 .encode = .{ .asrv, .Wd, .Wn, .Wm },
263 },299 },
264 .{300 .{
265 .pattern = "ASRV <Xd>, <Xn>, <Xm>",301 .pattern = "ASRV <Xd>, <Xn>, <Xm>",
266 .symbols = .{302 .symbols = .{
267 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },303 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
268 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },304 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
269 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },305 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
270 },306 },
271 .encode = .{ .asrv, .Xd, .Xn, .Xm },307 .encode = .{ .asrv, .Xd, .Xn, .Xm },
272 },308 },
273 // C6.2.35 BLR
274 .{
275 .pattern = "BLR <Xn>",
276 .symbols = .{
277 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
278 },
279 .encode = .{ .blr, .Xn },
280 },
281 // C6.2.30 BFM309 // C6.2.30 BFM
282 .{310 .{
283 .pattern = "BFM <Wd>, <Wn>, #<immr>, #<imms>",311 .pattern = "BFM <Wd>, <Wn>, #<immr>, #<imms>",
284 .symbols = .{312 .symbols = .{
285 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },313 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
286 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },314 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
287 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },315 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
288 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },316 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
289 },317 },
...@@ -292,18 +320,26 @@...@@ -292,18 +320,26 @@
292 .{320 .{
293 .pattern = "BFM <Xd>, <Xn>, #<immr>, #<imms>",321 .pattern = "BFM <Xd>, <Xn>, #<immr>, #<imms>",
294 .symbols = .{322 .symbols = .{
295 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },323 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
296 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },324 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
297 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },325 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
298 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },326 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
299 },327 },
300 .encode = .{ .bfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },328 .encode = .{ .bfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
301 },329 },
330 // C6.2.35 BLR
331 .{
332 .pattern = "BLR <Xn>",
333 .symbols = .{
334 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
335 },
336 .encode = .{ .blr, .Xn },
337 },
302 // C6.2.37 BR338 // C6.2.37 BR
303 .{339 .{
304 .pattern = "BR <Xn>",340 .pattern = "BR <Xn>",
305 .symbols = .{341 .symbols = .{
306 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },342 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
307 },343 },
308 .encode = .{ .br, .Xn },344 .encode = .{ .br, .Xn },
309 },345 },
...@@ -328,60 +364,94 @@...@@ -328,60 +364,94 @@
328 },364 },
329 .encode = .{ .clrex, .imm },365 .encode = .{ .clrex, .imm },
330 },366 },
367 // C6.2.57 CLS
368 .{
369 .pattern = "CLS <Wd>, <Wn>",
370 .symbols = .{
371 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
372 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
373 },
374 .encode = .{ .cls, .Wd, .Wn },
375 },
376 .{
377 .pattern = "CLS <Xd>, <Xn>",
378 .symbols = .{
379 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
380 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
381 },
382 .encode = .{ .cls, .Xd, .Xn },
383 },
384 // C6.2.58 CLZ
385 .{
386 .pattern = "CLZ <Wd>, <Wn>",
387 .symbols = .{
388 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
389 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
390 },
391 .encode = .{ .clz, .Wd, .Wn },
392 },
393 .{
394 .pattern = "CLZ <Xd>, <Xn>",
395 .symbols = .{
396 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
397 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
398 },
399 .encode = .{ .clz, .Xd, .Xn },
400 },
331 // C6.2.109 DC401 // C6.2.109 DC
332 .{402 .{
333 .pattern = "DC IVAC, <Xt>",403 .pattern = "DC IVAC, <Xt>",
334 .symbols = .{404 .symbols = .{
335 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },405 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
336 },406 },
337 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b001, .Xt },407 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b001, .Xt },
338 },408 },
339 .{409 .{
340 .pattern = "DC ISW, <Xt>",410 .pattern = "DC ISW, <Xt>",
341 .symbols = .{411 .symbols = .{
342 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },412 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
343 },413 },
344 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b010, .Xt },414 .encode = .{ .sys, 0b000, 0b0111, 0b0110, 0b010, .Xt },
345 },415 },
346 .{416 .{
347 .pattern = "DC CSW, <Xt>",417 .pattern = "DC CSW, <Xt>",
348 .symbols = .{418 .symbols = .{
349 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },419 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
350 },420 },
351 .encode = .{ .sys, 0b000, 0b0111, 0b1010, 0b010, .Xt },421 .encode = .{ .sys, 0b000, 0b0111, 0b1010, 0b010, .Xt },
352 },422 },
353 .{423 .{
354 .pattern = "DC CISW, <Xt>",424 .pattern = "DC CISW, <Xt>",
355 .symbols = .{425 .symbols = .{
356 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },426 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
357 },427 },
358 .encode = .{ .sys, 0b000, 0b0111, 0b1110, 0b010, .Xt },428 .encode = .{ .sys, 0b000, 0b0111, 0b1110, 0b010, .Xt },
359 },429 },
360 .{430 .{
361 .pattern = "DC ZVA, <Xt>",431 .pattern = "DC ZVA, <Xt>",
362 .symbols = .{432 .symbols = .{
363 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },433 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
364 },434 },
365 .encode = .{ .sys, 0b011, 0b0111, 0b0100, 0b001, .Xt },435 .encode = .{ .sys, 0b011, 0b0111, 0b0100, 0b001, .Xt },
366 },436 },
367 .{437 .{
368 .pattern = "DC CVAC, <Xt>",438 .pattern = "DC CVAC, <Xt>",
369 .symbols = .{439 .symbols = .{
370 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },440 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
371 },441 },
372 .encode = .{ .sys, 0b011, 0b0111, 0b1010, 0b001, .Xt },442 .encode = .{ .sys, 0b011, 0b0111, 0b1010, 0b001, .Xt },
373 },443 },
374 .{444 .{
375 .pattern = "DC CVAU, <Xt>",445 .pattern = "DC CVAU, <Xt>",
376 .symbols = .{446 .symbols = .{
377 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },447 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
378 },448 },
379 .encode = .{ .sys, 0b011, 0b0111, 0b1011, 0b001, .Xt },449 .encode = .{ .sys, 0b011, 0b0111, 0b1011, 0b001, .Xt },
380 },450 },
381 .{451 .{
382 .pattern = "DC CIVAC, <Xt>",452 .pattern = "DC CIVAC, <Xt>",
383 .symbols = .{453 .symbols = .{
384 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },454 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
385 },455 },
386 .encode = .{ .sys, 0b011, 0b0111, 0b1110, 0b001, .Xt },456 .encode = .{ .sys, 0b011, 0b0111, 0b1110, 0b001, .Xt },
387 },457 },
...@@ -443,50 +513,58 @@...@@ -443,50 +513,58 @@
443 .{513 .{
444 .pattern = "EOR <Wd>, <Wn>, <Wm>",514 .pattern = "EOR <Wd>, <Wn>, <Wm>",
445 .symbols = .{515 .symbols = .{
446 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },516 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
447 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },517 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
448 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },518 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
449 },519 },
450 .encode = .{ .eor, .Wd, .Wn, .{ .register = .Wm } },520 .encode = .{ .eor, .Wd, .Wn, .{ .register = .Wm } },
451 },521 },
452 .{522 .{
453 .pattern = "EOR <Wd>, <Wn>, <Wm>, <shift> #<amount>",523 .pattern = "EOR <Wd>, <Wn>, <Wm>, <shift> #<amount>",
454 .symbols = .{524 .symbols = .{
455 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },525 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
456 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },526 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
457 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },527 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
458 .shift = .{ .shift = .{} },528 .shift = .{ .shift = .{} },
459 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },529 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
460 },530 },
461 .encode = .{ .eor, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },531 .encode = .{ .eor, .Wd, .Wn, .{ .shifted_register_explicit = .{
532 .register = .Wm,
533 .shift = .shift,
534 .amount = .amount,
535 } } },
462 },536 },
463 .{537 .{
464 .pattern = "EOR <Xd>, <Xn>, <Xm>",538 .pattern = "EOR <Xd>, <Xn>, <Xm>",
465 .symbols = .{539 .symbols = .{
466 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },540 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
467 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },541 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
468 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },542 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
469 },543 },
470 .encode = .{ .eor, .Xd, .Xn, .{ .register = .Xm } },544 .encode = .{ .eor, .Xd, .Xn, .{ .register = .Xm } },
471 },545 },
472 .{546 .{
473 .pattern = "EOR <Xd>, <Xn>, <Xm>, <shift> #<amount>",547 .pattern = "EOR <Xd>, <Xn>, <Xm>, <shift> #<amount>",
474 .symbols = .{548 .symbols = .{
475 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },549 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
476 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },550 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
477 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },551 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
478 .shift = .{ .shift = .{} },552 .shift = .{ .shift = .{} },
479 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },553 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
480 },554 },
481 .encode = .{ .eor, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },555 .encode = .{ .eor, .Xd, .Xn, .{ .shifted_register_explicit = .{
556 .register = .Xm,
557 .shift = .shift,
558 .amount = .amount,
559 } } },
482 },560 },
483 // C6.2.124 EXTR561 // C6.2.124 EXTR
484 .{562 .{
485 .pattern = "EXTR <Wd>, <Wn>, <Wm>, #<lsb>",563 .pattern = "EXTR <Wd>, <Wn>, <Wm>, #<lsb>",
486 .symbols = .{564 .symbols = .{
487 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },565 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
488 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },566 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
489 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },567 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
490 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },568 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
491 },569 },
492 .encode = .{ .extr, .Wd, .Wn, .Wm, .lsb },570 .encode = .{ .extr, .Wd, .Wn, .Wm, .lsb },
...@@ -494,9 +572,9 @@...@@ -494,9 +572,9 @@
494 .{572 .{
495 .pattern = "EXTR <Xd>, <Xn>, <Xm>, #<lsb>",573 .pattern = "EXTR <Xd>, <Xn>, <Xm>, #<lsb>",
496 .symbols = .{574 .symbols = .{
497 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },575 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
498 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },576 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
499 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },577 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
500 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },578 .lsb = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
501 },579 },
502 .encode = .{ .extr, .Xd, .Xn, .Xm, .lsb },580 .encode = .{ .extr, .Xd, .Xn, .Xm, .lsb },
...@@ -528,43 +606,37 @@...@@ -528,43 +606,37 @@
528 // C6.2.129 IC606 // C6.2.129 IC
529 .{607 .{
530 .pattern = "IC IALLUIS",608 .pattern = "IC IALLUIS",
531 .symbols = .{609 .symbols = .{},
532 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
533 },
534 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .xzr },610 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .xzr },
535 },611 },
536 .{612 .{
537 .pattern = "IC IALLUIS, <Xt>",613 .pattern = "IC IALLUIS, <Xt>",
538 .symbols = .{614 .symbols = .{
539 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },615 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
540 },616 },
541 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .Xt },617 .encode = .{ .sys, 0b000, 0b0111, 0b0001, 0b000, .Xt },
542 },618 },
543 .{619 .{
544 .pattern = "IC IALLU",620 .pattern = "IC IALLU",
545 .symbols = .{621 .symbols = .{},
546 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
547 },
548 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .xzr },622 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .xzr },
549 },623 },
550 .{624 .{
551 .pattern = "IC IALLU, <Xt>",625 .pattern = "IC IALLU, <Xt>",
552 .symbols = .{626 .symbols = .{
553 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },627 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
554 },628 },
555 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .Xt },629 .encode = .{ .sys, 0b000, 0b0111, 0b0101, 0b000, .Xt },
556 },630 },
557 .{631 .{
558 .pattern = "IC IVAU",632 .pattern = "IC IVAU",
559 .symbols = .{633 .symbols = .{},
560 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
561 },
562 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .xzr },634 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .xzr },
563 },635 },
564 .{636 .{
565 .pattern = "IC IVAU, <Xt>",637 .pattern = "IC IVAU, <Xt>",
566 .symbols = .{638 .symbols = .{
567 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },639 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
568 },640 },
569 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .Xt },641 .encode = .{ .sys, 0b011, 0b0111, 0b0101, 0b001, .Xt },
570 },642 },
...@@ -592,9 +664,9 @@...@@ -592,9 +664,9 @@
592 .{664 .{
593 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",665 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",
594 .symbols = .{666 .symbols = .{
595 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },667 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
596 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },668 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
597 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },669 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
598 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },670 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
599 },671 },
600 .encode = .{ .ldp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },672 .encode = .{ .ldp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
...@@ -602,9 +674,9 @@...@@ -602,9 +674,9 @@
602 .{674 .{
603 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",675 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",
604 .symbols = .{676 .symbols = .{
605 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },677 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
606 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },678 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
607 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },679 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
608 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },680 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
609 },681 },
610 .encode = .{ .ldp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },682 .encode = .{ .ldp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
...@@ -612,9 +684,9 @@...@@ -612,9 +684,9 @@
612 .{684 .{
613 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",685 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",
614 .symbols = .{686 .symbols = .{
615 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },687 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
616 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },688 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
617 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },689 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
618 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },690 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
619 },691 },
620 .encode = .{ .ldp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },692 .encode = .{ .ldp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
...@@ -622,9 +694,9 @@...@@ -622,9 +694,9 @@
622 .{694 .{
623 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",695 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",
624 .symbols = .{696 .symbols = .{
625 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },697 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
626 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },698 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
627 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },699 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
628 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },700 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
629 },701 },
630 .encode = .{ .ldp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },702 .encode = .{ .ldp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
...@@ -632,18 +704,18 @@...@@ -632,18 +704,18 @@
632 .{704 .{
633 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>]",705 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>]",
634 .symbols = .{706 .symbols = .{
635 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },707 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
636 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },708 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
637 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },709 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
638 },710 },
639 .encode = .{ .ldp, .Wt1, .Wt2, .{ .base = .Xn } },711 .encode = .{ .ldp, .Wt1, .Wt2, .{ .base = .Xn } },
640 },712 },
641 .{713 .{
642 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",714 .pattern = "LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",
643 .symbols = .{715 .symbols = .{
644 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },716 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
645 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },717 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
646 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },718 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
647 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },719 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
648 },720 },
649 .encode = .{ .ldp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },721 .encode = .{ .ldp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
...@@ -651,18 +723,18 @@...@@ -651,18 +723,18 @@
651 .{723 .{
652 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>]",724 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>]",
653 .symbols = .{725 .symbols = .{
654 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },726 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
655 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },727 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
656 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },728 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
657 },729 },
658 .encode = .{ .ldp, .Xt1, .Xt2, .{ .base = .Xn } },730 .encode = .{ .ldp, .Xt1, .Xt2, .{ .base = .Xn } },
659 },731 },
660 .{732 .{
661 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",733 .pattern = "LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",
662 .symbols = .{734 .symbols = .{
663 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },735 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
664 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },736 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
665 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },737 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
666 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },738 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
667 },739 },
668 .encode = .{ .ldp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },740 .encode = .{ .ldp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
...@@ -671,8 +743,8 @@...@@ -671,8 +743,8 @@
671 .{743 .{
672 .pattern = "LDR <Wt>, [<Xn|SP>], #<simm>",744 .pattern = "LDR <Wt>, [<Xn|SP>], #<simm>",
673 .symbols = .{745 .symbols = .{
674 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },746 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
675 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },747 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
676 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },748 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
677 },749 },
678 .encode = .{ .ldr, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },750 .encode = .{ .ldr, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
...@@ -680,8 +752,8 @@...@@ -680,8 +752,8 @@
680 .{752 .{
681 .pattern = "LDR <Xt>, [<Xn|SP>], #<simm>",753 .pattern = "LDR <Xt>, [<Xn|SP>], #<simm>",
682 .symbols = .{754 .symbols = .{
683 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },755 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
684 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },756 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
685 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },757 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
686 },758 },
687 .encode = .{ .ldr, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },759 .encode = .{ .ldr, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
...@@ -689,8 +761,8 @@...@@ -689,8 +761,8 @@
689 .{761 .{
690 .pattern = "LDR <Wt>, [<Xn|SP>, #<simm>]!",762 .pattern = "LDR <Wt>, [<Xn|SP>, #<simm>]!",
691 .symbols = .{763 .symbols = .{
692 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },764 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
693 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },765 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
694 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },766 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
695 },767 },
696 .encode = .{ .ldr, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },768 .encode = .{ .ldr, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
...@@ -698,8 +770,8 @@...@@ -698,8 +770,8 @@
698 .{770 .{
699 .pattern = "LDR <Xt>, [<Xn|SP>, #<simm>]!",771 .pattern = "LDR <Xt>, [<Xn|SP>, #<simm>]!",
700 .symbols = .{772 .symbols = .{
701 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },773 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
702 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },774 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
703 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },775 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
704 },776 },
705 .encode = .{ .ldr, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },777 .encode = .{ .ldr, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
...@@ -707,16 +779,16 @@...@@ -707,16 +779,16 @@
707 .{779 .{
708 .pattern = "LDR <Wt>, [<Xn|SP>]",780 .pattern = "LDR <Wt>, [<Xn|SP>]",
709 .symbols = .{781 .symbols = .{
710 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },782 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
711 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },783 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
712 },784 },
713 .encode = .{ .ldr, .Wt, .{ .base = .Xn } },785 .encode = .{ .ldr, .Wt, .{ .base = .Xn } },
714 },786 },
715 .{787 .{
716 .pattern = "LDR <Wt>, [<Xn|SP>, #<pimm>]",788 .pattern = "LDR <Wt>, [<Xn|SP>, #<pimm>]",
717 .symbols = .{789 .symbols = .{
718 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },790 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
719 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },791 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
720 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },792 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },
721 },793 },
722 .encode = .{ .ldr, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },794 .encode = .{ .ldr, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
...@@ -724,16 +796,16 @@...@@ -724,16 +796,16 @@
724 .{796 .{
725 .pattern = "LDR <Xt>, [<Xn|SP>]",797 .pattern = "LDR <Xt>, [<Xn|SP>]",
726 .symbols = .{798 .symbols = .{
727 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },799 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
728 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },800 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
729 },801 },
730 .encode = .{ .ldr, .Xt, .{ .base = .Xn } },802 .encode = .{ .ldr, .Xt, .{ .base = .Xn } },
731 },803 },
732 .{804 .{
733 .pattern = "LDR <Xt>, [<Xn|SP>, #<pimm>]",805 .pattern = "LDR <Xt>, [<Xn|SP>, #<pimm>]",
734 .symbols = .{806 .symbols = .{
735 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },807 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
736 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },808 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
737 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },809 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },
738 },810 },
739 .encode = .{ .ldr, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },811 .encode = .{ .ldr, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
...@@ -742,18 +814,18 @@...@@ -742,18 +814,18 @@
742 .{814 .{
743 .pattern = "LSL <Wd>, <Wn>, <Wm>",815 .pattern = "LSL <Wd>, <Wn>, <Wm>",
744 .symbols = .{816 .symbols = .{
745 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },817 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
746 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },818 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
747 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },819 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
748 },820 },
749 .encode = .{ .lslv, .Wd, .Wn, .Wm },821 .encode = .{ .lslv, .Wd, .Wn, .Wm },
750 },822 },
751 .{823 .{
752 .pattern = "LSL <Xd>, <Xn>, <Xm>",824 .pattern = "LSL <Xd>, <Xn>, <Xm>",
753 .symbols = .{825 .symbols = .{
754 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },826 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
755 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },827 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
756 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },828 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
757 },829 },
758 .encode = .{ .lslv, .Xd, .Xn, .Xm },830 .encode = .{ .lslv, .Xd, .Xn, .Xm },
759 },831 },
...@@ -761,18 +833,18 @@...@@ -761,18 +833,18 @@
761 .{833 .{
762 .pattern = "LSLV <Wd>, <Wn>, <Wm>",834 .pattern = "LSLV <Wd>, <Wn>, <Wm>",
763 .symbols = .{835 .symbols = .{
764 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },836 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
765 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },837 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
766 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },838 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
767 },839 },
768 .encode = .{ .lslv, .Wd, .Wn, .Wm },840 .encode = .{ .lslv, .Wd, .Wn, .Wm },
769 },841 },
770 .{842 .{
771 .pattern = "LSLV <Xd>, <Xn>, <Xm>",843 .pattern = "LSLV <Xd>, <Xn>, <Xm>",
772 .symbols = .{844 .symbols = .{
773 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },845 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
774 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },846 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
775 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },847 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
776 },848 },
777 .encode = .{ .lslv, .Xd, .Xn, .Xm },849 .encode = .{ .lslv, .Xd, .Xn, .Xm },
778 },850 },
...@@ -780,18 +852,18 @@...@@ -780,18 +852,18 @@
780 .{852 .{
781 .pattern = "LSR <Wd>, <Wn>, <Wm>",853 .pattern = "LSR <Wd>, <Wn>, <Wm>",
782 .symbols = .{854 .symbols = .{
783 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },855 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
784 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },856 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
785 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },857 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
786 },858 },
787 .encode = .{ .lsrv, .Wd, .Wn, .Wm },859 .encode = .{ .lsrv, .Wd, .Wn, .Wm },
788 },860 },
789 .{861 .{
790 .pattern = "LSR <Xd>, <Xn>, <Xm>",862 .pattern = "LSR <Xd>, <Xn>, <Xm>",
791 .symbols = .{863 .symbols = .{
792 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },864 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
793 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },865 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
794 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },866 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
795 },867 },
796 .encode = .{ .lsrv, .Xd, .Xn, .Xm },868 .encode = .{ .lsrv, .Xd, .Xn, .Xm },
797 },869 },
...@@ -799,47 +871,87 @@...@@ -799,47 +871,87 @@
799 .{871 .{
800 .pattern = "LSRV <Wd>, <Wn>, <Wm>",872 .pattern = "LSRV <Wd>, <Wn>, <Wm>",
801 .symbols = .{873 .symbols = .{
802 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },874 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
803 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },875 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
804 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },876 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
805 },877 },
806 .encode = .{ .lsrv, .Wd, .Wn, .Wm },878 .encode = .{ .lsrv, .Wd, .Wn, .Wm },
807 },879 },
808 .{880 .{
809 .pattern = "LSRV <Xd>, <Xn>, <Xm>",881 .pattern = "LSRV <Xd>, <Xn>, <Xm>",
810 .symbols = .{882 .symbols = .{
811 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },883 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
812 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },884 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
813 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },885 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
814 },886 },
815 .encode = .{ .lsrv, .Xd, .Xn, .Xm },887 .encode = .{ .lsrv, .Xd, .Xn, .Xm },
816 },888 },
889 // C6.2.218 MADD
890 .{
891 .pattern = "MADD <Wd>, <Wn>, <Wm>, <Wa>",
892 .symbols = .{
893 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
894 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
895 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
896 .Wa = .{ .reg = .{ .format = .{ .general = .word } } },
897 },
898 .encode = .{ .madd, .Wd, .Wn, .Wm, .Wa },
899 },
900 .{
901 .pattern = "MADD <Xd>, <Xn>, <Xm>, <Xa>",
902 .symbols = .{
903 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
904 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
905 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
906 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
907 },
908 .encode = .{ .madd, .Xd, .Xn, .Xm, .Xa },
909 },
910 // C6.2.219 MNEG
911 .{
912 .pattern = "MNEG <Wd>, <Wn>, <Wm>",
913 .symbols = .{
914 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
915 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
916 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
917 },
918 .encode = .{ .msub, .Wd, .Wn, .Wm, .wzr },
919 },
920 .{
921 .pattern = "MNEG <Xd>, <Xn>, <Xm>",
922 .symbols = .{
923 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
924 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
925 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
926 },
927 .encode = .{ .msub, .Xd, .Xn, .Xm, .xzr },
928 },
817 // C6.2.220 MOV (to/from SP)929 // C6.2.220 MOV (to/from SP)
818 .{930 .{
819 .pattern = "MOV WSP, <Wn|WSP>",931 .pattern = "MOV WSP, <Wn|WSP>",
820 .symbols = .{932 .symbols = .{
821 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },933 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
822 },934 },
823 .encode = .{ .add, .wsp, .Wn, .{ .immediate = 0 } },935 .encode = .{ .add, .wsp, .Wn, .{ .immediate = 0 } },
824 },936 },
825 .{937 .{
826 .pattern = "MOV <Wd|WSP>, WSP",938 .pattern = "MOV <Wd|WSP>, WSP",
827 .symbols = .{939 .symbols = .{
828 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },940 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
829 },941 },
830 .encode = .{ .add, .Wd, .wsp, .{ .immediate = 0 } },942 .encode = .{ .add, .Wd, .wsp, .{ .immediate = 0 } },
831 },943 },
832 .{944 .{
833 .pattern = "MOV SP, <Xn|SP>",945 .pattern = "MOV SP, <Xn|SP>",
834 .symbols = .{946 .symbols = .{
835 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },947 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
836 },948 },
837 .encode = .{ .add, .sp, .Xn, .{ .immediate = 0 } },949 .encode = .{ .add, .sp, .Xn, .{ .immediate = 0 } },
838 },950 },
839 .{951 .{
840 .pattern = "MOV <Xd|SP>, SP",952 .pattern = "MOV <Xd|SP>, SP",
841 .symbols = .{953 .symbols = .{
842 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },954 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
843 },955 },
844 .encode = .{ .add, .Xd, .sp, .{ .immediate = 0 } },956 .encode = .{ .add, .Xd, .sp, .{ .immediate = 0 } },
845 },957 },
...@@ -847,7 +959,7 @@...@@ -847,7 +959,7 @@
847 .{959 .{
848 .pattern = "MOV <Wd>, #<imm>",960 .pattern = "MOV <Wd>, #<imm>",
849 .symbols = .{961 .symbols = .{
850 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },962 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
851 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },963 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
852 },964 },
853 .encode = .{ .movz, .Wd, .imm, .{ .lsl = .@"0" } },965 .encode = .{ .movz, .Wd, .imm, .{ .lsl = .@"0" } },
...@@ -855,7 +967,7 @@...@@ -855,7 +967,7 @@
855 .{967 .{
856 .pattern = "MOV <Xd>, #<imm>",968 .pattern = "MOV <Xd>, #<imm>",
857 .symbols = .{969 .symbols = .{
858 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },970 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
859 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },971 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
860 },972 },
861 .encode = .{ .movz, .Xd, .imm, .{ .lsl = .@"0" } },973 .encode = .{ .movz, .Xd, .imm, .{ .lsl = .@"0" } },
...@@ -864,16 +976,16 @@...@@ -864,16 +976,16 @@
864 .{976 .{
865 .pattern = "MOV <Wd>, <Wm>",977 .pattern = "MOV <Wd>, <Wm>",
866 .symbols = .{978 .symbols = .{
867 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },979 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
868 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },980 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
869 },981 },
870 .encode = .{ .orr, .Wd, .wzr, .{ .register = .Wm } },982 .encode = .{ .orr, .Wd, .wzr, .{ .register = .Wm } },
871 },983 },
872 .{984 .{
873 .pattern = "MOV <Xd>, <Xm>",985 .pattern = "MOV <Xd>, <Xm>",
874 .symbols = .{986 .symbols = .{
875 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },987 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
876 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },988 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
877 },989 },
878 .encode = .{ .orr, .Xd, .xzr, .{ .register = .Xm } },990 .encode = .{ .orr, .Xd, .xzr, .{ .register = .Xm } },
879 },991 },
...@@ -881,7 +993,7 @@...@@ -881,7 +993,7 @@
881 .{993 .{
882 .pattern = "MOVK <Wd>, #<imm>",994 .pattern = "MOVK <Wd>, #<imm>",
883 .symbols = .{995 .symbols = .{
884 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },996 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
885 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },997 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
886 },998 },
887 .encode = .{ .movk, .Wd, .imm, .{} },999 .encode = .{ .movk, .Wd, .imm, .{} },
...@@ -889,7 +1001,7 @@...@@ -889,7 +1001,7 @@
889 .{1001 .{
890 .pattern = "MOVK <Wd>, #<imm>, LSL #<shift>",1002 .pattern = "MOVK <Wd>, #<imm>, LSL #<shift>",
891 .symbols = .{1003 .symbols = .{
892 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1004 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
893 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1005 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
894 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },1006 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
895 },1007 },
...@@ -898,7 +1010,7 @@...@@ -898,7 +1010,7 @@
898 .{1010 .{
899 .pattern = "MOVK <Xd>, #<imm>",1011 .pattern = "MOVK <Xd>, #<imm>",
900 .symbols = .{1012 .symbols = .{
901 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1013 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
902 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1014 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
903 },1015 },
904 .encode = .{ .movk, .Xd, .imm, .{} },1016 .encode = .{ .movk, .Xd, .imm, .{} },
...@@ -906,7 +1018,7 @@...@@ -906,7 +1018,7 @@
906 .{1018 .{
907 .pattern = "MOVK <Xd>, #<imm>, LSL #<shift>",1019 .pattern = "MOVK <Xd>, #<imm>, LSL #<shift>",
908 .symbols = .{1020 .symbols = .{
909 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1021 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
910 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1022 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
911 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },1023 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
912 },1024 },
...@@ -916,7 +1028,7 @@...@@ -916,7 +1028,7 @@
916 .{1028 .{
917 .pattern = "MOVN <Wd>, #<imm>",1029 .pattern = "MOVN <Wd>, #<imm>",
918 .symbols = .{1030 .symbols = .{
919 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1031 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
920 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1032 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
921 },1033 },
922 .encode = .{ .movn, .Wd, .imm, .{} },1034 .encode = .{ .movn, .Wd, .imm, .{} },
...@@ -924,7 +1036,7 @@...@@ -924,7 +1036,7 @@
924 .{1036 .{
925 .pattern = "MOVN <Wd>, #<imm>, LSL #<shift>",1037 .pattern = "MOVN <Wd>, #<imm>, LSL #<shift>",
926 .symbols = .{1038 .symbols = .{
927 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1039 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
928 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1040 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
929 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },1041 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
930 },1042 },
...@@ -933,7 +1045,7 @@...@@ -933,7 +1045,7 @@
933 .{1045 .{
934 .pattern = "MOVN <Xd>, #<imm>",1046 .pattern = "MOVN <Xd>, #<imm>",
935 .symbols = .{1047 .symbols = .{
936 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1048 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
937 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1049 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
938 },1050 },
939 .encode = .{ .movn, .Xd, .imm, .{} },1051 .encode = .{ .movn, .Xd, .imm, .{} },
...@@ -941,7 +1053,7 @@...@@ -941,7 +1053,7 @@
941 .{1053 .{
942 .pattern = "MOVN <Xd>, #<imm>, LSL #<shift>",1054 .pattern = "MOVN <Xd>, #<imm>, LSL #<shift>",
943 .symbols = .{1055 .symbols = .{
944 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1056 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
945 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1057 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
946 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },1058 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
947 },1059 },
...@@ -951,7 +1063,7 @@...@@ -951,7 +1063,7 @@
951 .{1063 .{
952 .pattern = "MOVZ <Wd>, #<imm>",1064 .pattern = "MOVZ <Wd>, #<imm>",
953 .symbols = .{1065 .symbols = .{
954 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1066 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
955 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1067 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
956 },1068 },
957 .encode = .{ .movz, .Wd, .imm, .{} },1069 .encode = .{ .movz, .Wd, .imm, .{} },
...@@ -959,7 +1071,7 @@...@@ -959,7 +1071,7 @@
959 .{1071 .{
960 .pattern = "MOVZ <Wd>, #<imm>, LSL #<shift>",1072 .pattern = "MOVZ <Wd>, #<imm>, LSL #<shift>",
961 .symbols = .{1073 .symbols = .{
962 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1074 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
963 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1075 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
964 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },1076 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 }, .multiple_of = 16 } },
965 },1077 },
...@@ -968,7 +1080,7 @@...@@ -968,7 +1080,7 @@
968 .{1080 .{
969 .pattern = "MOVZ <Xd>, #<imm>",1081 .pattern = "MOVZ <Xd>, #<imm>",
970 .symbols = .{1082 .symbols = .{
971 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1083 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
972 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1084 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
973 },1085 },
974 .encode = .{ .movz, .Xd, .imm, .{} },1086 .encode = .{ .movz, .Xd, .imm, .{} },
...@@ -976,7 +1088,7 @@...@@ -976,7 +1088,7 @@
976 .{1088 .{
977 .pattern = "MOVZ <Xd>, #<imm>, LSL #<shift>",1089 .pattern = "MOVZ <Xd>, #<imm>, LSL #<shift>",
978 .symbols = .{1090 .symbols = .{
979 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1091 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
980 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },1092 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 16 } } },
981 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },1093 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 }, .multiple_of = 16 } },
982 },1094 },
...@@ -986,7 +1098,7 @@...@@ -986,7 +1098,7 @@
986 .{1098 .{
987 .pattern = "MRS <Xt>, <systemreg>",1099 .pattern = "MRS <Xt>, <systemreg>",
988 .symbols = .{1100 .symbols = .{
989 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1101 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
990 .systemreg = .systemreg,1102 .systemreg = .systemreg,
991 },1103 },
992 .encode = .{ .mrs, .Xt, .systemreg },1104 .encode = .{ .mrs, .Xt, .systemreg },
...@@ -996,46 +1108,94 @@...@@ -996,46 +1108,94 @@
996 .pattern = "MSR <systemreg>, <Xt>",1108 .pattern = "MSR <systemreg>, <Xt>",
997 .symbols = .{1109 .symbols = .{
998 .systemreg = .systemreg,1110 .systemreg = .systemreg,
999 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1111 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1000 },1112 },
1001 .encode = .{ .msr, .systemreg, .Xt },1113 .encode = .{ .msr, .systemreg, .Xt },
1002 },1114 },
1115 // C6.2.231 MSUB
1116 .{
1117 .pattern = "MSUB <Wd>, <Wn>, <Wm>, <Wa>",
1118 .symbols = .{
1119 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1120 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1121 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1122 .Wa = .{ .reg = .{ .format = .{ .general = .word } } },
1123 },
1124 .encode = .{ .msub, .Wd, .Wn, .Wm, .Wa },
1125 },
1126 .{
1127 .pattern = "MSUB <Xd>, <Xn>, <Xm>, <Xa>",
1128 .symbols = .{
1129 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1130 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1131 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1132 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1133 },
1134 .encode = .{ .msub, .Xd, .Xn, .Xm, .Xa },
1135 },
1136 // C6.2.232 MUL
1137 .{
1138 .pattern = "MUL <Wd>, <Wn>, <Wm>",
1139 .symbols = .{
1140 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1141 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1142 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1143 },
1144 .encode = .{ .madd, .Wd, .Wn, .Wm, .wzr },
1145 },
1146 .{
1147 .pattern = "MUL <Xd>, <Xn>, <Xm>",
1148 .symbols = .{
1149 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1150 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1151 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1152 },
1153 .encode = .{ .madd, .Xd, .Xn, .Xm, .xzr },
1154 },
1003 // C6.2.234 NEG1155 // C6.2.234 NEG
1004 .{1156 .{
1005 .pattern = "NEG <Wd>, <Wm>",1157 .pattern = "NEG <Wd>, <Wm>",
1006 .symbols = .{1158 .symbols = .{
1007 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1159 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1008 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1160 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1009 },1161 },
1010 .encode = .{ .sub, .Wd, .wzr, .{ .register = .Wm } },1162 .encode = .{ .sub, .Wd, .wzr, .{ .register = .Wm } },
1011 },1163 },
1012 .{1164 .{
1013 .pattern = "NEG <Wd>, <Wm>, <shift> #<amount>",1165 .pattern = "NEG <Wd>, <Wm>, <shift> #<amount>",
1014 .symbols = .{1166 .symbols = .{
1015 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1016 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1168 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1017 .shift = .{ .shift = .{ .allow_ror = false } },1169 .shift = .{ .shift = .{ .allow_ror = false } },
1018 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1170 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1019 },1171 },
1020 .encode = .{ .sub, .Wd, .wzr, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },1172 .encode = .{ .sub, .Wd, .wzr, .{ .shifted_register_explicit = .{
1173 .register = .Wm,
1174 .shift = .shift,
1175 .amount = .amount,
1176 } } },
1021 },1177 },
1022 .{1178 .{
1023 .pattern = "NEG <Xd>, <Xm>",1179 .pattern = "NEG <Xd>, <Xm>",
1024 .symbols = .{1180 .symbols = .{
1025 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1181 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1026 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1182 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1027 },1183 },
1028 .encode = .{ .sub, .Xd, .xzr, .{ .register = .Xm } },1184 .encode = .{ .sub, .Xd, .xzr, .{ .register = .Xm } },
1029 },1185 },
1030 .{1186 .{
1031 .pattern = "NEG <Xd>, <Xm>, <shift> #<amount>",1187 .pattern = "NEG <Xd>, <Xm>, <shift> #<amount>",
1032 .symbols = .{1188 .symbols = .{
1033 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1189 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1034 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1190 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1035 .shift = .{ .shift = .{ .allow_ror = false } },1191 .shift = .{ .shift = .{ .allow_ror = false } },
1036 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1192 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1037 },1193 },
1038 .encode = .{ .sub, .Xd, .xzr, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },1194 .encode = .{ .sub, .Xd, .xzr, .{ .shifted_register_explicit = .{
1195 .register = .Xm,
1196 .shift = .shift,
1197 .amount = .amount,
1198 } } },
1039 },1199 },
1040 // C6.2.238 NOP1200 // C6.2.238 NOP
1041 .{1201 .{
...@@ -1047,42 +1207,67 @@...@@ -1047,42 +1207,67 @@
1047 .{1207 .{
1048 .pattern = "ORR <Wd>, <Wn>, <Wm>",1208 .pattern = "ORR <Wd>, <Wn>, <Wm>",
1049 .symbols = .{1209 .symbols = .{
1050 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1210 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1051 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1211 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1052 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1212 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1053 },1213 },
1054 .encode = .{ .orr, .Wd, .Wn, .{ .register = .Wm } },1214 .encode = .{ .orr, .Wd, .Wn, .{ .register = .Wm } },
1055 },1215 },
1056 .{1216 .{
1057 .pattern = "ORR <Wd>, <Wn>, <Wm>, <shift> #<amount>",1217 .pattern = "ORR <Wd>, <Wn>, <Wm>, <shift> #<amount>",
1058 .symbols = .{1218 .symbols = .{
1059 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1219 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1060 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1220 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1061 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1221 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1062 .shift = .{ .shift = .{} },1222 .shift = .{ .shift = .{} },
1063 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1223 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1064 },1224 },
1065 .encode = .{ .orr, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },1225 .encode = .{ .orr, .Wd, .Wn, .{ .shifted_register_explicit = .{
1226 .register = .Wm,
1227 .shift = .shift,
1228 .amount = .amount,
1229 } } },
1066 },1230 },
1067 .{1231 .{
1068 .pattern = "ORR <Xd>, <Xn>, <Xm>",1232 .pattern = "ORR <Xd>, <Xn>, <Xm>",
1069 .symbols = .{1233 .symbols = .{
1070 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1234 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1071 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1235 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1072 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1236 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1073 },1237 },
1074 .encode = .{ .orr, .Xd, .Xn, .{ .register = .Xm } },1238 .encode = .{ .orr, .Xd, .Xn, .{ .register = .Xm } },
1075 },1239 },
1076 .{1240 .{
1077 .pattern = "ORR <Xd>, <Xn>, <Xm>, <shift> #<amount>",1241 .pattern = "ORR <Xd>, <Xn>, <Xm>, <shift> #<amount>",
1078 .symbols = .{1242 .symbols = .{
1079 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1243 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1080 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1244 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1081 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1245 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1082 .shift = .{ .shift = .{} },1246 .shift = .{ .shift = .{} },
1083 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1247 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1084 },1248 },
1085 .encode = .{ .orr, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },1249 .encode = .{ .orr, .Xd, .Xn, .{ .shifted_register_explicit = .{
1250 .register = .Xm,
1251 .shift = .shift,
1252 .amount = .amount,
1253 } } },
1254 },
1255 // C6.2.253 RBIT
1256 .{
1257 .pattern = "RBIT <Wd>, <Wn>",
1258 .symbols = .{
1259 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1260 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1261 },
1262 .encode = .{ .rbit, .Wd, .Wn },
1263 },
1264 .{
1265 .pattern = "RBIT <Xd>, <Xn>",
1266 .symbols = .{
1267 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1268 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1269 },
1270 .encode = .{ .rbit, .Xd, .Xn },
1086 },1271 },
1087 // C6.2.254 RET1272 // C6.2.254 RET
1088 .{1273 .{
...@@ -1093,16 +1278,68 @@...@@ -1093,16 +1278,68 @@
1093 .{1278 .{
1094 .pattern = "RET <Xn>",1279 .pattern = "RET <Xn>",
1095 .symbols = .{1280 .symbols = .{
1096 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1281 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1097 },1282 },
1098 .encode = .{ .ret, .Xn },1283 .encode = .{ .ret, .Xn },
1099 },1284 },
1285 // C6.2.256 REV
1286 .{
1287 .pattern = "REV <Wd>, <Wn>",
1288 .symbols = .{
1289 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1290 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1291 },
1292 .encode = .{ .rev, .Wd, .Wn },
1293 },
1294 .{
1295 .pattern = "REV <Xd>, <Xn>",
1296 .symbols = .{
1297 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1298 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1299 },
1300 .encode = .{ .rev, .Xd, .Xn },
1301 },
1302 // C6.2.257 REV16
1303 .{
1304 .pattern = "REV16 <Wd>, <Wn>",
1305 .symbols = .{
1306 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1307 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1308 },
1309 .encode = .{ .rev16, .Wd, .Wn },
1310 },
1311 .{
1312 .pattern = "REV16 <Xd>, <Xn>",
1313 .symbols = .{
1314 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1315 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1316 },
1317 .encode = .{ .rev16, .Xd, .Xn },
1318 },
1319 // C6.2.258 REV32
1320 .{
1321 .pattern = "REV32 <Xd>, <Xn>",
1322 .symbols = .{
1323 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1324 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1325 },
1326 .encode = .{ .rev32, .Xd, .Xn },
1327 },
1328 // C6.2.259 REV64
1329 .{
1330 .pattern = "REV64 <Xd>, <Xn>",
1331 .symbols = .{
1332 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1333 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1334 },
1335 .encode = .{ .rev, .Xd, .Xn },
1336 },
1100 // C6.2.261 ROR (immediate)1337 // C6.2.261 ROR (immediate)
1101 .{1338 .{
1102 .pattern = "ROR <Wd>, <Ws>, #<shift>",1339 .pattern = "ROR <Wd>, <Ws>, #<shift>",
1103 .symbols = .{1340 .symbols = .{
1104 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1341 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1105 .Ws = .{ .reg = .{ .format = .{ .integer = .word } } },1342 .Ws = .{ .reg = .{ .format = .{ .general = .word } } },
1106 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1343 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1107 },1344 },
1108 .encode = .{ .extr, .Wd, .Ws, .Ws, .shift },1345 .encode = .{ .extr, .Wd, .Ws, .Ws, .shift },
...@@ -1110,8 +1347,8 @@...@@ -1110,8 +1347,8 @@
1110 .{1347 .{
1111 .pattern = "ROR <Xd>, <Xs>, #<shift>",1348 .pattern = "ROR <Xd>, <Xs>, #<shift>",
1112 .symbols = .{1349 .symbols = .{
1113 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1350 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1114 .Xs = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1351 .Xs = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1115 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1352 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1116 },1353 },
1117 .encode = .{ .extr, .Xd, .Xs, .Xs, .shift },1354 .encode = .{ .extr, .Xd, .Xs, .Xs, .shift },
...@@ -1120,18 +1357,18 @@...@@ -1120,18 +1357,18 @@
1120 .{1357 .{
1121 .pattern = "ROR <Wd>, <Wn>, <Wm>",1358 .pattern = "ROR <Wd>, <Wn>, <Wm>",
1122 .symbols = .{1359 .symbols = .{
1123 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1360 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1124 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1361 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1125 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1362 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1126 },1363 },
1127 .encode = .{ .rorv, .Wd, .Wn, .Wm },1364 .encode = .{ .rorv, .Wd, .Wn, .Wm },
1128 },1365 },
1129 .{1366 .{
1130 .pattern = "ROR <Xd>, <Xn>, <Xm>",1367 .pattern = "ROR <Xd>, <Xn>, <Xm>",
1131 .symbols = .{1368 .symbols = .{
1132 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1369 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1133 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1370 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1134 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1371 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1135 },1372 },
1136 .encode = .{ .rorv, .Xd, .Xn, .Xm },1373 .encode = .{ .rorv, .Xd, .Xn, .Xm },
1137 },1374 },
...@@ -1139,18 +1376,18 @@...@@ -1139,18 +1376,18 @@
1139 .{1376 .{
1140 .pattern = "RORV <Wd>, <Wn>, <Wm>",1377 .pattern = "RORV <Wd>, <Wn>, <Wm>",
1141 .symbols = .{1378 .symbols = .{
1142 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1379 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1143 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1380 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1144 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1381 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1145 },1382 },
1146 .encode = .{ .rorv, .Wd, .Wn, .Wm },1383 .encode = .{ .rorv, .Wd, .Wn, .Wm },
1147 },1384 },
1148 .{1385 .{
1149 .pattern = "RORV <Xd>, <Xn>, <Xm>",1386 .pattern = "RORV <Xd>, <Xn>, <Xm>",
1150 .symbols = .{1387 .symbols = .{
1151 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1388 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1152 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1389 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1153 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1390 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1154 },1391 },
1155 .encode = .{ .rorv, .Xd, .Xn, .Xm },1392 .encode = .{ .rorv, .Xd, .Xn, .Xm },
1156 },1393 },
...@@ -1158,8 +1395,8 @@...@@ -1158,8 +1395,8 @@
1158 .{1395 .{
1159 .pattern = "SBFM <Wd>, <Wn>, #<immr>, #<imms>",1396 .pattern = "SBFM <Wd>, <Wn>, #<immr>, #<imms>",
1160 .symbols = .{1397 .symbols = .{
1161 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1398 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1162 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1399 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1163 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1400 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1164 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1401 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1165 },1402 },
...@@ -1168,13 +1405,32 @@...@@ -1168,13 +1405,32 @@
1168 .{1405 .{
1169 .pattern = "SBFM <Xd>, <Xn>, #<immr>, #<imms>",1406 .pattern = "SBFM <Xd>, <Xn>, #<immr>, #<imms>",
1170 .symbols = .{1407 .symbols = .{
1171 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1408 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1172 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1409 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1173 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1410 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1174 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1411 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1175 },1412 },
1176 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },1413 .encode = .{ .sbfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
1177 },1414 },
1415 // C6.2.270 SDIV
1416 .{
1417 .pattern = "SDIV <Wd>, <Wn>, <Wm>",
1418 .symbols = .{
1419 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1420 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1421 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1422 },
1423 .encode = .{ .sdiv, .Wd, .Wn, .Wm },
1424 },
1425 .{
1426 .pattern = "SDIV <Xd>, <Xn>, <Xm>",
1427 .symbols = .{
1428 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1429 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1430 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1431 },
1432 .encode = .{ .sdiv, .Xd, .Xn, .Xm },
1433 },
1178 // C6.2.280 SEV1434 // C6.2.280 SEV
1179 .{1435 .{
1180 .pattern = "SEV",1436 .pattern = "SEV",
...@@ -1187,6 +1443,17 @@...@@ -1187,6 +1443,17 @@
1187 .symbols = .{},1443 .symbols = .{},
1188 .encode = .{.sevl},1444 .encode = .{.sevl},
1189 },1445 },
1446 // C6.2.282 SMADDL
1447 .{
1448 .pattern = "SMADDL <Xd>, <Wn>, <Wm>, <Xa>",
1449 .symbols = .{
1450 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1451 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1452 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1453 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1454 },
1455 .encode = .{ .smaddl, .Xd, .Wn, .Wm, .Xa },
1456 },
1190 // C6.2.283 SMC1457 // C6.2.283 SMC
1191 .{1458 .{
1192 .pattern = "SMC #<imm>",1459 .pattern = "SMC #<imm>",
...@@ -1195,13 +1462,54 @@...@@ -1195,13 +1462,54 @@
1195 },1462 },
1196 .encode = .{ .smc, .imm },1463 .encode = .{ .smc, .imm },
1197 },1464 },
1465 // C6.2.284 SMNEGL
1466 .{
1467 .pattern = "SMNEGL <Xd>, <Wn>, <Wm>",
1468 .symbols = .{
1469 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1470 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1471 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1472 },
1473 .encode = .{ .smsubl, .Xd, .Wn, .Wm, .xzr },
1474 },
1475 // C6.2.287 SMSUBL
1476 .{
1477 .pattern = "SMSUBL <Xd>, <Wn>, <Wm>, <Xa>",
1478 .symbols = .{
1479 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1480 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1481 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1482 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1483 },
1484 .encode = .{ .smsubl, .Xd, .Wn, .Wm, .Xa },
1485 },
1486 // C6.2.288 SMULH
1487 .{
1488 .pattern = "SMULH <Xd>, <Xn>, <Xm>",
1489 .symbols = .{
1490 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1491 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1492 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1493 },
1494 .encode = .{ .smulh, .Xd, .Xn, .Xm },
1495 },
1496 // C6.2.289 SMULL
1497 .{
1498 .pattern = "SMULL <Xd>, <Wn>, <Wm>",
1499 .symbols = .{
1500 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1501 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1502 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1503 },
1504 .encode = .{ .smaddl, .Xd, .Wn, .Wm, .xzr },
1505 },
1198 // C6.2.321 STP1506 // C6.2.321 STP
1199 .{1507 .{
1200 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",1508 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>",
1201 .symbols = .{1509 .symbols = .{
1202 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },1510 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1203 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },1511 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1204 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1512 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1205 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },1513 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
1206 },1514 },
1207 .encode = .{ .stp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },1515 .encode = .{ .stp, .Wt1, .Wt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
...@@ -1209,9 +1517,9 @@...@@ -1209,9 +1517,9 @@
1209 .{1517 .{
1210 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",1518 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>",
1211 .symbols = .{1519 .symbols = .{
1212 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1520 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1213 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1521 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1214 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1522 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1215 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },1523 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
1216 },1524 },
1217 .encode = .{ .stp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },1525 .encode = .{ .stp, .Xt1, .Xt2, .{ .post_index = .{ .base = .Xn, .index = .imm } } },
...@@ -1219,9 +1527,9 @@...@@ -1219,9 +1527,9 @@
1219 .{1527 .{
1220 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",1528 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!",
1221 .symbols = .{1529 .symbols = .{
1222 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },1530 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1223 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },1531 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1224 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1532 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1225 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },1533 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
1226 },1534 },
1227 .encode = .{ .stp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },1535 .encode = .{ .stp, .Wt1, .Wt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
...@@ -1229,9 +1537,9 @@...@@ -1229,9 +1537,9 @@
1229 .{1537 .{
1230 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",1538 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!",
1231 .symbols = .{1539 .symbols = .{
1232 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1540 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1233 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1541 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1234 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1542 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1235 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },1543 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
1236 },1544 },
1237 .encode = .{ .stp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },1545 .encode = .{ .stp, .Xt1, .Xt2, .{ .pre_index = .{ .base = .Xn, .index = .imm } } },
...@@ -1239,18 +1547,18 @@...@@ -1239,18 +1547,18 @@
1239 .{1547 .{
1240 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>]",1548 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>]",
1241 .symbols = .{1549 .symbols = .{
1242 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },1550 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1243 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },1551 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1244 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1552 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1245 },1553 },
1246 .encode = .{ .stp, .Wt1, .Wt2, .{ .base = .Xn } },1554 .encode = .{ .stp, .Wt1, .Wt2, .{ .base = .Xn } },
1247 },1555 },
1248 .{1556 .{
1249 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",1557 .pattern = "STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]",
1250 .symbols = .{1558 .symbols = .{
1251 .Wt1 = .{ .reg = .{ .format = .{ .integer = .word } } },1559 .Wt1 = .{ .reg = .{ .format = .{ .general = .word } } },
1252 .Wt2 = .{ .reg = .{ .format = .{ .integer = .word } } },1560 .Wt2 = .{ .reg = .{ .format = .{ .general = .word } } },
1253 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1561 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1254 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },1562 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 }, .multiple_of = 4 } },
1255 },1563 },
1256 .encode = .{ .stp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },1564 .encode = .{ .stp, .Wt1, .Wt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
...@@ -1258,18 +1566,18 @@...@@ -1258,18 +1566,18 @@
1258 .{1566 .{
1259 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>]",1567 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>]",
1260 .symbols = .{1568 .symbols = .{
1261 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1569 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1262 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1570 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1263 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1571 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1264 },1572 },
1265 .encode = .{ .stp, .Xt1, .Xt2, .{ .base = .Xn } },1573 .encode = .{ .stp, .Xt1, .Xt2, .{ .base = .Xn } },
1266 },1574 },
1267 .{1575 .{
1268 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",1576 .pattern = "STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]",
1269 .symbols = .{1577 .symbols = .{
1270 .Xt1 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1578 .Xt1 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1271 .Xt2 = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1579 .Xt2 = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1272 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1580 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1273 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },1581 .imm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 10 }, .multiple_of = 8 } },
1274 },1582 },
1275 .encode = .{ .stp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },1583 .encode = .{ .stp, .Xt1, .Xt2, .{ .signed_offset = .{ .base = .Xn, .offset = .imm } } },
...@@ -1278,8 +1586,8 @@...@@ -1278,8 +1586,8 @@
1278 .{1586 .{
1279 .pattern = "STR <Wt>, [<Xn|SP>], #<simm>",1587 .pattern = "STR <Wt>, [<Xn|SP>], #<simm>",
1280 .symbols = .{1588 .symbols = .{
1281 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },1589 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1282 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1590 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1283 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },1591 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
1284 },1592 },
1285 .encode = .{ .str, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },1593 .encode = .{ .str, .Wt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
...@@ -1287,8 +1595,8 @@...@@ -1287,8 +1595,8 @@
1287 .{1595 .{
1288 .pattern = "STR <Xt>, [<Xn|SP>], #<simm>",1596 .pattern = "STR <Xt>, [<Xn|SP>], #<simm>",
1289 .symbols = .{1597 .symbols = .{
1290 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1598 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1291 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1599 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1292 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },1600 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
1293 },1601 },
1294 .encode = .{ .str, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },1602 .encode = .{ .str, .Xt, .{ .post_index = .{ .base = .Xn, .index = .simm } } },
...@@ -1296,8 +1604,8 @@...@@ -1296,8 +1604,8 @@
1296 .{1604 .{
1297 .pattern = "STR <Wt>, [<Xn|SP>, #<simm>]!",1605 .pattern = "STR <Wt>, [<Xn|SP>, #<simm>]!",
1298 .symbols = .{1606 .symbols = .{
1299 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },1607 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1300 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1608 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1301 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },1609 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
1302 },1610 },
1303 .encode = .{ .str, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },1611 .encode = .{ .str, .Wt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
...@@ -1305,8 +1613,8 @@...@@ -1305,8 +1613,8 @@
1305 .{1613 .{
1306 .pattern = "STR <Xt>, [<Xn|SP>, #<simm>]!",1614 .pattern = "STR <Xt>, [<Xn|SP>, #<simm>]!",
1307 .symbols = .{1615 .symbols = .{
1308 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1616 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1309 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1617 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1310 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },1618 .simm = .{ .imm = .{ .type = .{ .signedness = .signed, .bits = 9 } } },
1311 },1619 },
1312 .encode = .{ .str, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },1620 .encode = .{ .str, .Xt, .{ .pre_index = .{ .base = .Xn, .index = .simm } } },
...@@ -1314,16 +1622,16 @@...@@ -1314,16 +1622,16 @@
1314 .{1622 .{
1315 .pattern = "STR <Wt>, [<Xn|SP>]",1623 .pattern = "STR <Wt>, [<Xn|SP>]",
1316 .symbols = .{1624 .symbols = .{
1317 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },1625 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1318 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1626 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1319 },1627 },
1320 .encode = .{ .str, .Wt, .{ .base = .Xn } },1628 .encode = .{ .str, .Wt, .{ .base = .Xn } },
1321 },1629 },
1322 .{1630 .{
1323 .pattern = "STR <Wt>, [<Xn|SP>, #<pimm>]",1631 .pattern = "STR <Wt>, [<Xn|SP>, #<pimm>]",
1324 .symbols = .{1632 .symbols = .{
1325 .Wt = .{ .reg = .{ .format = .{ .integer = .word } } },1633 .Wt = .{ .reg = .{ .format = .{ .general = .word } } },
1326 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1634 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1327 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },1635 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 14 }, .multiple_of = 4 } },
1328 },1636 },
1329 .encode = .{ .str, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },1637 .encode = .{ .str, .Wt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
...@@ -1331,16 +1639,16 @@...@@ -1331,16 +1639,16 @@
1331 .{1639 .{
1332 .pattern = "STR <Xt>, [<Xn|SP>]",1640 .pattern = "STR <Xt>, [<Xn|SP>]",
1333 .symbols = .{1641 .symbols = .{
1334 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1642 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1335 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1643 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1336 },1644 },
1337 .encode = .{ .str, .Xt, .{ .base = .Xn } },1645 .encode = .{ .str, .Xt, .{ .base = .Xn } },
1338 },1646 },
1339 .{1647 .{
1340 .pattern = "STR <Xt>, [<Xn|SP>, #<pimm>]",1648 .pattern = "STR <Xt>, [<Xn|SP>, #<pimm>]",
1341 .symbols = .{1649 .symbols = .{
1342 .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1650 .Xt = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1343 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1651 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1344 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },1652 .pimm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 15 }, .multiple_of = 8 } },
1345 },1653 },
1346 .encode = .{ .str, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },1654 .encode = .{ .str, .Xt, .{ .unsigned_offset = .{ .base = .Xn, .offset = .pimm } } },
...@@ -1349,60 +1657,72 @@...@@ -1349,60 +1657,72 @@
1349 .{1657 .{
1350 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>",1658 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>",
1351 .symbols = .{1659 .symbols = .{
1352 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1660 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1353 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1661 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1354 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1662 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1355 },1663 },
1356 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },1664 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },
1357 },1665 },
1358 .{1666 .{
1359 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",1667 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, <Wm>, <extend> #<amount>",
1360 .symbols = .{1668 .symbols = .{
1361 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1669 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1362 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1670 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1363 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1671 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1364 .extend = .{ .extend = .{ .size = .word } },1672 .extend = .{ .extend = .{ .size = .word } },
1365 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },1673 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
1366 },1674 },
1367 .encode = .{ .sub, .Wd, .Wn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },1675 .encode = .{ .sub, .Wd, .Wn, .{ .extended_register_explicit = .{
1676 .register = .Wm,
1677 .option = .extend,
1678 .amount = .amount,
1679 } } },
1368 },1680 },
1369 .{1681 .{
1370 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>",1682 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>",
1371 .symbols = .{1683 .symbols = .{
1372 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1684 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1373 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1685 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1374 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1686 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1375 },1687 },
1376 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },1688 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },
1377 },1689 },
1378 .{1690 .{
1379 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",1691 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Wm>, <extend> #<amount>",
1380 .symbols = .{1692 .symbols = .{
1381 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1693 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1382 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1694 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1383 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1695 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1384 .extend = .{ .extend = .{ .size = .word } },1696 .extend = .{ .extend = .{ .size = .word } },
1385 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },1697 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
1386 },1698 },
1387 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Wm, .option = .extend, .amount = .amount } } },1699 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{
1700 .register = .Wm,
1701 .option = .extend,
1702 .amount = .amount,
1703 } } },
1388 },1704 },
1389 .{1705 .{
1390 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",1706 .pattern = "SUB <Xd|SP>, <Xn|SP>, <Xm>, <extend> #<amount>",
1391 .symbols = .{1707 .symbols = .{
1392 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1708 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1393 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1709 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1394 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1710 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1395 .extend = .{ .extend = .{ .size = .doubleword } },1711 .extend = .{ .extend = .{ .size = .doubleword } },
1396 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },1712 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 }, .max_valid = 4 } },
1397 },1713 },
1398 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{ .register = .Xm, .option = .extend, .amount = .amount } } },1714 .encode = .{ .sub, .Xd, .Xn, .{ .extended_register_explicit = .{
1715 .register = .Xm,
1716 .option = .extend,
1717 .amount = .amount,
1718 } } },
1399 },1719 },
1400 // C6.2.357 SUB (immediate)1720 // C6.2.357 SUB (immediate)
1401 .{1721 .{
1402 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>",1722 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>",
1403 .symbols = .{1723 .symbols = .{
1404 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1724 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1405 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1725 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1406 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },1726 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
1407 },1727 },
1408 .encode = .{ .sub, .Wd, .Wn, .{ .immediate = .imm } },1728 .encode = .{ .sub, .Wd, .Wn, .{ .immediate = .imm } },
...@@ -1410,8 +1730,8 @@...@@ -1410,8 +1730,8 @@
1410 .{1730 .{
1411 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",1731 .pattern = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>, LSL #<shift>",
1412 .symbols = .{1732 .symbols = .{
1413 .Wd = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1733 .Wd = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1414 .Wn = .{ .reg = .{ .format = .{ .integer = .word }, .allow_sp = true } },1734 .Wn = .{ .reg = .{ .format = .{ .general = .word }, .allow_sp = true } },
1415 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },1735 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
1416 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },1736 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
1417 },1737 },
...@@ -1420,8 +1740,8 @@...@@ -1420,8 +1740,8 @@
1420 .{1740 .{
1421 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>",1741 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>",
1422 .symbols = .{1742 .symbols = .{
1423 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1743 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1424 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1744 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1425 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },1745 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
1426 },1746 },
1427 .encode = .{ .sub, .Xd, .Xn, .{ .immediate = .imm } },1747 .encode = .{ .sub, .Xd, .Xn, .{ .immediate = .imm } },
...@@ -1429,8 +1749,8 @@...@@ -1429,8 +1749,8 @@
1429 .{1749 .{
1430 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",1750 .pattern = "SUB <Xd|SP>, <Xn|SP>, #<imm>, LSL #<shift>",
1431 .symbols = .{1751 .symbols = .{
1432 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1752 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1433 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword }, .allow_sp = true } },1753 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword }, .allow_sp = true } },
1434 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },1754 .imm = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 12 } } },
1435 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },1755 .shift = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 }, .multiple_of = 12 } },
1436 },1756 },
...@@ -1440,42 +1760,50 @@...@@ -1440,42 +1760,50 @@
1440 .{1760 .{
1441 .pattern = "SUB <Wd>, <Wn>, <Wm>",1761 .pattern = "SUB <Wd>, <Wn>, <Wm>",
1442 .symbols = .{1762 .symbols = .{
1443 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1763 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1444 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1764 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1445 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1765 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1446 },1766 },
1447 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },1767 .encode = .{ .sub, .Wd, .Wn, .{ .register = .Wm } },
1448 },1768 },
1449 .{1769 .{
1450 .pattern = "SUB <Wd>, <Wn>, <Wm>, <shift> #<amount>",1770 .pattern = "SUB <Wd>, <Wn>, <Wm>, <shift> #<amount>",
1451 .symbols = .{1771 .symbols = .{
1452 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1772 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1453 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1773 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1454 .Wm = .{ .reg = .{ .format = .{ .integer = .word } } },1774 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1455 .shift = .{ .shift = .{ .allow_ror = false } },1775 .shift = .{ .shift = .{ .allow_ror = false } },
1456 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1776 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1457 },1777 },
1458 .encode = .{ .sub, .Wd, .Wn, .{ .shifted_register_explicit = .{ .register = .Wm, .shift = .shift, .amount = .amount } } },1778 .encode = .{ .sub, .Wd, .Wn, .{ .shifted_register_explicit = .{
1779 .register = .Wm,
1780 .shift = .shift,
1781 .amount = .amount,
1782 } } },
1459 },1783 },
1460 .{1784 .{
1461 .pattern = "SUB <Xd>, <Xn>, <Xm>",1785 .pattern = "SUB <Xd>, <Xn>, <Xm>",
1462 .symbols = .{1786 .symbols = .{
1463 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1787 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1464 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1788 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1465 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1789 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1466 },1790 },
1467 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },1791 .encode = .{ .sub, .Xd, .Xn, .{ .register = .Xm } },
1468 },1792 },
1469 .{1793 .{
1470 .pattern = "SUB <Xd>, <Xn>, <Xm>, <shift> #<amount>",1794 .pattern = "SUB <Xd>, <Xn>, <Xm>, <shift> #<amount>",
1471 .symbols = .{1795 .symbols = .{
1472 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1796 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1473 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1797 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1474 .Xm = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1798 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1475 .shift = .{ .shift = .{ .allow_ror = false } },1799 .shift = .{ .shift = .{ .allow_ror = false } },
1476 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1800 .amount = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1477 },1801 },
1478 .encode = .{ .sub, .Xd, .Xn, .{ .shifted_register_explicit = .{ .register = .Xm, .shift = .shift, .amount = .amount } } },1802 .encode = .{ .sub, .Xd, .Xn, .{ .shifted_register_explicit = .{
1803 .register = .Xm,
1804 .shift = .shift,
1805 .amount = .amount,
1806 } } },
1479 },1807 },
1480 // C6.2.365 SVC1808 // C6.2.365 SVC
1481 .{1809 .{
...@@ -1497,8 +1825,8 @@...@@ -1497,8 +1825,8 @@
1497 .{1825 .{
1498 .pattern = "UBFM <Wd>, <Wn>, #<immr>, #<imms>",1826 .pattern = "UBFM <Wd>, <Wn>, #<immr>, #<imms>",
1499 .symbols = .{1827 .symbols = .{
1500 .Wd = .{ .reg = .{ .format = .{ .integer = .word } } },1828 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1501 .Wn = .{ .reg = .{ .format = .{ .integer = .word } } },1829 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1502 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1830 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1503 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },1831 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 5 } } },
1504 },1832 },
...@@ -1507,13 +1835,32 @@...@@ -1507,13 +1835,32 @@
1507 .{1835 .{
1508 .pattern = "UBFM <Xd>, <Xn>, #<immr>, #<imms>",1836 .pattern = "UBFM <Xd>, <Xn>, #<immr>, #<imms>",
1509 .symbols = .{1837 .symbols = .{
1510 .Xd = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1838 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1511 .Xn = .{ .reg = .{ .format = .{ .integer = .doubleword } } },1839 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1512 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1840 .immr = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1513 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },1841 .imms = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 6 } } },
1514 },1842 },
1515 .encode = .{ .ubfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },1843 .encode = .{ .ubfm, .Xd, .Xn, .{ .N = .doubleword, .immr = .immr, .imms = .imms } },
1516 },1844 },
1845 // C6.2.388 UDIV
1846 .{
1847 .pattern = "UDIV <Wd>, <Wn>, <Wm>",
1848 .symbols = .{
1849 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
1850 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1851 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1852 },
1853 .encode = .{ .udiv, .Wd, .Wn, .Wm },
1854 },
1855 .{
1856 .pattern = "UDIV <Xd>, <Xn>, <Xm>",
1857 .symbols = .{
1858 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1859 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1860 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1861 },
1862 .encode = .{ .udiv, .Xd, .Xn, .Xm },
1863 },
1517 // C6.2.387 UDF1864 // C6.2.387 UDF
1518 .{1865 .{
1519 .pattern = "UDF #<imm>",1866 .pattern = "UDF #<imm>",
...@@ -1522,6 +1869,58 @@...@@ -1522,6 +1869,58 @@
1522 },1869 },
1523 .encode = .{ .udf, .imm },1870 .encode = .{ .udf, .imm },
1524 },1871 },
1872 // C6.2.389 UMADDL
1873 .{
1874 .pattern = "UMADDL <Xd>, <Wn>, <Wm>, <Xa>",
1875 .symbols = .{
1876 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1877 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1878 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1879 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1880 },
1881 .encode = .{ .umaddl, .Xd, .Wn, .Wm, .Xa },
1882 },
1883 // C6.2.390 UMNEGL
1884 .{
1885 .pattern = "UMNEGL <Xd>, <Wn>, <Wm>",
1886 .symbols = .{
1887 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1888 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1889 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1890 },
1891 .encode = .{ .umsubl, .Xd, .Wn, .Wm, .xzr },
1892 },
1893 // C6.2.391 UMSUBL
1894 .{
1895 .pattern = "UMSUBL <Xd>, <Wn>, <Wm>, <Xa>",
1896 .symbols = .{
1897 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1898 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1899 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1900 .Xa = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1901 },
1902 .encode = .{ .umsubl, .Xd, .Wn, .Wm, .Xa },
1903 },
1904 // C6.2.292 UMULH
1905 .{
1906 .pattern = "UMULH <Xd>, <Xn>, <Xm>",
1907 .symbols = .{
1908 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1909 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1910 .Xm = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1911 },
1912 .encode = .{ .umulh, .Xd, .Xn, .Xm },
1913 },
1914 // C6.2.393 UMULL
1915 .{
1916 .pattern = "UMULL <Xd>, <Wn>, <Wm>",
1917 .symbols = .{
1918 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
1919 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
1920 .Wm = .{ .reg = .{ .format = .{ .general = .word } } },
1921 },
1922 .encode = .{ .umaddl, .Xd, .Wn, .Wm, .xzr },
1923 },
1525 // C6.2.396 WFE1924 // C6.2.396 WFE
1526 .{1925 .{
1527 .pattern = "WFE",1926 .pattern = "WFE",
...@@ -1540,4 +1939,3216 @@...@@ -1540,4 +1939,3216 @@
1540 .symbols = .{},1939 .symbols = .{},
1541 .encode = .{.yield},1940 .encode = .{.yield},
1542 },1941 },
1942
1943 // C7.2.1 ABS
1944 .{
1945 .pattern = "ABS <Vd>, <Vn>",
1946 .symbols = .{
1947 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1948 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1949 },
1950 .encode = .{ .abs, .Vd, .Vn },
1951 },
1952 .{
1953 .pattern = "ABS <Vd>.<T>, <Vn>.<T>",
1954 .symbols = .{
1955 .Vd = .{ .reg_alias = .vector },
1956 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
1957 .Vn = .{ .reg_alias = .vector },
1958 },
1959 .encode = .{
1960 .abs,
1961 .{ .alias = .Vd, .format = .{ .vector = .T } },
1962 .{ .alias = .Vn, .format = .{ .vector = .T } },
1963 },
1964 },
1965 // C7.2.28 CMEQ (zero)
1966 .{
1967 .pattern = "CMEQ <Vd>, <Vn>, #<0>",
1968 .symbols = .{
1969 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1970 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1971 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1972 },
1973 .encode = .{ .cmeq, .Vd, .Vn, .zero },
1974 },
1975 .{
1976 .pattern = "CMEQ <Vd>.<T>, <Vn>.<T>, #<0>",
1977 .symbols = .{
1978 .Vd = .{ .reg_alias = .vector },
1979 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
1980 .Vn = .{ .reg_alias = .vector },
1981 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1982 },
1983 .encode = .{
1984 .cmeq,
1985 .{ .alias = .Vd, .format = .{ .vector = .T } },
1986 .{ .alias = .Vn, .format = .{ .vector = .T } },
1987 .zero,
1988 },
1989 },
1990 // C7.2.30 CMGE (zero)
1991 .{
1992 .pattern = "CMGE <Vd>, <Vn>, #<0>",
1993 .symbols = .{
1994 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
1995 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
1996 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
1997 },
1998 .encode = .{ .cmge, .Vd, .Vn, .zero },
1999 },
2000 .{
2001 .pattern = "CMGE <Vd>.<T>, <Vn>.<T>, #<0>",
2002 .symbols = .{
2003 .Vd = .{ .reg_alias = .vector },
2004 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2005 .Vn = .{ .reg_alias = .vector },
2006 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2007 },
2008 .encode = .{
2009 .cmge,
2010 .{ .alias = .Vd, .format = .{ .vector = .T } },
2011 .{ .alias = .Vn, .format = .{ .vector = .T } },
2012 .zero,
2013 },
2014 },
2015 // C7.2.32 CMGT (zero)
2016 .{
2017 .pattern = "CMGT <Vd>, <Vn>, #<0>",
2018 .symbols = .{
2019 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2020 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2021 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2022 },
2023 .encode = .{ .cmgt, .Vd, .Vn, .zero },
2024 },
2025 .{
2026 .pattern = "CMGT <Vd>.<T>, <Vn>.<T>, #<0>",
2027 .symbols = .{
2028 .Vd = .{ .reg_alias = .vector },
2029 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2030 .Vn = .{ .reg_alias = .vector },
2031 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2032 },
2033 .encode = .{
2034 .cmgt,
2035 .{ .alias = .Vd, .format = .{ .vector = .T } },
2036 .{ .alias = .Vn, .format = .{ .vector = .T } },
2037 .zero,
2038 },
2039 },
2040 // C7.2.35 CMLE (zero)
2041 .{
2042 .pattern = "CMLE <Vd>, <Vn>, #<0>",
2043 .symbols = .{
2044 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2045 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2046 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2047 },
2048 .encode = .{ .cmle, .Vd, .Vn, .zero },
2049 },
2050 .{
2051 .pattern = "CMLE <Vd>.<T>, <Vn>.<T>, #<0>",
2052 .symbols = .{
2053 .Vd = .{ .reg_alias = .vector },
2054 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2055 .Vn = .{ .reg_alias = .vector },
2056 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2057 },
2058 .encode = .{
2059 .cmle,
2060 .{ .alias = .Vd, .format = .{ .vector = .T } },
2061 .{ .alias = .Vn, .format = .{ .vector = .T } },
2062 .zero,
2063 },
2064 },
2065 // C7.2.36 CMLT (zero)
2066 .{
2067 .pattern = "CMLT <Vd>, <Vn>, #<0>",
2068 .symbols = .{
2069 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2070 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2071 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2072 },
2073 .encode = .{ .cmlt, .Vd, .Vn, .zero },
2074 },
2075 .{
2076 .pattern = "CMLT <Vd>.<T>, <Vn>.<T>, #<0>",
2077 .symbols = .{
2078 .Vd = .{ .reg_alias = .vector },
2079 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
2080 .Vn = .{ .reg_alias = .vector },
2081 .@"0" = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 0 } } },
2082 },
2083 .encode = .{
2084 .cmlt,
2085 .{ .alias = .Vd, .format = .{ .vector = .T } },
2086 .{ .alias = .Vn, .format = .{ .vector = .T } },
2087 .zero,
2088 },
2089 },
2090 // C7.2.38 CNT
2091 .{
2092 .pattern = "CNT <Vd>.<T>, <Vn>.<T>",
2093 .symbols = .{
2094 .Vd = .{ .reg_alias = .vector },
2095 .T = .{ .arrangement = .{ .elem_size = .byte } },
2096 .Vn = .{ .reg_alias = .vector },
2097 },
2098 .encode = .{
2099 .cnt,
2100 .{ .alias = .Vd, .format = .{ .vector = .T } },
2101 .{ .alias = .Vn, .format = .{ .vector = .T } },
2102 },
2103 },
2104 // C7.2.39 DUP (element)
2105 .{
2106 .pattern = "DUP <Vd>, <Vn>.B[<index>]",
2107 .symbols = .{
2108 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
2109 .Vn = .{ .reg_alias = .vector },
2110 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
2111 },
2112 .encode = .{
2113 .dup,
2114 .Vd,
2115 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
2116 },
2117 },
2118 .{
2119 .pattern = "DUP <Vd>, <Vn>.H[<index>]",
2120 .symbols = .{
2121 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2122 .Vn = .{ .reg_alias = .vector },
2123 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
2124 },
2125 .encode = .{
2126 .dup,
2127 .Vd,
2128 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
2129 },
2130 },
2131 .{
2132 .pattern = "DUP <Vd>, <Vn>.S[<index>]",
2133 .symbols = .{
2134 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2135 .Vn = .{ .reg_alias = .vector },
2136 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
2137 },
2138 .encode = .{
2139 .dup,
2140 .Vd,
2141 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
2142 },
2143 },
2144 .{
2145 .pattern = "DUP <Vd>, <Vn>.D[<index>]",
2146 .symbols = .{
2147 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2148 .Vn = .{ .reg_alias = .vector },
2149 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
2150 },
2151 .encode = .{
2152 .dup,
2153 .Vd,
2154 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
2155 },
2156 },
2157 .{
2158 .pattern = "DUP <Vd>.<T>, <Vn>.B[<index>]",
2159 .symbols = .{
2160 .Vd = .{ .reg_alias = .vector },
2161 .T = .{ .arrangement = .{ .elem_size = .byte } },
2162 .Vn = .{ .reg_alias = .vector },
2163 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
2164 },
2165 .encode = .{
2166 .dup,
2167 .{ .alias = .Vd, .format = .{ .vector = .T } },
2168 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
2169 },
2170 },
2171 .{
2172 .pattern = "DUP <Vd>.<T>, <Vn>.H[<index>]",
2173 .symbols = .{
2174 .Vd = .{ .reg_alias = .vector },
2175 .T = .{ .arrangement = .{ .elem_size = .half } },
2176 .Vn = .{ .reg_alias = .vector },
2177 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
2178 },
2179 .encode = .{
2180 .dup,
2181 .{ .alias = .Vd, .format = .{ .vector = .T } },
2182 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
2183 },
2184 },
2185 .{
2186 .pattern = "DUP <Vd>.<T>, <Vn>.S[<index>]",
2187 .symbols = .{
2188 .Vd = .{ .reg_alias = .vector },
2189 .T = .{ .arrangement = .{ .elem_size = .single } },
2190 .Vn = .{ .reg_alias = .vector },
2191 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
2192 },
2193 .encode = .{
2194 .dup,
2195 .{ .alias = .Vd, .format = .{ .vector = .T } },
2196 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
2197 },
2198 },
2199 .{
2200 .pattern = "DUP <Vd>.2D, <Vn>.D[<index>]",
2201 .symbols = .{
2202 .Vd = .{ .reg_alias = .vector },
2203 .Vn = .{ .reg_alias = .vector },
2204 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
2205 },
2206 .encode = .{
2207 .dup,
2208 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2209 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
2210 },
2211 },
2212 // C7.2.40 DUP (general)
2213 .{
2214 .pattern = "DUP <Vd>.<T>, <Wn>",
2215 .symbols = .{
2216 .Vd = .{ .reg_alias = .vector },
2217 .T = .{ .arrangement = .{ .allow_double = false } },
2218 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
2219 },
2220 .encode = .{ .dup, .{ .alias = .Vd, .format = .{ .vector = .T } }, .Wn },
2221 },
2222 .{
2223 .pattern = "DUP <Vd>.2D, <Xn>",
2224 .symbols = .{
2225 .Vd = .{ .reg_alias = .vector },
2226 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2227 },
2228 .encode = .{ .dup, .{ .alias = .Vd, .format = .{ .vector = .@"2d" } }, .Xn },
2229 },
2230 // C7.2.57 FCMEQ (zero)
2231 .{
2232 .requires = .{.fullfp16},
2233 .pattern = "FCMEQ <Hd>, <Hn>, #<0.0>",
2234 .symbols = .{
2235 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2236 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2237 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2238 },
2239 .encode = .{ .fcmeq, .Hd, .Hn, .zero },
2240 },
2241 .{
2242 .pattern = "FCMEQ <Sd>, <Sn>, #<0.0>",
2243 .symbols = .{
2244 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2245 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2246 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2247 },
2248 .encode = .{ .fcmeq, .Sd, .Sn, .zero },
2249 },
2250 .{
2251 .pattern = "FCMEQ <Dd>, <Dn>, #<0.0>",
2252 .symbols = .{
2253 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2254 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2255 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2256 },
2257 .encode = .{ .fcmeq, .Dd, .Dn, .zero },
2258 },
2259 .{
2260 .requires = .{.fullfp16},
2261 .pattern = "FCMEQ <Vd>.<T>, <Vn>.<T>, #<0.0>",
2262 .symbols = .{
2263 .Vd = .{ .reg_alias = .vector },
2264 .T = .{ .arrangement = .{ .elem_size = .half } },
2265 .Vn = .{ .reg_alias = .vector },
2266 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2267 },
2268 .encode = .{
2269 .fcmeq,
2270 .{ .alias = .Vd, .format = .{ .vector = .T } },
2271 .{ .alias = .Vn, .format = .{ .vector = .T } },
2272 .zero,
2273 },
2274 },
2275 .{
2276 .pattern = "FCMEQ <Vd>.<T>, <Vn>.<T>, #<0.0>",
2277 .symbols = .{
2278 .Vd = .{ .reg_alias = .vector },
2279 .T = .{ .arrangement = .{ .elem_size = .single } },
2280 .Vn = .{ .reg_alias = .vector },
2281 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2282 },
2283 .encode = .{
2284 .fcmeq,
2285 .{ .alias = .Vd, .format = .{ .vector = .T } },
2286 .{ .alias = .Vn, .format = .{ .vector = .T } },
2287 .zero,
2288 },
2289 },
2290 .{
2291 .pattern = "FCMEQ <Vd>.2D, <Vn>.2D, #<0.0>",
2292 .symbols = .{
2293 .Vd = .{ .reg_alias = .vector },
2294 .Vn = .{ .reg_alias = .vector },
2295 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2296 },
2297 .encode = .{
2298 .fcmeq,
2299 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2300 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2301 .zero,
2302 },
2303 },
2304 // C7.2.59 FCMGE (zero)
2305 .{
2306 .requires = .{.fullfp16},
2307 .pattern = "FCMGE <Hd>, <Hn>, #<0.0>",
2308 .symbols = .{
2309 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2310 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2311 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2312 },
2313 .encode = .{ .fcmge, .Hd, .Hn, .zero },
2314 },
2315 .{
2316 .pattern = "FCMGE <Sd>, <Sn>, #<0.0>",
2317 .symbols = .{
2318 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2319 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2320 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2321 },
2322 .encode = .{ .fcmge, .Sd, .Sn, .zero },
2323 },
2324 .{
2325 .pattern = "FCMGE <Dd>, <Dn>, #<0.0>",
2326 .symbols = .{
2327 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2328 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2329 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2330 },
2331 .encode = .{ .fcmge, .Dd, .Dn, .zero },
2332 },
2333 .{
2334 .requires = .{.fullfp16},
2335 .pattern = "FCMGE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2336 .symbols = .{
2337 .Vd = .{ .reg_alias = .vector },
2338 .T = .{ .arrangement = .{ .elem_size = .half } },
2339 .Vn = .{ .reg_alias = .vector },
2340 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2341 },
2342 .encode = .{
2343 .fcmge,
2344 .{ .alias = .Vd, .format = .{ .vector = .T } },
2345 .{ .alias = .Vn, .format = .{ .vector = .T } },
2346 .zero,
2347 },
2348 },
2349 .{
2350 .pattern = "FCMGE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2351 .symbols = .{
2352 .Vd = .{ .reg_alias = .vector },
2353 .T = .{ .arrangement = .{ .elem_size = .single } },
2354 .Vn = .{ .reg_alias = .vector },
2355 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2356 },
2357 .encode = .{
2358 .fcmge,
2359 .{ .alias = .Vd, .format = .{ .vector = .T } },
2360 .{ .alias = .Vn, .format = .{ .vector = .T } },
2361 .zero,
2362 },
2363 },
2364 .{
2365 .pattern = "FCMGE <Vd>.2D, <Vn>.2D, #<0.0>",
2366 .symbols = .{
2367 .Vd = .{ .reg_alias = .vector },
2368 .Vn = .{ .reg_alias = .vector },
2369 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2370 },
2371 .encode = .{
2372 .fcmge,
2373 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2374 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2375 .zero,
2376 },
2377 },
2378 // C7.2.61 FCMGT (zero)
2379 .{
2380 .requires = .{.fullfp16},
2381 .pattern = "FCMGT <Hd>, <Hn>, #<0.0>",
2382 .symbols = .{
2383 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2384 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2385 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2386 },
2387 .encode = .{ .fcmgt, .Hd, .Hn, .zero },
2388 },
2389 .{
2390 .pattern = "FCMGT <Sd>, <Sn>, #<0.0>",
2391 .symbols = .{
2392 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2393 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2394 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2395 },
2396 .encode = .{ .fcmgt, .Sd, .Sn, .zero },
2397 },
2398 .{
2399 .pattern = "FCMGT <Dd>, <Dn>, #<0.0>",
2400 .symbols = .{
2401 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2402 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2403 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2404 },
2405 .encode = .{ .fcmgt, .Dd, .Dn, .zero },
2406 },
2407 .{
2408 .requires = .{.fullfp16},
2409 .pattern = "FCMGT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2410 .symbols = .{
2411 .Vd = .{ .reg_alias = .vector },
2412 .T = .{ .arrangement = .{ .elem_size = .half } },
2413 .Vn = .{ .reg_alias = .vector },
2414 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2415 },
2416 .encode = .{
2417 .fcmgt,
2418 .{ .alias = .Vd, .format = .{ .vector = .T } },
2419 .{ .alias = .Vn, .format = .{ .vector = .T } },
2420 .zero,
2421 },
2422 },
2423 .{
2424 .pattern = "FCMGT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2425 .symbols = .{
2426 .Vd = .{ .reg_alias = .vector },
2427 .T = .{ .arrangement = .{ .elem_size = .single } },
2428 .Vn = .{ .reg_alias = .vector },
2429 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2430 },
2431 .encode = .{
2432 .fcmgt,
2433 .{ .alias = .Vd, .format = .{ .vector = .T } },
2434 .{ .alias = .Vn, .format = .{ .vector = .T } },
2435 .zero,
2436 },
2437 },
2438 .{
2439 .pattern = "FCMGT <Vd>.2D, <Vn>.2D, #<0.0>",
2440 .symbols = .{
2441 .Vd = .{ .reg_alias = .vector },
2442 .Vn = .{ .reg_alias = .vector },
2443 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2444 },
2445 .encode = .{
2446 .fcmgt,
2447 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2448 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2449 .zero,
2450 },
2451 },
2452 // C7.2.64 FCMLE (zero)
2453 .{
2454 .requires = .{.fullfp16},
2455 .pattern = "FCMLE <Hd>, <Hn>, #<0.0>",
2456 .symbols = .{
2457 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2458 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2459 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2460 },
2461 .encode = .{ .fcmle, .Hd, .Hn, .zero },
2462 },
2463 .{
2464 .pattern = "FCMLE <Sd>, <Sn>, #<0.0>",
2465 .symbols = .{
2466 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2467 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2468 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2469 },
2470 .encode = .{ .fcmle, .Sd, .Sn, .zero },
2471 },
2472 .{
2473 .pattern = "FCMLE <Dd>, <Dn>, #<0.0>",
2474 .symbols = .{
2475 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2476 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2477 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2478 },
2479 .encode = .{ .fcmle, .Dd, .Dn, .zero },
2480 },
2481 .{
2482 .requires = .{.fullfp16},
2483 .pattern = "FCMLE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2484 .symbols = .{
2485 .Vd = .{ .reg_alias = .vector },
2486 .T = .{ .arrangement = .{ .elem_size = .half } },
2487 .Vn = .{ .reg_alias = .vector },
2488 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2489 },
2490 .encode = .{
2491 .fcmle,
2492 .{ .alias = .Vd, .format = .{ .vector = .T } },
2493 .{ .alias = .Vn, .format = .{ .vector = .T } },
2494 .zero,
2495 },
2496 },
2497 .{
2498 .pattern = "FCMLE <Vd>.<T>, <Vn>.<T>, #<0.0>",
2499 .symbols = .{
2500 .Vd = .{ .reg_alias = .vector },
2501 .T = .{ .arrangement = .{ .elem_size = .single } },
2502 .Vn = .{ .reg_alias = .vector },
2503 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2504 },
2505 .encode = .{
2506 .fcmle,
2507 .{ .alias = .Vd, .format = .{ .vector = .T } },
2508 .{ .alias = .Vn, .format = .{ .vector = .T } },
2509 .zero,
2510 },
2511 },
2512 .{
2513 .pattern = "FCMLE <Vd>.2D, <Vn>.2D, #<0.0>",
2514 .symbols = .{
2515 .Vd = .{ .reg_alias = .vector },
2516 .Vn = .{ .reg_alias = .vector },
2517 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2518 },
2519 .encode = .{
2520 .fcmle,
2521 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2522 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2523 .zero,
2524 },
2525 },
2526 // C7.2.65 FCMLT (zero)
2527 .{
2528 .requires = .{.fullfp16},
2529 .pattern = "FCMLT <Hd>, <Hn>, #<0.0>",
2530 .symbols = .{
2531 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2532 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2533 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2534 },
2535 .encode = .{ .fcmlt, .Hd, .Hn, .zero },
2536 },
2537 .{
2538 .pattern = "FCMLT <Sd>, <Sn>, #<0.0>",
2539 .symbols = .{
2540 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2541 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2542 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2543 },
2544 .encode = .{ .fcmlt, .Sd, .Sn, .zero },
2545 },
2546 .{
2547 .pattern = "FCMLT <Dd>, <Dn>, #<0.0>",
2548 .symbols = .{
2549 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2550 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2551 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2552 },
2553 .encode = .{ .fcmlt, .Dd, .Dn, .zero },
2554 },
2555 .{
2556 .requires = .{.fullfp16},
2557 .pattern = "FCMLT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2558 .symbols = .{
2559 .Vd = .{ .reg_alias = .vector },
2560 .T = .{ .arrangement = .{ .elem_size = .half } },
2561 .Vn = .{ .reg_alias = .vector },
2562 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2563 },
2564 .encode = .{
2565 .fcmlt,
2566 .{ .alias = .Vd, .format = .{ .vector = .T } },
2567 .{ .alias = .Vn, .format = .{ .vector = .T } },
2568 .zero,
2569 },
2570 },
2571 .{
2572 .pattern = "FCMLT <Vd>.<T>, <Vn>.<T>, #<0.0>",
2573 .symbols = .{
2574 .Vd = .{ .reg_alias = .vector },
2575 .T = .{ .arrangement = .{ .elem_size = .single } },
2576 .Vn = .{ .reg_alias = .vector },
2577 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2578 },
2579 .encode = .{
2580 .fcmlt,
2581 .{ .alias = .Vd, .format = .{ .vector = .T } },
2582 .{ .alias = .Vn, .format = .{ .vector = .T } },
2583 .zero,
2584 },
2585 },
2586 .{
2587 .pattern = "FCMLT <Vd>.2D, <Vn>.2D, #<0.0>",
2588 .symbols = .{
2589 .Vd = .{ .reg_alias = .vector },
2590 .Vn = .{ .reg_alias = .vector },
2591 .@"0.0" = .{ .fimm = .{ .only_valid = 0.0 } },
2592 },
2593 .encode = .{
2594 .fcmlt,
2595 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2596 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2597 .zero,
2598 },
2599 },
2600 // C7.2.70 FCVTAS (vector)
2601 .{
2602 .requires = .{.fullfp16},
2603 .pattern = "FCVTAS <Hd>, <Hn>",
2604 .symbols = .{
2605 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2606 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2607 },
2608 .encode = .{ .fcvtas, .Hd, .Hn },
2609 },
2610 .{
2611 .pattern = "FCVTAS <Sd>, <Sn>",
2612 .symbols = .{
2613 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2614 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2615 },
2616 .encode = .{ .fcvtas, .Sd, .Sn },
2617 },
2618 .{
2619 .pattern = "FCVTAS <Dd>, <Dn>",
2620 .symbols = .{
2621 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2622 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2623 },
2624 .encode = .{ .fcvtas, .Dd, .Dn },
2625 },
2626 .{
2627 .requires = .{.fullfp16},
2628 .pattern = "FCVTAS <Vd>.<T>, <Vn>.<T>",
2629 .symbols = .{
2630 .Vd = .{ .reg_alias = .vector },
2631 .T = .{ .arrangement = .{ .elem_size = .half } },
2632 .Vn = .{ .reg_alias = .vector },
2633 },
2634 .encode = .{
2635 .fcvtas,
2636 .{ .alias = .Vd, .format = .{ .vector = .T } },
2637 .{ .alias = .Vn, .format = .{ .vector = .T } },
2638 },
2639 },
2640 .{
2641 .pattern = "FCVTAS <Vd>.<T>, <Vn>.<T>",
2642 .symbols = .{
2643 .Vd = .{ .reg_alias = .vector },
2644 .T = .{ .arrangement = .{ .elem_size = .single } },
2645 .Vn = .{ .reg_alias = .vector },
2646 },
2647 .encode = .{
2648 .fcvtas,
2649 .{ .alias = .Vd, .format = .{ .vector = .T } },
2650 .{ .alias = .Vn, .format = .{ .vector = .T } },
2651 },
2652 },
2653 .{
2654 .pattern = "FCVTAS <Vd>.2D, <Vn>.2D",
2655 .symbols = .{
2656 .Vd = .{ .reg_alias = .vector },
2657 .Vn = .{ .reg_alias = .vector },
2658 },
2659 .encode = .{
2660 .fcvtas,
2661 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2662 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2663 },
2664 },
2665 // C7.2.71 FCVTAS (scalar)
2666 .{
2667 .requires = .{.fullfp16},
2668 .pattern = "FCVTAS <Wd>, <Hn>",
2669 .symbols = .{
2670 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2671 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2672 },
2673 .encode = .{ .fcvtas, .Wd, .Hn },
2674 },
2675 .{
2676 .requires = .{.fullfp16},
2677 .pattern = "FCVTAS <Xd>, <Hn>",
2678 .symbols = .{
2679 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2680 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2681 },
2682 .encode = .{ .fcvtas, .Xd, .Hn },
2683 },
2684 .{
2685 .pattern = "FCVTAS <Wd>, <Sn>",
2686 .symbols = .{
2687 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2688 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2689 },
2690 .encode = .{ .fcvtas, .Wd, .Sn },
2691 },
2692 .{
2693 .pattern = "FCVTAS <Xd>, <Sn>",
2694 .symbols = .{
2695 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2696 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2697 },
2698 .encode = .{ .fcvtas, .Xd, .Sn },
2699 },
2700 .{
2701 .pattern = "FCVTAS <Wd>, <Dn>",
2702 .symbols = .{
2703 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2704 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2705 },
2706 .encode = .{ .fcvtas, .Wd, .Dn },
2707 },
2708 .{
2709 .pattern = "FCVTAS <Xd>, <Dn>",
2710 .symbols = .{
2711 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2712 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2713 },
2714 .encode = .{ .fcvtas, .Xd, .Dn },
2715 },
2716 // C7.2.72 FCVTAU (vector)
2717 .{
2718 .requires = .{.fullfp16},
2719 .pattern = "FCVTAU <Hd>, <Hn>",
2720 .symbols = .{
2721 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2722 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2723 },
2724 .encode = .{ .fcvtau, .Hd, .Hn },
2725 },
2726 .{
2727 .pattern = "FCVTAU <Sd>, <Sn>",
2728 .symbols = .{
2729 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2730 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2731 },
2732 .encode = .{ .fcvtau, .Sd, .Sn },
2733 },
2734 .{
2735 .pattern = "FCVTAU <Dd>, <Dn>",
2736 .symbols = .{
2737 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2738 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2739 },
2740 .encode = .{ .fcvtau, .Dd, .Dn },
2741 },
2742 .{
2743 .requires = .{.fullfp16},
2744 .pattern = "FCVTAU <Vd>.<T>, <Vn>.<T>",
2745 .symbols = .{
2746 .Vd = .{ .reg_alias = .vector },
2747 .T = .{ .arrangement = .{ .elem_size = .half } },
2748 .Vn = .{ .reg_alias = .vector },
2749 },
2750 .encode = .{
2751 .fcvtau,
2752 .{ .alias = .Vd, .format = .{ .vector = .T } },
2753 .{ .alias = .Vn, .format = .{ .vector = .T } },
2754 },
2755 },
2756 .{
2757 .pattern = "FCVTAU <Vd>.<T>, <Vn>.<T>",
2758 .symbols = .{
2759 .Vd = .{ .reg_alias = .vector },
2760 .T = .{ .arrangement = .{ .elem_size = .single } },
2761 .Vn = .{ .reg_alias = .vector },
2762 },
2763 .encode = .{
2764 .fcvtau,
2765 .{ .alias = .Vd, .format = .{ .vector = .T } },
2766 .{ .alias = .Vn, .format = .{ .vector = .T } },
2767 },
2768 },
2769 .{
2770 .pattern = "FCVTAU <Vd>.2D, <Vn>.2D",
2771 .symbols = .{
2772 .Vd = .{ .reg_alias = .vector },
2773 .Vn = .{ .reg_alias = .vector },
2774 },
2775 .encode = .{
2776 .fcvtau,
2777 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2778 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2779 },
2780 },
2781 // C7.2.73 FCVTAU (scalar)
2782 .{
2783 .requires = .{.fullfp16},
2784 .pattern = "FCVTAU <Wd>, <Hn>",
2785 .symbols = .{
2786 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2787 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2788 },
2789 .encode = .{ .fcvtau, .Wd, .Hn },
2790 },
2791 .{
2792 .requires = .{.fullfp16},
2793 .pattern = "FCVTAU <Xd>, <Hn>",
2794 .symbols = .{
2795 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2796 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2797 },
2798 .encode = .{ .fcvtau, .Xd, .Hn },
2799 },
2800 .{
2801 .pattern = "FCVTAU <Wd>, <Sn>",
2802 .symbols = .{
2803 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2804 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2805 },
2806 .encode = .{ .fcvtau, .Wd, .Sn },
2807 },
2808 .{
2809 .pattern = "FCVTAU <Xd>, <Sn>",
2810 .symbols = .{
2811 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2812 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2813 },
2814 .encode = .{ .fcvtau, .Xd, .Sn },
2815 },
2816 .{
2817 .pattern = "FCVTAU <Wd>, <Dn>",
2818 .symbols = .{
2819 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2820 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2821 },
2822 .encode = .{ .fcvtau, .Wd, .Dn },
2823 },
2824 .{
2825 .pattern = "FCVTAU <Xd>, <Dn>",
2826 .symbols = .{
2827 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2828 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2829 },
2830 .encode = .{ .fcvtau, .Xd, .Dn },
2831 },
2832 // C7.2.75 FCVTMS (vector)
2833 .{
2834 .requires = .{.fullfp16},
2835 .pattern = "FCVTMS <Hd>, <Hn>",
2836 .symbols = .{
2837 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2838 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2839 },
2840 .encode = .{ .fcvtms, .Hd, .Hn },
2841 },
2842 .{
2843 .pattern = "FCVTMS <Sd>, <Sn>",
2844 .symbols = .{
2845 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2846 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2847 },
2848 .encode = .{ .fcvtms, .Sd, .Sn },
2849 },
2850 .{
2851 .pattern = "FCVTMS <Dd>, <Dn>",
2852 .symbols = .{
2853 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2854 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2855 },
2856 .encode = .{ .fcvtms, .Dd, .Dn },
2857 },
2858 .{
2859 .requires = .{.fullfp16},
2860 .pattern = "FCVTMS <Vd>.<T>, <Vn>.<T>",
2861 .symbols = .{
2862 .Vd = .{ .reg_alias = .vector },
2863 .T = .{ .arrangement = .{ .elem_size = .half } },
2864 .Vn = .{ .reg_alias = .vector },
2865 },
2866 .encode = .{
2867 .fcvtms,
2868 .{ .alias = .Vd, .format = .{ .vector = .T } },
2869 .{ .alias = .Vn, .format = .{ .vector = .T } },
2870 },
2871 },
2872 .{
2873 .pattern = "FCVTMS <Vd>.<T>, <Vn>.<T>",
2874 .symbols = .{
2875 .Vd = .{ .reg_alias = .vector },
2876 .T = .{ .arrangement = .{ .elem_size = .single } },
2877 .Vn = .{ .reg_alias = .vector },
2878 },
2879 .encode = .{
2880 .fcvtms,
2881 .{ .alias = .Vd, .format = .{ .vector = .T } },
2882 .{ .alias = .Vn, .format = .{ .vector = .T } },
2883 },
2884 },
2885 .{
2886 .pattern = "FCVTMS <Vd>.2D, <Vn>.2D",
2887 .symbols = .{
2888 .Vd = .{ .reg_alias = .vector },
2889 .Vn = .{ .reg_alias = .vector },
2890 },
2891 .encode = .{
2892 .fcvtms,
2893 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
2894 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
2895 },
2896 },
2897 // C7.2.76 FCVTMS (scalar)
2898 .{
2899 .requires = .{.fullfp16},
2900 .pattern = "FCVTMS <Wd>, <Hn>",
2901 .symbols = .{
2902 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2903 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2904 },
2905 .encode = .{ .fcvtms, .Wd, .Hn },
2906 },
2907 .{
2908 .requires = .{.fullfp16},
2909 .pattern = "FCVTMS <Xd>, <Hn>",
2910 .symbols = .{
2911 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2912 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2913 },
2914 .encode = .{ .fcvtms, .Xd, .Hn },
2915 },
2916 .{
2917 .pattern = "FCVTMS <Wd>, <Sn>",
2918 .symbols = .{
2919 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2920 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2921 },
2922 .encode = .{ .fcvtms, .Wd, .Sn },
2923 },
2924 .{
2925 .pattern = "FCVTMS <Xd>, <Sn>",
2926 .symbols = .{
2927 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2928 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2929 },
2930 .encode = .{ .fcvtms, .Xd, .Sn },
2931 },
2932 .{
2933 .pattern = "FCVTMS <Wd>, <Dn>",
2934 .symbols = .{
2935 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
2936 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2937 },
2938 .encode = .{ .fcvtms, .Wd, .Dn },
2939 },
2940 .{
2941 .pattern = "FCVTMS <Xd>, <Dn>",
2942 .symbols = .{
2943 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
2944 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2945 },
2946 .encode = .{ .fcvtms, .Xd, .Dn },
2947 },
2948 // C7.2.77 FCVTMU (vector)
2949 .{
2950 .requires = .{.fullfp16},
2951 .pattern = "FCVTMU <Hd>, <Hn>",
2952 .symbols = .{
2953 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
2954 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
2955 },
2956 .encode = .{ .fcvtmu, .Hd, .Hn },
2957 },
2958 .{
2959 .pattern = "FCVTMU <Sd>, <Sn>",
2960 .symbols = .{
2961 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
2962 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
2963 },
2964 .encode = .{ .fcvtmu, .Sd, .Sn },
2965 },
2966 .{
2967 .pattern = "FCVTMU <Dd>, <Dn>",
2968 .symbols = .{
2969 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
2970 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
2971 },
2972 .encode = .{ .fcvtmu, .Dd, .Dn },
2973 },
2974 .{
2975 .requires = .{.fullfp16},
2976 .pattern = "FCVTMU <Vd>.<T>, <Vn>.<T>",
2977 .symbols = .{
2978 .Vd = .{ .reg_alias = .vector },
2979 .T = .{ .arrangement = .{ .elem_size = .half } },
2980 .Vn = .{ .reg_alias = .vector },
2981 },
2982 .encode = .{
2983 .fcvtmu,
2984 .{ .alias = .Vd, .format = .{ .vector = .T } },
2985 .{ .alias = .Vn, .format = .{ .vector = .T } },
2986 },
2987 },
2988 .{
2989 .pattern = "FCVTMU <Vd>.<T>, <Vn>.<T>",
2990 .symbols = .{
2991 .Vd = .{ .reg_alias = .vector },
2992 .T = .{ .arrangement = .{ .elem_size = .single } },
2993 .Vn = .{ .reg_alias = .vector },
2994 },
2995 .encode = .{
2996 .fcvtmu,
2997 .{ .alias = .Vd, .format = .{ .vector = .T } },
2998 .{ .alias = .Vn, .format = .{ .vector = .T } },
2999 },
3000 },
3001 .{
3002 .pattern = "FCVTMU <Vd>.2D, <Vn>.2D",
3003 .symbols = .{
3004 .Vd = .{ .reg_alias = .vector },
3005 .Vn = .{ .reg_alias = .vector },
3006 },
3007 .encode = .{
3008 .fcvtmu,
3009 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3010 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3011 },
3012 },
3013 // C7.2.78 FCVTMU (scalar)
3014 .{
3015 .requires = .{.fullfp16},
3016 .pattern = "FCVTMU <Wd>, <Hn>",
3017 .symbols = .{
3018 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3019 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3020 },
3021 .encode = .{ .fcvtmu, .Wd, .Hn },
3022 },
3023 .{
3024 .requires = .{.fullfp16},
3025 .pattern = "FCVTMU <Xd>, <Hn>",
3026 .symbols = .{
3027 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3028 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3029 },
3030 .encode = .{ .fcvtmu, .Xd, .Hn },
3031 },
3032 .{
3033 .pattern = "FCVTMU <Wd>, <Sn>",
3034 .symbols = .{
3035 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3036 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3037 },
3038 .encode = .{ .fcvtmu, .Wd, .Sn },
3039 },
3040 .{
3041 .pattern = "FCVTMU <Xd>, <Sn>",
3042 .symbols = .{
3043 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3044 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3045 },
3046 .encode = .{ .fcvtmu, .Xd, .Sn },
3047 },
3048 .{
3049 .pattern = "FCVTMU <Wd>, <Dn>",
3050 .symbols = .{
3051 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3052 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3053 },
3054 .encode = .{ .fcvtmu, .Wd, .Dn },
3055 },
3056 .{
3057 .pattern = "FCVTMU <Xd>, <Dn>",
3058 .symbols = .{
3059 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3060 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3061 },
3062 .encode = .{ .fcvtmu, .Xd, .Dn },
3063 },
3064 // C7.2.80 FCVTNS (vector)
3065 .{
3066 .requires = .{.fullfp16},
3067 .pattern = "FCVTNS <Hd>, <Hn>",
3068 .symbols = .{
3069 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3070 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3071 },
3072 .encode = .{ .fcvtns, .Hd, .Hn },
3073 },
3074 .{
3075 .pattern = "FCVTNS <Sd>, <Sn>",
3076 .symbols = .{
3077 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3078 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3079 },
3080 .encode = .{ .fcvtns, .Sd, .Sn },
3081 },
3082 .{
3083 .pattern = "FCVTNS <Dd>, <Dn>",
3084 .symbols = .{
3085 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3086 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3087 },
3088 .encode = .{ .fcvtns, .Dd, .Dn },
3089 },
3090 .{
3091 .requires = .{.fullfp16},
3092 .pattern = "FCVTNS <Vd>.<T>, <Vn>.<T>",
3093 .symbols = .{
3094 .Vd = .{ .reg_alias = .vector },
3095 .T = .{ .arrangement = .{ .elem_size = .half } },
3096 .Vn = .{ .reg_alias = .vector },
3097 },
3098 .encode = .{
3099 .fcvtns,
3100 .{ .alias = .Vd, .format = .{ .vector = .T } },
3101 .{ .alias = .Vn, .format = .{ .vector = .T } },
3102 },
3103 },
3104 .{
3105 .pattern = "FCVTNS <Vd>.<T>, <Vn>.<T>",
3106 .symbols = .{
3107 .Vd = .{ .reg_alias = .vector },
3108 .T = .{ .arrangement = .{ .elem_size = .single } },
3109 .Vn = .{ .reg_alias = .vector },
3110 },
3111 .encode = .{
3112 .fcvtns,
3113 .{ .alias = .Vd, .format = .{ .vector = .T } },
3114 .{ .alias = .Vn, .format = .{ .vector = .T } },
3115 },
3116 },
3117 .{
3118 .pattern = "FCVTNS <Vd>.2D, <Vn>.2D",
3119 .symbols = .{
3120 .Vd = .{ .reg_alias = .vector },
3121 .Vn = .{ .reg_alias = .vector },
3122 },
3123 .encode = .{
3124 .fcvtns,
3125 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3126 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3127 },
3128 },
3129 // C7.2.81 FCVTNS (scalar)
3130 .{
3131 .requires = .{.fullfp16},
3132 .pattern = "FCVTNS <Wd>, <Hn>",
3133 .symbols = .{
3134 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3135 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3136 },
3137 .encode = .{ .fcvtns, .Wd, .Hn },
3138 },
3139 .{
3140 .requires = .{.fullfp16},
3141 .pattern = "FCVTNS <Xd>, <Hn>",
3142 .symbols = .{
3143 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3144 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3145 },
3146 .encode = .{ .fcvtns, .Xd, .Hn },
3147 },
3148 .{
3149 .pattern = "FCVTNS <Wd>, <Sn>",
3150 .symbols = .{
3151 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3152 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3153 },
3154 .encode = .{ .fcvtns, .Wd, .Sn },
3155 },
3156 .{
3157 .pattern = "FCVTNS <Xd>, <Sn>",
3158 .symbols = .{
3159 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3160 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3161 },
3162 .encode = .{ .fcvtns, .Xd, .Sn },
3163 },
3164 .{
3165 .pattern = "FCVTNS <Wd>, <Dn>",
3166 .symbols = .{
3167 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3168 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3169 },
3170 .encode = .{ .fcvtns, .Wd, .Dn },
3171 },
3172 .{
3173 .pattern = "FCVTNS <Xd>, <Dn>",
3174 .symbols = .{
3175 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3176 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3177 },
3178 .encode = .{ .fcvtns, .Xd, .Dn },
3179 },
3180 // C7.2.82 FCVTNU (vector)
3181 .{
3182 .requires = .{.fullfp16},
3183 .pattern = "FCVTNU <Hd>, <Hn>",
3184 .symbols = .{
3185 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3186 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3187 },
3188 .encode = .{ .fcvtnu, .Hd, .Hn },
3189 },
3190 .{
3191 .pattern = "FCVTNU <Sd>, <Sn>",
3192 .symbols = .{
3193 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3194 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3195 },
3196 .encode = .{ .fcvtnu, .Sd, .Sn },
3197 },
3198 .{
3199 .pattern = "FCVTNU <Dd>, <Dn>",
3200 .symbols = .{
3201 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3202 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3203 },
3204 .encode = .{ .fcvtnu, .Dd, .Dn },
3205 },
3206 .{
3207 .requires = .{.fullfp16},
3208 .pattern = "FCVTNU <Vd>.<T>, <Vn>.<T>",
3209 .symbols = .{
3210 .Vd = .{ .reg_alias = .vector },
3211 .T = .{ .arrangement = .{ .elem_size = .half } },
3212 .Vn = .{ .reg_alias = .vector },
3213 },
3214 .encode = .{
3215 .fcvtnu,
3216 .{ .alias = .Vd, .format = .{ .vector = .T } },
3217 .{ .alias = .Vn, .format = .{ .vector = .T } },
3218 },
3219 },
3220 .{
3221 .pattern = "FCVTNU <Vd>.<T>, <Vn>.<T>",
3222 .symbols = .{
3223 .Vd = .{ .reg_alias = .vector },
3224 .T = .{ .arrangement = .{ .elem_size = .single } },
3225 .Vn = .{ .reg_alias = .vector },
3226 },
3227 .encode = .{
3228 .fcvtnu,
3229 .{ .alias = .Vd, .format = .{ .vector = .T } },
3230 .{ .alias = .Vn, .format = .{ .vector = .T } },
3231 },
3232 },
3233 .{
3234 .pattern = "FCVTNU <Vd>.2D, <Vn>.2D",
3235 .symbols = .{
3236 .Vd = .{ .reg_alias = .vector },
3237 .Vn = .{ .reg_alias = .vector },
3238 },
3239 .encode = .{
3240 .fcvtnu,
3241 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3242 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3243 },
3244 },
3245 // C7.2.83 FCVTNU (scalar)
3246 .{
3247 .requires = .{.fullfp16},
3248 .pattern = "FCVTNU <Wd>, <Hn>",
3249 .symbols = .{
3250 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3251 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3252 },
3253 .encode = .{ .fcvtnu, .Wd, .Hn },
3254 },
3255 .{
3256 .requires = .{.fullfp16},
3257 .pattern = "FCVTNU <Xd>, <Hn>",
3258 .symbols = .{
3259 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3260 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3261 },
3262 .encode = .{ .fcvtnu, .Xd, .Hn },
3263 },
3264 .{
3265 .pattern = "FCVTNU <Wd>, <Sn>",
3266 .symbols = .{
3267 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3268 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3269 },
3270 .encode = .{ .fcvtnu, .Wd, .Sn },
3271 },
3272 .{
3273 .pattern = "FCVTNU <Xd>, <Sn>",
3274 .symbols = .{
3275 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3276 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3277 },
3278 .encode = .{ .fcvtnu, .Xd, .Sn },
3279 },
3280 .{
3281 .pattern = "FCVTNU <Wd>, <Dn>",
3282 .symbols = .{
3283 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3284 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3285 },
3286 .encode = .{ .fcvtnu, .Wd, .Dn },
3287 },
3288 .{
3289 .pattern = "FCVTNU <Xd>, <Dn>",
3290 .symbols = .{
3291 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3292 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3293 },
3294 .encode = .{ .fcvtnu, .Xd, .Dn },
3295 },
3296 // C7.2.84 FCVTPS (vector)
3297 .{
3298 .requires = .{.fullfp16},
3299 .pattern = "FCVTPS <Hd>, <Hn>",
3300 .symbols = .{
3301 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3302 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3303 },
3304 .encode = .{ .fcvtps, .Hd, .Hn },
3305 },
3306 .{
3307 .pattern = "FCVTPS <Sd>, <Sn>",
3308 .symbols = .{
3309 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3310 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3311 },
3312 .encode = .{ .fcvtps, .Sd, .Sn },
3313 },
3314 .{
3315 .pattern = "FCVTPS <Dd>, <Dn>",
3316 .symbols = .{
3317 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3318 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3319 },
3320 .encode = .{ .fcvtps, .Dd, .Dn },
3321 },
3322 .{
3323 .requires = .{.fullfp16},
3324 .pattern = "FCVTPS <Vd>.<T>, <Vn>.<T>",
3325 .symbols = .{
3326 .Vd = .{ .reg_alias = .vector },
3327 .T = .{ .arrangement = .{ .elem_size = .half } },
3328 .Vn = .{ .reg_alias = .vector },
3329 },
3330 .encode = .{
3331 .fcvtps,
3332 .{ .alias = .Vd, .format = .{ .vector = .T } },
3333 .{ .alias = .Vn, .format = .{ .vector = .T } },
3334 },
3335 },
3336 .{
3337 .pattern = "FCVTPS <Vd>.<T>, <Vn>.<T>",
3338 .symbols = .{
3339 .Vd = .{ .reg_alias = .vector },
3340 .T = .{ .arrangement = .{ .elem_size = .single } },
3341 .Vn = .{ .reg_alias = .vector },
3342 },
3343 .encode = .{
3344 .fcvtps,
3345 .{ .alias = .Vd, .format = .{ .vector = .T } },
3346 .{ .alias = .Vn, .format = .{ .vector = .T } },
3347 },
3348 },
3349 .{
3350 .pattern = "FCVTPS <Vd>.2D, <Vn>.2D",
3351 .symbols = .{
3352 .Vd = .{ .reg_alias = .vector },
3353 .Vn = .{ .reg_alias = .vector },
3354 },
3355 .encode = .{
3356 .fcvtps,
3357 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3358 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3359 },
3360 },
3361 // C7.2.85 FCVTPS (scalar)
3362 .{
3363 .requires = .{.fullfp16},
3364 .pattern = "FCVTPS <Wd>, <Hn>",
3365 .symbols = .{
3366 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3367 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3368 },
3369 .encode = .{ .fcvtps, .Wd, .Hn },
3370 },
3371 .{
3372 .requires = .{.fullfp16},
3373 .pattern = "FCVTPS <Xd>, <Hn>",
3374 .symbols = .{
3375 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3376 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3377 },
3378 .encode = .{ .fcvtps, .Xd, .Hn },
3379 },
3380 .{
3381 .pattern = "FCVTPS <Wd>, <Sn>",
3382 .symbols = .{
3383 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3384 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3385 },
3386 .encode = .{ .fcvtps, .Wd, .Sn },
3387 },
3388 .{
3389 .pattern = "FCVTPS <Xd>, <Sn>",
3390 .symbols = .{
3391 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3392 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3393 },
3394 .encode = .{ .fcvtps, .Xd, .Sn },
3395 },
3396 .{
3397 .pattern = "FCVTPS <Wd>, <Dn>",
3398 .symbols = .{
3399 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3400 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3401 },
3402 .encode = .{ .fcvtps, .Wd, .Dn },
3403 },
3404 .{
3405 .pattern = "FCVTPS <Xd>, <Dn>",
3406 .symbols = .{
3407 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3408 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3409 },
3410 .encode = .{ .fcvtps, .Xd, .Dn },
3411 },
3412 // C7.2.86 FCVTPU (vector)
3413 .{
3414 .requires = .{.fullfp16},
3415 .pattern = "FCVTPU <Hd>, <Hn>",
3416 .symbols = .{
3417 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3418 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3419 },
3420 .encode = .{ .fcvtpu, .Hd, .Hn },
3421 },
3422 .{
3423 .pattern = "FCVTPU <Sd>, <Sn>",
3424 .symbols = .{
3425 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3426 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3427 },
3428 .encode = .{ .fcvtpu, .Sd, .Sn },
3429 },
3430 .{
3431 .pattern = "FCVTPU <Dd>, <Dn>",
3432 .symbols = .{
3433 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3434 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3435 },
3436 .encode = .{ .fcvtpu, .Dd, .Dn },
3437 },
3438 .{
3439 .requires = .{.fullfp16},
3440 .pattern = "FCVTPU <Vd>.<T>, <Vn>.<T>",
3441 .symbols = .{
3442 .Vd = .{ .reg_alias = .vector },
3443 .T = .{ .arrangement = .{ .elem_size = .half } },
3444 .Vn = .{ .reg_alias = .vector },
3445 },
3446 .encode = .{
3447 .fcvtpu,
3448 .{ .alias = .Vd, .format = .{ .vector = .T } },
3449 .{ .alias = .Vn, .format = .{ .vector = .T } },
3450 },
3451 },
3452 .{
3453 .pattern = "FCVTPU <Vd>.<T>, <Vn>.<T>",
3454 .symbols = .{
3455 .Vd = .{ .reg_alias = .vector },
3456 .T = .{ .arrangement = .{ .elem_size = .single } },
3457 .Vn = .{ .reg_alias = .vector },
3458 },
3459 .encode = .{
3460 .fcvtpu,
3461 .{ .alias = .Vd, .format = .{ .vector = .T } },
3462 .{ .alias = .Vn, .format = .{ .vector = .T } },
3463 },
3464 },
3465 .{
3466 .pattern = "FCVTPU <Vd>.2D, <Vn>.2D",
3467 .symbols = .{
3468 .Vd = .{ .reg_alias = .vector },
3469 .Vn = .{ .reg_alias = .vector },
3470 },
3471 .encode = .{
3472 .fcvtpu,
3473 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3474 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3475 },
3476 },
3477 // C7.2.87 FCVTPU (scalar)
3478 .{
3479 .requires = .{.fullfp16},
3480 .pattern = "FCVTPU <Wd>, <Hn>",
3481 .symbols = .{
3482 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3483 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3484 },
3485 .encode = .{ .fcvtpu, .Wd, .Hn },
3486 },
3487 .{
3488 .requires = .{.fullfp16},
3489 .pattern = "FCVTPU <Xd>, <Hn>",
3490 .symbols = .{
3491 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3492 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3493 },
3494 .encode = .{ .fcvtpu, .Xd, .Hn },
3495 },
3496 .{
3497 .pattern = "FCVTPU <Wd>, <Sn>",
3498 .symbols = .{
3499 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3500 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3501 },
3502 .encode = .{ .fcvtpu, .Wd, .Sn },
3503 },
3504 .{
3505 .pattern = "FCVTPU <Xd>, <Sn>",
3506 .symbols = .{
3507 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3508 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3509 },
3510 .encode = .{ .fcvtpu, .Xd, .Sn },
3511 },
3512 .{
3513 .pattern = "FCVTPU <Wd>, <Dn>",
3514 .symbols = .{
3515 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3516 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3517 },
3518 .encode = .{ .fcvtpu, .Wd, .Dn },
3519 },
3520 .{
3521 .pattern = "FCVTPU <Xd>, <Dn>",
3522 .symbols = .{
3523 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3524 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3525 },
3526 .encode = .{ .fcvtpu, .Xd, .Dn },
3527 },
3528 // C7.2.90 FCVTZS (vector, integer)
3529 .{
3530 .requires = .{.fullfp16},
3531 .pattern = "FCVTZS <Hd>, <Hn>",
3532 .symbols = .{
3533 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3534 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3535 },
3536 .encode = .{ .fcvtzs, .Hd, .Hn },
3537 },
3538 .{
3539 .pattern = "FCVTZS <Sd>, <Sn>",
3540 .symbols = .{
3541 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3542 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3543 },
3544 .encode = .{ .fcvtzs, .Sd, .Sn },
3545 },
3546 .{
3547 .pattern = "FCVTZS <Dd>, <Dn>",
3548 .symbols = .{
3549 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3550 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3551 },
3552 .encode = .{ .fcvtzs, .Dd, .Dn },
3553 },
3554 .{
3555 .requires = .{.fullfp16},
3556 .pattern = "FCVTZS <Vd>.<T>, <Vn>.<T>",
3557 .symbols = .{
3558 .Vd = .{ .reg_alias = .vector },
3559 .T = .{ .arrangement = .{ .elem_size = .half } },
3560 .Vn = .{ .reg_alias = .vector },
3561 },
3562 .encode = .{
3563 .fcvtzs,
3564 .{ .alias = .Vd, .format = .{ .vector = .T } },
3565 .{ .alias = .Vn, .format = .{ .vector = .T } },
3566 },
3567 },
3568 .{
3569 .pattern = "FCVTZS <Vd>.<T>, <Vn>.<T>",
3570 .symbols = .{
3571 .Vd = .{ .reg_alias = .vector },
3572 .T = .{ .arrangement = .{ .elem_size = .single } },
3573 .Vn = .{ .reg_alias = .vector },
3574 },
3575 .encode = .{
3576 .fcvtzs,
3577 .{ .alias = .Vd, .format = .{ .vector = .T } },
3578 .{ .alias = .Vn, .format = .{ .vector = .T } },
3579 },
3580 },
3581 .{
3582 .pattern = "FCVTZS <Vd>.2D, <Vn>.2D",
3583 .symbols = .{
3584 .Vd = .{ .reg_alias = .vector },
3585 .Vn = .{ .reg_alias = .vector },
3586 },
3587 .encode = .{
3588 .fcvtzs,
3589 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3590 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3591 },
3592 },
3593 // C7.2.92 FCVTZS (scalar, integer)
3594 .{
3595 .requires = .{.fullfp16},
3596 .pattern = "FCVTZS <Wd>, <Hn>",
3597 .symbols = .{
3598 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3599 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3600 },
3601 .encode = .{ .fcvtzs, .Wd, .Hn },
3602 },
3603 .{
3604 .requires = .{.fullfp16},
3605 .pattern = "FCVTZS <Xd>, <Hn>",
3606 .symbols = .{
3607 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3608 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3609 },
3610 .encode = .{ .fcvtzs, .Xd, .Hn },
3611 },
3612 .{
3613 .pattern = "FCVTZS <Wd>, <Sn>",
3614 .symbols = .{
3615 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3616 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3617 },
3618 .encode = .{ .fcvtzs, .Wd, .Sn },
3619 },
3620 .{
3621 .pattern = "FCVTZS <Xd>, <Sn>",
3622 .symbols = .{
3623 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3624 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3625 },
3626 .encode = .{ .fcvtzs, .Xd, .Sn },
3627 },
3628 .{
3629 .pattern = "FCVTZS <Wd>, <Dn>",
3630 .symbols = .{
3631 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3632 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3633 },
3634 .encode = .{ .fcvtzs, .Wd, .Dn },
3635 },
3636 .{
3637 .pattern = "FCVTZS <Xd>, <Dn>",
3638 .symbols = .{
3639 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3640 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3641 },
3642 .encode = .{ .fcvtzs, .Xd, .Dn },
3643 },
3644 // C7.2.94 FCVTZU (vector, integer)
3645 .{
3646 .requires = .{.fullfp16},
3647 .pattern = "FCVTZU <Hd>, <Hn>",
3648 .symbols = .{
3649 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3650 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3651 },
3652 .encode = .{ .fcvtzu, .Hd, .Hn },
3653 },
3654 .{
3655 .pattern = "FCVTZU <Sd>, <Sn>",
3656 .symbols = .{
3657 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3658 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3659 },
3660 .encode = .{ .fcvtzu, .Sd, .Sn },
3661 },
3662 .{
3663 .pattern = "FCVTZU <Dd>, <Dn>",
3664 .symbols = .{
3665 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3666 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3667 },
3668 .encode = .{ .fcvtzu, .Dd, .Dn },
3669 },
3670 .{
3671 .requires = .{.fullfp16},
3672 .pattern = "FCVTZU <Vd>.<T>, <Vn>.<T>",
3673 .symbols = .{
3674 .Vd = .{ .reg_alias = .vector },
3675 .T = .{ .arrangement = .{ .elem_size = .half } },
3676 .Vn = .{ .reg_alias = .vector },
3677 },
3678 .encode = .{
3679 .fcvtzu,
3680 .{ .alias = .Vd, .format = .{ .vector = .T } },
3681 .{ .alias = .Vn, .format = .{ .vector = .T } },
3682 },
3683 },
3684 .{
3685 .pattern = "FCVTZU <Vd>.<T>, <Vn>.<T>",
3686 .symbols = .{
3687 .Vd = .{ .reg_alias = .vector },
3688 .T = .{ .arrangement = .{ .elem_size = .single } },
3689 .Vn = .{ .reg_alias = .vector },
3690 },
3691 .encode = .{
3692 .fcvtzu,
3693 .{ .alias = .Vd, .format = .{ .vector = .T } },
3694 .{ .alias = .Vn, .format = .{ .vector = .T } },
3695 },
3696 },
3697 .{
3698 .pattern = "FCVTZU <Vd>.2D, <Vn>.2D",
3699 .symbols = .{
3700 .Vd = .{ .reg_alias = .vector },
3701 .Vn = .{ .reg_alias = .vector },
3702 },
3703 .encode = .{
3704 .fcvtzu,
3705 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3706 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3707 },
3708 },
3709 // C7.2.96 FCVTZU (scalar, integer)
3710 .{
3711 .requires = .{.fullfp16},
3712 .pattern = "FCVTZU <Wd>, <Hn>",
3713 .symbols = .{
3714 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3715 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3716 },
3717 .encode = .{ .fcvtzu, .Wd, .Hn },
3718 },
3719 .{
3720 .requires = .{.fullfp16},
3721 .pattern = "FCVTZU <Xd>, <Hn>",
3722 .symbols = .{
3723 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3724 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3725 },
3726 .encode = .{ .fcvtzu, .Xd, .Hn },
3727 },
3728 .{
3729 .pattern = "FCVTZU <Wd>, <Sn>",
3730 .symbols = .{
3731 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3732 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3733 },
3734 .encode = .{ .fcvtzu, .Wd, .Sn },
3735 },
3736 .{
3737 .pattern = "FCVTZU <Xd>, <Sn>",
3738 .symbols = .{
3739 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3740 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3741 },
3742 .encode = .{ .fcvtzu, .Xd, .Sn },
3743 },
3744 .{
3745 .pattern = "FCVTZU <Wd>, <Dn>",
3746 .symbols = .{
3747 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3748 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3749 },
3750 .encode = .{ .fcvtzu, .Wd, .Dn },
3751 },
3752 .{
3753 .pattern = "FCVTZU <Xd>, <Dn>",
3754 .symbols = .{
3755 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3756 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3757 },
3758 .encode = .{ .fcvtzu, .Xd, .Dn },
3759 },
3760 // C7.2.129 FMOV (vector, immediate)
3761 .{
3762 .requires = .{.fullfp16},
3763 .pattern = "FMOV <Vd>.<T>, #<imm>",
3764 .symbols = .{
3765 .Vd = .{ .reg_alias = .vector },
3766 .T = .{ .arrangement = .{ .elem_size = .half } },
3767 .imm = .{ .fimm = .{} },
3768 },
3769 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .T } }, .{ .immediate = .imm } },
3770 },
3771 .{
3772 .pattern = "FMOV <Vd>.<T>, #<imm>",
3773 .symbols = .{
3774 .Vd = .{ .reg_alias = .vector },
3775 .T = .{ .arrangement = .{ .elem_size = .single } },
3776 .imm = .{ .fimm = .{} },
3777 },
3778 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .T } }, .{ .immediate = .imm } },
3779 },
3780 .{
3781 .pattern = "FMOV <Vd>.2D, #<imm>",
3782 .symbols = .{
3783 .Vd = .{ .reg_alias = .vector },
3784 .imm = .{ .fimm = .{} },
3785 },
3786 .encode = .{ .fmov, .{ .alias = .Vd, .format = .{ .vector = .@"2d" } }, .{ .immediate = .imm } },
3787 },
3788 // C7.2.130 FMOV (register)
3789 .{
3790 .requires = .{.fullfp16},
3791 .pattern = "FMOV <Hd>, <Hn>",
3792 .symbols = .{
3793 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3794 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3795 },
3796 .encode = .{ .fmov, .Hd, .{ .register = .Hn } },
3797 },
3798 .{
3799 .pattern = "FMOV <Sd>, <Sn>",
3800 .symbols = .{
3801 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3802 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3803 },
3804 .encode = .{ .fmov, .Sd, .{ .register = .Sn } },
3805 },
3806 .{
3807 .pattern = "FMOV <Dd>, <Dn>",
3808 .symbols = .{
3809 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3810 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3811 },
3812 .encode = .{ .fmov, .Dd, .{ .register = .Dn } },
3813 },
3814 // C7.2.131 FMOV (general)
3815 .{
3816 .requires = .{.fullfp16},
3817 .pattern = "FMOV <Wd>, <Hn>",
3818 .symbols = .{
3819 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3820 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3821 },
3822 .encode = .{ .fmov, .Wd, .{ .register = .Hn } },
3823 },
3824 .{
3825 .requires = .{.fullfp16},
3826 .pattern = "FMOV <Xd>, <Hn>",
3827 .symbols = .{
3828 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3829 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3830 },
3831 .encode = .{ .fmov, .Xd, .{ .register = .Hn } },
3832 },
3833 .{
3834 .requires = .{.fullfp16},
3835 .pattern = "FMOV <Hd>, <Wn>",
3836 .symbols = .{
3837 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3838 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
3839 },
3840 .encode = .{ .fmov, .Hd, .{ .register = .Wn } },
3841 },
3842 .{
3843 .pattern = "FMOV <Sd>, <Wn>",
3844 .symbols = .{
3845 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3846 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
3847 },
3848 .encode = .{ .fmov, .Sd, .{ .register = .Wn } },
3849 },
3850 .{
3851 .pattern = "FMOV <Wd>, <Sn>",
3852 .symbols = .{
3853 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
3854 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3855 },
3856 .encode = .{ .fmov, .Wd, .{ .register = .Sn } },
3857 },
3858 .{
3859 .requires = .{.fullfp16},
3860 .pattern = "FMOV <Hd>, <Xn>",
3861 .symbols = .{
3862 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3863 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3864 },
3865 .encode = .{ .fmov, .Hd, .{ .register = .Xn } },
3866 },
3867 .{
3868 .pattern = "FMOV <Dd>, <Xn>",
3869 .symbols = .{
3870 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3871 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3872 },
3873 .encode = .{ .fmov, .Dd, .{ .register = .Xn } },
3874 },
3875 .{
3876 .pattern = "FMOV <Vd>.D[<index>], <Xn>",
3877 .symbols = .{
3878 .Vd = .{ .reg_alias = .vector },
3879 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 }, .min_valid = 1 } },
3880 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3881 },
3882 .encode = .{
3883 .fmov,
3884 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
3885 .{ .register = .Xn },
3886 },
3887 },
3888 .{
3889 .pattern = "FMOV <Xd>, <Dn>",
3890 .symbols = .{
3891 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3892 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3893 },
3894 .encode = .{ .fmov, .Xd, .{ .register = .Dn } },
3895 },
3896 .{
3897 .pattern = "FMOV <Xd>, <Vn>.D[<index>]",
3898 .symbols = .{
3899 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
3900 .Vn = .{ .reg_alias = .vector },
3901 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 }, .min_valid = 1 } },
3902 },
3903 .encode = .{ .fmov, .Xd, .{
3904 .register = .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
3905 } },
3906 },
3907 // C7.2.132 FMOV (scalar, immediate)
3908 .{
3909 .requires = .{.fullfp16},
3910 .pattern = "FMOV <Hd>, #<imm>",
3911 .symbols = .{
3912 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3913 .imm = .{ .fimm = .{} },
3914 },
3915 .encode = .{ .fmov, .Hd, .{ .immediate = .imm } },
3916 },
3917 .{
3918 .pattern = "FMOV <Sd>, #<imm>",
3919 .symbols = .{
3920 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3921 .imm = .{ .fimm = .{} },
3922 },
3923 .encode = .{ .fmov, .Sd, .{ .immediate = .imm } },
3924 },
3925 .{
3926 .pattern = "FMOV <Dd>, #<imm>",
3927 .symbols = .{
3928 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3929 .imm = .{ .fimm = .{} },
3930 },
3931 .encode = .{ .fmov, .Dd, .{ .immediate = .imm } },
3932 },
3933 // C7.2.157 FRINTI (vector)
3934 .{
3935 .requires = .{.fullfp16},
3936 .pattern = "FRINTI <Vd>.<T>, <Vn>.<T>",
3937 .symbols = .{
3938 .Vd = .{ .reg_alias = .vector },
3939 .T = .{ .arrangement = .{ .elem_size = .half } },
3940 .Vn = .{ .reg_alias = .vector },
3941 },
3942 .encode = .{
3943 .frinti,
3944 .{ .alias = .Vd, .format = .{ .vector = .T } },
3945 .{ .alias = .Vn, .format = .{ .vector = .T } },
3946 },
3947 },
3948 .{
3949 .pattern = "FRINTI <Vd>.<T>, <Vn>.<T>",
3950 .symbols = .{
3951 .Vd = .{ .reg_alias = .vector },
3952 .T = .{ .arrangement = .{ .elem_size = .single } },
3953 .Vn = .{ .reg_alias = .vector },
3954 },
3955 .encode = .{
3956 .frinti,
3957 .{ .alias = .Vd, .format = .{ .vector = .T } },
3958 .{ .alias = .Vn, .format = .{ .vector = .T } },
3959 },
3960 },
3961 .{
3962 .pattern = "FRINTI <Vd>.2D, <Vn>.2D",
3963 .symbols = .{
3964 .Vd = .{ .reg_alias = .vector },
3965 .Vn = .{ .reg_alias = .vector },
3966 },
3967 .encode = .{
3968 .frinti,
3969 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
3970 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
3971 },
3972 },
3973 // C7.2.168 FRINTI (scalar)
3974 .{
3975 .requires = .{.fullfp16},
3976 .pattern = "FRINTI <Hd>, <Hn>",
3977 .symbols = .{
3978 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
3979 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
3980 },
3981 .encode = .{ .frinti, .Hd, .Hn },
3982 },
3983 .{
3984 .pattern = "FRINTI <Sd>, <Sn>",
3985 .symbols = .{
3986 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
3987 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
3988 },
3989 .encode = .{ .frinti, .Sd, .Sn },
3990 },
3991 .{
3992 .pattern = "FRINTI <Dd>, <Dn>",
3993 .symbols = .{
3994 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
3995 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
3996 },
3997 .encode = .{ .frinti, .Dd, .Dn },
3998 },
3999 // C7.2.159 FRINTM (vector)
4000 .{
4001 .requires = .{.fullfp16},
4002 .pattern = "FRINTM <Vd>.<T>, <Vn>.<T>",
4003 .symbols = .{
4004 .Vd = .{ .reg_alias = .vector },
4005 .T = .{ .arrangement = .{ .elem_size = .half } },
4006 .Vn = .{ .reg_alias = .vector },
4007 },
4008 .encode = .{
4009 .frintm,
4010 .{ .alias = .Vd, .format = .{ .vector = .T } },
4011 .{ .alias = .Vn, .format = .{ .vector = .T } },
4012 },
4013 },
4014 .{
4015 .pattern = "FRINTM <Vd>.<T>, <Vn>.<T>",
4016 .symbols = .{
4017 .Vd = .{ .reg_alias = .vector },
4018 .T = .{ .arrangement = .{ .elem_size = .single } },
4019 .Vn = .{ .reg_alias = .vector },
4020 },
4021 .encode = .{
4022 .frintm,
4023 .{ .alias = .Vd, .format = .{ .vector = .T } },
4024 .{ .alias = .Vn, .format = .{ .vector = .T } },
4025 },
4026 },
4027 .{
4028 .pattern = "FRINTM <Vd>.2D, <Vn>.2D",
4029 .symbols = .{
4030 .Vd = .{ .reg_alias = .vector },
4031 .Vn = .{ .reg_alias = .vector },
4032 },
4033 .encode = .{
4034 .frintm,
4035 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4036 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4037 },
4038 },
4039 // C7.2.160 FRINTM (scalar)
4040 .{
4041 .requires = .{.fullfp16},
4042 .pattern = "FRINTM <Hd>, <Hn>",
4043 .symbols = .{
4044 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4045 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4046 },
4047 .encode = .{ .frintm, .Hd, .Hn },
4048 },
4049 .{
4050 .pattern = "FRINTM <Sd>, <Sn>",
4051 .symbols = .{
4052 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4053 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4054 },
4055 .encode = .{ .frintm, .Sd, .Sn },
4056 },
4057 .{
4058 .pattern = "FRINTM <Dd>, <Dn>",
4059 .symbols = .{
4060 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4061 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4062 },
4063 .encode = .{ .frintm, .Dd, .Dn },
4064 },
4065 // C7.2.161 FRINTN (vector)
4066 .{
4067 .requires = .{.fullfp16},
4068 .pattern = "FRINTN <Vd>.<T>, <Vn>.<T>",
4069 .symbols = .{
4070 .Vd = .{ .reg_alias = .vector },
4071 .T = .{ .arrangement = .{ .elem_size = .half } },
4072 .Vn = .{ .reg_alias = .vector },
4073 },
4074 .encode = .{
4075 .frintn,
4076 .{ .alias = .Vd, .format = .{ .vector = .T } },
4077 .{ .alias = .Vn, .format = .{ .vector = .T } },
4078 },
4079 },
4080 .{
4081 .pattern = "FRINTN <Vd>.<T>, <Vn>.<T>",
4082 .symbols = .{
4083 .Vd = .{ .reg_alias = .vector },
4084 .T = .{ .arrangement = .{ .elem_size = .single } },
4085 .Vn = .{ .reg_alias = .vector },
4086 },
4087 .encode = .{
4088 .frintn,
4089 .{ .alias = .Vd, .format = .{ .vector = .T } },
4090 .{ .alias = .Vn, .format = .{ .vector = .T } },
4091 },
4092 },
4093 .{
4094 .pattern = "FRINTN <Vd>.2D, <Vn>.2D",
4095 .symbols = .{
4096 .Vd = .{ .reg_alias = .vector },
4097 .Vn = .{ .reg_alias = .vector },
4098 },
4099 .encode = .{
4100 .frintn,
4101 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4102 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4103 },
4104 },
4105 // C7.2.162 FRINTN (scalar)
4106 .{
4107 .requires = .{.fullfp16},
4108 .pattern = "FRINTN <Hd>, <Hn>",
4109 .symbols = .{
4110 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4111 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4112 },
4113 .encode = .{ .frintn, .Hd, .Hn },
4114 },
4115 .{
4116 .pattern = "FRINTN <Sd>, <Sn>",
4117 .symbols = .{
4118 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4119 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4120 },
4121 .encode = .{ .frintn, .Sd, .Sn },
4122 },
4123 .{
4124 .pattern = "FRINTN <Dd>, <Dn>",
4125 .symbols = .{
4126 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4127 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4128 },
4129 .encode = .{ .frintn, .Dd, .Dn },
4130 },
4131 // C7.2.163 FRINTP (vector)
4132 .{
4133 .requires = .{.fullfp16},
4134 .pattern = "FRINTP <Vd>.<T>, <Vn>.<T>",
4135 .symbols = .{
4136 .Vd = .{ .reg_alias = .vector },
4137 .T = .{ .arrangement = .{ .elem_size = .half } },
4138 .Vn = .{ .reg_alias = .vector },
4139 },
4140 .encode = .{
4141 .frintp,
4142 .{ .alias = .Vd, .format = .{ .vector = .T } },
4143 .{ .alias = .Vn, .format = .{ .vector = .T } },
4144 },
4145 },
4146 .{
4147 .pattern = "FRINTP <Vd>.<T>, <Vn>.<T>",
4148 .symbols = .{
4149 .Vd = .{ .reg_alias = .vector },
4150 .T = .{ .arrangement = .{ .elem_size = .single } },
4151 .Vn = .{ .reg_alias = .vector },
4152 },
4153 .encode = .{
4154 .frintp,
4155 .{ .alias = .Vd, .format = .{ .vector = .T } },
4156 .{ .alias = .Vn, .format = .{ .vector = .T } },
4157 },
4158 },
4159 .{
4160 .pattern = "FRINTP <Vd>.2D, <Vn>.2D",
4161 .symbols = .{
4162 .Vd = .{ .reg_alias = .vector },
4163 .Vn = .{ .reg_alias = .vector },
4164 },
4165 .encode = .{
4166 .frintp,
4167 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4168 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4169 },
4170 },
4171 // C7.2.164 FRINTP (scalar)
4172 .{
4173 .requires = .{.fullfp16},
4174 .pattern = "FRINTP <Hd>, <Hn>",
4175 .symbols = .{
4176 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4177 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4178 },
4179 .encode = .{ .frintp, .Hd, .Hn },
4180 },
4181 .{
4182 .pattern = "FRINTP <Sd>, <Sn>",
4183 .symbols = .{
4184 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4185 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4186 },
4187 .encode = .{ .frintp, .Sd, .Sn },
4188 },
4189 .{
4190 .pattern = "FRINTP <Dd>, <Dn>",
4191 .symbols = .{
4192 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4193 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4194 },
4195 .encode = .{ .frintp, .Dd, .Dn },
4196 },
4197 // C7.2.167 FRINTZ (vector)
4198 .{
4199 .requires = .{.fullfp16},
4200 .pattern = "FRINTZ <Vd>.<T>, <Vn>.<T>",
4201 .symbols = .{
4202 .Vd = .{ .reg_alias = .vector },
4203 .T = .{ .arrangement = .{ .elem_size = .half } },
4204 .Vn = .{ .reg_alias = .vector },
4205 },
4206 .encode = .{
4207 .frintz,
4208 .{ .alias = .Vd, .format = .{ .vector = .T } },
4209 .{ .alias = .Vn, .format = .{ .vector = .T } },
4210 },
4211 },
4212 .{
4213 .pattern = "FRINTZ <Vd>.<T>, <Vn>.<T>",
4214 .symbols = .{
4215 .Vd = .{ .reg_alias = .vector },
4216 .T = .{ .arrangement = .{ .elem_size = .single } },
4217 .Vn = .{ .reg_alias = .vector },
4218 },
4219 .encode = .{
4220 .frintz,
4221 .{ .alias = .Vd, .format = .{ .vector = .T } },
4222 .{ .alias = .Vn, .format = .{ .vector = .T } },
4223 },
4224 },
4225 .{
4226 .pattern = "FRINTZ <Vd>.2D, <Vn>.2D",
4227 .symbols = .{
4228 .Vd = .{ .reg_alias = .vector },
4229 .Vn = .{ .reg_alias = .vector },
4230 },
4231 .encode = .{
4232 .frintz,
4233 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4234 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4235 },
4236 },
4237 // C7.2.168 FRINTZ (scalar)
4238 .{
4239 .requires = .{.fullfp16},
4240 .pattern = "FRINTZ <Hd>, <Hn>",
4241 .symbols = .{
4242 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4243 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4244 },
4245 .encode = .{ .frintz, .Hd, .Hn },
4246 },
4247 .{
4248 .pattern = "FRINTZ <Sd>, <Sn>",
4249 .symbols = .{
4250 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4251 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4252 },
4253 .encode = .{ .frintz, .Sd, .Sn },
4254 },
4255 .{
4256 .pattern = "FRINTZ <Dd>, <Dn>",
4257 .symbols = .{
4258 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4259 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4260 },
4261 .encode = .{ .frintz, .Dd, .Dn },
4262 },
4263 // C7.2.175 INS (element)
4264 .{
4265 .pattern = "INS <Vd>.B[<index1>], <Vn>.B[<index2>]",
4266 .symbols = .{
4267 .Vd = .{ .reg_alias = .vector },
4268 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4269 .Vn = .{ .reg_alias = .vector },
4270 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4271 },
4272 .encode = .{
4273 .ins,
4274 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index1 } } },
4275 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index2 } } },
4276 },
4277 },
4278 .{
4279 .pattern = "INS <Vd>.H[<index1>], <Vn>.H[<index2>]",
4280 .symbols = .{
4281 .Vd = .{ .reg_alias = .vector },
4282 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4283 .Vn = .{ .reg_alias = .vector },
4284 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4285 },
4286 .encode = .{
4287 .ins,
4288 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index1 } } },
4289 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index2 } } },
4290 },
4291 },
4292 .{
4293 .pattern = "INS <Vd>.S[<index1>], <Vn>.S[<index2>]",
4294 .symbols = .{
4295 .Vd = .{ .reg_alias = .vector },
4296 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4297 .Vn = .{ .reg_alias = .vector },
4298 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4299 },
4300 .encode = .{
4301 .ins,
4302 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index1 } } },
4303 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index2 } } },
4304 },
4305 },
4306 .{
4307 .pattern = "INS <Vd>.D[<index1>], <Vn>.D[<index2>]",
4308 .symbols = .{
4309 .Vd = .{ .reg_alias = .vector },
4310 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4311 .Vn = .{ .reg_alias = .vector },
4312 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4313 },
4314 .encode = .{
4315 .ins,
4316 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index1 } } },
4317 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index2 } } },
4318 },
4319 },
4320 // C7.2.176 INS (general)
4321 .{
4322 .pattern = "INS <Vd>.B[<index>], <Wn>",
4323 .symbols = .{
4324 .Vd = .{ .reg_alias = .vector },
4325 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4326 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4327 },
4328 .encode = .{
4329 .ins,
4330 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4331 .Wn,
4332 },
4333 },
4334 .{
4335 .pattern = "INS <Vd>.H[<index>], <Wn>",
4336 .symbols = .{
4337 .Vd = .{ .reg_alias = .vector },
4338 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4339 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4340 },
4341 .encode = .{
4342 .ins,
4343 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index } } },
4344 .Wn,
4345 },
4346 },
4347 .{
4348 .pattern = "INS <Vd>.S[<index>], <Wn>",
4349 .symbols = .{
4350 .Vd = .{ .reg_alias = .vector },
4351 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4352 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4353 },
4354 .encode = .{
4355 .ins,
4356 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index } } },
4357 .Wn,
4358 },
4359 },
4360 .{
4361 .pattern = "INS <Vd>.D[<index>], <Xn>",
4362 .symbols = .{
4363 .Vd = .{ .reg_alias = .vector },
4364 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4365 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4366 },
4367 .encode = .{
4368 .ins,
4369 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
4370 .Xn,
4371 },
4372 },
4373 // C7.2.199 MOV (scalar)
4374 .{
4375 .pattern = "MOV <Vd>, <Vn>.B[<index>]",
4376 .symbols = .{
4377 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4378 .Vn = .{ .reg_alias = .vector },
4379 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4380 },
4381 .encode = .{
4382 .dup,
4383 .Vd,
4384 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4385 },
4386 },
4387 .{
4388 .pattern = "MOV <Vd>, <Vn>.H[<index>]",
4389 .symbols = .{
4390 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4391 .Vn = .{ .reg_alias = .vector },
4392 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4393 },
4394 .encode = .{
4395 .dup,
4396 .Vd,
4397 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4398 },
4399 },
4400 .{
4401 .pattern = "MOV <Vd>, <Vn>.S[<index>]",
4402 .symbols = .{
4403 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4404 .Vn = .{ .reg_alias = .vector },
4405 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4406 },
4407 .encode = .{
4408 .dup,
4409 .Vd,
4410 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4411 },
4412 },
4413 .{
4414 .pattern = "MOV <Vd>, <Vn>.D[<index>]",
4415 .symbols = .{
4416 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4417 .Vn = .{ .reg_alias = .vector },
4418 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4419 },
4420 .encode = .{
4421 .dup,
4422 .Vd,
4423 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
4424 },
4425 },
4426 // C7.2.200 MOV (element)
4427 .{
4428 .pattern = "MOV <Vd>.B[<index1>], <Vn>.B[<index2>]",
4429 .symbols = .{
4430 .Vd = .{ .reg_alias = .vector },
4431 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4432 .Vn = .{ .reg_alias = .vector },
4433 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4434 },
4435 .encode = .{
4436 .ins,
4437 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index1 } } },
4438 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index2 } } },
4439 },
4440 },
4441 .{
4442 .pattern = "MOV <Vd>.H[<index1>], <Vn>.H[<index2>]",
4443 .symbols = .{
4444 .Vd = .{ .reg_alias = .vector },
4445 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4446 .Vn = .{ .reg_alias = .vector },
4447 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4448 },
4449 .encode = .{
4450 .ins,
4451 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index1 } } },
4452 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index2 } } },
4453 },
4454 },
4455 .{
4456 .pattern = "MOV <Vd>.S[<index1>], <Vn>.S[<index2>]",
4457 .symbols = .{
4458 .Vd = .{ .reg_alias = .vector },
4459 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4460 .Vn = .{ .reg_alias = .vector },
4461 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4462 },
4463 .encode = .{
4464 .ins,
4465 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index1 } } },
4466 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index2 } } },
4467 },
4468 },
4469 .{
4470 .pattern = "MOV <Vd>.D[<index1>], <Vn>.D[<index2>]",
4471 .symbols = .{
4472 .Vd = .{ .reg_alias = .vector },
4473 .index1 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4474 .Vn = .{ .reg_alias = .vector },
4475 .index2 = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4476 },
4477 .encode = .{
4478 .ins,
4479 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index1 } } },
4480 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index2 } } },
4481 },
4482 },
4483 // C7.2.201 MOV (from general)
4484 .{
4485 .pattern = "MOV <Vd>.B[<index>], <Wn>",
4486 .symbols = .{
4487 .Vd = .{ .reg_alias = .vector },
4488 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4489 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4490 },
4491 .encode = .{
4492 .ins,
4493 .{ .alias = .Vd, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4494 .Wn,
4495 },
4496 },
4497 .{
4498 .pattern = "MOV <Vd>.H[<index>], <Wn>",
4499 .symbols = .{
4500 .Vd = .{ .reg_alias = .vector },
4501 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4502 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4503 },
4504 .encode = .{
4505 .ins,
4506 .{ .alias = .Vd, .format = .{ .element = .{ .size = .half, .index = .index } } },
4507 .Wn,
4508 },
4509 },
4510 .{
4511 .pattern = "MOV <Vd>.S[<index>], <Wn>",
4512 .symbols = .{
4513 .Vd = .{ .reg_alias = .vector },
4514 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4515 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4516 },
4517 .encode = .{
4518 .ins,
4519 .{ .alias = .Vd, .format = .{ .element = .{ .size = .single, .index = .index } } },
4520 .Wn,
4521 },
4522 },
4523 .{
4524 .pattern = "MOV <Vd>.D[<index>], <Xn>",
4525 .symbols = .{
4526 .Vd = .{ .reg_alias = .vector },
4527 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4528 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4529 },
4530 .encode = .{
4531 .ins,
4532 .{ .alias = .Vd, .format = .{ .element = .{ .size = .double, .index = .index } } },
4533 .Xn,
4534 },
4535 },
4536 // C7.2.202 MOV (vector)
4537 .{
4538 .pattern = "MOV <Vd>.<T>, <Vn>.<T>",
4539 .symbols = .{
4540 .Vd = .{ .reg_alias = .vector },
4541 .T = .{ .arrangement = .{ .elem_size = .byte } },
4542 .Vn = .{ .reg_alias = .vector },
4543 },
4544 .encode = .{
4545 .orr,
4546 .{ .alias = .Vd, .format = .{ .vector = .T } },
4547 .{ .alias = .Vn, .format = .{ .vector = .T } },
4548 .{ .register = .{ .alias = .Vn, .format = .{ .vector = .T } } },
4549 },
4550 },
4551 // C7.2.203 MOV (to general)
4552 .{
4553 .pattern = "MOV <Wd>, <Vn>.S[<index>]",
4554 .symbols = .{
4555 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4556 .Vn = .{ .reg_alias = .vector },
4557 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4558 },
4559 .encode = .{
4560 .umov,
4561 .Wd,
4562 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4563 },
4564 },
4565 .{
4566 .pattern = "MOV <Xd>, <Vn>.D[<index>]",
4567 .symbols = .{
4568 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4569 .Vn = .{ .reg_alias = .vector },
4570 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
4571 },
4572 .encode = .{
4573 .umov,
4574 .Xd,
4575 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
4576 },
4577 },
4578 // C7.2.209 NEG (vector)
4579 .{
4580 .pattern = "NEG <Vd>, <Vn>",
4581 .symbols = .{
4582 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4583 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4584 },
4585 .encode = .{ .neg, .Vd, .Vn },
4586 },
4587 .{
4588 .pattern = "NEG <Vd>.<T>, <Vn>.<T>",
4589 .symbols = .{
4590 .Vd = .{ .reg_alias = .vector },
4591 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4592 .Vn = .{ .reg_alias = .vector },
4593 },
4594 .encode = .{
4595 .neg,
4596 .{ .alias = .Vd, .format = .{ .vector = .T } },
4597 .{ .alias = .Vn, .format = .{ .vector = .T } },
4598 },
4599 },
4600 // C7.2.210 NOT
4601 .{
4602 .pattern = "NOT <Vd>.<T>, <Vn>.<T>",
4603 .symbols = .{
4604 .Vd = .{ .reg_alias = .vector },
4605 .T = .{ .arrangement = .{ .elem_size = .byte } },
4606 .Vn = .{ .reg_alias = .vector },
4607 },
4608 .encode = .{
4609 .not,
4610 .{ .alias = .Vd, .format = .{ .vector = .T } },
4611 .{ .alias = .Vn, .format = .{ .vector = .T } },
4612 },
4613 },
4614 // C7.2.234 SCVTF (vector, integer)
4615 .{
4616 .requires = .{.fullfp16},
4617 .pattern = "SCVTF <Hd>, <Hn>",
4618 .symbols = .{
4619 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4620 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4621 },
4622 .encode = .{ .scvtf, .Hd, .Hn },
4623 },
4624 .{
4625 .pattern = "SCVTF <Sd>, <Sn>",
4626 .symbols = .{
4627 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4628 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4629 },
4630 .encode = .{ .scvtf, .Sd, .Sn },
4631 },
4632 .{
4633 .pattern = "SCVTF <Dd>, <Dn>",
4634 .symbols = .{
4635 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4636 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4637 },
4638 .encode = .{ .scvtf, .Dd, .Dn },
4639 },
4640 .{
4641 .requires = .{.fullfp16},
4642 .pattern = "SCVTF <Vd>.<T>, <Vn>.<T>",
4643 .symbols = .{
4644 .Vd = .{ .reg_alias = .vector },
4645 .T = .{ .arrangement = .{ .elem_size = .half } },
4646 .Vn = .{ .reg_alias = .vector },
4647 },
4648 .encode = .{
4649 .scvtf,
4650 .{ .alias = .Vd, .format = .{ .vector = .T } },
4651 .{ .alias = .Vn, .format = .{ .vector = .T } },
4652 },
4653 },
4654 .{
4655 .pattern = "SCVTF <Vd>.<T>, <Vn>.<T>",
4656 .symbols = .{
4657 .Vd = .{ .reg_alias = .vector },
4658 .T = .{ .arrangement = .{ .elem_size = .single } },
4659 .Vn = .{ .reg_alias = .vector },
4660 },
4661 .encode = .{
4662 .scvtf,
4663 .{ .alias = .Vd, .format = .{ .vector = .T } },
4664 .{ .alias = .Vn, .format = .{ .vector = .T } },
4665 },
4666 },
4667 .{
4668 .pattern = "SCVTF <Vd>.2D, <Vn>.2D",
4669 .symbols = .{
4670 .Vd = .{ .reg_alias = .vector },
4671 .Vn = .{ .reg_alias = .vector },
4672 },
4673 .encode = .{
4674 .scvtf,
4675 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
4676 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4677 },
4678 },
4679 // C7.2.236 SCVTF (scalar, integer)
4680 .{
4681 .requires = .{.fullfp16},
4682 .pattern = "SCVTF <Hd>, <Wn>",
4683 .symbols = .{
4684 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4685 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4686 },
4687 .encode = .{ .scvtf, .Hd, .Wn },
4688 },
4689 .{
4690 .pattern = "SCVTF <Sd>, <Wn>",
4691 .symbols = .{
4692 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4693 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4694 },
4695 .encode = .{ .scvtf, .Sd, .Wn },
4696 },
4697 .{
4698 .pattern = "SCVTF <Dd>, <Wn>",
4699 .symbols = .{
4700 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4701 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
4702 },
4703 .encode = .{ .scvtf, .Dd, .Wn },
4704 },
4705 .{
4706 .requires = .{.fullfp16},
4707 .pattern = "SCVTF <Hd>, <Xn>",
4708 .symbols = .{
4709 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4710 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4711 },
4712 .encode = .{ .scvtf, .Hd, .Xn },
4713 },
4714 .{
4715 .pattern = "SCVTF <Sd>, <Xn>",
4716 .symbols = .{
4717 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4718 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4719 },
4720 .encode = .{ .scvtf, .Sd, .Xn },
4721 },
4722 .{
4723 .pattern = "SCVTF <Dd>, <Xn>",
4724 .symbols = .{
4725 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4726 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4727 },
4728 .encode = .{ .scvtf, .Dd, .Xn },
4729 },
4730 // C7.2.279 SMOV
4731 .{
4732 .pattern = "SMOV <Wd>, <Vn>.B[<index>]",
4733 .symbols = .{
4734 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4735 .Vn = .{ .reg_alias = .vector },
4736 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4737 },
4738 .encode = .{
4739 .smov,
4740 .Wd,
4741 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4742 },
4743 },
4744 .{
4745 .pattern = "SMOV <Xd>, <Vn>.B[<index>]",
4746 .symbols = .{
4747 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4748 .Vn = .{ .reg_alias = .vector },
4749 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
4750 },
4751 .encode = .{
4752 .smov,
4753 .Xd,
4754 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
4755 },
4756 },
4757 .{
4758 .pattern = "SMOV <Wd>, <Vn>.H[<index>]",
4759 .symbols = .{
4760 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
4761 .Vn = .{ .reg_alias = .vector },
4762 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4763 },
4764 .encode = .{
4765 .smov,
4766 .Wd,
4767 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4768 },
4769 },
4770 .{
4771 .pattern = "SMOV <Xd>, <Vn>.H[<index>]",
4772 .symbols = .{
4773 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4774 .Vn = .{ .reg_alias = .vector },
4775 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
4776 },
4777 .encode = .{
4778 .smov,
4779 .Xd,
4780 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
4781 },
4782 },
4783 .{
4784 .pattern = "SMOV <Xd>, <Vn>.S[<index>]",
4785 .symbols = .{
4786 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
4787 .Vn = .{ .reg_alias = .vector },
4788 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
4789 },
4790 .encode = .{
4791 .smov,
4792 .Xd,
4793 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
4794 },
4795 },
4796 // C7.2.282 SQABS
4797 .{
4798 .pattern = "SQABS <Vd>, <Vn>",
4799 .symbols = .{
4800 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4801 .Vn = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4802 },
4803 .encode = .{ .sqabs, .Vd, .Vn },
4804 },
4805 .{
4806 .pattern = "SQABS <Vd>, <Vn>",
4807 .symbols = .{
4808 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4809 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4810 },
4811 .encode = .{ .sqabs, .Vd, .Vn },
4812 },
4813 .{
4814 .pattern = "SQABS <Vd>, <Vn>",
4815 .symbols = .{
4816 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4817 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4818 },
4819 .encode = .{ .sqabs, .Vd, .Vn },
4820 },
4821 .{
4822 .pattern = "SQABS <Vd>, <Vn>",
4823 .symbols = .{
4824 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4825 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4826 },
4827 .encode = .{ .sqabs, .Vd, .Vn },
4828 },
4829 .{
4830 .pattern = "SQABS <Vd>.<T>, <Vn>.<T>",
4831 .symbols = .{
4832 .Vd = .{ .reg_alias = .vector },
4833 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4834 .Vn = .{ .reg_alias = .vector },
4835 },
4836 .encode = .{
4837 .sqabs,
4838 .{ .alias = .Vd, .format = .{ .vector = .T } },
4839 .{ .alias = .Vn, .format = .{ .vector = .T } },
4840 },
4841 },
4842 // C7.2.308 SQXTN, SQXTN2
4843 .{
4844 .pattern = "SQXTN <Vd>, <Vn>",
4845 .symbols = .{
4846 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4847 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4848 },
4849 .encode = .{ .sqxtn, .Vd, .Vn },
4850 },
4851 .{
4852 .pattern = "SQXTN <Vd>, <Vn>",
4853 .symbols = .{
4854 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4855 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4856 },
4857 .encode = .{ .sqxtn, .Vd, .Vn },
4858 },
4859 .{
4860 .pattern = "SQXTN <Vd>, <Vn>",
4861 .symbols = .{
4862 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4863 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4864 },
4865 .encode = .{ .sqxtn, .Vd, .Vn },
4866 },
4867 .{
4868 .pattern = "SQXTN <Vd>.8B, <Vn>.8H",
4869 .symbols = .{
4870 .Vd = .{ .reg_alias = .vector },
4871 .Vn = .{ .reg_alias = .vector },
4872 },
4873 .encode = .{
4874 .sqxtn,
4875 .{ .alias = .Vd, .format = .{ .vector = .@"8b" } },
4876 .{ .alias = .Vn, .format = .{ .vector = .@"8h" } },
4877 },
4878 },
4879 .{
4880 .pattern = "SQXTN2 <Vd>.16B, <Vn>.8H",
4881 .symbols = .{
4882 .Vd = .{ .reg_alias = .vector },
4883 .Vn = .{ .reg_alias = .vector },
4884 },
4885 .encode = .{
4886 .sqxtn2,
4887 .{ .alias = .Vd, .format = .{ .vector = .@"16b" } },
4888 .{ .alias = .Vn, .format = .{ .vector = .@"8h" } },
4889 },
4890 },
4891 .{
4892 .pattern = "SQXTN <Vd>.4H, <Vn>.4S",
4893 .symbols = .{
4894 .Vd = .{ .reg_alias = .vector },
4895 .Vn = .{ .reg_alias = .vector },
4896 },
4897 .encode = .{
4898 .sqxtn,
4899 .{ .alias = .Vd, .format = .{ .vector = .@"4h" } },
4900 .{ .alias = .Vn, .format = .{ .vector = .@"4s" } },
4901 },
4902 },
4903 .{
4904 .pattern = "SQXTN2 <Vd>.8H, <Vn>.4S",
4905 .symbols = .{
4906 .Vd = .{ .reg_alias = .vector },
4907 .Vn = .{ .reg_alias = .vector },
4908 },
4909 .encode = .{
4910 .sqxtn2,
4911 .{ .alias = .Vd, .format = .{ .vector = .@"8h" } },
4912 .{ .alias = .Vn, .format = .{ .vector = .@"4s" } },
4913 },
4914 },
4915 .{
4916 .pattern = "SQXTN <Vd>.2S, <Vn>.2D",
4917 .symbols = .{
4918 .Vd = .{ .reg_alias = .vector },
4919 .Vn = .{ .reg_alias = .vector },
4920 },
4921 .encode = .{
4922 .sqxtn,
4923 .{ .alias = .Vd, .format = .{ .vector = .@"2s" } },
4924 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4925 },
4926 },
4927 .{
4928 .pattern = "SQXTN2 <Vd>.4S, <Vn>.2D",
4929 .symbols = .{
4930 .Vd = .{ .reg_alias = .vector },
4931 .Vn = .{ .reg_alias = .vector },
4932 },
4933 .encode = .{
4934 .sqxtn2,
4935 .{ .alias = .Vd, .format = .{ .vector = .@"4s" } },
4936 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
4937 },
4938 },
4939 // C7.2.337 SUQADD
4940 .{
4941 .pattern = "SUQADD <Vd>, <Vn>",
4942 .symbols = .{
4943 .Vd = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4944 .Vn = .{ .reg = .{ .format = .{ .scalar = .byte } } },
4945 },
4946 .encode = .{ .suqadd, .Vd, .Vn },
4947 },
4948 .{
4949 .pattern = "SUQADD <Vd>, <Vn>",
4950 .symbols = .{
4951 .Vd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4952 .Vn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4953 },
4954 .encode = .{ .suqadd, .Vd, .Vn },
4955 },
4956 .{
4957 .pattern = "SUQADD <Vd>, <Vn>",
4958 .symbols = .{
4959 .Vd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4960 .Vn = .{ .reg = .{ .format = .{ .scalar = .single } } },
4961 },
4962 .encode = .{ .suqadd, .Vd, .Vn },
4963 },
4964 .{
4965 .pattern = "SUQADD <Vd>, <Vn>",
4966 .symbols = .{
4967 .Vd = .{ .reg = .{ .format = .{ .scalar = .double } } },
4968 .Vn = .{ .reg = .{ .format = .{ .scalar = .double } } },
4969 },
4970 .encode = .{ .suqadd, .Vd, .Vn },
4971 },
4972 .{
4973 .pattern = "SUQADD <Vd>.<T>, <Vn>.<T>",
4974 .symbols = .{
4975 .Vd = .{ .reg_alias = .vector },
4976 .T = .{ .arrangement = .{ .min_valid_len = 2 } },
4977 .Vn = .{ .reg_alias = .vector },
4978 },
4979 .encode = .{
4980 .suqadd,
4981 .{ .alias = .Vd, .format = .{ .vector = .T } },
4982 .{ .alias = .Vn, .format = .{ .vector = .T } },
4983 },
4984 },
4985 // C7.2.353 UCVTF (vector, integer)
4986 .{
4987 .requires = .{.fullfp16},
4988 .pattern = "UCVTF <Hd>, <Hn>",
4989 .symbols = .{
4990 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
4991 .Hn = .{ .reg = .{ .format = .{ .scalar = .half } } },
4992 },
4993 .encode = .{ .ucvtf, .Hd, .Hn },
4994 },
4995 .{
4996 .pattern = "UCVTF <Sd>, <Sn>",
4997 .symbols = .{
4998 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
4999 .Sn = .{ .reg = .{ .format = .{ .scalar = .single } } },
5000 },
5001 .encode = .{ .ucvtf, .Sd, .Sn },
5002 },
5003 .{
5004 .pattern = "UCVTF <Dd>, <Dn>",
5005 .symbols = .{
5006 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5007 .Dn = .{ .reg = .{ .format = .{ .scalar = .double } } },
5008 },
5009 .encode = .{ .ucvtf, .Dd, .Dn },
5010 },
5011 .{
5012 .requires = .{.fullfp16},
5013 .pattern = "UCVTF <Vd>.<T>, <Vn>.<T>",
5014 .symbols = .{
5015 .Vd = .{ .reg_alias = .vector },
5016 .T = .{ .arrangement = .{ .elem_size = .half } },
5017 .Vn = .{ .reg_alias = .vector },
5018 },
5019 .encode = .{
5020 .ucvtf,
5021 .{ .alias = .Vd, .format = .{ .vector = .T } },
5022 .{ .alias = .Vn, .format = .{ .vector = .T } },
5023 },
5024 },
5025 .{
5026 .pattern = "UCVTF <Vd>.<T>, <Vn>.<T>",
5027 .symbols = .{
5028 .Vd = .{ .reg_alias = .vector },
5029 .T = .{ .arrangement = .{ .elem_size = .single } },
5030 .Vn = .{ .reg_alias = .vector },
5031 },
5032 .encode = .{
5033 .ucvtf,
5034 .{ .alias = .Vd, .format = .{ .vector = .T } },
5035 .{ .alias = .Vn, .format = .{ .vector = .T } },
5036 },
5037 },
5038 .{
5039 .pattern = "UCVTF <Vd>.2D, <Vn>.2D",
5040 .symbols = .{
5041 .Vd = .{ .reg_alias = .vector },
5042 .Vn = .{ .reg_alias = .vector },
5043 },
5044 .encode = .{
5045 .ucvtf,
5046 .{ .alias = .Vd, .format = .{ .vector = .@"2d" } },
5047 .{ .alias = .Vn, .format = .{ .vector = .@"2d" } },
5048 },
5049 },
5050 // C7.2.355 UCVTF (scalar, integer)
5051 .{
5052 .requires = .{.fullfp16},
5053 .pattern = "UCVTF <Hd>, <Wn>",
5054 .symbols = .{
5055 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
5056 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5057 },
5058 .encode = .{ .ucvtf, .Hd, .Wn },
5059 },
5060 .{
5061 .pattern = "UCVTF <Sd>, <Wn>",
5062 .symbols = .{
5063 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
5064 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5065 },
5066 .encode = .{ .ucvtf, .Sd, .Wn },
5067 },
5068 .{
5069 .pattern = "UCVTF <Dd>, <Wn>",
5070 .symbols = .{
5071 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5072 .Wn = .{ .reg = .{ .format = .{ .general = .word } } },
5073 },
5074 .encode = .{ .ucvtf, .Dd, .Wn },
5075 },
5076 .{
5077 .requires = .{.fullfp16},
5078 .pattern = "UCVTF <Hd>, <Xn>",
5079 .symbols = .{
5080 .Hd = .{ .reg = .{ .format = .{ .scalar = .half } } },
5081 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5082 },
5083 .encode = .{ .ucvtf, .Hd, .Xn },
5084 },
5085 .{
5086 .pattern = "UCVTF <Sd>, <Xn>",
5087 .symbols = .{
5088 .Sd = .{ .reg = .{ .format = .{ .scalar = .single } } },
5089 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5090 },
5091 .encode = .{ .ucvtf, .Sd, .Xn },
5092 },
5093 .{
5094 .pattern = "UCVTF <Dd>, <Xn>",
5095 .symbols = .{
5096 .Dd = .{ .reg = .{ .format = .{ .scalar = .double } } },
5097 .Xn = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5098 },
5099 .encode = .{ .ucvtf, .Dd, .Xn },
5100 },
5101 // C7.2.371 UMOV
5102 .{
5103 .pattern = "UMOV <Wd>, <Vn>.B[<index>]",
5104 .symbols = .{
5105 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5106 .Vn = .{ .reg_alias = .vector },
5107 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 4 } } },
5108 },
5109 .encode = .{
5110 .umov,
5111 .Wd,
5112 .{ .alias = .Vn, .format = .{ .element = .{ .size = .byte, .index = .index } } },
5113 },
5114 },
5115 .{
5116 .pattern = "UMOV <Wd>, <Vn>.H[<index>]",
5117 .symbols = .{
5118 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5119 .Vn = .{ .reg_alias = .vector },
5120 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 3 } } },
5121 },
5122 .encode = .{
5123 .umov,
5124 .Wd,
5125 .{ .alias = .Vn, .format = .{ .element = .{ .size = .half, .index = .index } } },
5126 },
5127 },
5128 .{
5129 .pattern = "UMOV <Wd>, <Vn>.S[<index>]",
5130 .symbols = .{
5131 .Wd = .{ .reg = .{ .format = .{ .general = .word } } },
5132 .Vn = .{ .reg_alias = .vector },
5133 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 2 } } },
5134 },
5135 .encode = .{
5136 .umov,
5137 .Wd,
5138 .{ .alias = .Vn, .format = .{ .element = .{ .size = .single, .index = .index } } },
5139 },
5140 },
5141 .{
5142 .pattern = "UMOV <Xd>, <Vn>.D[<index>]",
5143 .symbols = .{
5144 .Xd = .{ .reg = .{ .format = .{ .general = .doubleword } } },
5145 .Vn = .{ .reg_alias = .vector },
5146 .index = .{ .imm = .{ .type = .{ .signedness = .unsigned, .bits = 1 } } },
5147 },
5148 .encode = .{
5149 .umov,
5150 .Xd,
5151 .{ .alias = .Vn, .format = .{ .element = .{ .size = .double, .index = .index } } },
5152 },
5153 },
1543}5154}
src/link/MachO/Atom.zig+7-7
...@@ -829,21 +829,21 @@ fn resolveRelocInner(...@@ -829,21 +829,21 @@ fn resolveRelocInner(
829 const rd, const rn = switch (aarch64.encoding.Instruction.read(inst_code).decode()) {829 const rd, const rn = switch (aarch64.encoding.Instruction.read(inst_code).decode()) {
830 else => unreachable,830 else => unreachable,
831 .data_processing_immediate => |decoded| .{831 .data_processing_immediate => |decoded| .{
832 decoded.add_subtract_immediate.group.Rd.decodeInteger(.doubleword, .{ .sp = true }),832 decoded.add_subtract_immediate.group.Rd.decode(.{ .sp = true }),
833 decoded.add_subtract_immediate.group.Rn.decodeInteger(.doubleword, .{ .sp = true }),833 decoded.add_subtract_immediate.group.Rn.decode(.{ .sp = true }),
834 },834 },
835 .load_store => |decoded| .{835 .load_store => |decoded| .{
836 decoded.register_unsigned_immediate.integer.group.Rt.decodeInteger(.doubleword, .{}),836 decoded.register_unsigned_immediate.integer.group.Rt.decode(.{}),
837 decoded.register_unsigned_immediate.group.Rn.decodeInteger(.doubleword, .{ .sp = true }),837 decoded.register_unsigned_immediate.group.Rn.decode(.{ .sp = true }),
838 },838 },
839 };839 };
840840
841 try writer.writeInt(u32, @bitCast(@as(841 try writer.writeInt(u32, @bitCast(@as(
842 aarch64.encoding.Instruction,842 aarch64.encoding.Instruction,
843 if (sym.getSectionFlags().tlv_ptr) .ldr(rd, .{ .unsigned_offset = .{843 if (sym.getSectionFlags().tlv_ptr) .ldr(rd.x(), .{ .unsigned_offset = .{
844 .base = rn,844 .base = rn.x(),
845 .offset = try divExact(self, rel, @truncate(target), 8, macho_file) * 8,845 .offset = try divExact(self, rel, @truncate(target), 8, macho_file) * 8,
846 } }) else .add(rd, rn, .{ .immediate = @truncate(target) }),846 } }) else .add(rd.x(), rn.x(), .{ .immediate = @truncate(target) }),
847 )), .little);847 )), .little);
848 },848 },
849 }849 }