authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-08-06 22:34:20+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-08-12 16:08:28-07:00
logd6f997259487fc01b1aa6d24bdc7b960c4aaec46
tree8bc66b10c07bbc616f8a3016eac90a93b7b4a02a
parent6d23850108b5d3278f5b1cad395ff8da4fdfebeb

all: Handle spirv in addition to spirv(32,64) where applicable.

Some of this is arbitrary since spirv (as opposed to spirv32/spirv64) refers to the version with logical memory layout, i.e. no 'real' pointers. This change at least matches what clang does.

6 files changed, 19 insertions(+), 20 deletions(-)

lib/std/Target.zig+7-7
......@@ -1163,7 +1163,7 @@ pub const Cpu = struct {
11631163
11641164 pub inline fn isSpirV(arch: Arch) bool {
11651165 return switch (arch) {
1166 .spirv32, .spirv64 => true,
1166 .spirv, .spirv32, .spirv64 => true,
11671167 else => false,
11681168 };
11691169 }
......@@ -1348,8 +1348,8 @@ pub const Cpu = struct {
13481348
13491349 /// Returns whether this architecture supports the address space
13501350 pub fn supportsAddressSpace(arch: Arch, address_space: std.builtin.AddressSpace) bool {
1351 const is_nvptx = arch == .nvptx or arch == .nvptx64;
1352 const is_spirv = arch == .spirv32 or arch == .spirv64;
1351 const is_nvptx = arch.isNvptx();
1352 const is_spirv = arch.isSpirV();
13531353 const is_gpu = is_nvptx or is_spirv or arch == .amdgcn;
13541354 return switch (address_space) {
13551355 .generic => true,
......@@ -1378,7 +1378,7 @@ pub const Cpu = struct {
13781378 .x86, .x86_64 => "x86",
13791379 .nvptx, .nvptx64 => "nvptx",
13801380 .wasm32, .wasm64 => "wasm",
1381 .spirv32, .spirv64 => "spirv",
1381 .spirv, .spirv32, .spirv64 => "spirv",
13821382 else => @tagName(arch),
13831383 };
13841384 }
......@@ -1401,7 +1401,7 @@ pub const Cpu = struct {
14011401 .amdgcn => &amdgpu.all_features,
14021402 .riscv32, .riscv64 => &riscv.all_features,
14031403 .sparc, .sparc64 => &sparc.all_features,
1404 .spirv32, .spirv64 => &spirv.all_features,
1404 .spirv, .spirv32, .spirv64 => &spirv.all_features,
14051405 .s390x => &s390x.all_features,
14061406 .x86, .x86_64 => &x86.all_features,
14071407 .xtensa => &xtensa.all_features,
......@@ -1431,7 +1431,7 @@ pub const Cpu = struct {
14311431 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
14321432 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
14331433 .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
1434 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
1434 .spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
14351435 .s390x => comptime allCpusFromDecls(s390x.cpu),
14361436 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
14371437 .xtensa => comptime allCpusFromDecls(xtensa.cpu),
......@@ -1521,7 +1521,7 @@ pub const Cpu = struct {
15211521 .amdgcn => &amdgpu.cpu.generic,
15221522 .riscv32 => &riscv.cpu.generic_rv32,
15231523 .riscv64 => &riscv.cpu.generic_rv64,
1524 .spirv32, .spirv64 => &spirv.cpu.generic,
1524 .spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
15251525 .sparc => &sparc.cpu.generic,
15261526 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
15271527 .s390x => &s390x.cpu.generic,
src/Compilation.zig+2-2
......@@ -6266,7 +6266,7 @@ fn canBuildLibCompilerRt(target: std.Target, use_llvm: bool) bool {
62666266 else => {},
62676267 }
62686268 switch (target.cpu.arch) {
6269 .spirv32, .spirv64 => return false,
6269 .spirv, .spirv32, .spirv64 => return false,
62706270 else => {},
62716271 }
62726272 return switch (target_util.zigBackend(target, use_llvm)) {
......@@ -6284,7 +6284,7 @@ fn canBuildZigLibC(target: std.Target, use_llvm: bool) bool {
62846284 else => {},
62856285 }
62866286 switch (target.cpu.arch) {
6287 .spirv32, .spirv64 => return false,
6287 .spirv, .spirv32, .spirv64 => return false,
62886288 else => {},
62896289 }
62906290 return switch (target_util.zigBackend(target, use_llvm)) {
src/Sema.zig+5-5
......@@ -10038,11 +10038,11 @@ fn finishFunc(
1003810038 else => "x86_64",
1003910039 },
1004010040 .Kernel => switch (arch) {
10041 .nvptx, .nvptx64, .amdgcn, .spirv32, .spirv64 => null,
10041 .nvptx, .nvptx64, .amdgcn, .spirv, .spirv32, .spirv64 => null,
1004210042 else => "nvptx, amdgcn and SPIR-V",
1004310043 },
1004410044 .Fragment, .Vertex => switch (arch) {
10045 .spirv32, .spirv64 => null,
10045 .spirv, .spirv32, .spirv64 => null,
1004610046 else => "SPIR-V",
1004710047 },
1004810048 })) |allowed_platform| {
......@@ -26703,7 +26703,7 @@ fn zirWorkItem(
2670326703
2670426704 switch (target.cpu.arch) {
2670526705 // TODO: Allow for other GPU targets.
26706 .amdgcn, .spirv64, .spirv32 => {},
26706 .amdgcn, .spirv, .spirv64, .spirv32 => {},
2670726707 else => {
2670826708 return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)});
2670926709 },
......@@ -37323,9 +37323,9 @@ pub fn analyzeAsAddressSpace(
3732337323 const target = pt.zcu.getTarget();
3732437324 const arch = target.cpu.arch;
3732537325
37326 const is_nv = arch == .nvptx or arch == .nvptx64;
37326 const is_nv = arch.isNvptx();
3732737327 const is_amd = arch == .amdgcn;
37328 const is_spirv = arch == .spirv32 or arch == .spirv64;
37328 const is_spirv = arch.isSpirV();
3732937329 const is_gpu = is_nv or is_amd or is_spirv;
3733037330
3733137331 const supported = switch (address_space) {
src/Zcu.zig+1-2
......@@ -2910,6 +2910,7 @@ pub fn atomicPtrAlignment(
29102910 .s390x,
29112911 .wasm64,
29122912 .ve,
2913 .spirv,
29132914 .spirv64,
29142915 .loongarch64,
29152916 => 64,
......@@ -2919,8 +2920,6 @@ pub fn atomicPtrAlignment(
29192920 => 128,
29202921
29212922 .x86_64 => if (std.Target.x86.featureSetHas(target.cpu.features, .cx16)) 128 else 64,
2922
2923 .spirv => @panic("TODO what should this value be?"),
29242923 };
29252924
29262925 if (ty.toIntern() == .bool_type) return .none;
src/link/SpirV.zig+1-1
......@@ -80,7 +80,7 @@ pub fn createEmpty(
8080 errdefer self.deinit();
8181
8282 switch (target.cpu.arch) {
83 .spirv32, .spirv64 => {},
83 .spirv, .spirv32, .spirv64 => {},
8484 else => unreachable, // Caught by Compilation.Config.resolve.
8585 }
8686
src/target.zig+3-3
......@@ -196,7 +196,7 @@ pub fn supportsStackProtector(target: std.Target, backend: std.builtin.CompilerB
196196 else => {},
197197 }
198198 switch (target.cpu.arch) {
199 .spirv32, .spirv64 => return false,
199 .spirv, .spirv32, .spirv64 => return false,
200200 else => {},
201201 }
202202 return switch (backend) {
......@@ -207,7 +207,7 @@ pub fn supportsStackProtector(target: std.Target, backend: std.builtin.CompilerB
207207
208208pub fn clangSupportsStackProtector(target: std.Target) bool {
209209 return switch (target.cpu.arch) {
210 .spirv32, .spirv64 => return false,
210 .spirv, .spirv32, .spirv64 => return false,
211211 else => true,
212212 };
213213}
......@@ -220,7 +220,7 @@ pub fn supportsReturnAddress(target: std.Target) bool {
220220 return switch (target.cpu.arch) {
221221 .wasm32, .wasm64 => target.os.tag == .emscripten,
222222 .bpfel, .bpfeb => false,
223 .spirv32, .spirv64 => false,
223 .spirv, .spirv32, .spirv64 => false,
224224 else => true,
225225 };
226226}