authorgravatar for paul.verigo@gmail.comPavel Verigo <paul.verigo@gmail.com> 2026-04-19 17:30:35+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2026-04-19 21:49:51+02:00
logd840583458f03f5dcf75982e187e36796db8a9c8
treef64d8886b5b26bed461bc97df94121824b983863
parentdea6914aaa615c91c0e23ce3c4d4dfb2095de2b0

remove AIR .bool_or/.bool_and

14 files changed, 29 insertions(+), 85 deletions(-)

src/Air.zig-10
......@@ -538,12 +538,6 @@ pub const Inst = struct {
538538 /// Result type is always bool.
539539 /// Uses the `un_op` field.
540540 is_non_err_ptr,
541 /// Result type is always bool.
542 /// Uses the `bin_op` field.
543 bool_and,
544 /// Result type is always bool.
545 /// Uses the `bin_op` field.
546 bool_or,
547541 /// Read a value from a pointer.
548542 /// Uses the `ty_op` field.
549543 load,
......@@ -1580,8 +1574,6 @@ pub fn typeOfIndex(air: *const Air, inst: Air.Inst.Index, ip: *const InternPool)
15801574 .shl_sat,
15811575 .min,
15821576 .max,
1583 .bool_and,
1584 .bool_or,
15851577 .add_optimized,
15861578 .sub_optimized,
15871579 .mul_optimized,
......@@ -2010,8 +2002,6 @@ pub fn mustLower(air: Air, inst: Air.Inst.Index, ip: *const InternPool) bool {
20102002 .is_non_null,
20112003 .is_err,
20122004 .is_non_err,
2013 .bool_and,
2014 .bool_or,
20152005 .fptrunc,
20162006 .fpext,
20172007 .intcast,
src/Air/Legalize.zig+2-4
......@@ -713,8 +713,6 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void {
713713 .is_non_err,
714714 .is_err_ptr,
715715 .is_non_err_ptr,
716 .bool_and,
717 .bool_or,
718716 => {},
719717 .load => if (l.features.has(.expand_packed_load)) {
720718 const ty_op = l.air_instructions.items(.data)[@intFromEnum(inst)].ty_op;
......@@ -2018,7 +2016,7 @@ fn safeIntcastBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index) Error!Air.In
20182016 } else undefined;
20192017 const out_of_range_inst: Air.Inst.Index = inst: {
20202018 if (have_min_check and have_max_check) break :inst cur_block.add(l, .{
2021 .tag = .bool_or,
2019 .tag = .bit_or,
20222020 .data = .{ .bin_op = .{
20232021 .lhs = below_min_inst.toRef(),
20242022 .rhs = above_max_inst.toRef(),
......@@ -2156,7 +2154,7 @@ fn safeIntFromFloatBlockPayload(l: *Legalize, orig_inst: Air.Inst.Index, optimiz
21562154
21572155 // Combine the conditions.
21582156 const out_of_bounds_inst: Air.Inst.Index = main_block.add(l, .{
2159 .tag = .bool_or,
2157 .tag = .bit_or,
21602158 .data = .{ .bin_op = .{
21612159 .lhs = below_min_inst.toRef(),
21622160 .rhs = above_max_inst.toRef(),
src/Air/Liveness.zig-2
......@@ -436,8 +436,6 @@ fn analyzeInst(
436436 .cmp_gt_optimized,
437437 .cmp_neq,
438438 .cmp_neq_optimized,
439 .bool_and,
440 .bool_or,
441439 .store,
442440 .store_safe,
443441 .array_elem_val,
src/Air/Liveness/Verify.zig-2
......@@ -249,8 +249,6 @@ fn verifyBody(self: *Verify, body: []const Air.Inst.Index) Error!void {
249249 .cmp_gt_optimized,
250250 .cmp_neq,
251251 .cmp_neq_optimized,
252 .bool_and,
253 .bool_or,
254252 .store,
255253 .store_safe,
256254 .array_elem_val,
src/Air/print.zig-2
......@@ -148,8 +148,6 @@ const Writer = struct {
148148 .cmp_gte,
149149 .cmp_gt,
150150 .cmp_neq,
151 .bool_and,
152 .bool_or,
153151 .store,
154152 .store_safe,
155153 .array_elem_val,
src/Sema.zig+9-9
......@@ -4109,7 +4109,7 @@ fn zirForLen(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Air.
41094109 if (i == len_idx) continue;
41104110 const eq = try block.addBinOp(.cmp_eq, len, arg_len);
41114111 ok = if (ok != .none)
4112 try block.addBinOp(.bool_and, ok, eq)
4112 try block.addBinOp(.bit_and, ok, eq)
41134113 else
41144114 eq;
41154115 }
......@@ -7699,7 +7699,7 @@ fn zirErrorFromInt(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstD
76997699 const is_lte_len = try block.addUnOp(.cmp_lte_errors_len, operand);
77007700 const zero_val = Air.internedToRef((try pt.intValue(err_int_ty, 0)).toIntern());
77017701 const is_non_zero = try block.addBinOp(.cmp_neq, operand, zero_val);
7702 const ok = try block.addBinOp(.bool_and, is_lte_len, is_non_zero);
7702 const ok = try block.addBinOp(.bit_and, is_lte_len, is_non_zero);
77037703 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);
77047704 }
77057705 return block.addInst(.{
......@@ -14561,7 +14561,7 @@ fn addDivIntOverflowSafety(
1456114561 break :ok try block.addCmpVector(casted_rhs, neg_one_ref, .neq);
1456214562 };
1456314563
14564 const ok = try block.addReduce(try block.addBinOp(.bool_or, lhs_ok, rhs_ok), .And);
14564 const ok = try block.addReduce(try block.addBinOp(.bit_or, lhs_ok, rhs_ok), .And);
1456514565 try sema.addSafetyCheck(block, src, ok, .integer_overflow);
1456614566 } else {
1456714567 const lhs_ok: Air.Inst.Ref = if (maybe_lhs_val == null) ok: {
......@@ -14574,7 +14574,7 @@ fn addDivIntOverflowSafety(
1457414574 } else .none; // means false
1457514575
1457614576 const ok = if (lhs_ok != .none and rhs_ok != .none)
14577 try block.addBinOp(.bool_or, lhs_ok, rhs_ok)
14577 try block.addBinOp(.bit_or, lhs_ok, rhs_ok)
1457814578 else if (lhs_ok != .none)
1457914579 lhs_ok
1458014580 else if (rhs_ok != .none)
......@@ -21236,7 +21236,7 @@ fn zirErrorCast(sema: *Sema, block: *Block, extended: Zir.Inst.Extended.InstData
2123621236 } else {
2123721237 // Error must be in destination set or zero.
2123821238 const has_value = try block.addTyOp(.error_set_has_value, dest_err_ty, err_int_inst);
21239 const ok = try block.addBinOp(.bool_or, has_value, is_zero);
21239 const ok = try block.addBinOp(.bit_or, has_value, is_zero);
2124021240 try sema.addSafetyCheck(block, src, ok, .invalid_error_code);
2124121241 }
2124221242 } else {
......@@ -21794,7 +21794,7 @@ fn ptrCastFull(
2179421794 assert(operand_ptr_int != .none);
2179521795 const ptr_is_non_zero = try block.addBinOp(.cmp_neq, operand_ptr_int, .zero_usize);
2179621796 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {
21797 break :ok try block.addBinOp(.bool_or, operand_len_is_zero, ptr_is_non_zero);
21797 break :ok try block.addBinOp(.bit_or, operand_len_is_zero, ptr_is_non_zero);
2179821798 } else ptr_is_non_zero;
2179921799 try sema.addSafetyCheck(block, src, ok, .cast_to_null);
2180021800 }
......@@ -21807,7 +21807,7 @@ fn ptrCastFull(
2180721807 const ptr_masked = try block.addBinOp(.bit_and, operand_ptr_int, align_mask);
2180821808 const is_aligned = try block.addBinOp(.cmp_eq, ptr_masked, .zero_usize);
2180921809 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {
21810 break :ok try block.addBinOp(.bool_or, operand_len_is_zero, is_aligned);
21810 break :ok try block.addBinOp(.bit_or, operand_len_is_zero, is_aligned);
2181121811 } else is_aligned;
2181221812 try sema.addSafetyCheck(block, src, ok, .incorrect_alignment);
2181321813 }
......@@ -24317,7 +24317,7 @@ fn zirMemcpy(
2431724317 const dest_plus_len = try sema.analyzePtrArithmetic(block, src, raw_dest_ptr, len, .ptr_add, src);
2431824318 const ok1 = try block.addBinOp(.cmp_gte, raw_dest_ptr, src_plus_len);
2431924319 const ok2 = try block.addBinOp(.cmp_gte, new_src_ptr, dest_plus_len);
24320 const ok = try block.addBinOp(.bool_or, ok1, ok2);
24320 const ok = try block.addBinOp(.bit_or, ok1, ok2);
2432124321 try sema.addSafetyCheck(block, src, ok, .memcpy_alias);
2432224322 }
2432324323
......@@ -29524,7 +29524,7 @@ fn coerceCompatiblePtrs(
2952429524 const ok = if (inst_ty.isSlice(zcu)) ok: {
2952529525 const len = try sema.analyzeSliceLen(block, inst_src, inst);
2952629526 const len_zero = try block.addBinOp(.cmp_eq, len, .zero_usize);
29527 break :ok try block.addBinOp(.bool_or, len_zero, is_non_zero);
29527 break :ok try block.addBinOp(.bit_or, len_zero, is_non_zero);
2952829528 } else is_non_zero;
2952929529 try sema.addSafetyCheck(block, inst_src, ok, .cast_to_null);
2953029530 }
src/codegen/aarch64/Select.zig+3-5
......@@ -203,8 +203,6 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void {
203203 .cmp_gt_optimized,
204204 .cmp_neq,
205205 .cmp_neq_optimized,
206 .bool_and,
207 .bool_or,
208206 .array_elem_val,
209207 .slice_elem_val,
210208 .ptr_elem_val,
......@@ -2883,7 +2881,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
28832881
28842882 if (air.next()) |next_air_tag| continue :air_tag next_air_tag;
28852883 },
2886 .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| {
2884 .bit_and, .bit_or, .xor => |air_tag| {
28872885 if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| {
28882886 defer res_vi.value.deref(isel);
28892887
......@@ -2914,12 +2912,12 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
29142912 const rhs_part_mat = try rhs_part_vi.?.matReg(isel);
29152913 try isel.emit(switch (air_tag) {
29162914 else => unreachable,
2917 .bit_and, .bool_and => switch (size) {
2915 .bit_and => switch (size) {
29182916 else => unreachable,
29192917 1, 2, 4 => .@"and"(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),
29202918 8 => .@"and"(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),
29212919 },
2922 .bit_or, .bool_or => switch (size) {
2920 .bit_or => switch (size) {
29232921 else => unreachable,
29242922 1, 2, 4 => .orr(res_part_ra.w(), lhs_part_mat.ra.w(), .{ .register = rhs_part_mat.ra.w() }),
29252923 8 => .orr(res_part_ra.x(), lhs_part_mat.ra.x(), .{ .register = rhs_part_mat.ra.x() }),
src/codegen/c.zig+2-3
......@@ -2728,9 +2728,8 @@ fn genBodyInner(f: *Function, body: []const Air.Inst.Index) Error!void {
27282728 },
27292729 .cmp_lte_errors_len => try airCmpLteErrorsLen(f, inst),
27302730
2731 // bool_and and bool_or are non-short-circuit operations
2732 .bool_and, .bit_and => try airBinOp(f, inst, "&", "and", .none),
2733 .bool_or, .bit_or => try airBinOp(f, inst, "|", "or", .none),
2731 .bit_and => try airBinOp(f, inst, "&", "and", .none),
2732 .bit_or => try airBinOp(f, inst, "|", "or", .none),
27342733 .xor => try airBinOp(f, inst, "^", "xor", .none),
27352734 .shr, .shr_exact => try airBinBuiltinCall(f, inst, "shr", .none),
27362735 .shl, => try airBinBuiltinCall(f, inst, "shlw", .bits),
src/codegen/llvm/FuncGen.zig+5-5
......@@ -258,11 +258,11 @@ pub fn genBody(self: *FuncGen, body: []const Air.Inst.Index, coverage_point: Air
258258 .mul_with_overflow => try self.airOverflow(inst, .@"smul.with.overflow", .@"umul.with.overflow"),
259259 .shl_with_overflow => try self.airShlWithOverflow(inst),
260260
261 .bit_and, .bool_and => try self.airAnd(inst),
262 .bit_or, .bool_or => try self.airOr(inst),
263 .xor => try self.airXor(inst),
264 .shr => try self.airShr(inst, false),
265 .shr_exact => try self.airShr(inst, true),
261 .bit_and => try self.airAnd(inst),
262 .bit_or => try self.airOr(inst),
263 .xor => try self.airXor(inst),
264 .shr => try self.airShr(inst, false),
265 .shr_exact => try self.airShr(inst, true),
266266
267267 .sqrt => try self.airUnaryOp(inst, .sqrt),
268268 .sin => try self.airUnaryOp(inst, .sin),
src/codegen/riscv64/CodeGen.zig+2-13
......@@ -1415,8 +1415,6 @@ fn genBody(func: *Func, body: []const Air.Inst.Index) InnerError!void {
14151415 .shl, .shl_exact,
14161416 .shr, .shr_exact,
14171417
1418 .bool_and,
1419 .bool_or,
14201418 .bit_and,
14211419 .bit_or,
14221420
......@@ -2702,13 +2700,11 @@ fn genBinOp(
27022700
27032701 .bit_and,
27042702 .bit_or,
2705 .bool_and,
2706 .bool_or,
27072703 => {
27082704 _ = try func.addInst(.{
27092705 .tag = switch (tag) {
2710 .bit_and, .bool_and => .@"and",
2711 .bit_or, .bool_or => .@"or",
2706 .bit_and => .@"and",
2707 .bit_or => .@"or",
27122708 else => unreachable,
27132709 },
27142710 .data = .{
......@@ -2719,13 +2715,6 @@ fn genBinOp(
27192715 },
27202716 },
27212717 });
2722
2723 switch (tag) {
2724 .bool_and,
2725 .bool_or,
2726 => try func.truncateRegister(Type.bool, dst_reg),
2727 else => {},
2728 }
27292718 },
27302719
27312720 .shr,
src/codegen/sparc64/CodeGen.zig-22
......@@ -499,8 +499,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
499499 .shl_exact => try self.airBinOp(inst, .shl_exact),
500500 .shr => try self.airBinOp(inst, .shr),
501501 .shr_exact => try self.airBinOp(inst, .shr_exact),
502 .bool_and => try self.airBinOp(inst, .bool_and),
503 .bool_or => try self.airBinOp(inst, .bool_or),
504502 .bit_and => try self.airBinOp(inst, .bit_and),
505503 .bit_or => try self.airBinOp(inst, .bit_or),
506504 .xor => try self.airBinOp(inst, .xor),
......@@ -2941,26 +2939,6 @@ fn binOp(
29412939 }
29422940 },
29432941
2944 .bool_and,
2945 .bool_or,
2946 => {
2947 switch (lhs_ty.zigTypeTag(zcu)) {
2948 .bool => {
2949 assert(lhs != .immediate); // should have been handled by Sema
2950 assert(rhs != .immediate); // should have been handled by Sema
2951
2952 const mir_tag: Mir.Inst.Tag = switch (tag) {
2953 .bool_and => .@"and",
2954 .bool_or => .@"or",
2955 else => unreachable,
2956 };
2957
2958 return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
2959 },
2960 else => unreachable,
2961 }
2962 },
2963
29642942 .shl,
29652943 .shr,
29662944 => {
src/codegen/spirv/CodeGen.zig-2
......@@ -2693,8 +2693,6 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) Error!void {
26932693 .bit_and => try cg.airBinOpSimple(inst, .OpBitwiseAnd),
26942694 .bit_or => try cg.airBinOpSimple(inst, .OpBitwiseOr),
26952695 .xor => try cg.airBinOpSimple(inst, .OpBitwiseXor),
2696 .bool_and => try cg.airBinOpSimple(inst, .OpLogicalAnd),
2697 .bool_or => try cg.airBinOpSimple(inst, .OpLogicalOr),
26982696
26992697 .shl, .shl_exact => try cg.airShift(inst, .OpShiftLeftLogical, .OpShiftLeftLogical),
27002698 .shr, .shr_exact => try cg.airShift(inst, .OpShiftRightLogical, .OpShiftRightArithmetic),
src/codegen/wasm/CodeGen.zig+3-3
......@@ -1516,7 +1516,7 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
15161516 try cg.finishAir(inst, result, &.{ bin_op.lhs, bin_op.rhs });
15171517 },
15181518
1519 .bit_and, .bit_or, .bool_and, .bool_or, .xor, .shl_exact, .shr, .shr_exact => |tag| {
1519 .bit_and, .bit_or, .xor, .shl_exact, .shr, .shr_exact => |tag| {
15201520 const bin_op = cg.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
15211521 const lhs = try cg.resolveInst(bin_op.lhs);
15221522 const rhs = try cg.resolveInst(bin_op.rhs);
......@@ -1528,8 +1528,8 @@ fn genInst(cg: *CodeGen, inst: Air.Inst.Index) InnerError!void {
15281528
15291529 const int_ty: IntType = .fromType(cg, ty);
15301530 const result = switch (tag) {
1531 .bit_and, .bool_and => try cg.intAnd(int_ty, lhs, rhs),
1532 .bit_or, .bool_or => try cg.intOr(int_ty, lhs, rhs),
1531 .bit_and => try cg.intAnd(int_ty, lhs, rhs),
1532 .bit_or => try cg.intOr(int_ty, lhs, rhs),
15331533 .xor => try cg.intXor(int_ty, lhs, rhs),
15341534 .shl_exact => try cg.intShl(int_ty, lhs, rhs),
15351535 .shr, .shr_exact => try cg.intShr(int_ty, lhs, rhs),
src/codegen/x86_64/CodeGen.zig+3-3
......@@ -60839,14 +60839,14 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
6083960839 try slot.finish(inst, &.{}, &.{}, cg);
6084060840 },
6084160841 .assembly => try cg.airAsm(inst),
60842 .bit_and, .bit_or, .xor, .bool_and, .bool_or => |air_tag| {
60842 .bit_and, .bit_or, .xor => |air_tag| {
6084360843 const bin_op = air_datas[@intFromEnum(inst)].bin_op;
6084460844 var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs });
6084560845 var res: [1]Temp = undefined;
6084660846 cg.select(&res, &.{cg.typeOf(bin_op.lhs)}, &ops, switch (@as(Mir.Inst.Tag, switch (air_tag) {
6084760847 else => unreachable,
60848 .bit_and, .bool_and => .@"and",
60849 .bit_or, .bool_or => .@"or",
60848 .bit_and => .@"and",
60849 .bit_or => .@"or",
6085060850 .xor => .xor,
6085160851 })) {
6085260852 else => unreachable,