| ... | @@ -24,7 +24,7 @@ pub const Branch = struct { | ... | @@ -24,7 +24,7 @@ pub const Branch = struct { |
| 24 | log.debug(" | displacement 0x{x}", .{displacement}); | 24 | log.debug(" | displacement 0x{x}", .{displacement}); |
| 25 | | 25 | |
| 26 | var inst = branch.inst; | 26 | var inst = branch.inst; |
| 27 | inst.UnconditionalBranchImmediate.imm26 = @truncate(u26, @bitCast(u28, displacement) >> 2); | 27 | inst.unconditional_branch_immediate.imm26 = @truncate(u26, @bitCast(u28, displacement) >> 2); |
| 28 | mem.writeIntLittle(u32, branch.base.code[0..4], inst.toU32()); | 28 | mem.writeIntLittle(u32, branch.base.code[0..4], inst.toU32()); |
| 29 | } | 29 | } |
| 30 | }; | 30 | }; |
| ... | @@ -47,8 +47,8 @@ pub const Page = struct { | ... | @@ -47,8 +47,8 @@ pub const Page = struct { |
| 47 | log.debug(" | moving by {} pages", .{pages}); | 47 | log.debug(" | moving by {} pages", .{pages}); |
| 48 | | 48 | |
| 49 | var inst = page.inst; | 49 | var inst = page.inst; |
| 50 | inst.PCRelativeAddress.immhi = @truncate(u19, pages >> 2); | 50 | inst.pc_relative_address.immhi = @truncate(u19, pages >> 2); |
| 51 | inst.PCRelativeAddress.immlo = @truncate(u2, pages); | 51 | inst.pc_relative_address.immlo = @truncate(u2, pages); |
| 52 | | 52 | |
| 53 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); | 53 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); |
| 54 | } | 54 | } |
| ... | @@ -76,22 +76,22 @@ pub const PageOff = struct { | ... | @@ -76,22 +76,22 @@ pub const PageOff = struct { |
| 76 | | 76 | |
| 77 | var inst = page_off.inst; | 77 | var inst = page_off.inst; |
| 78 | if (page_off.op_kind == .arithmetic) { | 78 | if (page_off.op_kind == .arithmetic) { |
| 79 | inst.AddSubtractImmediate.imm12 = narrowed; | 79 | inst.add_subtract_immediate.imm12 = narrowed; |
| 80 | } else { | 80 | } else { |
| 81 | const offset: u12 = blk: { | 81 | const offset: u12 = blk: { |
| 82 | if (inst.LoadStoreRegister.size == 0) { | 82 | if (inst.load_store_register.size == 0) { |
| 83 | if (inst.LoadStoreRegister.v == 1) { | 83 | if (inst.load_store_register.v == 1) { |
| 84 | // 128-bit SIMD is scaled by 16. | 84 | // 128-bit SIMD is scaled by 16. |
| 85 | break :blk try math.divExact(u12, narrowed, 16); | 85 | break :blk try math.divExact(u12, narrowed, 16); |
| 86 | } | 86 | } |
| 87 | // Otherwise, 8-bit SIMD or ldrb. | 87 | // Otherwise, 8-bit SIMD or ldrb. |
| 88 | break :blk narrowed; | 88 | break :blk narrowed; |
| 89 | } else { | 89 | } else { |
| 90 | const denom: u4 = try math.powi(u4, 2, inst.LoadStoreRegister.size); | 90 | const denom: u4 = try math.powi(u4, 2, inst.load_store_register.size); |
| 91 | break :blk try math.divExact(u12, narrowed, denom); | 91 | break :blk try math.divExact(u12, narrowed, denom); |
| 92 | } | 92 | } |
| 93 | }; | 93 | }; |
| 94 | inst.LoadStoreRegister.offset = offset; | 94 | inst.load_store_register.offset = offset; |
| 95 | } | 95 | } |
| 96 | | 96 | |
| 97 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); | 97 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); |
| ... | @@ -113,8 +113,8 @@ pub const GotPage = struct { | ... | @@ -113,8 +113,8 @@ pub const GotPage = struct { |
| 113 | log.debug(" | moving by {} pages", .{pages}); | 113 | log.debug(" | moving by {} pages", .{pages}); |
| 114 | | 114 | |
| 115 | var inst = page.inst; | 115 | var inst = page.inst; |
| 116 | inst.PCRelativeAddress.immhi = @truncate(u19, pages >> 2); | 116 | inst.pc_relative_address.immhi = @truncate(u19, pages >> 2); |
| 117 | inst.PCRelativeAddress.immlo = @truncate(u2, pages); | 117 | inst.pc_relative_address.immlo = @truncate(u2, pages); |
| 118 | | 118 | |
| 119 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); | 119 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); |
| 120 | } | 120 | } |
| ... | @@ -134,7 +134,7 @@ pub const GotPageOff = struct { | ... | @@ -134,7 +134,7 @@ pub const GotPageOff = struct { |
| 134 | | 134 | |
| 135 | var inst = page_off.inst; | 135 | var inst = page_off.inst; |
| 136 | const offset = try math.divExact(u12, narrowed, 8); | 136 | const offset = try math.divExact(u12, narrowed, 8); |
| 137 | inst.LoadStoreRegister.offset = offset; | 137 | inst.load_store_register.offset = offset; |
| 138 | | 138 | |
| 139 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); | 139 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); |
| 140 | } | 140 | } |
| ... | @@ -155,8 +155,8 @@ pub const TlvpPage = struct { | ... | @@ -155,8 +155,8 @@ pub const TlvpPage = struct { |
| 155 | log.debug(" | moving by {} pages", .{pages}); | 155 | log.debug(" | moving by {} pages", .{pages}); |
| 156 | | 156 | |
| 157 | var inst = page.inst; | 157 | var inst = page.inst; |
| 158 | inst.PCRelativeAddress.immhi = @truncate(u19, pages >> 2); | 158 | inst.pc_relative_address.immhi = @truncate(u19, pages >> 2); |
| 159 | inst.PCRelativeAddress.immlo = @truncate(u2, pages); | 159 | inst.pc_relative_address.immlo = @truncate(u2, pages); |
| 160 | | 160 | |
| 161 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); | 161 | mem.writeIntLittle(u32, page.base.code[0..4], inst.toU32()); |
| 162 | } | 162 | } |
| ... | @@ -177,7 +177,7 @@ pub const TlvpPageOff = struct { | ... | @@ -177,7 +177,7 @@ pub const TlvpPageOff = struct { |
| 177 | log.debug(" | narrowed address within the page 0x{x}", .{narrowed}); | 177 | log.debug(" | narrowed address within the page 0x{x}", .{narrowed}); |
| 178 | | 178 | |
| 179 | var inst = page_off.inst; | 179 | var inst = page_off.inst; |
| 180 | inst.AddSubtractImmediate.imm12 = narrowed; | 180 | inst.add_subtract_immediate.imm12 = narrowed; |
| 181 | | 181 | |
| 182 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); | 182 | mem.writeIntLittle(u32, page_off.base.code[0..4], inst.toU32()); |
| 183 | } | 183 | } |
| ... | @@ -260,10 +260,10 @@ pub const Parser = struct { | ... | @@ -260,10 +260,10 @@ pub const Parser = struct { |
| 260 | | 260 | |
| 261 | const offset = @intCast(u32, rel.r_address); | 261 | const offset = @intCast(u32, rel.r_address); |
| 262 | const inst = parser.code[offset..][0..4]; | 262 | const inst = parser.code[offset..][0..4]; |
| 263 | const parsed_inst = aarch64.Instruction{ .UnconditionalBranchImmediate = mem.bytesToValue( | 263 | const parsed_inst = aarch64.Instruction{ .unconditional_branch_immediate = mem.bytesToValue( |
| 264 | meta.TagPayload( | 264 | meta.TagPayload( |
| 265 | aarch64.Instruction, | 265 | aarch64.Instruction, |
| 266 | aarch64.Instruction.UnconditionalBranchImmediate, | 266 | aarch64.Instruction.unconditional_branch_immediate, |
| 267 | ), | 267 | ), |
| 268 | inst, | 268 | inst, |
| 269 | ) }; | 269 | ) }; |
| ... | @@ -296,9 +296,9 @@ pub const Parser = struct { | ... | @@ -296,9 +296,9 @@ pub const Parser = struct { |
| 296 | | 296 | |
| 297 | const offset = @intCast(u32, rel.r_address); | 297 | const offset = @intCast(u32, rel.r_address); |
| 298 | const inst = parser.code[offset..][0..4]; | 298 | const inst = parser.code[offset..][0..4]; |
| 299 | const parsed_inst = aarch64.Instruction{ .PCRelativeAddress = mem.bytesToValue(meta.TagPayload( | 299 | const parsed_inst = aarch64.Instruction{ .pc_relative_address = mem.bytesToValue(meta.TagPayload( |
| 300 | aarch64.Instruction, | 300 | aarch64.Instruction, |
| 301 | aarch64.Instruction.PCRelativeAddress, | 301 | aarch64.Instruction.pc_relative_address, |
| 302 | ), inst) }; | 302 | ), inst) }; |
| 303 | | 303 | |
| 304 | const ptr: *Relocation = ptr: { | 304 | const ptr: *Relocation = ptr: { |
| ... | @@ -387,15 +387,15 @@ pub const Parser = struct { | ... | @@ -387,15 +387,15 @@ pub const Parser = struct { |
| 387 | var parsed_inst: aarch64.Instruction = undefined; | 387 | var parsed_inst: aarch64.Instruction = undefined; |
| 388 | if (isArithmeticOp(inst)) { | 388 | if (isArithmeticOp(inst)) { |
| 389 | op_kind = .arithmetic; | 389 | op_kind = .arithmetic; |
| 390 | parsed_inst = .{ .AddSubtractImmediate = mem.bytesToValue(meta.TagPayload( | 390 | parsed_inst = .{ .add_subtract_immediate = mem.bytesToValue(meta.TagPayload( |
| 391 | aarch64.Instruction, | 391 | aarch64.Instruction, |
| 392 | aarch64.Instruction.AddSubtractImmediate, | 392 | aarch64.Instruction.add_subtract_immediate, |
| 393 | ), inst) }; | 393 | ), inst) }; |
| 394 | } else { | 394 | } else { |
| 395 | op_kind = .load_store; | 395 | op_kind = .load_store; |
| 396 | parsed_inst = .{ .LoadStoreRegister = mem.bytesToValue(meta.TagPayload( | 396 | parsed_inst = .{ .load_store_register = mem.bytesToValue(meta.TagPayload( |
| 397 | aarch64.Instruction, | 397 | aarch64.Instruction, |
| 398 | aarch64.Instruction.LoadStoreRegister, | 398 | aarch64.Instruction.load_store_register, |
| 399 | ), inst) }; | 399 | ), inst) }; |
| 400 | } | 400 | } |
| 401 | const target = Relocation.Target.from_reloc(rel); | 401 | const target = Relocation.Target.from_reloc(rel); |
| ... | @@ -431,7 +431,7 @@ pub const Parser = struct { | ... | @@ -431,7 +431,7 @@ pub const Parser = struct { |
| 431 | | 431 | |
| 432 | const parsed_inst = mem.bytesToValue(meta.TagPayload( | 432 | const parsed_inst = mem.bytesToValue(meta.TagPayload( |
| 433 | aarch64.Instruction, | 433 | aarch64.Instruction, |
| 434 | aarch64.Instruction.LoadStoreRegister, | 434 | aarch64.Instruction.load_store_register, |
| 435 | ), inst); | 435 | ), inst); |
| 436 | assert(parsed_inst.size == 3); | 436 | assert(parsed_inst.size == 3); |
| 437 | | 437 | |
| ... | @@ -448,7 +448,7 @@ pub const Parser = struct { | ... | @@ -448,7 +448,7 @@ pub const Parser = struct { |
| 448 | .target = target, | 448 | .target = target, |
| 449 | }, | 449 | }, |
| 450 | .inst = .{ | 450 | .inst = .{ |
| 451 | .LoadStoreRegister = parsed_inst, | 451 | .load_store_register = parsed_inst, |
| 452 | }, | 452 | }, |
| 453 | }; | 453 | }; |
| 454 | | 454 | |
| ... | @@ -474,7 +474,7 @@ pub const Parser = struct { | ... | @@ -474,7 +474,7 @@ pub const Parser = struct { |
| 474 | if (isArithmeticOp(inst)) { | 474 | if (isArithmeticOp(inst)) { |
| 475 | const parsed_inst = mem.bytesAsValue(meta.TagPayload( | 475 | const parsed_inst = mem.bytesAsValue(meta.TagPayload( |
| 476 | aarch64.Instruction, | 476 | aarch64.Instruction, |
| 477 | aarch64.Instruction.AddSubtractImmediate, | 477 | aarch64.Instruction.add_subtract_immediate, |
| 478 | ), inst); | 478 | ), inst); |
| 479 | break :parsed .{ | 479 | break :parsed .{ |
| 480 | .rd = parsed_inst.rd, | 480 | .rd = parsed_inst.rd, |
| ... | @@ -484,7 +484,7 @@ pub const Parser = struct { | ... | @@ -484,7 +484,7 @@ pub const Parser = struct { |
| 484 | } else { | 484 | } else { |
| 485 | const parsed_inst = mem.bytesAsValue(meta.TagPayload( | 485 | const parsed_inst = mem.bytesAsValue(meta.TagPayload( |
| 486 | aarch64.Instruction, | 486 | aarch64.Instruction, |
| 487 | aarch64.Instruction.LoadStoreRegister, | 487 | aarch64.Instruction.load_store_register, |
| 488 | ), inst); | 488 | ), inst); |
| 489 | break :parsed .{ | 489 | break :parsed .{ |
| 490 | .rd = parsed_inst.rt, | 490 | .rd = parsed_inst.rt, |
| ... | @@ -507,7 +507,7 @@ pub const Parser = struct { | ... | @@ -507,7 +507,7 @@ pub const Parser = struct { |
| 507 | .target = target, | 507 | .target = target, |
| 508 | }, | 508 | }, |
| 509 | .inst = .{ | 509 | .inst = .{ |
| 510 | .AddSubtractImmediate = .{ | 510 | .add_subtract_immediate = .{ |
| 511 | .rd = parsed.rd, | 511 | .rd = parsed.rd, |
| 512 | .rn = parsed.rn, | 512 | .rn = parsed.rn, |
| 513 | .imm12 = 0, // This will be filled when target addresses are known. | 513 | .imm12 = 0, // This will be filled when target addresses are known. |