| ... | @@ -163,61 +163,113 @@ const ArmCpuinfoImpl = struct { | ... | @@ -163,61 +163,113 @@ const ArmCpuinfoImpl = struct { |
| 163 | const A32 = Target.arm.cpu; | 163 | const A32 = Target.arm.cpu; |
| 164 | const A64 = Target.aarch64.cpu; | 164 | const A64 = Target.aarch64.cpu; |
| 165 | | 165 | |
| | 166 | const E = struct { |
| | 167 | part: u16, |
| | 168 | variant: ?u8 = null, // null if matches any variant |
| | 169 | m32: ?*const Target.Cpu.Model = null, |
| | 170 | m64: ?*const Target.Cpu.Model = null, |
| | 171 | }; |
| | 172 | |
| 166 | // implementer = 0x41 | 173 | // implementer = 0x41 |
| 167 | const ARM = .{ | 174 | const ARM = [_]E{ |
| 168 | .{ 0x926, &A32.arm926ej_s, null }, | 175 | E{ .part = 0x926, .m32 = &A32.arm926ej_s, .m64 = null }, |
| 169 | .{ 0xb02, &A32.mpcore, null }, | 176 | E{ .part = 0xb02, .m32 = &A32.mpcore, .m64 = null }, |
| 170 | .{ 0xb36, &A32.arm1136j_s, null }, | 177 | E{ .part = 0xb36, .m32 = &A32.arm1136j_s, .m64 = null }, |
| 171 | .{ 0xb56, &A32.arm1156t2_s, null }, | 178 | E{ .part = 0xb56, .m32 = &A32.arm1156t2_s, .m64 = null }, |
| 172 | .{ 0xb76, &A32.arm1176jz_s, null }, | 179 | E{ .part = 0xb76, .m32 = &A32.arm1176jz_s, .m64 = null }, |
| 173 | .{ 0xc05, &A32.cortex_a5, null }, | 180 | E{ .part = 0xc05, .m32 = &A32.cortex_a5, .m64 = null }, |
| 174 | .{ 0xc07, &A32.cortex_a7, null }, | 181 | E{ .part = 0xc07, .m32 = &A32.cortex_a7, .m64 = null }, |
| 175 | .{ 0xc08, &A32.cortex_a8, null }, | 182 | E{ .part = 0xc08, .m32 = &A32.cortex_a8, .m64 = null }, |
| 176 | .{ 0xc09, &A32.cortex_a9, null }, | 183 | E{ .part = 0xc09, .m32 = &A32.cortex_a9, .m64 = null }, |
| 177 | .{ 0xc0d, &A32.cortex_a17, null }, | 184 | E{ .part = 0xc0d, .m32 = &A32.cortex_a17, .m64 = null }, |
| 178 | .{ 0xc0f, &A32.cortex_a15, null }, | 185 | E{ .part = 0xc0f, .m32 = &A32.cortex_a15, .m64 = null }, |
| 179 | .{ 0xc0e, &A32.cortex_a17, null }, | 186 | E{ .part = 0xc0e, .m32 = &A32.cortex_a17, .m64 = null }, |
| 180 | .{ 0xc14, &A32.cortex_r4, null }, | 187 | E{ .part = 0xc14, .m32 = &A32.cortex_r4, .m64 = null }, |
| 181 | .{ 0xc15, &A32.cortex_r5, null }, | 188 | E{ .part = 0xc15, .m32 = &A32.cortex_r5, .m64 = null }, |
| 182 | .{ 0xc17, &A32.cortex_r7, null }, | 189 | E{ .part = 0xc17, .m32 = &A32.cortex_r7, .m64 = null }, |
| 183 | .{ 0xc18, &A32.cortex_r8, null }, | 190 | E{ .part = 0xc18, .m32 = &A32.cortex_r8, .m64 = null }, |
| 184 | .{ 0xc20, &A32.cortex_m0, null }, | 191 | E{ .part = 0xc20, .m32 = &A32.cortex_m0, .m64 = null }, |
| 185 | .{ 0xc21, &A32.cortex_m1, null }, | 192 | E{ .part = 0xc21, .m32 = &A32.cortex_m1, .m64 = null }, |
| 186 | .{ 0xc23, &A32.cortex_m3, null }, | 193 | E{ .part = 0xc23, .m32 = &A32.cortex_m3, .m64 = null }, |
| 187 | .{ 0xc24, &A32.cortex_m4, null }, | 194 | E{ .part = 0xc24, .m32 = &A32.cortex_m4, .m64 = null }, |
| 188 | .{ 0xc27, &A32.cortex_m7, null }, | 195 | E{ .part = 0xc27, .m32 = &A32.cortex_m7, .m64 = null }, |
| 189 | .{ 0xc60, &A32.cortex_m0plus, null }, | 196 | E{ .part = 0xc60, .m32 = &A32.cortex_m0plus, .m64 = null }, |
| 190 | .{ 0xd01, &A32.cortex_a32, null }, | 197 | E{ .part = 0xd01, .m32 = &A32.cortex_a32, .m64 = null }, |
| 191 | .{ 0xd03, &A32.cortex_a53, &A64.cortex_a53 }, | 198 | E{ .part = 0xd03, .m32 = &A32.cortex_a53, .m64 = &A64.cortex_a53 }, |
| 192 | .{ 0xd04, &A32.cortex_a35, &A64.cortex_a35 }, | 199 | E{ .part = 0xd04, .m32 = &A32.cortex_a35, .m64 = &A64.cortex_a35 }, |
| 193 | .{ 0xd05, &A32.cortex_a55, &A64.cortex_a55 }, | 200 | E{ .part = 0xd05, .m32 = &A32.cortex_a55, .m64 = &A64.cortex_a55 }, |
| 194 | .{ 0xd07, &A32.cortex_a57, &A64.cortex_a57 }, | 201 | E{ .part = 0xd07, .m32 = &A32.cortex_a57, .m64 = &A64.cortex_a57 }, |
| 195 | .{ 0xd08, &A32.cortex_a72, &A64.cortex_a72 }, | 202 | E{ .part = 0xd08, .m32 = &A32.cortex_a72, .m64 = &A64.cortex_a72 }, |
| 196 | .{ 0xd09, &A32.cortex_a73, &A64.cortex_a73 }, | 203 | E{ .part = 0xd09, .m32 = &A32.cortex_a73, .m64 = &A64.cortex_a73 }, |
| 197 | .{ 0xd0a, &A32.cortex_a75, &A64.cortex_a75 }, | 204 | E{ .part = 0xd0a, .m32 = &A32.cortex_a75, .m64 = &A64.cortex_a75 }, |
| 198 | .{ 0xd0b, &A32.cortex_a76, &A64.cortex_a76 }, | 205 | E{ .part = 0xd0b, .m32 = &A32.cortex_a76, .m64 = &A64.cortex_a76 }, |
| 199 | .{ 0xd0c, &A32.neoverse_n1, null }, | 206 | E{ .part = 0xd0c, .m32 = &A32.neoverse_n1, .m64 = null }, |
| 200 | .{ 0xd0d, &A32.cortex_a77, &A64.cortex_a77 }, | 207 | E{ .part = 0xd0d, .m32 = &A32.cortex_a77, .m64 = &A64.cortex_a77 }, |
| 201 | .{ 0xd13, &A32.cortex_r52, null }, | 208 | E{ .part = 0xd13, .m32 = &A32.cortex_r52, .m64 = null }, |
| 202 | .{ 0xd20, &A32.cortex_m23, null }, | 209 | E{ .part = 0xd20, .m32 = &A32.cortex_m23, .m64 = null }, |
| 203 | .{ 0xd21, &A32.cortex_m33, null }, | 210 | E{ .part = 0xd21, .m32 = &A32.cortex_m33, .m64 = null }, |
| 204 | .{ 0xd41, &A32.cortex_a78, &A64.cortex_a78 }, | 211 | E{ .part = 0xd41, .m32 = &A32.cortex_a78, .m64 = &A64.cortex_a78 }, |
| 205 | .{ 0xd4b, &A32.cortex_a78c, &A64.cortex_a78c }, | 212 | E{ .part = 0xd4b, .m32 = &A32.cortex_a78c, .m64 = &A64.cortex_a78c }, |
| 206 | .{ 0xd44, &A32.cortex_x1, &A64.cortex_x1 }, | 213 | E{ .part = 0xd44, .m32 = &A32.cortex_x1, .m64 = &A64.cortex_x1 }, |
| 207 | .{ 0xd02, null, &A64.cortex_a34 }, | 214 | E{ .part = 0xd02, .m64 = &A64.cortex_a34 }, |
| 208 | .{ 0xd06, null, &A64.cortex_a65 }, | 215 | E{ .part = 0xd06, .m64 = &A64.cortex_a65 }, |
| 209 | .{ 0xd43, null, &A64.cortex_a65ae }, | 216 | E{ .part = 0xd43, .m64 = &A64.cortex_a65ae }, |
| | 217 | }; |
| | 218 | // implementer = 0x42 |
| | 219 | const Broadcom = [_]E{ |
| | 220 | E{ .part = 0x516, .m64 = &A64.thunderx2t99 }, |
| | 221 | }; |
| | 222 | // implementer = 0x43 |
| | 223 | const Cavium = [_]E{ |
| | 224 | E{ .part = 0x0a0, .m64 = &A64.thunderx }, |
| | 225 | E{ .part = 0x0a2, .m64 = &A64.thunderxt81 }, |
| | 226 | E{ .part = 0x0a3, .m64 = &A64.thunderxt83 }, |
| | 227 | E{ .part = 0x0a1, .m64 = &A64.thunderxt88 }, |
| | 228 | E{ .part = 0x0af, .m64 = &A64.thunderx2t99 }, |
| | 229 | }; |
| | 230 | // implementer = 0x46 |
| | 231 | const Fujitsu = [_]E{ |
| | 232 | E{ .part = 0x001, .m64 = &A64.a64fx }, |
| | 233 | }; |
| | 234 | // implementer = 0x48 |
| | 235 | const HiSilicon = [_]E{ |
| | 236 | E{ .part = 0xd01, .m64 = &A64.tsv110 }, |
| | 237 | }; |
| | 238 | // implementer = 0x4e |
| | 239 | const Nvidia = [_]E{ |
| | 240 | E{ .part = 0x004, .m64 = &A64.carmel }, |
| | 241 | }; |
| | 242 | // implementer = 0x51 |
| | 243 | const Qualcomm = [_]E{ |
| | 244 | E{ .part = 0x06f, .m32 = &A32.krait }, |
| | 245 | E{ .part = 0x201, .m64 = &A64.kryo, .m32 = &A64.kryo }, |
| | 246 | E{ .part = 0x205, .m64 = &A64.kryo, .m32 = &A64.kryo }, |
| | 247 | E{ .part = 0x211, .m64 = &A64.kryo, .m32 = &A64.kryo }, |
| | 248 | E{ .part = 0x800, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 }, |
| | 249 | E{ .part = 0x801, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 }, |
| | 250 | E{ .part = 0x802, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 }, |
| | 251 | E{ .part = 0x803, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 }, |
| | 252 | E{ .part = 0x804, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 }, |
| | 253 | E{ .part = 0x805, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 }, |
| | 254 | E{ .part = 0xc00, .m64 = &A64.falkor }, |
| | 255 | E{ .part = 0xc01, .m64 = &A64.saphira }, |
| 210 | }; | 256 | }; |
| 211 | | 257 | |
| 212 | fn isKnown(implementer: u8, part: u16, is_64bit: bool) ?*const Target.Cpu.Model { | 258 | fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model { |
| 213 | const models = switch (implementer) { | 259 | const models = switch (core.implementer) { |
| 214 | 0x41 => ARM, | 260 | 0x41 => &ARM, |
| | 261 | 0x42 => &Broadcom, |
| | 262 | 0x43 => &Cavium, |
| | 263 | 0x46 => &Fujitsu, |
| | 264 | 0x48 => &HiSilicon, |
| | 265 | 0x51 => &Qualcomm, |
| 215 | else => return null, | 266 | else => return null, |
| 216 | }; | 267 | }; |
| 217 | | 268 | |
| 218 | inline for (models) |model| { | 269 | for (models) |model| { |
| 219 | if (model[0] == part) | 270 | if (model.part == core.part and |
| 220 | return if (is_64bit) model[2] else model[1]; | 271 | (model.variant == null or model.variant.? == core.variant)) |
| | 272 | return if (is_64bit) model.m64 else model.m32; |
| 221 | } | 273 | } |
| 222 | | 274 | |
| 223 | return null; | 275 | return null; |
| ... | @@ -287,8 +339,7 @@ const ArmCpuinfoImpl = struct { | ... | @@ -287,8 +339,7 @@ const ArmCpuinfoImpl = struct { |
| 287 | | 339 | |
| 288 | var known_models: [self.cores.len]?*const Target.Cpu.Model = undefined; | 340 | var known_models: [self.cores.len]?*const Target.Cpu.Model = undefined; |
| 289 | for (self.cores[0..self.core_no]) |core, i| { | 341 | for (self.cores[0..self.core_no]) |core, i| { |
| 290 | known_models[i] = | 342 | known_models[i] = cpu_models.isKnown(core, is_64bit); |
| 291 | cpu_models.isKnown(core.implementer, core.part, is_64bit); | | |
| 292 | } | 343 | } |
| 293 | | 344 | |
| 294 | // XXX We pick the first core on big.LITTLE systems, hopefully the | 345 | // XXX We pick the first core on big.LITTLE systems, hopefully the |
LemonBoy <thatlemon@gmail.com> 2021-05-02 19:35:06+02:00