authorgravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-13 00:25:24+07:00
committergravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-24 21:08:41+07:00
loge7fde5f64e29ad5a730f18e82485dda00f658db8
tree074f093ae025bcff4616ac78b8b62f097cf9adb6
parentaccc3bad6377394531a9ee772e1f90018d058d06

stage2: sparc64: Introduce condition_register MCValue type

Introduce condition_register MCValue type for future uses with BPr/MOVr (mostly when needing to compare a signed value with zero)

4 files changed, 98 insertions(+), 7 deletions(-)

src/arch/sparc64/CodeGen.zig+57-3
......@@ -96,6 +96,9 @@ stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
9696/// Tracks the current instruction allocated to the condition flags
9797condition_flags_inst: ?Air.Inst.Index = null,
9898
99/// Tracks the current instruction allocated to the condition register
100condition_register_inst: ?Air.Inst.Index = null,
101
99102/// Offset from the stack base, representing the end of the stack frame.
100103max_end_stack: u32 = 0,
101104/// Represents the current end stack offset. If there is no existing slot
......@@ -148,6 +151,13 @@ const MCValue = union(enum) {
148151 cond: Instruction.Condition,
149152 ccr: Instruction.CCR,
150153 },
154 /// The value is in the specified Register. The value is 1 (if
155 /// the type is u1) or true (if the type in bool) iff the
156 /// specified condition is true.
157 condition_register: struct {
158 cond: Instruction.RCondition,
159 reg: Register,
160 },
151161
152162 fn isMemory(mcv: MCValue) bool {
153163 return switch (mcv) {
......@@ -171,6 +181,8 @@ const MCValue = union(enum) {
171181
172182 .immediate,
173183 .memory,
184 .condition_flags,
185 .condition_register,
174186 .ptr_stack_offset,
175187 .undef,
176188 => false,
......@@ -1748,7 +1760,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
17481760 _ = try self.addInst(.{
17491761 .tag = .movcc,
17501762 .data = .{
1751 .conditional_move = .{
1763 .conditional_move_int = .{
17521764 .ccr = rwo.flag.ccr,
17531765 .cond = .{ .icond = rwo.flag.cond },
17541766 .is_imm = true,
......@@ -2401,6 +2413,17 @@ fn condBr(self: *Self, condition: MCValue) !Mir.Inst.Index {
24012413 },
24022414 },
24032415 }),
2416 .condition_register => |reg| try self.addInst(.{
2417 .tag = .bpr,
2418 .data = .{
2419 .branch_predict_reg = .{
2420 .rs1 = reg.reg,
2421 // Here we map to the opposite condition because the jump is to the false branch.
2422 .cond = reg.cond.negate(),
2423 .inst = undefined, // Will be filled by performReloc
2424 },
2425 },
2426 }),
24042427 else => blk: {
24052428 const reg = switch (condition) {
24062429 .register => |r| r,
......@@ -2655,7 +2678,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
26552678 _ = try self.addInst(.{
26562679 .tag = .movcc,
26572680 .data = .{
2658 .conditional_move = .{
2681 .conditional_move_int = .{
26592682 .ccr = ccr,
26602683 .cond = condition,
26612684 .is_imm = true,
......@@ -2665,6 +2688,34 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
26652688 },
26662689 });
26672690 },
2691 .condition_register => |op| {
2692 const condition = op.cond;
2693 const register = op.reg;
2694
2695 _ = try self.addInst(.{
2696 .tag = .mov,
2697 .data = .{
2698 .arithmetic_2op = .{
2699 .is_imm = false,
2700 .rs1 = reg,
2701 .rs2_or_imm = .{ .rs2 = .g0 },
2702 },
2703 },
2704 });
2705
2706 _ = try self.addInst(.{
2707 .tag = .movr,
2708 .data = .{
2709 .conditional_move_reg = .{
2710 .cond = condition,
2711 .is_imm = true,
2712 .rd = reg,
2713 .rs1 = register,
2714 .rs2_or_imm = .{ .imm = 1 },
2715 },
2716 },
2717 });
2718 },
26682719 .undef => {
26692720 if (!self.wantSafety())
26702721 return; // The already existing value will do just fine.
......@@ -2832,6 +2883,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
28322883 }
28332884 },
28342885 .condition_flags,
2886 .condition_register,
28352887 .immediate,
28362888 .ptr_stack_offset,
28372889 => {
......@@ -2872,7 +2924,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
28722924 _ = try self.addInst(.{
28732925 .tag = .movcc,
28742926 .data = .{
2875 .conditional_move = .{
2927 .conditional_move_int = .{
28762928 .ccr = rwo.flag.ccr,
28772929 .cond = .{ .icond = rwo.flag.cond },
28782930 .is_imm = true,
......@@ -3124,6 +3176,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
31243176 .unreach => unreachable,
31253177 .dead => unreachable,
31263178 .condition_flags,
3179 .condition_register,
31273180 .register_with_overflow,
31283181 => unreachable, // cannot hold an address
31293182 .immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
......@@ -3475,6 +3528,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
34753528 .unreach => unreachable,
34763529 .dead => unreachable,
34773530 .condition_flags,
3531 .condition_register,
34783532 .register_with_overflow,
34793533 => unreachable, // cannot hold an address
34803534 .immediate => |imm| {
src/arch/sparc64/Emit.zig+3-1
......@@ -99,6 +99,8 @@ pub fn emitMir(
9999
100100 .movcc => try emit.mirConditionalMove(inst),
101101
102 .movr => @panic("TODO implement sparc64 movr"),
103
102104 .mulx => try emit.mirArithmetic3Op(inst),
103105
104106 .nop => try emit.mirNop(),
......@@ -314,7 +316,7 @@ fn mirConditionalMove(emit: *Emit, inst: Mir.Inst.Index) !void {
314316
315317 switch (tag) {
316318 .movcc => {
317 const data = emit.mir.instructions.items(.data)[inst].conditional_move;
319 const data = emit.mir.instructions.items(.data)[inst].conditional_move_int;
318320 if (data.is_imm) {
319321 try emit.writeInstruction(Instruction.movcc(
320322 i11,
src/arch/sparc64/Mir.zig+23-3
......@@ -78,9 +78,13 @@ pub const Inst = struct {
7878 xnor,
7979
8080 /// A.35 Move Integer Register on Condition (MOVcc)
81 /// This uses the conditional_move field.
81 /// This uses the conditional_move_int field.
8282 movcc,
8383
84 /// A.36 Move Integer Register on Register Condition (MOVr)
85 /// This uses the conditional_move_reg field.
86 movr,
87
8488 /// A.37 Multiply and Divide (64-bit)
8589 /// This uses the arithmetic_3op field.
8690 // TODO add other operations.
......@@ -230,12 +234,12 @@ pub const Inst = struct {
230234 inst: Index,
231235 },
232236
233 /// Conditional move.
237 /// Conditional move, checking the integer status code
234238 /// if is_imm true then it uses the imm field of rs2_or_imm,
235239 /// otherwise it uses rs2 field.
236240 ///
237241 /// Used by e.g. movcc
238 conditional_move: struct {
242 conditional_move_int: struct {
239243 is_imm: bool,
240244 ccr: Instruction.CCR,
241245 cond: Instruction.Condition,
......@@ -246,6 +250,22 @@ pub const Inst = struct {
246250 },
247251 },
248252
253 /// Conditional move, comparing a register's content with zero
254 /// if is_imm true then it uses the imm field of rs2_or_imm,
255 /// otherwise it uses rs2 field.
256 ///
257 /// Used by e.g. movr
258 conditional_move_reg: struct {
259 is_imm: bool,
260 cond: Instruction.RCondition,
261 rd: Register,
262 rs1: Register,
263 rs2_or_imm: union {
264 rs2: Register,
265 imm: i10,
266 },
267 },
268
249269 /// No additional data
250270 ///
251271 /// Used by e.g. flushw
src/arch/sparc64/bits.zig+15
......@@ -475,6 +475,21 @@ pub const Instruction = union(enum) {
475475 ne_zero,
476476 gt_zero,
477477 ge_zero,
478
479 /// Returns the condition which is true iff the given condition is
480 /// false (if such a condition exists).
481 pub fn negate(cond: RCondition) RCondition {
482 return switch (cond) {
483 .eq_zero => .ne_zero,
484 .ne_zero => .eq_zero,
485 .lt_zero => .ge_zero,
486 .ge_zero => .lt_zero,
487 .le_zero => .gt_zero,
488 .gt_zero => .le_zero,
489 .reserved1 => unreachable,
490 .reserved2 => unreachable,
491 };
492 }
478493 };
479494
480495 pub const ASI = enum(u8) {