Commit e98e58691f2c0759c8534080446cf6faecd30eb0 | zig

author	Jacob Young <jacobly@ziglang.org> 2023-05-08 18:34:45-04:00
committer	Jacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log	e98e58691f2c0759c8534080446cf6faecd30eb0
tree	824e8ea79f463ca7e9e9f7666ad4d1d329f7161b
parent	019c8844811ffb8b385ac8891cfd17cbf60d104a

1 files changed, 10 insertions(+), 9 deletions(-)

src/arch/x86_64/CodeGen.zig+10-9

 @@ -1460,6 +1460,15 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, reg: Regist
 }
 fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immediate) !void {
+    const payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) {
+        .signed => |s| @bitCast(u32, s),
+        .unsigned => |u| @intCast(u32, u),
+    } });
+    assert(payload + 1 == switch (m) {
+        .sib => try self.addExtra(Mir.MemorySib.encode(m)),
+        .rip => try self.addExtra(Mir.MemoryRip.encode(m)),
+        else => unreachable,
+    });
     _ = try self.addInst(.{
         .tag = tag[1],
         .ops = switch (m) {
 @@ -1475,17 +1484,9 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immed
         },
         .data = .{ .x = .{
             .fixes = tag[0],
-            .payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) {
+            .payload = payload,
-                .signed => |s| @bitCast(u32, s),
-                .unsigned => |u| @intCast(u32, u),
-            } }),
         } },
     });
-    _ = switch (m) {
-        .sib => try self.addExtra(Mir.MemorySib.encode(m)),
-        .rip => try self.addExtra(Mir.MemoryRip.encode(m)),
-        else => unreachable,
-    };
 }
 fn asmMemoryRegisterRegister(