authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 14:10:07+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-21 22:38:30+02:00
logf1e0c35db4167b8cc5a70d2270028287e737fff4
treecbd5e142e629b2fca80af47ebbc3cf94b2e757ba
parent67a052df81dbd40a49ce07b58e854d56b1def03a
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove `hsail`/`hsail64` arch tags.

This seems to just be dead. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project%20hsail&type=code See: https://github.com/HSAFoundation/HSAIL-Tools/commits/master

6 files changed, 0 insertions(+), 34 deletions(-)

lib/compiler/aro/aro/target.zig-6
...@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
480 .x86,480 .x86,
481 .xcore,481 .xcore,
482 .nvptx,482 .nvptx,
483 .hsail,
484 .spir,483 .spir,
485 .kalimba,484 .kalimba,
486 .shave,485 .shave,
...@@ -497,7 +496,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {...@@ -497,7 +496,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
497 .aarch64_be => copy.cpu.arch = .armeb,496 .aarch64_be => copy.cpu.arch = .armeb,
498 .nvptx64 => copy.cpu.arch = .nvptx,497 .nvptx64 => copy.cpu.arch = .nvptx,
499 .wasm64 => copy.cpu.arch = .wasm32,498 .wasm64 => copy.cpu.arch = .wasm32,
500 .hsail64 => copy.cpu.arch = .hsail,
501 .spir64 => copy.cpu.arch = .spir,499 .spir64 => copy.cpu.arch = .spir,
502 .spirv64 => copy.cpu.arch = .spirv32,500 .spirv64 => copy.cpu.arch = .spirv32,
503 .loongarch64 => copy.cpu.arch = .loongarch32,501 .loongarch64 => copy.cpu.arch = .loongarch32,
...@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
540 .bpfel,538 .bpfel,
541 .nvptx64,539 .nvptx64,
542 .wasm64,540 .wasm64,
543 .hsail64,
544 .spir64,541 .spir64,
545 .spirv64,542 .spirv64,
546 .loongarch64,543 .loongarch64,
...@@ -558,7 +555,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {...@@ -558,7 +555,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
558 .aarch64_32 => copy.cpu.arch = .aarch64,555 .aarch64_32 => copy.cpu.arch = .aarch64,
559 .arm => copy.cpu.arch = .aarch64,556 .arm => copy.cpu.arch = .aarch64,
560 .armeb => copy.cpu.arch = .aarch64_be,557 .armeb => copy.cpu.arch = .aarch64_be,
561 .hsail => copy.cpu.arch = .hsail64,
562 .loongarch32 => copy.cpu.arch = .loongarch64,558 .loongarch32 => copy.cpu.arch = .loongarch64,
563 .mips => copy.cpu.arch = .mips64,559 .mips => copy.cpu.arch = .mips64,
564 .mipsel => copy.cpu.arch = .mips64el,560 .mipsel => copy.cpu.arch = .mips64el,
...@@ -627,8 +623,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {...@@ -627,8 +623,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
627 .xtensa => "xtensa",623 .xtensa => "xtensa",
628 .nvptx => "nvptx",624 .nvptx => "nvptx",
629 .nvptx64 => "nvptx64",625 .nvptx64 => "nvptx64",
630 .hsail => "hsail",
631 .hsail64 => "hsail64",
632 .spir => "spir",626 .spir => "spir",
633 .spir64 => "spir64",627 .spir64 => "spir64",
634 .spirv32 => "spirv32",628 .spirv32 => "spirv32",
lib/std/Target.zig-16
...@@ -1011,8 +1011,6 @@ pub const Cpu = struct {...@@ -1011,8 +1011,6 @@ pub const Cpu = struct {
1011 xtensa,1011 xtensa,
1012 nvptx,1012 nvptx,
1013 nvptx64,1013 nvptx64,
1014 hsail,
1015 hsail64,
1016 spir,1014 spir,
1017 spir64,1015 spir64,
1018 spirv,1016 spirv,
...@@ -1154,7 +1152,6 @@ pub const Cpu = struct {...@@ -1154,7 +1152,6 @@ pub const Cpu = struct {
1154 .xcore => .XCORE,1152 .xcore => .XCORE,
1155 .xtensa => .XTENSA,1153 .xtensa => .XTENSA,
1156 .nvptx => .NONE,1154 .nvptx => .NONE,
1157 .hsail => .NONE,
1158 .spir => .NONE,1155 .spir => .NONE,
1159 .kalimba => .CSR_KALIMBA,1156 .kalimba => .CSR_KALIMBA,
1160 .shave => .NONE,1157 .shave => .NONE,
...@@ -1170,7 +1167,6 @@ pub const Cpu = struct {...@@ -1170,7 +1167,6 @@ pub const Cpu = struct {
1170 .riscv64 => .RISCV,1167 .riscv64 => .RISCV,
1171 .x86_64 => .X86_64,1168 .x86_64 => .X86_64,
1172 .nvptx64 => .NONE,1169 .nvptx64 => .NONE,
1173 .hsail64 => .NONE,
1174 .spir64 => .NONE,1170 .spir64 => .NONE,
1175 .wasm64 => .NONE,1171 .wasm64 => .NONE,
1176 .amdgcn => .AMDGPU,1172 .amdgcn => .AMDGPU,
...@@ -1213,7 +1209,6 @@ pub const Cpu = struct {...@@ -1213,7 +1209,6 @@ pub const Cpu = struct {
1213 .xcore => .Unknown,1209 .xcore => .Unknown,
1214 .xtensa => .Unknown,1210 .xtensa => .Unknown,
1215 .nvptx => .Unknown,1211 .nvptx => .Unknown,
1216 .hsail => .Unknown,
1217 .spir => .Unknown,1212 .spir => .Unknown,
1218 .kalimba => .Unknown,1213 .kalimba => .Unknown,
1219 .shave => .Unknown,1214 .shave => .Unknown,
...@@ -1229,7 +1224,6 @@ pub const Cpu = struct {...@@ -1229,7 +1224,6 @@ pub const Cpu = struct {
1229 .riscv64 => .RISCV64,1224 .riscv64 => .RISCV64,
1230 .x86_64 => .X64,1225 .x86_64 => .X64,
1231 .nvptx64 => .Unknown,1226 .nvptx64 => .Unknown,
1232 .hsail64 => .Unknown,
1233 .spir64 => .Unknown,1227 .spir64 => .Unknown,
1234 .wasm64 => .Unknown,1228 .wasm64 => .Unknown,
1235 .amdgcn => .Unknown,1229 .amdgcn => .Unknown,
...@@ -1259,8 +1253,6 @@ pub const Cpu = struct {...@@ -1259,8 +1253,6 @@ pub const Cpu = struct {
1259 .csky,1253 .csky,
1260 .xtensa,1254 .xtensa,
1261 .hexagon,1255 .hexagon,
1262 .hsail,
1263 .hsail64,
1264 .kalimba,1256 .kalimba,
1265 .mipsel,1257 .mipsel,
1266 .mips64el,1258 .mips64el,
...@@ -1764,8 +1756,6 @@ pub const DynamicLinker = struct {...@@ -1764,8 +1756,6 @@ pub const DynamicLinker = struct {
1764 .tce,1756 .tce,
1765 .tcele,1757 .tcele,
1766 .xcore,1758 .xcore,
1767 .hsail,
1768 .hsail64,
1769 .spir,1759 .spir,
1770 .spir64,1760 .spir64,
1771 .kalimba,1761 .kalimba,
...@@ -1868,7 +1858,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1868,7 +1858,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1868 .x86,1858 .x86,
1869 .xcore,1859 .xcore,
1870 .nvptx,1860 .nvptx,
1871 .hsail,
1872 .spir,1861 .spir,
1873 .kalimba,1862 .kalimba,
1874 .shave,1863 .shave,
...@@ -1890,7 +1879,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -1890,7 +1879,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1890 .riscv64,1879 .riscv64,
1891 .x86_64,1880 .x86_64,
1892 .nvptx64,1881 .nvptx64,
1893 .hsail64,
1894 .spir64,1882 .spir64,
1895 .wasm64,1883 .wasm64,
1896 .amdgcn,1884 .amdgcn,
...@@ -2390,7 +2378,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2390,7 +2378,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2390 .loongarch32,2378 .loongarch32,
2391 .tce,2379 .tce,
2392 .tcele,2380 .tcele,
2393 .hsail,
2394 .spir,2381 .spir,
2395 .spirv32,2382 .spirv32,
2396 .kalimba,2383 .kalimba,
...@@ -2405,7 +2392,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {...@@ -2405,7 +2392,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2405 .bpfel,2392 .bpfel,
2406 .bpfeb,2393 .bpfeb,
2407 .hexagon,2394 .hexagon,
2408 .hsail64,
2409 .loongarch64,2395 .loongarch64,
2410 .m68k,2396 .m68k,
2411 .mips,2397 .mips,
...@@ -2504,7 +2490,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2504,7 +2490,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2504 .loongarch32,2490 .loongarch32,
2505 .tce,2491 .tce,
2506 .tcele,2492 .tcele,
2507 .hsail,
2508 .spir,2493 .spir,
2509 .spirv32,2494 .spirv32,
2510 .kalimba,2495 .kalimba,
...@@ -2525,7 +2510,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {...@@ -2525,7 +2510,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2525 .bpfel,2510 .bpfel,
2526 .bpfeb,2511 .bpfeb,
2527 .hexagon,2512 .hexagon,
2528 .hsail64,
2529 .x86,2513 .x86,
2530 .loongarch64,2514 .loongarch64,
2531 .m68k,2515 .m68k,
src/Type.zig-2
...@@ -1650,13 +1650,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {...@@ -1650,13 +1650,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1650 .m68k,1650 .m68k,
1651 .tce,1651 .tce,
1652 .tcele,1652 .tcele,
1653 .hsail,
1654 .spir,1653 .spir,
1655 .kalimba,1654 .kalimba,
1656 .spirv,1655 .spirv,
1657 .spirv32,1656 .spirv32,
1658 .shave,1657 .shave,
1659 .hsail64,
1660 .spir64,1658 .spir64,
1661 .ve,1659 .ve,
1662 .spirv64,1660 .spirv64,
src/Zcu.zig-2
...@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(...@@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment(
3255 .thumbeb,3255 .thumbeb,
3256 .x86,3256 .x86,
3257 .xcore,3257 .xcore,
3258 .hsail,
3259 .spir,3258 .spir,
3260 .kalimba,3259 .kalimba,
3261 .lanai,3260 .lanai,
...@@ -3279,7 +3278,6 @@ pub fn atomicPtrAlignment(...@@ -3279,7 +3278,6 @@ pub fn atomicPtrAlignment(
3279 .riscv64,3278 .riscv64,
3280 .sparc64,3279 .sparc64,
3281 .s390x,3280 .s390x,
3282 .hsail64,
3283 .spir64,3281 .spir64,
3284 .wasm64,3282 .wasm64,
3285 .ve,3283 .ve,
src/codegen/llvm.zig-6
...@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
82 .xtensa => "xtensa",82 .xtensa => "xtensa",
83 .nvptx => "nvptx",83 .nvptx => "nvptx",
84 .nvptx64 => "nvptx64",84 .nvptx64 => "nvptx64",
85 .hsail => "hsail",
86 .hsail64 => "hsail64",
87 .spir => "spir",85 .spir => "spir",
88 .spir64 => "spir64",86 .spir64 => "spir64",
89 .spirv => "spirv",87 .spirv => "spirv",
...@@ -301,8 +299,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {...@@ -301,8 +299,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
301 .xtensa => .xtensa,299 .xtensa => .xtensa,
302 .nvptx => .nvptx,300 .nvptx => .nvptx,
303 .nvptx64 => .nvptx64,301 .nvptx64 => .nvptx64,
304 .hsail => .hsail,
305 .hsail64 => .hsail64,
306 .spir => .spir,302 .spir => .spir,
307 .spir64 => .spir64,303 .spir64 => .spir64,
308 .spirv => .spirv,304 .spirv => .spirv,
...@@ -12084,8 +12080,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -12084,8 +12080,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12084 // LLVM backends that have no initialization functions.12080 // LLVM backends that have no initialization functions.
12085 .tce,12081 .tce,
12086 .tcele,12082 .tcele,
12087 .hsail,
12088 .hsail64,
12089 .shave,12083 .shave,
12090 .spir,12084 .spir,
12091 .spir64,12085 .spir64,
src/target.zig-2
...@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
152 .xtensa,152 .xtensa,
153 .nvptx,153 .nvptx,
154 .nvptx64,154 .nvptx64,
155 .hsail,
156 .hsail64,
157 .spir,155 .spir,
158 .spir64,156 .spir64,
159 .spirv,157 .spirv,