llvm: Disable f16 lowering for hexagon.
In theory, this should work for v68+. In practice, it runs into an LLVM
assertion when using a `freeze` instruction on `f16` values, similar to the
issue we had for LoongArch.
1 files changed, 1 insertions(+), 0 deletions(-)
src/codegen/llvm.zig+1
| ... | ... | @@ -12380,6 +12380,7 @@ fn backendSupportsF80(target: std.Target) bool { |
| 12380 | 12380 | /// if it produces miscompilations. |
| 12381 | 12381 | fn backendSupportsF16(target: std.Target) bool { |
| 12382 | 12382 | return switch (target.cpu.arch) { |
| 12383 | .hexagon, |
| 12383 | 12384 | .powerpc, |
| 12384 | 12385 | .powerpcle, |
| 12385 | 12386 | .powerpc64, |
Alex Rønne Petersen <alex@alexrp.com> 2024-10-02 08:16:05+02:00