| ... | ... | @@ -328,6 +328,8 @@ pub const Helper = enum(i32) { |
| 328 | 328 | _, |
| 329 | 329 | }; |
| 330 | 330 | |
| 331 | // TODO: determine that this is the expected bit layout for both little and big |
| 332 | // endian systems |
| 331 | 333 | /// a single BPF instruction |
| 332 | 334 | pub const Insn = packed struct { |
| 333 | 335 | code: u8, |
| ... | ... | @@ -340,19 +342,30 @@ pub const Insn = packed struct { |
| 340 | 342 | /// frame |
| 341 | 343 | pub const Reg = packed enum(u4) { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 }; |
| 342 | 344 | const Source = packed enum(u1) { reg, imm }; |
| 345 | |
| 346 | const Mode = packed enum(u8) { |
| 347 | imm = IMM, |
| 348 | abs = ABS, |
| 349 | ind = IND, |
| 350 | mem = MEM, |
| 351 | len = LEN, |
| 352 | msh = MSH, |
| 353 | }; |
| 354 | |
| 343 | 355 | const AluOp = packed enum(u8) { |
| 344 | 356 | add = ADD, |
| 345 | 357 | sub = SUB, |
| 346 | 358 | mul = MUL, |
| 347 | 359 | div = DIV, |
| 348 | | op_or = OR, |
| 349 | | op_and = AND, |
| 360 | alu_or = OR, |
| 361 | alu_and = AND, |
| 350 | 362 | lsh = LSH, |
| 351 | 363 | rsh = RSH, |
| 352 | 364 | neg = NEG, |
| 353 | 365 | mod = MOD, |
| 354 | 366 | xor = XOR, |
| 355 | 367 | mov = MOV, |
| 368 | arsh = ARSH, |
| 356 | 369 | }; |
| 357 | 370 | |
| 358 | 371 | pub const Size = packed enum(u8) { |
| ... | ... | @@ -368,6 +381,13 @@ pub const Insn = packed struct { |
| 368 | 381 | jgt = JGT, |
| 369 | 382 | jge = JGE, |
| 370 | 383 | jset = JSET, |
| 384 | jlt = JLT, |
| 385 | jle = JLE, |
| 386 | jne = JNE, |
| 387 | jsgt = JSGT, |
| 388 | jsge = JSGE, |
| 389 | jslt = JSLT, |
| 390 | jsle = JSLE, |
| 371 | 391 | }; |
| 372 | 392 | |
| 373 | 393 | const ImmOrReg = union(Source) { |
| ... | ... | @@ -419,22 +439,100 @@ pub const Insn = packed struct { |
| 419 | 439 | return alu(64, .add, dst, src); |
| 420 | 440 | } |
| 421 | 441 | |
| 442 | pub fn sub(dst: Reg, src: anytype) Insn { |
| 443 | return alu(64, .sub, dst, src); |
| 444 | } |
| 445 | |
| 446 | pub fn mul(dst: Reg, src: anytype) Insn { |
| 447 | return alu(64, .mul, dst, src); |
| 448 | } |
| 449 | |
| 450 | pub fn div(dst: Reg, src: anytype) Insn { |
| 451 | return alu(64, .div, dst, src); |
| 452 | } |
| 453 | |
| 454 | pub fn alu_or(dst: Reg, src: anytype) Insn { |
| 455 | return alu(64, .alu_or, dst, src); |
| 456 | } |
| 457 | |
| 458 | pub fn alu_and(dst: Reg, src: anytype) Insn { |
| 459 | return alu(64, .alu_and, dst, src); |
| 460 | } |
| 461 | |
| 462 | pub fn lsh(dst: Reg, src: anytype) Insn { |
| 463 | return alu(64, .lsh, dst, src); |
| 464 | } |
| 465 | |
| 466 | pub fn rsh(dst: Reg, src: anytype) Insn { |
| 467 | return alu(64, .rsh, dst, src); |
| 468 | } |
| 469 | |
| 470 | pub fn neg(dst: Reg) Insn { |
| 471 | return alu(64, .neg, dst, 0); |
| 472 | } |
| 473 | |
| 474 | pub fn mod(dst: Reg, src: anytype) Insn { |
| 475 | return alu(64, .mod, dst, src); |
| 476 | } |
| 477 | |
| 478 | pub fn xor(dst: Reg, src: anytype) Insn { |
| 479 | return alu(64, .xor, dst, src); |
| 480 | } |
| 481 | |
| 482 | pub fn arsh(dst: Reg, src: anytype) Insn { |
| 483 | return alu(64, .arsh, dst, src); |
| 484 | } |
| 485 | |
| 422 | 486 | fn jmp(op: JmpOp, dst: Reg, src: anytype, off: i16) Insn { |
| 423 | 487 | return imm_reg(JMP | @enumToInt(op), dst, src, off); |
| 424 | 488 | } |
| 425 | 489 | |
| 490 | pub fn ja(off: i16) Insn { |
| 491 | return jmp(.ja, .r0, 0, off); |
| 492 | } |
| 493 | |
| 426 | 494 | pub fn jeq(dst: Reg, src: anytype, off: i16) Insn { |
| 427 | 495 | return jmp(.jeq, dst, src, off); |
| 428 | 496 | } |
| 429 | 497 | |
| 430 | | pub fn stx_mem(size: Size, dst: Reg, src: Reg, off: i16) Insn { |
| 431 | | return Insn{ |
| 432 | | .code = STX | @enumToInt(size) | MEM, |
| 433 | | .dst = @enumToInt(dst), |
| 434 | | .src = @enumToInt(src), |
| 435 | | .off = off, |
| 436 | | .imm = 0, |
| 437 | | }; |
| 498 | pub fn jgt(dst: Reg, src: anytype, off: i16) Insn { |
| 499 | return jmp(.jgt, dst, src, off); |
| 500 | } |
| 501 | |
| 502 | pub fn jge(dst: Reg, src: anytype, off: i16) Insn { |
| 503 | return jmp(.jge, dst, src, off); |
| 504 | } |
| 505 | |
| 506 | pub fn jlt(dst: Reg, src: anytype, off: i16) Insn { |
| 507 | return jmp(.jlt, dst, src, off); |
| 508 | } |
| 509 | |
| 510 | pub fn jle(dst: Reg, src: anytype, off: i16) Insn { |
| 511 | return jmp(.jle, dst, src, off); |
| 512 | } |
| 513 | |
| 514 | pub fn jset(dst: Reg, src: anytype, off: i16) Insn { |
| 515 | return jmp(.jset, dst, src, off); |
| 516 | } |
| 517 | |
| 518 | pub fn jne(dst: Reg, src: anytype, off: i16) Insn { |
| 519 | return jmp(.jne, dst, src, off); |
| 520 | } |
| 521 | |
| 522 | pub fn jsgt(dst: Reg, src: anytype, off: i16) Insn { |
| 523 | return jmp(.jsgt, dst, src, off); |
| 524 | } |
| 525 | |
| 526 | pub fn jsge(dst: Reg, src: anytype, off: i16) Insn { |
| 527 | return jmp(.jsge, dst, src, off); |
| 528 | } |
| 529 | |
| 530 | pub fn jslt(dst: Reg, src: anytype, off: i16) Insn { |
| 531 | return jmp(.jslt, dst, src, off); |
| 532 | } |
| 533 | |
| 534 | pub fn jsle(dst: Reg, src: anytype, off: i16) Insn { |
| 535 | return jmp(.jsle, dst, src, off); |
| 438 | 536 | } |
| 439 | 537 | |
| 440 | 538 | pub fn xadd(dst: Reg, src: Reg) Insn { |
| ... | ... | @@ -447,17 +545,34 @@ pub const Insn = packed struct { |
| 447 | 545 | }; |
| 448 | 546 | } |
| 449 | 547 | |
| 450 | | /// direct packet access, R0 = *(uint *)(skb->data + imm32) |
| 451 | | pub fn ld_abs(size: Size, imm: i32) Insn { |
| 548 | fn ld(mode: Mode, size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| 452 | 549 | return Insn{ |
| 453 | | .code = LD | @enumToInt(size) | ABS, |
| 454 | | .dst = 0, |
| 455 | | .src = 0, |
| 550 | .code = @enumToInt(mode) | @enumToInt(size) | LD, |
| 551 | .dst = @enumToInt(dst), |
| 552 | .src = @enumToInt(src), |
| 456 | 553 | .off = 0, |
| 457 | 554 | .imm = imm, |
| 458 | 555 | }; |
| 459 | 556 | } |
| 460 | 557 | |
| 558 | pub fn ld_abs(size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| 559 | return ld(.abs, size, dst, src, imm); |
| 560 | } |
| 561 | |
| 562 | pub fn ld_ind(size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| 563 | return ld(.ind, size, dst, src, imm); |
| 564 | } |
| 565 | |
| 566 | pub fn ldx(size: Size, dst: Reg, src: Reg, off: i16) Insn { |
| 567 | return Insn{ |
| 568 | .code = MEM | @enumToInt(size) | LDX, |
| 569 | .dst = @enumToInt(dst), |
| 570 | .src = @enumToInt(src), |
| 571 | .off = off, |
| 572 | .imm = 0, |
| 573 | }; |
| 574 | } |
| 575 | |
| 461 | 576 | fn ld_imm_impl1(dst: Reg, src: Reg, imm: u64) Insn { |
| 462 | 577 | return Insn{ |
| 463 | 578 | .code = LD | DW | IMM, |
| ... | ... | @@ -478,6 +593,14 @@ pub const Insn = packed struct { |
| 478 | 593 | }; |
| 479 | 594 | } |
| 480 | 595 | |
| 596 | pub fn ld_dw1(dst: Reg, imm: u64) Insn { |
| 597 | return ld_imm_impl1(dst, .r0, imm); |
| 598 | } |
| 599 | |
| 600 | pub fn ld_dw2(imm: u64) Insn { |
| 601 | return ld_imm_impl2(imm); |
| 602 | } |
| 603 | |
| 481 | 604 | pub fn ld_map_fd1(dst: Reg, map_fd: fd_t) Insn { |
| 482 | 605 | return ld_imm_impl1(dst, @intToEnum(Reg, PSEUDO_MAP_FD), @intCast(u64, map_fd)); |
| 483 | 606 | } |
| ... | ... | @@ -486,6 +609,53 @@ pub const Insn = packed struct { |
| 486 | 609 | return ld_imm_impl2(@intCast(u64, map_fd)); |
| 487 | 610 | } |
| 488 | 611 | |
| 612 | pub fn st(comptime size: Size, dst: Reg, off: i16, imm: i32) Insn { |
| 613 | if (size == .double_word) @compileError("TODO: need to determine how to correctly handle double words"); |
| 614 | return Insn{ |
| 615 | .code = MEM | @enumToInt(size) | ST, |
| 616 | .dst = @enumToInt(dst), |
| 617 | .src = 0, |
| 618 | .off = off, |
| 619 | .imm = imm, |
| 620 | }; |
| 621 | } |
| 622 | |
| 623 | pub fn stx(size: Size, dst: Reg, off: i16, src: Reg) Insn { |
| 624 | return Insn{ |
| 625 | .code = MEM | @enumToInt(size) | STX, |
| 626 | .dst = @enumToInt(dst), |
| 627 | .src = @enumToInt(src), |
| 628 | .off = off, |
| 629 | .imm = 0, |
| 630 | }; |
| 631 | } |
| 632 | |
| 633 | fn endian_swap(endian: std.builtin.Endian, comptime size: Size, dst: Reg) Insn { |
| 634 | return Insn{ |
| 635 | .code = switch (endian) { |
| 636 | .Big => 0xdc, |
| 637 | .Little => 0xd4, |
| 638 | }, |
| 639 | .dst = @enumToInt(dst), |
| 640 | .src = 0, |
| 641 | .off = 0, |
| 642 | .imm = switch (size) { |
| 643 | .byte => @compileError("can't swap a single byte"), |
| 644 | .half_word => 16, |
| 645 | .word => 32, |
| 646 | .double_word => 64, |
| 647 | }, |
| 648 | }; |
| 649 | } |
| 650 | |
| 651 | pub fn le(comptime size: Size, dst: Reg) Insn { |
| 652 | return endian_swap(.Little, size, dst); |
| 653 | } |
| 654 | |
| 655 | pub fn be(comptime size: Size, dst: Reg) Insn { |
| 656 | return endian_swap(.Big, size, dst); |
| 657 | } |
| 658 | |
| 489 | 659 | pub fn call(helper: Helper) Insn { |
| 490 | 660 | return Insn{ |
| 491 | 661 | .code = JMP | CALL, |
| ... | ... | @@ -508,59 +678,122 @@ pub const Insn = packed struct { |
| 508 | 678 | } |
| 509 | 679 | }; |
| 510 | 680 | |
| 511 | | fn expect_insn(insn: Insn, val: u64) void { |
| 512 | | expectEqual(@bitCast(u64, insn), val); |
| 513 | | } |
| 514 | | |
| 515 | 681 | test "insn bitsize" { |
| 516 | 682 | expectEqual(@bitSizeOf(Insn), 64); |
| 517 | 683 | } |
| 518 | 684 | |
| 519 | | // mov instructions |
| 520 | | test "mov imm" { |
| 521 | | expect_insn(Insn.mov(.r1, 1), 0x00000001000001b7); |
| 522 | | } |
| 523 | | |
| 524 | | test "mov reg" { |
| 525 | | expect_insn(Insn.mov(.r6, .r1), 0x00000000000016bf); |
| 526 | | } |
| 527 | | |
| 528 | | // alu instructions |
| 529 | | test "add imm" { |
| 530 | | expect_insn(Insn.add(.r2, -4), 0xfffffffc00000207); |
| 531 | | } |
| 532 | | |
| 533 | | // ld instructions |
| 534 | | test "ld_abs" { |
| 535 | | expect_insn(Insn.ld_abs(.byte, 42), 0x0000002a00000030); |
| 536 | | } |
| 537 | | |
| 538 | | test "ld_map_fd" { |
| 539 | | expect_insn(Insn.ld_map_fd1(.r1, 42), 0x0000002a00001118); |
| 540 | | expect_insn(Insn.ld_map_fd2(42), 0x0000000000000000); |
| 541 | | } |
| 542 | | |
| 543 | | // st instructions |
| 544 | | test "stx_mem" { |
| 545 | | expect_insn(Insn.stx_mem(.word, .r10, .r0, -4), 0x00000000fffc0a63); |
| 546 | | } |
| 547 | | |
| 548 | | test "xadd" { |
| 549 | | expect_insn(Insn.xadd(.r0, .r1), 0x00000000000010db); |
| 550 | | } |
| 551 | | |
| 552 | | // jmp instructions |
| 553 | | test "jeq imm" { |
| 554 | | expect_insn(Insn.jeq(.r0, 0, 2), 0x0000000000020015); |
| 555 | | } |
| 556 | | |
| 557 | | // other instructions |
| 558 | | test "call" { |
| 559 | | expect_insn(Insn.call(.map_lookup_elem), 0x0000000100000085); |
| 685 | fn expect_opcode(code: u8, insn: Insn) void { |
| 686 | expectEqual(code, insn.code); |
| 560 | 687 | } |
| 561 | 688 | |
| 562 | | test "exit" { |
| 563 | | expect_insn(Insn.exit(), 0x0000000000000095); |
| 689 | // The opcodes were grabbed from https://github.com/iovisor/bpf-docs/blob/master/eBPF.md |
| 690 | test "opcodes" { |
| 691 | // instructions that have a name that end with 1 or 2 are consecutive for |
| 692 | // loading 64-bit immediates (imm is only 32 bits wide) |
| 693 | |
| 694 | // alu instructions |
| 695 | expect_opcode(0x07, Insn.add(.r1, 0)); |
| 696 | expect_opcode(0x0f, Insn.add(.r1, .r2)); |
| 697 | expect_opcode(0x17, Insn.sub(.r1, 0)); |
| 698 | expect_opcode(0x1f, Insn.sub(.r1, .r2)); |
| 699 | expect_opcode(0x27, Insn.mul(.r1, 0)); |
| 700 | expect_opcode(0x2f, Insn.mul(.r1, .r2)); |
| 701 | expect_opcode(0x37, Insn.div(.r1, 0)); |
| 702 | expect_opcode(0x3f, Insn.div(.r1, .r2)); |
| 703 | expect_opcode(0x47, Insn.alu_or(.r1, 0)); |
| 704 | expect_opcode(0x4f, Insn.alu_or(.r1, .r2)); |
| 705 | expect_opcode(0x57, Insn.alu_and(.r1, 0)); |
| 706 | expect_opcode(0x5f, Insn.alu_and(.r1, .r2)); |
| 707 | expect_opcode(0x67, Insn.lsh(.r1, 0)); |
| 708 | expect_opcode(0x6f, Insn.lsh(.r1, .r2)); |
| 709 | expect_opcode(0x77, Insn.rsh(.r1, 0)); |
| 710 | expect_opcode(0x7f, Insn.rsh(.r1, .r2)); |
| 711 | expect_opcode(0x87, Insn.neg(.r1)); |
| 712 | expect_opcode(0x97, Insn.mod(.r1, 0)); |
| 713 | expect_opcode(0x9f, Insn.mod(.r1, .r2)); |
| 714 | expect_opcode(0xa7, Insn.xor(.r1, 0)); |
| 715 | expect_opcode(0xaf, Insn.xor(.r1, .r2)); |
| 716 | expect_opcode(0xb7, Insn.mov(.r1, 0)); |
| 717 | expect_opcode(0xbf, Insn.mov(.r1, .r2)); |
| 718 | expect_opcode(0xc7, Insn.arsh(.r1, 0)); |
| 719 | expect_opcode(0xcf, Insn.arsh(.r1, .r2)); |
| 720 | |
| 721 | // atomic instructions: might be more of these not documented in the wild |
| 722 | expect_opcode(0xdb, Insn.xadd(.r1, .r2)); |
| 723 | |
| 724 | // TODO: byteswap instructions |
| 725 | expect_opcode(0xd4, Insn.le(.half_word, .r1)); |
| 726 | expectEqual(@intCast(i32, 16), Insn.le(.half_word, .r1).imm); |
| 727 | expect_opcode(0xd4, Insn.le(.word, .r1)); |
| 728 | expectEqual(@intCast(i32, 32), Insn.le(.word, .r1).imm); |
| 729 | expect_opcode(0xd4, Insn.le(.double_word, .r1)); |
| 730 | expectEqual(@intCast(i32, 64), Insn.le(.double_word, .r1).imm); |
| 731 | expect_opcode(0xdc, Insn.be(.half_word, .r1)); |
| 732 | expectEqual(@intCast(i32, 16), Insn.be(.half_word, .r1).imm); |
| 733 | expect_opcode(0xdc, Insn.be(.word, .r1)); |
| 734 | expectEqual(@intCast(i32, 32), Insn.be(.word, .r1).imm); |
| 735 | expect_opcode(0xdc, Insn.be(.double_word, .r1)); |
| 736 | expectEqual(@intCast(i32, 64), Insn.be(.double_word, .r1).imm); |
| 737 | |
| 738 | // memory instructions |
| 739 | expect_opcode(0x18, Insn.ld_dw1(.r1, 0)); |
| 740 | expect_opcode(0x00, Insn.ld_dw2(0)); |
| 741 | |
| 742 | // loading a map fd |
| 743 | expect_opcode(0x18, Insn.ld_map_fd1(.r1, 0)); |
| 744 | expectEqual(@intCast(u4, PSEUDO_MAP_FD), Insn.ld_map_fd1(.r1, 0).src); |
| 745 | expect_opcode(0x00, Insn.ld_map_fd2(0)); |
| 746 | |
| 747 | expect_opcode(0x38, Insn.ld_abs(.double_word, .r1, .r2, 0)); |
| 748 | expect_opcode(0x20, Insn.ld_abs(.word, .r1, .r2, 0)); |
| 749 | expect_opcode(0x28, Insn.ld_abs(.half_word, .r1, .r2, 0)); |
| 750 | expect_opcode(0x30, Insn.ld_abs(.byte, .r1, .r2, 0)); |
| 751 | |
| 752 | expect_opcode(0x58, Insn.ld_ind(.double_word, .r1, .r2, 0)); |
| 753 | expect_opcode(0x40, Insn.ld_ind(.word, .r1, .r2, 0)); |
| 754 | expect_opcode(0x48, Insn.ld_ind(.half_word, .r1, .r2, 0)); |
| 755 | expect_opcode(0x50, Insn.ld_ind(.byte, .r1, .r2, 0)); |
| 756 | |
| 757 | expect_opcode(0x79, Insn.ldx(.double_word, .r1, .r2, 0)); |
| 758 | expect_opcode(0x61, Insn.ldx(.word, .r1, .r2, 0)); |
| 759 | expect_opcode(0x69, Insn.ldx(.half_word, .r1, .r2, 0)); |
| 760 | expect_opcode(0x71, Insn.ldx(.byte, .r1, .r2, 0)); |
| 761 | |
| 762 | expect_opcode(0x62, Insn.st(.word, .r1, 0, 0)); |
| 763 | expect_opcode(0x6a, Insn.st(.half_word, .r1, 0, 0)); |
| 764 | expect_opcode(0x72, Insn.st(.byte, .r1, 0, 0)); |
| 765 | |
| 766 | expect_opcode(0x63, Insn.stx(.word, .r1, 0, .r2)); |
| 767 | expect_opcode(0x6b, Insn.stx(.half_word, .r1, 0, .r2)); |
| 768 | expect_opcode(0x73, Insn.stx(.byte, .r1, 0, .r2)); |
| 769 | expect_opcode(0x7b, Insn.stx(.double_word, .r1, 0, .r2)); |
| 770 | |
| 771 | // branch instructions |
| 772 | expect_opcode(0x05, Insn.ja(0)); |
| 773 | expect_opcode(0x15, Insn.jeq(.r1, 0, 0)); |
| 774 | expect_opcode(0x1d, Insn.jeq(.r1, .r2, 0)); |
| 775 | expect_opcode(0x25, Insn.jgt(.r1, 0, 0)); |
| 776 | expect_opcode(0x2d, Insn.jgt(.r1, .r2, 0)); |
| 777 | expect_opcode(0x35, Insn.jge(.r1, 0, 0)); |
| 778 | expect_opcode(0x3d, Insn.jge(.r1, .r2, 0)); |
| 779 | expect_opcode(0xa5, Insn.jlt(.r1, 0, 0)); |
| 780 | expect_opcode(0xad, Insn.jlt(.r1, .r2, 0)); |
| 781 | expect_opcode(0xb5, Insn.jle(.r1, 0, 0)); |
| 782 | expect_opcode(0xbd, Insn.jle(.r1, .r2, 0)); |
| 783 | expect_opcode(0x45, Insn.jset(.r1, 0, 0)); |
| 784 | expect_opcode(0x4d, Insn.jset(.r1, .r2, 0)); |
| 785 | expect_opcode(0x55, Insn.jne(.r1, 0, 0)); |
| 786 | expect_opcode(0x5d, Insn.jne(.r1, .r2, 0)); |
| 787 | expect_opcode(0x65, Insn.jsgt(.r1, 0, 0)); |
| 788 | expect_opcode(0x6d, Insn.jsgt(.r1, .r2, 0)); |
| 789 | expect_opcode(0x75, Insn.jsge(.r1, 0, 0)); |
| 790 | expect_opcode(0x7d, Insn.jsge(.r1, .r2, 0)); |
| 791 | expect_opcode(0xc5, Insn.jslt(.r1, 0, 0)); |
| 792 | expect_opcode(0xcd, Insn.jslt(.r1, .r2, 0)); |
| 793 | expect_opcode(0xd5, Insn.jsle(.r1, 0, 0)); |
| 794 | expect_opcode(0xdd, Insn.jsle(.r1, .r2, 0)); |
| 795 | expect_opcode(0x85, Insn.call(.unspec)); |
| 796 | expect_opcode(0x95, Insn.exit()); |
| 564 | 797 | } |
| 565 | 798 | |
| 566 | 799 | pub const Cmd = extern enum(usize) { |
Andrew Kelley <andrew@ziglang.org> 2020-09-07 15:39:42-04:00
GitHub <noreply@github.com> 2020-09-07 15:39:42-04:00
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