| author |  Andrew Kelley <andrew@ziglang.org> 2023-10-29 13:10:51-04:00 |
| committer |  GitHub <noreply@github.com> 2023-10-29 13:10:51-04:00 |
| log | fa022d1ecc148280a3b6e95312087b4e8c0c6166 |
| tree | 576863cc60c8626c8b89b01621d0538a4923a9ce |
| parent | 37295696ec5b1350333b88173187a3db8b199925 |
| parent | f6f2708d8289e1cd6c24b954c261d478ee73ccfc |
| signature |  Signed by PGP key 4AEE18F83AFDEB23 |
Merge pull request #17759 from jacobly0/x86_64
x86_64: pass more tests37 files changed, 1482 insertions(+), 1405 deletions(-)
lib
lib/compiler_rt/addf3_test.zig-4
| ... | @@ -35,8 +35,6 @@ fn test__addtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) !void { | ... | @@ -35,8 +35,6 @@ fn test__addtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) !void { |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | test "addtf3" { | 37 | test "addtf3" { |
| 38 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 39 | |||
| 40 | try test__addtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0); | 38 | try test__addtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0); |
| 41 | 39 | ||
| 42 | // NaN + any = NaN | 40 | // NaN + any = NaN |
| ... | @@ -106,8 +104,6 @@ fn test__addxf3(a: f80, b: f80, expected: u80) !void { | ... | @@ -106,8 +104,6 @@ fn test__addxf3(a: f80, b: f80, expected: u80) !void { |
| 106 | } | 104 | } |
| 107 | 105 | ||
| 108 | test "addxf3" { | 106 | test "addxf3" { |
| 109 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 110 | |||
| 111 | // NaN + any = NaN | 107 | // NaN + any = NaN |
| 112 | try test__addxf3(qnan80, 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80))); | 108 | try test__addxf3(qnan80, 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80))); |
| 113 | try test__addxf3(@as(f80, @bitCast(@as(u80, 0x7fff_8000_8000_3000_0000))), 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80))); | 109 | try test__addxf3(@as(f80, @bitCast(@as(u80, 0x7fff_8000_8000_3000_0000))), 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80))); |
lib/compiler_rt/addoti4_test.zig-2
| ... | @@ -23,8 +23,6 @@ fn simple_addoti4(a: i128, b: i128, overflow: *c_int) i128 { | ... | @@ -23,8 +23,6 @@ fn simple_addoti4(a: i128, b: i128, overflow: *c_int) i128 { |
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | test "addoti4" { | 25 | test "addoti4" { |
| 26 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 27 | |||
| 28 | const min: i128 = math.minInt(i128); | 26 | const min: i128 = math.minInt(i128); |
| 29 | const max: i128 = math.maxInt(i128); | 27 | const max: i128 = math.maxInt(i128); |
| 30 | var i: i128 = 1; | 28 | var i: i128 = 1; |
lib/compiler_rt/comparef.zig-2
| ... | @@ -98,8 +98,6 @@ pub inline fn cmp_f80(comptime RT: type, a: f80, b: f80) RT { | ... | @@ -98,8 +98,6 @@ pub inline fn cmp_f80(comptime RT: type, a: f80, b: f80) RT { |
| 98 | } | 98 | } |
| 99 | 99 | ||
| 100 | test "cmp_f80" { | 100 | test "cmp_f80" { |
| 101 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 102 | |||
| 103 | inline for (.{ LE, GE }) |RT| { | 101 | inline for (.{ LE, GE }) |RT| { |
| 104 | try std.testing.expect(cmp_f80(RT, 1.0, 1.0) == RT.Equal); | 102 | try std.testing.expect(cmp_f80(RT, 1.0, 1.0) == RT.Equal); |
| 105 | try std.testing.expect(cmp_f80(RT, 0.0, -0.0) == RT.Equal); | 103 | try std.testing.expect(cmp_f80(RT, 0.0, -0.0) == RT.Equal); |
lib/compiler_rt/cos.zig-2
| ... | @@ -134,8 +134,6 @@ pub fn cosl(x: c_longdouble) callconv(.C) c_longdouble { | ... | @@ -134,8 +134,6 @@ pub fn cosl(x: c_longdouble) callconv(.C) c_longdouble { |
| 134 | } | 134 | } |
| 135 | 135 | ||
| 136 | test "cos32" { | 136 | test "cos32" { |
| 137 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 138 | |||
| 139 | const epsilon = 0.00001; | 137 | const epsilon = 0.00001; |
| 140 | 138 | ||
| 141 | try expect(math.approxEqAbs(f32, cosf(0.0), 1.0, epsilon)); | 139 | try expect(math.approxEqAbs(f32, cosf(0.0), 1.0, epsilon)); |
lib/compiler_rt/divxf3_test.zig-2
| ... | @@ -39,8 +39,6 @@ fn test__divxf3(a: f80, b: f80) !void { | ... | @@ -39,8 +39,6 @@ fn test__divxf3(a: f80, b: f80) !void { |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | test "divxf3" { | 41 | test "divxf3" { |
| 42 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 43 | |||
| 44 | // NaN / any = NaN | 42 | // NaN / any = NaN |
| 45 | try expect__divxf3_result(math.nan(f80), 0x1.23456789abcdefp+5, 0x7fffC000000000000000); | 43 | try expect__divxf3_result(math.nan(f80), 0x1.23456789abcdefp+5, 0x7fffC000000000000000); |
| 46 | // inf / any(except inf and nan) = inf | 44 | // inf / any(except inf and nan) = inf |
lib/compiler_rt/fmodx_test.zig-3
| ... | @@ -23,9 +23,6 @@ fn test_fmodx_infs() !void { | ... | @@ -23,9 +23,6 @@ fn test_fmodx_infs() !void { |
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | test "fmodx" { | 25 | test "fmodx" { |
| 26 | if (builtin.zig_backend == .stage2_x86_64 and | ||
| 27 | !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .lzcnt)) return error.SkipZigTest; | ||
| 28 | |||
| 29 | try test_fmodx(6.4, 4.0, 2.4); | 26 | try test_fmodx(6.4, 4.0, 2.4); |
| 30 | try test_fmodx(6.4, -4.0, 2.4); | 27 | try test_fmodx(6.4, -4.0, 2.4); |
| 31 | try test_fmodx(-6.4, 4.0, -2.4); | 28 | try test_fmodx(-6.4, 4.0, -2.4); |
lib/compiler_rt/int_from_float_test.zig+1-36
| ... | @@ -41,8 +41,6 @@ fn test__fixunssfsi(a: f32, expected: u32) !void { | ... | @@ -41,8 +41,6 @@ fn test__fixunssfsi(a: f32, expected: u32) !void { |
| 41 | } | 41 | } |
| 42 | 42 | ||
| 43 | test "fixsfsi" { | 43 | test "fixsfsi" { |
| 44 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 45 | |||
| 46 | try test__fixsfsi(-math.floatMax(f32), math.minInt(i32)); | 44 | try test__fixsfsi(-math.floatMax(f32), math.minInt(i32)); |
| 47 | 45 | ||
| 48 | try test__fixsfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); | 46 | try test__fixsfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); |
| ... | @@ -71,6 +69,7 @@ test "fixsfsi" { | ... | @@ -71,6 +69,7 @@ test "fixsfsi" { |
| 71 | try test__fixsfsi(-1.0, -1); | 69 | try test__fixsfsi(-1.0, -1); |
| 72 | try test__fixsfsi(-0.99, 0); | 70 | try test__fixsfsi(-0.99, 0); |
| 73 | try test__fixsfsi(-0.5, 0); | 71 | try test__fixsfsi(-0.5, 0); |
| 72 | |||
| 74 | try test__fixsfsi(-math.floatMin(f32), 0); | 73 | try test__fixsfsi(-math.floatMin(f32), 0); |
| 75 | try test__fixsfsi(0.0, 0); | 74 | try test__fixsfsi(0.0, 0); |
| 76 | try test__fixsfsi(math.floatMin(f32), 0); | 75 | try test__fixsfsi(math.floatMin(f32), 0); |
| ... | @@ -106,8 +105,6 @@ test "fixsfsi" { | ... | @@ -106,8 +105,6 @@ test "fixsfsi" { |
| 106 | } | 105 | } |
| 107 | 106 | ||
| 108 | test "fixunssfsi" { | 107 | test "fixunssfsi" { |
| 109 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 110 | |||
| 111 | try test__fixunssfsi(0.0, 0); | 108 | try test__fixunssfsi(0.0, 0); |
| 112 | 109 | ||
| 113 | try test__fixunssfsi(0.5, 0); | 110 | try test__fixunssfsi(0.5, 0); |
| ... | @@ -147,8 +144,6 @@ fn test__fixunssfdi(a: f32, expected: u64) !void { | ... | @@ -147,8 +144,6 @@ fn test__fixunssfdi(a: f32, expected: u64) !void { |
| 147 | } | 144 | } |
| 148 | 145 | ||
| 149 | test "fixsfdi" { | 146 | test "fixsfdi" { |
| 150 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 151 | |||
| 152 | try test__fixsfdi(-math.floatMax(f32), math.minInt(i64)); | 147 | try test__fixsfdi(-math.floatMax(f32), math.minInt(i64)); |
| 153 | 148 | ||
| 154 | try test__fixsfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); | 149 | try test__fixsfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); |
| ... | @@ -204,8 +199,6 @@ test "fixsfdi" { | ... | @@ -204,8 +199,6 @@ test "fixsfdi" { |
| 204 | } | 199 | } |
| 205 | 200 | ||
| 206 | test "fixunssfdi" { | 201 | test "fixunssfdi" { |
| 207 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 208 | |||
| 209 | try test__fixunssfdi(0.0, 0); | 202 | try test__fixunssfdi(0.0, 0); |
| 210 | 203 | ||
| 211 | try test__fixunssfdi(0.5, 0); | 204 | try test__fixunssfdi(0.5, 0); |
| ... | @@ -244,8 +237,6 @@ fn test__fixunssfti(a: f32, expected: u128) !void { | ... | @@ -244,8 +237,6 @@ fn test__fixunssfti(a: f32, expected: u128) !void { |
| 244 | } | 237 | } |
| 245 | 238 | ||
| 246 | test "fixsfti" { | 239 | test "fixsfti" { |
| 247 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 248 | |||
| 249 | try test__fixsfti(-math.floatMax(f32), math.minInt(i128)); | 240 | try test__fixsfti(-math.floatMax(f32), math.minInt(i128)); |
| 250 | 241 | ||
| 251 | try test__fixsfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); | 242 | try test__fixsfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); |
| ... | @@ -317,8 +308,6 @@ test "fixsfti" { | ... | @@ -317,8 +308,6 @@ test "fixsfti" { |
| 317 | } | 308 | } |
| 318 | 309 | ||
| 319 | test "fixunssfti" { | 310 | test "fixunssfti" { |
| 320 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 321 | |||
| 322 | try test__fixunssfti(0.0, 0); | 311 | try test__fixunssfti(0.0, 0); |
| 323 | 312 | ||
| 324 | try test__fixunssfti(0.5, 0); | 313 | try test__fixunssfti(0.5, 0); |
| ... | @@ -365,8 +354,6 @@ fn test__fixunsdfsi(a: f64, expected: u32) !void { | ... | @@ -365,8 +354,6 @@ fn test__fixunsdfsi(a: f64, expected: u32) !void { |
| 365 | } | 354 | } |
| 366 | 355 | ||
| 367 | test "fixdfsi" { | 356 | test "fixdfsi" { |
| 368 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 369 | |||
| 370 | try test__fixdfsi(-math.floatMax(f64), math.minInt(i32)); | 357 | try test__fixdfsi(-math.floatMax(f64), math.minInt(i32)); |
| 371 | 358 | ||
| 372 | try test__fixdfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); | 359 | try test__fixdfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); |
| ... | @@ -428,8 +415,6 @@ test "fixdfsi" { | ... | @@ -428,8 +415,6 @@ test "fixdfsi" { |
| 428 | } | 415 | } |
| 429 | 416 | ||
| 430 | test "fixunsdfsi" { | 417 | test "fixunsdfsi" { |
| 431 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 432 | |||
| 433 | try test__fixunsdfsi(0.0, 0); | 418 | try test__fixunsdfsi(0.0, 0); |
| 434 | 419 | ||
| 435 | try test__fixunsdfsi(0.5, 0); | 420 | try test__fixunsdfsi(0.5, 0); |
| ... | @@ -472,8 +457,6 @@ fn test__fixunsdfdi(a: f64, expected: u64) !void { | ... | @@ -472,8 +457,6 @@ fn test__fixunsdfdi(a: f64, expected: u64) !void { |
| 472 | } | 457 | } |
| 473 | 458 | ||
| 474 | test "fixdfdi" { | 459 | test "fixdfdi" { |
| 475 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 476 | |||
| 477 | try test__fixdfdi(-math.floatMax(f64), math.minInt(i64)); | 460 | try test__fixdfdi(-math.floatMax(f64), math.minInt(i64)); |
| 478 | 461 | ||
| 479 | try test__fixdfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); | 462 | try test__fixdfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); |
| ... | @@ -527,8 +510,6 @@ test "fixdfdi" { | ... | @@ -527,8 +510,6 @@ test "fixdfdi" { |
| 527 | } | 510 | } |
| 528 | 511 | ||
| 529 | test "fixunsdfdi" { | 512 | test "fixunsdfdi" { |
| 530 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 531 | |||
| 532 | try test__fixunsdfdi(0.0, 0); | 513 | try test__fixunsdfdi(0.0, 0); |
| 533 | try test__fixunsdfdi(0.5, 0); | 514 | try test__fixunsdfdi(0.5, 0); |
| 534 | try test__fixunsdfdi(0.99, 0); | 515 | try test__fixunsdfdi(0.99, 0); |
| ... | @@ -571,8 +552,6 @@ fn test__fixunsdfti(a: f64, expected: u128) !void { | ... | @@ -571,8 +552,6 @@ fn test__fixunsdfti(a: f64, expected: u128) !void { |
| 571 | } | 552 | } |
| 572 | 553 | ||
| 573 | test "fixdfti" { | 554 | test "fixdfti" { |
| 574 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 575 | |||
| 576 | try test__fixdfti(-math.floatMax(f64), math.minInt(i128)); | 555 | try test__fixdfti(-math.floatMax(f64), math.minInt(i128)); |
| 577 | 556 | ||
| 578 | try test__fixdfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); | 557 | try test__fixdfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); |
| ... | @@ -626,8 +605,6 @@ test "fixdfti" { | ... | @@ -626,8 +605,6 @@ test "fixdfti" { |
| 626 | } | 605 | } |
| 627 | 606 | ||
| 628 | test "fixunsdfti" { | 607 | test "fixunsdfti" { |
| 629 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 630 | |||
| 631 | try test__fixunsdfti(0.0, 0); | 608 | try test__fixunsdfti(0.0, 0); |
| 632 | 609 | ||
| 633 | try test__fixunsdfti(0.5, 0); | 610 | try test__fixunsdfti(0.5, 0); |
| ... | @@ -677,8 +654,6 @@ fn test__fixunstfsi(a: f128, expected: u32) !void { | ... | @@ -677,8 +654,6 @@ fn test__fixunstfsi(a: f128, expected: u32) !void { |
| 677 | } | 654 | } |
| 678 | 655 | ||
| 679 | test "fixtfsi" { | 656 | test "fixtfsi" { |
| 680 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 681 | |||
| 682 | try test__fixtfsi(-math.floatMax(f128), math.minInt(i32)); | 657 | try test__fixtfsi(-math.floatMax(f128), math.minInt(i32)); |
| 683 | 658 | ||
| 684 | try test__fixtfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); | 659 | try test__fixtfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32)); |
| ... | @@ -742,8 +717,6 @@ test "fixtfsi" { | ... | @@ -742,8 +717,6 @@ test "fixtfsi" { |
| 742 | } | 717 | } |
| 743 | 718 | ||
| 744 | test "fixunstfsi" { | 719 | test "fixunstfsi" { |
| 745 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 746 | |||
| 747 | try test__fixunstfsi(math.inf(f128), 0xffffffff); | 720 | try test__fixunstfsi(math.inf(f128), 0xffffffff); |
| 748 | try test__fixunstfsi(0, 0x0); | 721 | try test__fixunstfsi(0, 0x0); |
| 749 | try test__fixunstfsi(0x1.23456789abcdefp+5, 0x24); | 722 | try test__fixunstfsi(0x1.23456789abcdefp+5, 0x24); |
| ... | @@ -767,8 +740,6 @@ fn test__fixunstfdi(a: f128, expected: u64) !void { | ... | @@ -767,8 +740,6 @@ fn test__fixunstfdi(a: f128, expected: u64) !void { |
| 767 | } | 740 | } |
| 768 | 741 | ||
| 769 | test "fixtfdi" { | 742 | test "fixtfdi" { |
| 770 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 771 | |||
| 772 | try test__fixtfdi(-math.floatMax(f128), math.minInt(i64)); | 743 | try test__fixtfdi(-math.floatMax(f128), math.minInt(i64)); |
| 773 | 744 | ||
| 774 | try test__fixtfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); | 745 | try test__fixtfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64)); |
| ... | @@ -832,8 +803,6 @@ test "fixtfdi" { | ... | @@ -832,8 +803,6 @@ test "fixtfdi" { |
| 832 | } | 803 | } |
| 833 | 804 | ||
| 834 | test "fixunstfdi" { | 805 | test "fixunstfdi" { |
| 835 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 836 | |||
| 837 | try test__fixunstfdi(0.0, 0); | 806 | try test__fixunstfdi(0.0, 0); |
| 838 | 807 | ||
| 839 | try test__fixunstfdi(0.5, 0); | 808 | try test__fixunstfdi(0.5, 0); |
| ... | @@ -886,8 +855,6 @@ fn test__fixunstfti(a: f128, expected: u128) !void { | ... | @@ -886,8 +855,6 @@ fn test__fixunstfti(a: f128, expected: u128) !void { |
| 886 | } | 855 | } |
| 887 | 856 | ||
| 888 | test "fixtfti" { | 857 | test "fixtfti" { |
| 889 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 890 | |||
| 891 | try test__fixtfti(-math.floatMax(f128), math.minInt(i128)); | 858 | try test__fixtfti(-math.floatMax(f128), math.minInt(i128)); |
| 892 | 859 | ||
| 893 | try test__fixtfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); | 860 | try test__fixtfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128)); |
| ... | @@ -969,8 +936,6 @@ fn test__fixunshfti(a: f16, expected: u128) !void { | ... | @@ -969,8 +936,6 @@ fn test__fixunshfti(a: f16, expected: u128) !void { |
| 969 | } | 936 | } |
| 970 | 937 | ||
| 971 | test "fixunshfti for f16" { | 938 | test "fixunshfti for f16" { |
| 972 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 973 | |||
| 974 | try test__fixunshfti(math.inf(f16), math.maxInt(u128)); | 939 | try test__fixunshfti(math.inf(f16), math.maxInt(u128)); |
| 975 | try test__fixunshfti(math.floatMax(f16), 65504); | 940 | try test__fixunshfti(math.floatMax(f16), 65504); |
| 976 | } | 941 | } |
lib/compiler_rt/negti2_test.zig-2
| ... | @@ -7,8 +7,6 @@ fn test__negti2(a: i128, expected: i128) !void { | ... | @@ -7,8 +7,6 @@ fn test__negti2(a: i128, expected: i128) !void { |
| 7 | } | 7 | } |
| 8 | 8 | ||
| 9 | test "negti2" { | 9 | test "negti2" { |
| 10 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 11 | |||
| 12 | // TODO ensuring that math.minInt(i128); returns error | 10 | // TODO ensuring that math.minInt(i128); returns error |
| 13 | 11 | ||
| 14 | try test__negti2(-3, 3); | 12 | try test__negti2(-3, 3); |
lib/compiler_rt/powiXf2_test.zig-7
| ... | @@ -34,9 +34,6 @@ fn test__powixf2(a: f80, b: i32, expected: f80) !void { | ... | @@ -34,9 +34,6 @@ fn test__powixf2(a: f80, b: i32, expected: f80) !void { |
| 34 | } | 34 | } |
| 35 | 35 | ||
| 36 | test "powihf2" { | 36 | test "powihf2" { |
| 37 | if (builtin.zig_backend == .stage2_x86_64 and | ||
| 38 | !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest; | ||
| 39 | |||
| 40 | const inf_f16 = math.inf(f16); | 37 | const inf_f16 = math.inf(f16); |
| 41 | try test__powisf2(0, 0, 1); | 38 | try test__powisf2(0, 0, 1); |
| 42 | try test__powihf2(1, 0, 1); | 39 | try test__powihf2(1, 0, 1); |
| ... | @@ -356,8 +353,6 @@ test "powidf2" { | ... | @@ -356,8 +353,6 @@ test "powidf2" { |
| 356 | } | 353 | } |
| 357 | 354 | ||
| 358 | test "powitf2" { | 355 | test "powitf2" { |
| 359 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 360 | |||
| 361 | const inf_f128 = math.inf(f128); | 356 | const inf_f128 = math.inf(f128); |
| 362 | try test__powitf2(0, 0, 1); | 357 | try test__powitf2(0, 0, 1); |
| 363 | try test__powitf2(1, 0, 1); | 358 | try test__powitf2(1, 0, 1); |
| ... | @@ -463,8 +458,6 @@ test "powitf2" { | ... | @@ -463,8 +458,6 @@ test "powitf2" { |
| 463 | } | 458 | } |
| 464 | 459 | ||
| 465 | test "powixf2" { | 460 | test "powixf2" { |
| 466 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 467 | |||
| 468 | const inf_f80 = math.inf(f80); | 461 | const inf_f80 = math.inf(f80); |
| 469 | try test__powixf2(0, 0, 1); | 462 | try test__powixf2(0, 0, 1); |
| 470 | try test__powixf2(1, 0, 1); | 463 | try test__powixf2(1, 0, 1); |
lib/compiler_rt/sin.zig-2
| ... | @@ -140,8 +140,6 @@ pub fn sinl(x: c_longdouble) callconv(.C) c_longdouble { | ... | @@ -140,8 +140,6 @@ pub fn sinl(x: c_longdouble) callconv(.C) c_longdouble { |
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | test "sin32" { | 142 | test "sin32" { |
| 143 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 144 | |||
| 145 | const epsilon = 0.00001; | 143 | const epsilon = 0.00001; |
| 146 | 144 | ||
| 147 | try expect(math.approxEqAbs(f32, sinf(0.0), 0.0, epsilon)); | 145 | try expect(math.approxEqAbs(f32, sinf(0.0), 0.0, epsilon)); |
lib/compiler_rt/suboti4_test.zig-2
| ... | @@ -27,8 +27,6 @@ pub fn simple_suboti4(a: i128, b: i128, overflow: *c_int) i128 { | ... | @@ -27,8 +27,6 @@ pub fn simple_suboti4(a: i128, b: i128, overflow: *c_int) i128 { |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | test "suboti3" { | 29 | test "suboti3" { |
| 30 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 31 | |||
| 32 | const min: i128 = math.minInt(i128); | 30 | const min: i128 = math.minInt(i128); |
| 33 | const max: i128 = math.maxInt(i128); | 31 | const max: i128 = math.maxInt(i128); |
| 34 | var i: i128 = 1; | 32 | var i: i128 = 1; |
lib/compiler_rt/tan.zig-2
| ... | @@ -131,8 +131,6 @@ test "tan" { | ... | @@ -131,8 +131,6 @@ test "tan" { |
| 131 | } | 131 | } |
| 132 | 132 | ||
| 133 | test "tan32" { | 133 | test "tan32" { |
| 134 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 135 | |||
| 136 | const epsilon = 0.00001; | 134 | const epsilon = 0.00001; |
| 137 | 135 | ||
| 138 | try expect(math.approxEqAbs(f32, tanf(0.0), 0.0, epsilon)); | 136 | try expect(math.approxEqAbs(f32, tanf(0.0), 0.0, epsilon)); |
lib/std/Thread/Condition.zig+2
| ... | @@ -440,6 +440,8 @@ test "Condition - multi signal" { | ... | @@ -440,6 +440,8 @@ test "Condition - multi signal" { |
| 440 | return error.SkipZigTest; | 440 | return error.SkipZigTest; |
| 441 | } | 441 | } |
| 442 | 442 | ||
| 443 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 444 | |||
| 443 | const num_threads = 4; | 445 | const num_threads = 4; |
| 444 | const num_iterations = 4; | 446 | const num_iterations = 4; |
| 445 | 447 |
lib/std/crypto/phc_encoding.zig-2
| ... | @@ -363,8 +363,6 @@ test "phc format - hash without salt" { | ... | @@ -363,8 +363,6 @@ test "phc format - hash without salt" { |
| 363 | } | 363 | } |
| 364 | 364 | ||
| 365 | test "phc format - calcSize" { | 365 | test "phc format - calcSize" { |
| 366 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 367 | |||
| 368 | const s = "$scrypt$v=1$ln=15,r=8,p=1$c2FsdHNhbHQ$dGVzdHBhc3M"; | 366 | const s = "$scrypt$v=1$ln=15,r=8,p=1$c2FsdHNhbHQ$dGVzdHBhc3M"; |
| 369 | const v = try deserialize(struct { | 367 | const v = try deserialize(struct { |
| 370 | alg_id: []const u8, | 368 | alg_id: []const u8, |
lib/std/dwarf/expressions.zig-2
| ... | @@ -1054,8 +1054,6 @@ fn isOpcodeRegisterLocation(opcode: u8) bool { | ... | @@ -1054,8 +1054,6 @@ fn isOpcodeRegisterLocation(opcode: u8) bool { |
| 1054 | 1054 | ||
| 1055 | const testing = std.testing; | 1055 | const testing = std.testing; |
| 1056 | test "DWARF expressions" { | 1056 | test "DWARF expressions" { |
| 1057 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 1058 | |||
| 1059 | const allocator = std.testing.allocator; | 1057 | const allocator = std.testing.allocator; |
| 1060 | 1058 | ||
| 1061 | const options = ExpressionOptions{}; | 1059 | const options = ExpressionOptions{}; |
lib/std/fmt.zig-2
| ... | @@ -2435,8 +2435,6 @@ test "float.hexadecimal" { | ... | @@ -2435,8 +2435,6 @@ test "float.hexadecimal" { |
| 2435 | } | 2435 | } |
| 2436 | 2436 | ||
| 2437 | test "float.hexadecimal.precision" { | 2437 | test "float.hexadecimal.precision" { |
| 2438 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 2439 | |||
| 2440 | try expectFmt("f16: 0x1.5p-2", "f16: {x:.1}", .{@as(f16, 1.0 / 3.0)}); | 2438 | try expectFmt("f16: 0x1.5p-2", "f16: {x:.1}", .{@as(f16, 1.0 / 3.0)}); |
| 2441 | try expectFmt("f32: 0x1.555p-2", "f32: {x:.3}", .{@as(f32, 1.0 / 3.0)}); | 2439 | try expectFmt("f32: 0x1.555p-2", "f32: {x:.3}", .{@as(f32, 1.0 / 3.0)}); |
| 2442 | try expectFmt("f64: 0x1.55555p-2", "f64: {x:.5}", .{@as(f64, 1.0 / 3.0)}); | 2440 | try expectFmt("f64: 0x1.55555p-2", "f64: {x:.5}", .{@as(f64, 1.0 / 3.0)}); |
lib/std/hash/auto_hash.zig-21
| ... | @@ -1,6 +1,5 @@ | ... | @@ -1,6 +1,5 @@ |
| 1 | const std = @import("std"); | 1 | const std = @import("std"); |
| 2 | const assert = std.debug.assert; | 2 | const assert = std.debug.assert; |
| 3 | const builtin = @import("builtin"); | ||
| 4 | const mem = std.mem; | 3 | const mem = std.mem; |
| 5 | const meta = std.meta; | 4 | const meta = std.meta; |
| 6 | 5 | ||
| ... | @@ -253,8 +252,6 @@ test "typeContainsSlice" { | ... | @@ -253,8 +252,6 @@ test "typeContainsSlice" { |
| 253 | } | 252 | } |
| 254 | 253 | ||
| 255 | test "hash pointer" { | 254 | test "hash pointer" { |
| 256 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 257 | |||
| 258 | const array = [_]u32{ 123, 123, 123 }; | 255 | const array = [_]u32{ 123, 123, 123 }; |
| 259 | const a = &array[0]; | 256 | const a = &array[0]; |
| 260 | const b = &array[1]; | 257 | const b = &array[1]; |
| ... | @@ -275,8 +272,6 @@ test "hash pointer" { | ... | @@ -275,8 +272,6 @@ test "hash pointer" { |
| 275 | } | 272 | } |
| 276 | 273 | ||
| 277 | test "hash slice shallow" { | 274 | test "hash slice shallow" { |
| 278 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 279 | |||
| 280 | // Allocate one array dynamically so that we're assured it is not merged | 275 | // Allocate one array dynamically so that we're assured it is not merged |
| 281 | // with the other by the optimization passes. | 276 | // with the other by the optimization passes. |
| 282 | const array1 = try std.testing.allocator.create([6]u32); | 277 | const array1 = try std.testing.allocator.create([6]u32); |
| ... | @@ -295,8 +290,6 @@ test "hash slice shallow" { | ... | @@ -295,8 +290,6 @@ test "hash slice shallow" { |
| 295 | } | 290 | } |
| 296 | 291 | ||
| 297 | test "hash slice deep" { | 292 | test "hash slice deep" { |
| 298 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 299 | |||
| 300 | // Allocate one array dynamically so that we're assured it is not merged | 293 | // Allocate one array dynamically so that we're assured it is not merged |
| 301 | // with the other by the optimization passes. | 294 | // with the other by the optimization passes. |
| 302 | const array1 = try std.testing.allocator.create([6]u32); | 295 | const array1 = try std.testing.allocator.create([6]u32); |
| ... | @@ -313,8 +306,6 @@ test "hash slice deep" { | ... | @@ -313,8 +306,6 @@ test "hash slice deep" { |
| 313 | } | 306 | } |
| 314 | 307 | ||
| 315 | test "hash struct deep" { | 308 | test "hash struct deep" { |
| 316 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 317 | |||
| 318 | const Foo = struct { | 309 | const Foo = struct { |
| 319 | a: u32, | 310 | a: u32, |
| 320 | b: u16, | 311 | b: u16, |
| ... | @@ -354,8 +345,6 @@ test "hash struct deep" { | ... | @@ -354,8 +345,6 @@ test "hash struct deep" { |
| 354 | } | 345 | } |
| 355 | 346 | ||
| 356 | test "testHash optional" { | 347 | test "testHash optional" { |
| 357 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 358 | |||
| 359 | const a: ?u32 = 123; | 348 | const a: ?u32 = 123; |
| 360 | const b: ?u32 = null; | 349 | const b: ?u32 = null; |
| 361 | try testing.expectEqual(testHash(a), testHash(@as(u32, 123))); | 350 | try testing.expectEqual(testHash(a), testHash(@as(u32, 123))); |
| ... | @@ -364,8 +353,6 @@ test "testHash optional" { | ... | @@ -364,8 +353,6 @@ test "testHash optional" { |
| 364 | } | 353 | } |
| 365 | 354 | ||
| 366 | test "testHash array" { | 355 | test "testHash array" { |
| 367 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 368 | |||
| 369 | const a = [_]u32{ 1, 2, 3 }; | 356 | const a = [_]u32{ 1, 2, 3 }; |
| 370 | const h = testHash(a); | 357 | const h = testHash(a); |
| 371 | var hasher = Wyhash.init(0); | 358 | var hasher = Wyhash.init(0); |
| ... | @@ -382,8 +369,6 @@ test "testHash multi-dimensional array" { | ... | @@ -382,8 +369,6 @@ test "testHash multi-dimensional array" { |
| 382 | } | 369 | } |
| 383 | 370 | ||
| 384 | test "testHash struct" { | 371 | test "testHash struct" { |
| 385 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 386 | |||
| 387 | const Foo = struct { | 372 | const Foo = struct { |
| 388 | a: u32 = 1, | 373 | a: u32 = 1, |
| 389 | b: u32 = 2, | 374 | b: u32 = 2, |
| ... | @@ -399,8 +384,6 @@ test "testHash struct" { | ... | @@ -399,8 +384,6 @@ test "testHash struct" { |
| 399 | } | 384 | } |
| 400 | 385 | ||
| 401 | test "testHash union" { | 386 | test "testHash union" { |
| 402 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 403 | |||
| 404 | const Foo = union(enum) { | 387 | const Foo = union(enum) { |
| 405 | A: u32, | 388 | A: u32, |
| 406 | B: bool, | 389 | B: bool, |
| ... | @@ -425,8 +408,6 @@ test "testHash union" { | ... | @@ -425,8 +408,6 @@ test "testHash union" { |
| 425 | } | 408 | } |
| 426 | 409 | ||
| 427 | test "testHash vector" { | 410 | test "testHash vector" { |
| 428 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 429 | |||
| 430 | const a: @Vector(4, u32) = [_]u32{ 1, 2, 3, 4 }; | 411 | const a: @Vector(4, u32) = [_]u32{ 1, 2, 3, 4 }; |
| 431 | const b: @Vector(4, u32) = [_]u32{ 1, 2, 3, 5 }; | 412 | const b: @Vector(4, u32) = [_]u32{ 1, 2, 3, 5 }; |
| 432 | try testing.expect(testHash(a) == testHash(a)); | 413 | try testing.expect(testHash(a) == testHash(a)); |
| ... | @@ -439,8 +420,6 @@ test "testHash vector" { | ... | @@ -439,8 +420,6 @@ test "testHash vector" { |
| 439 | } | 420 | } |
| 440 | 421 | ||
| 441 | test "testHash error union" { | 422 | test "testHash error union" { |
| 442 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 443 | |||
| 444 | const Errors = error{Test}; | 423 | const Errors = error{Test}; |
| 445 | const Foo = struct { | 424 | const Foo = struct { |
| 446 | a: u32 = 1, | 425 | a: u32 = 1, |
lib/std/hash/wyhash.zig-2
| ... | @@ -242,8 +242,6 @@ test "smhasher" { | ... | @@ -242,8 +242,6 @@ test "smhasher" { |
| 242 | } | 242 | } |
| 243 | 243 | ||
| 244 | test "iterative api" { | 244 | test "iterative api" { |
| 245 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 246 | |||
| 247 | const Test = struct { | 245 | const Test = struct { |
| 248 | fn do() !void { | 246 | fn do() !void { |
| 249 | try verify.iterativeApi(Wyhash); | 247 | try verify.iterativeApi(Wyhash); |
lib/std/io/bit_reader.zig-2
| ... | @@ -164,8 +164,6 @@ pub fn bitReader( | ... | @@ -164,8 +164,6 @@ pub fn bitReader( |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | test "api coverage" { | 166 | test "api coverage" { |
| 167 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 168 | |||
| 169 | const mem_be = [_]u8{ 0b11001101, 0b00001011 }; | 167 | const mem_be = [_]u8{ 0b11001101, 0b00001011 }; |
| 170 | const mem_le = [_]u8{ 0b00011101, 0b10010101 }; | 168 | const mem_le = [_]u8{ 0b00011101, 0b10010101 }; |
| 171 | 169 |
lib/std/io/test.zig+1-4
| ... | @@ -1,5 +1,4 @@ | ... | @@ -1,5 +1,4 @@ |
| 1 | const std = @import("std"); | 1 | const std = @import("std"); |
| 2 | const builtin = @import("builtin"); | ||
| 3 | const io = std.io; | 2 | const io = std.io; |
| 4 | const meta = std.meta; | 3 | const meta = std.meta; |
| 5 | const trait = std.trait; | 4 | const trait = std.trait; |
| ... | @@ -10,7 +9,7 @@ const expectError = std.testing.expectError; | ... | @@ -10,7 +9,7 @@ const expectError = std.testing.expectError; |
| 10 | const mem = std.mem; | 9 | const mem = std.mem; |
| 11 | const fs = std.fs; | 10 | const fs = std.fs; |
| 12 | const File = std.fs.File; | 11 | const File = std.fs.File; |
| 13 | const native_endian = builtin.target.cpu.arch.endian(); | 12 | const native_endian = @import("builtin").target.cpu.arch.endian(); |
| 14 | 13 | ||
| 15 | const tmpDir = std.testing.tmpDir; | 14 | const tmpDir = std.testing.tmpDir; |
| 16 | 15 | ||
| ... | @@ -61,8 +60,6 @@ test "write a file, read it, then delete it" { | ... | @@ -61,8 +60,6 @@ test "write a file, read it, then delete it" { |
| 61 | } | 60 | } |
| 62 | 61 | ||
| 63 | test "BitStreams with File Stream" { | 62 | test "BitStreams with File Stream" { |
| 64 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 65 | |||
| 66 | var tmp = tmpDir(.{}); | 63 | var tmp = tmpDir(.{}); |
| 67 | defer tmp.cleanup(); | 64 | defer tmp.cleanup(); |
| 68 | 65 |
lib/std/leb128.zig-5
| ... | @@ -1,4 +1,3 @@ | ... | @@ -1,4 +1,3 @@ |
| 1 | const builtin = @import("builtin"); | ||
| 2 | const std = @import("std"); | 1 | const std = @import("std"); |
| 3 | const testing = std.testing; | 2 | const testing = std.testing; |
| 4 | 3 | ||
| ... | @@ -215,8 +214,6 @@ fn test_read_uleb128_seq(comptime T: type, comptime N: usize, encoded: []const u | ... | @@ -215,8 +214,6 @@ fn test_read_uleb128_seq(comptime T: type, comptime N: usize, encoded: []const u |
| 215 | } | 214 | } |
| 216 | 215 | ||
| 217 | test "deserialize signed LEB128" { | 216 | test "deserialize signed LEB128" { |
| 218 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 219 | |||
| 220 | // Truncated | 217 | // Truncated |
| 221 | try testing.expectError(error.EndOfStream, test_read_stream_ileb128(i64, "\x80")); | 218 | try testing.expectError(error.EndOfStream, test_read_stream_ileb128(i64, "\x80")); |
| 222 | 219 | ||
| ... | @@ -363,8 +360,6 @@ test "serialize unsigned LEB128" { | ... | @@ -363,8 +360,6 @@ test "serialize unsigned LEB128" { |
| 363 | } | 360 | } |
| 364 | 361 | ||
| 365 | test "serialize signed LEB128" { | 362 | test "serialize signed LEB128" { |
| 366 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 367 | |||
| 368 | // explicitly test i0 because starting `t` at 0 | 363 | // explicitly test i0 because starting `t` at 0 |
| 369 | // will break the while loop | 364 | // will break the while loop |
| 370 | try test_write_leb128(@as(i0, 0)); | 365 | try test_write_leb128(@as(i0, 0)); |
lib/std/math/big/int_test.zig-4
| ... | @@ -990,8 +990,6 @@ test "big.int mul 0*0" { | ... | @@ -990,8 +990,6 @@ test "big.int mul 0*0" { |
| 990 | } | 990 | } |
| 991 | 991 | ||
| 992 | test "big.int mul large" { | 992 | test "big.int mul large" { |
| 993 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 994 | |||
| 995 | var a = try Managed.initCapacity(testing.allocator, 50); | 993 | var a = try Managed.initCapacity(testing.allocator, 50); |
| 996 | defer a.deinit(); | 994 | defer a.deinit(); |
| 997 | var b = try Managed.initCapacity(testing.allocator, 100); | 995 | var b = try Managed.initCapacity(testing.allocator, 100); |
| ... | @@ -1075,8 +1073,6 @@ test "big.int mulWrap multi-multi signed" { | ... | @@ -1075,8 +1073,6 @@ test "big.int mulWrap multi-multi signed" { |
| 1075 | } | 1073 | } |
| 1076 | 1074 | ||
| 1077 | test "big.int mulWrap large" { | 1075 | test "big.int mulWrap large" { |
| 1078 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 1079 | |||
| 1080 | var a = try Managed.initCapacity(testing.allocator, 50); | 1076 | var a = try Managed.initCapacity(testing.allocator, 50); |
| 1081 | defer a.deinit(); | 1077 | defer a.deinit(); |
| 1082 | var b = try Managed.initCapacity(testing.allocator, 100); | 1078 | var b = try Managed.initCapacity(testing.allocator, 100); |
lib/std/math/ilogb.zig-2
| ... | @@ -108,8 +108,6 @@ test "64" { | ... | @@ -108,8 +108,6 @@ test "64" { |
| 108 | } | 108 | } |
| 109 | 109 | ||
| 110 | test "80" { | 110 | test "80" { |
| 111 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 112 | |||
| 113 | try expect(ilogbX(f80, 0.0) == fp_ilogb0); | 111 | try expect(ilogbX(f80, 0.0) == fp_ilogb0); |
| 114 | try expect(ilogbX(f80, 0.5) == -1); | 112 | try expect(ilogbX(f80, 0.5) == -1); |
| 115 | try expect(ilogbX(f80, 0.8923) == -1); | 113 | try expect(ilogbX(f80, 0.8923) == -1); |
lib/std/math/ldexp.zig-2
| ... | @@ -67,8 +67,6 @@ pub fn ldexp(x: anytype, n: i32) @TypeOf(x) { | ... | @@ -67,8 +67,6 @@ pub fn ldexp(x: anytype, n: i32) @TypeOf(x) { |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | test "math.ldexp" { | 69 | test "math.ldexp" { |
| 70 | if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 71 | |||
| 72 | // subnormals | 70 | // subnormals |
| 73 | try expect(ldexp(@as(f16, 0x1.1FFp14), -14 - 9 - 15) == math.floatTrueMin(f16)); | 71 | try expect(ldexp(@as(f16, 0x1.1FFp14), -14 - 9 - 15) == math.floatTrueMin(f16)); |
| 74 | try expect(ldexp(@as(f32, 0x1.3FFFFFp-1), -126 - 22) == math.floatTrueMin(f32)); | 72 | try expect(ldexp(@as(f32, 0x1.3FFFFFp-1), -126 - 22) == math.floatTrueMin(f32)); |
src/arch/x86_64/CodeGen.zig+997-703
| ... | @@ -115,6 +115,7 @@ const mir_to_air_map_init = if (builtin.mode == .Debug) std.AutoHashMapUnmanaged | ... | @@ -115,6 +115,7 @@ const mir_to_air_map_init = if (builtin.mode == .Debug) std.AutoHashMapUnmanaged |
| 115 | 115 | ||
| 116 | const FrameAddr = struct { index: FrameIndex, off: i32 = 0 }; | 116 | const FrameAddr = struct { index: FrameIndex, off: i32 = 0 }; |
| 117 | const RegisterOffset = struct { reg: Register, off: i32 = 0 }; | 117 | const RegisterOffset = struct { reg: Register, off: i32 = 0 }; |
| 118 | const SymbolOffset = struct { sym: u32, off: i32 = 0 }; | ||
| 118 | 119 | ||
| 119 | const Owner = union(enum) { | 120 | const Owner = union(enum) { |
| 120 | func_index: InternPool.Index, | 121 | func_index: InternPool.Index, |
| ... | @@ -195,9 +196,9 @@ pub const MCValue = union(enum) { | ... | @@ -195,9 +196,9 @@ pub const MCValue = union(enum) { |
| 195 | memory: u64, | 196 | memory: u64, |
| 196 | /// The value is in memory at an address not-yet-allocated by the linker. | 197 | /// The value is in memory at an address not-yet-allocated by the linker. |
| 197 | /// This traditionally corresponds to a relocation emitted in a relocatable object file. | 198 | /// This traditionally corresponds to a relocation emitted in a relocatable object file. |
| 198 | load_symbol: u32, | 199 | load_symbol: SymbolOffset, |
| 199 | /// The address of the memory location not-yet-allocated by the linker. | 200 | /// The address of the memory location not-yet-allocated by the linker. |
| 200 | lea_symbol: u32, | 201 | lea_symbol: SymbolOffset, |
| 201 | /// The value is in memory at a constant offset from the address in a register. | 202 | /// The value is in memory at a constant offset from the address in a register. |
| 202 | indirect: RegisterOffset, | 203 | indirect: RegisterOffset, |
| 203 | /// The value is in memory. | 204 | /// The value is in memory. |
| ... | @@ -315,7 +316,7 @@ pub const MCValue = union(enum) { | ... | @@ -315,7 +316,7 @@ pub const MCValue = union(enum) { |
| 315 | .load_got => |sym_index| .{ .lea_got = sym_index }, | 316 | .load_got => |sym_index| .{ .lea_got = sym_index }, |
| 316 | .load_tlv => |sym_index| .{ .lea_tlv = sym_index }, | 317 | .load_tlv => |sym_index| .{ .lea_tlv = sym_index }, |
| 317 | .load_frame => |frame_addr| .{ .lea_frame = frame_addr }, | 318 | .load_frame => |frame_addr| .{ .lea_frame = frame_addr }, |
| 318 | .load_symbol => |sym_index| .{ .lea_symbol = sym_index }, | 319 | .load_symbol => |sym_off| .{ .lea_symbol = sym_off }, |
| 319 | }; | 320 | }; |
| 320 | } | 321 | } |
| 321 | 322 | ||
| ... | @@ -387,7 +388,7 @@ pub const MCValue = union(enum) { | ... | @@ -387,7 +388,7 @@ pub const MCValue = union(enum) { |
| 387 | }; | 388 | }; |
| 388 | } | 389 | } |
| 389 | 390 | ||
| 390 | fn mem(mcv: MCValue, ptr_size: Memory.PtrSize) Memory { | 391 | fn mem(mcv: MCValue, size: Memory.Size) Memory { |
| 391 | return switch (mcv) { | 392 | return switch (mcv) { |
| 392 | .none, | 393 | .none, |
| 393 | .unreach, | 394 | .unreach, |
| ... | @@ -411,18 +412,27 @@ pub const MCValue = union(enum) { | ... | @@ -411,18 +412,27 @@ pub const MCValue = union(enum) { |
| 411 | .load_symbol, | 412 | .load_symbol, |
| 412 | .lea_symbol, | 413 | .lea_symbol, |
| 413 | => unreachable, | 414 | => unreachable, |
| 414 | .memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |small_addr| | 415 | .memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |small_addr| .{ |
| 415 | Memory.sib(ptr_size, .{ .base = .{ .reg = .ds }, .disp = small_addr }) | 416 | .base = .{ .reg = .ds }, |
| 416 | else | 417 | .mod = .{ .rm = .{ |
| 417 | Memory.moffs(.ds, addr), | 418 | .size = size, |
| 418 | .indirect => |reg_off| Memory.sib(ptr_size, .{ | 419 | .disp = small_addr, |
| 420 | } }, | ||
| 421 | } else .{ .base = .{ .reg = .ds }, .mod = .{ .off = addr } }, | ||
| 422 | .indirect => |reg_off| .{ | ||
| 419 | .base = .{ .reg = reg_off.reg }, | 423 | .base = .{ .reg = reg_off.reg }, |
| 420 | .disp = reg_off.off, | 424 | .mod = .{ .rm = .{ |
| 421 | }), | 425 | .size = size, |
| 422 | .load_frame => |frame_addr| Memory.sib(ptr_size, .{ | 426 | .disp = reg_off.off, |
| 427 | } }, | ||
| 428 | }, | ||
| 429 | .load_frame => |frame_addr| .{ | ||
| 423 | .base = .{ .frame = frame_addr.index }, | 430 | .base = .{ .frame = frame_addr.index }, |
| 424 | .disp = frame_addr.off, | 431 | .mod = .{ .rm = .{ |
| 425 | }), | 432 | .size = size, |
| 433 | .disp = frame_addr.off, | ||
| 434 | } }, | ||
| 435 | }, | ||
| 426 | }; | 436 | }; |
| 427 | } | 437 | } |
| 428 | 438 | ||
| ... | @@ -442,6 +452,8 @@ pub const MCValue = union(enum) { | ... | @@ -442,6 +452,8 @@ pub const MCValue = union(enum) { |
| 442 | .register_overflow => |pl| try writer.print("{s}:{s}", .{ | 452 | .register_overflow => |pl| try writer.print("{s}:{s}", .{ |
| 443 | @tagName(pl.eflags), @tagName(pl.reg), | 453 | @tagName(pl.eflags), @tagName(pl.reg), |
| 444 | }), | 454 | }), |
| 455 | .load_symbol => |pl| try writer.print("[{} + 0x{x}]", .{ pl.sym, pl.off }), | ||
| 456 | .lea_symbol => |pl| try writer.print("{} + 0x{x}", .{ pl.sym, pl.off }), | ||
| 445 | .indirect => |pl| try writer.print("[{s} + 0x{x}]", .{ @tagName(pl.reg), pl.off }), | 457 | .indirect => |pl| try writer.print("[{s} + 0x{x}]", .{ @tagName(pl.reg), pl.off }), |
| 446 | .load_direct => |pl| try writer.print("[direct:{d}]", .{pl}), | 458 | .load_direct => |pl| try writer.print("[direct:{d}]", .{pl}), |
| 447 | .lea_direct => |pl| try writer.print("direct:{d}", .{pl}), | 459 | .lea_direct => |pl| try writer.print("direct:{d}", .{pl}), |
| ... | @@ -453,8 +465,6 @@ pub const MCValue = union(enum) { | ... | @@ -453,8 +465,6 @@ pub const MCValue = union(enum) { |
| 453 | .lea_frame => |pl| try writer.print("{} + 0x{x}", .{ pl.index, pl.off }), | 465 | .lea_frame => |pl| try writer.print("{} + 0x{x}", .{ pl.index, pl.off }), |
| 454 | .reserved_frame => |pl| try writer.print("(dead:{})", .{pl}), | 466 | .reserved_frame => |pl| try writer.print("(dead:{})", .{pl}), |
| 455 | .air_ref => |pl| try writer.print("(air:0x{x})", .{@intFromEnum(pl)}), | 467 | .air_ref => |pl| try writer.print("(air:0x{x})", .{@intFromEnum(pl)}), |
| 456 | .load_symbol => |pl| try writer.print("[symbol:{d}]", .{pl}), | ||
| 457 | .lea_symbol => |pl| try writer.print("symbol:{d}", .{pl}), | ||
| 458 | } | 468 | } |
| 459 | } | 469 | } |
| 460 | }; | 470 | }; |
| ... | @@ -888,7 +898,6 @@ pub fn generate( | ... | @@ -888,7 +898,6 @@ pub fn generate( |
| 888 | .cc = cc, | 898 | .cc = cc, |
| 889 | .src_loc = src_loc, | 899 | .src_loc = src_loc, |
| 890 | }, | 900 | }, |
| 891 | .bin_file = bin_file, | ||
| 892 | .debug_output = debug_output, | 901 | .debug_output = debug_output, |
| 893 | .code = code, | 902 | .code = code, |
| 894 | .prev_di_pc = 0, | 903 | .prev_di_pc = 0, |
| ... | @@ -976,7 +985,6 @@ pub fn generateLazy( | ... | @@ -976,7 +985,6 @@ pub fn generateLazy( |
| 976 | .cc = abi.resolveCallingConvention(.Unspecified, function.target.*), | 985 | .cc = abi.resolveCallingConvention(.Unspecified, function.target.*), |
| 977 | .src_loc = src_loc, | 986 | .src_loc = src_loc, |
| 978 | }, | 987 | }, |
| 979 | .bin_file = bin_file, | ||
| 980 | .debug_output = debug_output, | 988 | .debug_output = debug_output, |
| 981 | .code = code, | 989 | .code = code, |
| 982 | .prev_di_pc = undefined, // no debug info yet | 990 | .prev_di_pc = undefined, // no debug info yet |
| ... | @@ -1139,7 +1147,7 @@ fn addExtraAssumeCapacity(self: *Self, extra: anytype) u32 { | ... | @@ -1139,7 +1147,7 @@ fn addExtraAssumeCapacity(self: *Self, extra: anytype) u32 { |
| 1139 | inline for (fields) |field| { | 1147 | inline for (fields) |field| { |
| 1140 | self.mir_extra.appendAssumeCapacity(switch (field.type) { | 1148 | self.mir_extra.appendAssumeCapacity(switch (field.type) { |
| 1141 | u32 => @field(extra, field.name), | 1149 | u32 => @field(extra, field.name), |
| 1142 | i32 => @bitCast(@field(extra, field.name)), | 1150 | i32, Mir.Memory.Info => @bitCast(@field(extra, field.name)), |
| 1143 | else => @compileError("bad field type: " ++ field.name ++ ": " ++ @typeName(field.type)), | 1151 | else => @compileError("bad field type: " ++ field.name ++ ": " ++ @typeName(field.type)), |
| 1144 | }); | 1152 | }); |
| 1145 | } | 1153 | } |
| ... | @@ -1178,17 +1186,9 @@ fn asmCmovccRegisterMemory(self: *Self, cc: Condition, reg: Register, m: Memory) | ... | @@ -1178,17 +1186,9 @@ fn asmCmovccRegisterMemory(self: *Self, cc: Condition, reg: Register, m: Memory) |
| 1178 | .nz_or_p => .pseudo, | 1186 | .nz_or_p => .pseudo, |
| 1179 | }, | 1187 | }, |
| 1180 | .ops = switch (cc) { | 1188 | .ops = switch (cc) { |
| 1181 | else => switch (m) { | 1189 | else => .rm, |
| 1182 | .sib => .rm_sib, | ||
| 1183 | .rip => .rm_rip, | ||
| 1184 | else => unreachable, | ||
| 1185 | }, | ||
| 1186 | .z_and_np => unreachable, | 1190 | .z_and_np => unreachable, |
| 1187 | .nz_or_p => switch (m) { | 1191 | .nz_or_p => .pseudo_cmov_nz_or_p_rm, |
| 1188 | .sib => .pseudo_cmov_nz_or_p_rm_sib, | ||
| 1189 | .rip => .pseudo_cmov_nz_or_p_rm_rip, | ||
| 1190 | else => unreachable, | ||
| 1191 | }, | ||
| 1192 | }, | 1192 | }, |
| 1193 | .data = .{ .rx = .{ | 1193 | .data = .{ .rx = .{ |
| 1194 | .fixes = switch (cc) { | 1194 | .fixes = switch (cc) { |
| ... | @@ -1197,11 +1197,7 @@ fn asmCmovccRegisterMemory(self: *Self, cc: Condition, reg: Register, m: Memory) | ... | @@ -1197,11 +1197,7 @@ fn asmCmovccRegisterMemory(self: *Self, cc: Condition, reg: Register, m: Memory) |
| 1197 | .nz_or_p => ._, | 1197 | .nz_or_p => ._, |
| 1198 | }, | 1198 | }, |
| 1199 | .r1 = reg, | 1199 | .r1 = reg, |
| 1200 | .payload = switch (m) { | 1200 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1201 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1202 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1203 | else => unreachable, | ||
| 1204 | }, | ||
| 1205 | } }, | 1201 | } }, |
| 1206 | }); | 1202 | }); |
| 1207 | } | 1203 | } |
| ... | @@ -1231,32 +1227,16 @@ fn asmSetccRegister(self: *Self, cc: Condition, reg: Register) !void { | ... | @@ -1231,32 +1227,16 @@ fn asmSetccRegister(self: *Self, cc: Condition, reg: Register) !void { |
| 1231 | } | 1227 | } |
| 1232 | 1228 | ||
| 1233 | fn asmSetccMemory(self: *Self, cc: Condition, m: Memory) !void { | 1229 | fn asmSetccMemory(self: *Self, cc: Condition, m: Memory) !void { |
| 1234 | const payload = switch (m) { | 1230 | const payload = try self.addExtra(Mir.Memory.encode(m)); |
| 1235 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1236 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1237 | else => unreachable, | ||
| 1238 | }; | ||
| 1239 | _ = try self.addInst(.{ | 1231 | _ = try self.addInst(.{ |
| 1240 | .tag = switch (cc) { | 1232 | .tag = switch (cc) { |
| 1241 | else => .set, | 1233 | else => .set, |
| 1242 | .z_and_np, .nz_or_p => .pseudo, | 1234 | .z_and_np, .nz_or_p => .pseudo, |
| 1243 | }, | 1235 | }, |
| 1244 | .ops = switch (cc) { | 1236 | .ops = switch (cc) { |
| 1245 | else => switch (m) { | 1237 | else => .m, |
| 1246 | .sib => .m_sib, | 1238 | .z_and_np => .pseudo_set_z_and_np_m, |
| 1247 | .rip => .m_rip, | 1239 | .nz_or_p => .pseudo_set_nz_or_p_m, |
| 1248 | else => unreachable, | ||
| 1249 | }, | ||
| 1250 | .z_and_np => switch (m) { | ||
| 1251 | .sib => .pseudo_set_z_and_np_m_sib, | ||
| 1252 | .rip => .pseudo_set_z_and_np_m_rip, | ||
| 1253 | else => unreachable, | ||
| 1254 | }, | ||
| 1255 | .nz_or_p => switch (m) { | ||
| 1256 | .sib => .pseudo_set_nz_or_p_m_sib, | ||
| 1257 | .rip => .pseudo_set_nz_or_p_m_rip, | ||
| 1258 | else => unreachable, | ||
| 1259 | }, | ||
| 1260 | }, | 1240 | }, |
| 1261 | .data = switch (cc) { | 1241 | .data = switch (cc) { |
| 1262 | else => .{ .x = .{ | 1242 | else => .{ .x = .{ |
| ... | @@ -1504,20 +1484,12 @@ fn asmRegisterRegisterMemory( | ... | @@ -1504,20 +1484,12 @@ fn asmRegisterRegisterMemory( |
| 1504 | ) !void { | 1484 | ) !void { |
| 1505 | _ = try self.addInst(.{ | 1485 | _ = try self.addInst(.{ |
| 1506 | .tag = tag[1], | 1486 | .tag = tag[1], |
| 1507 | .ops = switch (m) { | 1487 | .ops = .rrm, |
| 1508 | .sib => .rrm_sib, | ||
| 1509 | .rip => .rrm_rip, | ||
| 1510 | else => unreachable, | ||
| 1511 | }, | ||
| 1512 | .data = .{ .rrx = .{ | 1488 | .data = .{ .rrx = .{ |
| 1513 | .fixes = tag[0], | 1489 | .fixes = tag[0], |
| 1514 | .r1 = reg1, | 1490 | .r1 = reg1, |
| 1515 | .r2 = reg2, | 1491 | .r2 = reg2, |
| 1516 | .payload = switch (m) { | 1492 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1517 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1518 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1519 | else => unreachable, | ||
| 1520 | }, | ||
| 1521 | } }, | 1493 | } }, |
| 1522 | }); | 1494 | }); |
| 1523 | } | 1495 | } |
| ... | @@ -1525,18 +1497,10 @@ fn asmRegisterRegisterMemory( | ... | @@ -1525,18 +1497,10 @@ fn asmRegisterRegisterMemory( |
| 1525 | fn asmMemory(self: *Self, tag: Mir.Inst.FixedTag, m: Memory) !void { | 1497 | fn asmMemory(self: *Self, tag: Mir.Inst.FixedTag, m: Memory) !void { |
| 1526 | _ = try self.addInst(.{ | 1498 | _ = try self.addInst(.{ |
| 1527 | .tag = tag[1], | 1499 | .tag = tag[1], |
| 1528 | .ops = switch (m) { | 1500 | .ops = .m, |
| 1529 | .sib => .m_sib, | ||
| 1530 | .rip => .m_rip, | ||
| 1531 | else => unreachable, | ||
| 1532 | }, | ||
| 1533 | .data = .{ .x = .{ | 1501 | .data = .{ .x = .{ |
| 1534 | .fixes = tag[0], | 1502 | .fixes = tag[0], |
| 1535 | .payload = switch (m) { | 1503 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1536 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1537 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1538 | else => unreachable, | ||
| 1539 | }, | ||
| 1540 | } }, | 1504 | } }, |
| 1541 | }); | 1505 | }); |
| 1542 | } | 1506 | } |
| ... | @@ -1544,19 +1508,11 @@ fn asmMemory(self: *Self, tag: Mir.Inst.FixedTag, m: Memory) !void { | ... | @@ -1544,19 +1508,11 @@ fn asmMemory(self: *Self, tag: Mir.Inst.FixedTag, m: Memory) !void { |
| 1544 | fn asmRegisterMemory(self: *Self, tag: Mir.Inst.FixedTag, reg: Register, m: Memory) !void { | 1508 | fn asmRegisterMemory(self: *Self, tag: Mir.Inst.FixedTag, reg: Register, m: Memory) !void { |
| 1545 | _ = try self.addInst(.{ | 1509 | _ = try self.addInst(.{ |
| 1546 | .tag = tag[1], | 1510 | .tag = tag[1], |
| 1547 | .ops = switch (m) { | 1511 | .ops = .rm, |
| 1548 | .sib => .rm_sib, | ||
| 1549 | .rip => .rm_rip, | ||
| 1550 | else => unreachable, | ||
| 1551 | }, | ||
| 1552 | .data = .{ .rx = .{ | 1512 | .data = .{ .rx = .{ |
| 1553 | .fixes = tag[0], | 1513 | .fixes = tag[0], |
| 1554 | .r1 = reg, | 1514 | .r1 = reg, |
| 1555 | .payload = switch (m) { | 1515 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1556 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1557 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1558 | else => unreachable, | ||
| 1559 | }, | ||
| 1560 | } }, | 1516 | } }, |
| 1561 | }); | 1517 | }); |
| 1562 | } | 1518 | } |
| ... | @@ -1574,20 +1530,12 @@ fn asmRegisterMemoryImmediate( | ... | @@ -1574,20 +1530,12 @@ fn asmRegisterMemoryImmediate( |
| 1574 | }) |small_imm| { | 1530 | }) |small_imm| { |
| 1575 | _ = try self.addInst(.{ | 1531 | _ = try self.addInst(.{ |
| 1576 | .tag = tag[1], | 1532 | .tag = tag[1], |
| 1577 | .ops = switch (m) { | 1533 | .ops = .rmi, |
| 1578 | .sib => .rmi_sib, | ||
| 1579 | .rip => .rmi_rip, | ||
| 1580 | else => unreachable, | ||
| 1581 | }, | ||
| 1582 | .data = .{ .rix = .{ | 1534 | .data = .{ .rix = .{ |
| 1583 | .fixes = tag[0], | 1535 | .fixes = tag[0], |
| 1584 | .r1 = reg, | 1536 | .r1 = reg, |
| 1585 | .i = small_imm, | 1537 | .i = small_imm, |
| 1586 | .payload = switch (m) { | 1538 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1587 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1588 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1589 | else => unreachable, | ||
| 1590 | }, | ||
| 1591 | } }, | 1539 | } }, |
| 1592 | }); | 1540 | }); |
| 1593 | } else { | 1541 | } else { |
| ... | @@ -1595,23 +1543,12 @@ fn asmRegisterMemoryImmediate( | ... | @@ -1595,23 +1543,12 @@ fn asmRegisterMemoryImmediate( |
| 1595 | .signed => |s| @bitCast(s), | 1543 | .signed => |s| @bitCast(s), |
| 1596 | .unsigned => unreachable, | 1544 | .unsigned => unreachable, |
| 1597 | } }); | 1545 | } }); |
| 1598 | assert(payload + 1 == switch (m) { | 1546 | assert(payload + 1 == try self.addExtra(Mir.Memory.encode(m))); |
| 1599 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1600 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1601 | else => unreachable, | ||
| 1602 | }); | ||
| 1603 | _ = try self.addInst(.{ | 1547 | _ = try self.addInst(.{ |
| 1604 | .tag = tag[1], | 1548 | .tag = tag[1], |
| 1605 | .ops = switch (m) { | 1549 | .ops = switch (imm) { |
| 1606 | .sib => switch (imm) { | 1550 | .signed => .rmi_s, |
| 1607 | .signed => .rmi_sib_s, | 1551 | .unsigned => .rmi_u, |
| 1608 | .unsigned => .rmi_sib_u, | ||
| 1609 | }, | ||
| 1610 | .rip => switch (imm) { | ||
| 1611 | .signed => .rmi_rip_s, | ||
| 1612 | .unsigned => .rmi_rip_u, | ||
| 1613 | }, | ||
| 1614 | else => unreachable, | ||
| 1615 | }, | 1552 | }, |
| 1616 | .data = .{ .rx = .{ | 1553 | .data = .{ .rx = .{ |
| 1617 | .fixes = tag[0], | 1554 | .fixes = tag[0], |
| ... | @@ -1632,21 +1569,13 @@ fn asmRegisterRegisterMemoryImmediate( | ... | @@ -1632,21 +1569,13 @@ fn asmRegisterRegisterMemoryImmediate( |
| 1632 | ) !void { | 1569 | ) !void { |
| 1633 | _ = try self.addInst(.{ | 1570 | _ = try self.addInst(.{ |
| 1634 | .tag = tag[1], | 1571 | .tag = tag[1], |
| 1635 | .ops = switch (m) { | 1572 | .ops = .rrmi, |
| 1636 | .sib => .rrmi_sib, | ||
| 1637 | .rip => .rrmi_rip, | ||
| 1638 | else => unreachable, | ||
| 1639 | }, | ||
| 1640 | .data = .{ .rrix = .{ | 1573 | .data = .{ .rrix = .{ |
| 1641 | .fixes = tag[0], | 1574 | .fixes = tag[0], |
| 1642 | .r1 = reg1, | 1575 | .r1 = reg1, |
| 1643 | .r2 = reg2, | 1576 | .r2 = reg2, |
| 1644 | .i = @intCast(imm.unsigned), | 1577 | .i = @intCast(imm.unsigned), |
| 1645 | .payload = switch (m) { | 1578 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1646 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1647 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1648 | else => unreachable, | ||
| 1649 | }, | ||
| 1650 | } }, | 1579 | } }, |
| 1651 | }); | 1580 | }); |
| 1652 | } | 1581 | } |
| ... | @@ -1654,19 +1583,11 @@ fn asmRegisterRegisterMemoryImmediate( | ... | @@ -1654,19 +1583,11 @@ fn asmRegisterRegisterMemoryImmediate( |
| 1654 | fn asmMemoryRegister(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, reg: Register) !void { | 1583 | fn asmMemoryRegister(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, reg: Register) !void { |
| 1655 | _ = try self.addInst(.{ | 1584 | _ = try self.addInst(.{ |
| 1656 | .tag = tag[1], | 1585 | .tag = tag[1], |
| 1657 | .ops = switch (m) { | 1586 | .ops = .mr, |
| 1658 | .sib => .mr_sib, | ||
| 1659 | .rip => .mr_rip, | ||
| 1660 | else => unreachable, | ||
| 1661 | }, | ||
| 1662 | .data = .{ .rx = .{ | 1587 | .data = .{ .rx = .{ |
| 1663 | .fixes = tag[0], | 1588 | .fixes = tag[0], |
| 1664 | .r1 = reg, | 1589 | .r1 = reg, |
| 1665 | .payload = switch (m) { | 1590 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1666 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1667 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1668 | else => unreachable, | ||
| 1669 | }, | ||
| 1670 | } }, | 1591 | } }, |
| 1671 | }); | 1592 | }); |
| 1672 | } | 1593 | } |
| ... | @@ -1676,23 +1597,12 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immed | ... | @@ -1676,23 +1597,12 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immed |
| 1676 | .signed => |s| @bitCast(s), | 1597 | .signed => |s| @bitCast(s), |
| 1677 | .unsigned => |u| @intCast(u), | 1598 | .unsigned => |u| @intCast(u), |
| 1678 | } }); | 1599 | } }); |
| 1679 | assert(payload + 1 == switch (m) { | 1600 | assert(payload + 1 == try self.addExtra(Mir.Memory.encode(m))); |
| 1680 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1681 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1682 | else => unreachable, | ||
| 1683 | }); | ||
| 1684 | _ = try self.addInst(.{ | 1601 | _ = try self.addInst(.{ |
| 1685 | .tag = tag[1], | 1602 | .tag = tag[1], |
| 1686 | .ops = switch (m) { | 1603 | .ops = switch (imm) { |
| 1687 | .sib => switch (imm) { | 1604 | .signed => .mi_s, |
| 1688 | .signed => .mi_sib_s, | 1605 | .unsigned => .mi_u, |
| 1689 | .unsigned => .mi_sib_u, | ||
| 1690 | }, | ||
| 1691 | .rip => switch (imm) { | ||
| 1692 | .signed => .mi_rip_s, | ||
| 1693 | .unsigned => .mi_rip_u, | ||
| 1694 | }, | ||
| 1695 | else => unreachable, | ||
| 1696 | }, | 1606 | }, |
| 1697 | .data = .{ .x = .{ | 1607 | .data = .{ .x = .{ |
| 1698 | .fixes = tag[0], | 1608 | .fixes = tag[0], |
| ... | @@ -1710,20 +1620,12 @@ fn asmMemoryRegisterRegister( | ... | @@ -1710,20 +1620,12 @@ fn asmMemoryRegisterRegister( |
| 1710 | ) !void { | 1620 | ) !void { |
| 1711 | _ = try self.addInst(.{ | 1621 | _ = try self.addInst(.{ |
| 1712 | .tag = tag[1], | 1622 | .tag = tag[1], |
| 1713 | .ops = switch (m) { | 1623 | .ops = .mrr, |
| 1714 | .sib => .mrr_sib, | ||
| 1715 | .rip => .mrr_rip, | ||
| 1716 | else => unreachable, | ||
| 1717 | }, | ||
| 1718 | .data = .{ .rrx = .{ | 1624 | .data = .{ .rrx = .{ |
| 1719 | .fixes = tag[0], | 1625 | .fixes = tag[0], |
| 1720 | .r1 = reg1, | 1626 | .r1 = reg1, |
| 1721 | .r2 = reg2, | 1627 | .r2 = reg2, |
| 1722 | .payload = switch (m) { | 1628 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1723 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1724 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1725 | else => unreachable, | ||
| 1726 | }, | ||
| 1727 | } }, | 1629 | } }, |
| 1728 | }); | 1630 | }); |
| 1729 | } | 1631 | } |
| ... | @@ -1737,20 +1639,12 @@ fn asmMemoryRegisterImmediate( | ... | @@ -1737,20 +1639,12 @@ fn asmMemoryRegisterImmediate( |
| 1737 | ) !void { | 1639 | ) !void { |
| 1738 | _ = try self.addInst(.{ | 1640 | _ = try self.addInst(.{ |
| 1739 | .tag = tag[1], | 1641 | .tag = tag[1], |
| 1740 | .ops = switch (m) { | 1642 | .ops = .mri, |
| 1741 | .sib => .mri_sib, | ||
| 1742 | .rip => .mri_rip, | ||
| 1743 | else => unreachable, | ||
| 1744 | }, | ||
| 1745 | .data = .{ .rix = .{ | 1643 | .data = .{ .rix = .{ |
| 1746 | .fixes = tag[0], | 1644 | .fixes = tag[0], |
| 1747 | .r1 = reg, | 1645 | .r1 = reg, |
| 1748 | .i = @intCast(imm.unsigned), | 1646 | .i = @intCast(imm.unsigned), |
| 1749 | .payload = switch (m) { | 1647 | .payload = try self.addExtra(Mir.Memory.encode(m)), |
| 1750 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), | ||
| 1751 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 1752 | else => unreachable, | ||
| 1753 | }, | ||
| 1754 | } }, | 1648 | } }, |
| 1755 | }); | 1649 | }); |
| 1756 | } | 1650 | } |
| ... | @@ -1916,13 +1810,16 @@ fn gen(self: *Self) InnerError!void { | ... | @@ -1916,13 +1810,16 @@ fn gen(self: *Self) InnerError!void { |
| 1916 | if (need_frame_align or need_stack_adjust) { | 1810 | if (need_frame_align or need_stack_adjust) { |
| 1917 | self.mir_instructions.set(backpatch_stack_dealloc, .{ | 1811 | self.mir_instructions.set(backpatch_stack_dealloc, .{ |
| 1918 | .tag = .lea, | 1812 | .tag = .lea, |
| 1919 | .ops = .rm_sib, | 1813 | .ops = .rm, |
| 1920 | .data = .{ .rx = .{ | 1814 | .data = .{ .rx = .{ |
| 1921 | .r1 = .rsp, | 1815 | .r1 = .rsp, |
| 1922 | .payload = try self.addExtra(Mir.MemorySib.encode(Memory.sib(.qword, .{ | 1816 | .payload = try self.addExtra(Mir.Memory.encode(.{ |
| 1923 | .base = .{ .reg = .rbp }, | 1817 | .base = .{ .reg = .rbp }, |
| 1924 | .disp = -frame_layout.save_reg_list.size(), | 1818 | .mod = .{ .rm = .{ |
| 1925 | }))), | 1819 | .size = .qword, |
| 1820 | .disp = -frame_layout.save_reg_list.size(), | ||
| 1821 | } }, | ||
| 1822 | })), | ||
| 1926 | } }, | 1823 | } }, |
| 1927 | }); | 1824 | }); |
| 1928 | } | 1825 | } |
| ... | @@ -3098,14 +2995,14 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3098,14 +2995,14 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void { |
| 3098 | .{ .vp_, .@"and" }, | 2995 | .{ .vp_, .@"and" }, |
| 3099 | dst_reg, | 2996 | dst_reg, |
| 3100 | dst_reg, | 2997 | dst_reg, |
| 3101 | splat_addr_mcv.deref().mem(Memory.PtrSize.fromSize(splat_abi_size)), | 2998 | splat_addr_mcv.deref().mem(Memory.Size.fromSize(splat_abi_size)), |
| 3102 | ); | 2999 | ); |
| 3103 | try self.asmRegisterRegisterRegister(mir_tag, dst_reg, dst_reg, dst_reg); | 3000 | try self.asmRegisterRegisterRegister(mir_tag, dst_reg, dst_reg, dst_reg); |
| 3104 | } else { | 3001 | } else { |
| 3105 | try self.asmRegisterMemory( | 3002 | try self.asmRegisterMemory( |
| 3106 | .{ .p_, .@"and" }, | 3003 | .{ .p_, .@"and" }, |
| 3107 | dst_reg, | 3004 | dst_reg, |
| 3108 | splat_addr_mcv.deref().mem(Memory.PtrSize.fromSize(splat_abi_size)), | 3005 | splat_addr_mcv.deref().mem(Memory.Size.fromSize(splat_abi_size)), |
| 3109 | ); | 3006 | ); |
| 3110 | try self.asmRegisterRegister(mir_tag, dst_reg, dst_reg); | 3007 | try self.asmRegisterRegister(mir_tag, dst_reg, dst_reg); |
| 3111 | } | 3008 | } |
| ... | @@ -3254,7 +3151,7 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3254,7 +3151,7 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { |
| 3254 | const frame_index = try self.allocFrameIndex(FrameAlloc.initType(Type.usize, mod)); | 3151 | const frame_index = try self.allocFrameIndex(FrameAlloc.initType(Type.usize, mod)); |
| 3255 | try self.asmMemoryImmediate( | 3152 | try self.asmMemoryImmediate( |
| 3256 | .{ ._, .mov }, | 3153 | .{ ._, .mov }, |
| 3257 | Memory.sib(.qword, .{ .base = .{ .frame = frame_index } }), | 3154 | .{ .base = .{ .frame = frame_index }, .mod = .{ .rm = .{ .size = .qword } } }, |
| 3258 | Immediate.u(0), | 3155 | Immediate.u(0), |
| 3259 | ); | 3156 | ); |
| 3260 | 3157 | ||
| ... | @@ -3338,9 +3235,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3338,9 +3235,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { |
| 3338 | call_mcv.register_pair[0], | 3235 | call_mcv.register_pair[0], |
| 3339 | call_mcv.register_pair[1], | 3236 | call_mcv.register_pair[1], |
| 3340 | ); | 3237 | ); |
| 3341 | try self.asmSetccMemory(.nz, Memory.sib(.byte, .{ | 3238 | try self.asmSetccMemory(.nz, .{ |
| 3342 | .base = .{ .frame = signed_div_floor_state.frame_index }, | 3239 | .base = .{ .frame = signed_div_floor_state.frame_index }, |
| 3343 | })); | 3240 | .mod = .{ .rm = .{ .size = .byte } }, |
| 3241 | }); | ||
| 3344 | try self.performReloc(signed_div_floor_state.reloc); | 3242 | try self.performReloc(signed_div_floor_state.reloc); |
| 3345 | const dst_mcv = try self.genCall( | 3243 | const dst_mcv = try self.genCall( |
| 3346 | .{ .lib = .{ | 3244 | .{ .lib = .{ |
| ... | @@ -3356,9 +3254,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3356,9 +3254,10 @@ fn airMulDivBinOp(self: *Self, inst: Air.Inst.Index) !void { |
| 3356 | try self.asmRegisterMemory( | 3254 | try self.asmRegisterMemory( |
| 3357 | .{ ._, .sub }, | 3255 | .{ ._, .sub }, |
| 3358 | dst_mcv.register_pair[0], | 3256 | dst_mcv.register_pair[0], |
| 3359 | Memory.sib(.qword, .{ | 3257 | .{ |
| 3360 | .base = .{ .frame = signed_div_floor_state.frame_index }, | 3258 | .base = .{ .frame = signed_div_floor_state.frame_index }, |
| 3361 | }), | 3259 | .mod = .{ .rm = .{ .size = .qword } }, |
| 3260 | }, | ||
| 3362 | ); | 3261 | ); |
| 3363 | try self.asmRegisterImmediate( | 3262 | try self.asmRegisterImmediate( |
| 3364 | .{ ._, .sbb }, | 3263 | .{ ._, .sbb }, |
| ... | @@ -3596,59 +3495,140 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3596,59 +3495,140 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void { |
| 3596 | const mod = self.bin_file.options.module.?; | 3495 | const mod = self.bin_file.options.module.?; |
| 3597 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; | 3496 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; |
| 3598 | const ty = self.typeOf(bin_op.lhs); | 3497 | const ty = self.typeOf(bin_op.lhs); |
| 3599 | if (ty.zigTypeTag(mod) == .Vector or ty.abiSize(mod) > 8) return self.fail( | ||
| 3600 | "TODO implement airMulSat for {}", | ||
| 3601 | .{ty.fmt(mod)}, | ||
| 3602 | ); | ||
| 3603 | 3498 | ||
| 3604 | try self.spillRegisters(&.{ .rax, .rdx }); | 3499 | const result = result: { |
| 3605 | const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx }); | 3500 | if (ty.toIntern() == .i128_type) { |
| 3606 | defer for (reg_locks) |reg_lock| if (reg_lock) |lock| self.register_manager.unlockReg(lock); | 3501 | const ptr_c_int = try mod.singleMutPtrType(Type.c_int); |
| 3502 | const overflow = try self.allocTempRegOrMem(Type.c_int, false); | ||
| 3503 | |||
| 3504 | const dst_mcv = try self.genCall(.{ .lib = .{ | ||
| 3505 | .return_type = .i128_type, | ||
| 3506 | .param_types = &.{ .i128_type, .i128_type, ptr_c_int.toIntern() }, | ||
| 3507 | .callee = "__muloti4", | ||
| 3508 | } }, &.{ Type.i128, Type.i128, ptr_c_int }, &.{ | ||
| 3509 | .{ .air_ref = bin_op.lhs }, | ||
| 3510 | .{ .air_ref = bin_op.rhs }, | ||
| 3511 | overflow.address(), | ||
| 3512 | }); | ||
| 3513 | const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_mcv.register_pair); | ||
| 3514 | defer for (dst_locks) |lock| self.register_manager.unlockReg(lock); | ||
| 3607 | 3515 | ||
| 3608 | const lhs_mcv = try self.resolveInst(bin_op.lhs); | 3516 | const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp); |
| 3609 | const lhs_lock = switch (lhs_mcv) { | 3517 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 3610 | .register => |reg| self.register_manager.lockRegAssumeUnused(reg), | 3518 | defer self.register_manager.unlockReg(tmp_lock); |
| 3611 | else => null, | ||
| 3612 | }; | ||
| 3613 | defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3614 | 3519 | ||
| 3615 | const rhs_mcv = try self.resolveInst(bin_op.rhs); | 3520 | const lhs_mcv = try self.resolveInst(bin_op.lhs); |
| 3616 | const rhs_lock = switch (rhs_mcv) { | 3521 | const mat_lhs_mcv = switch (lhs_mcv) { |
| 3617 | .register => |reg| self.register_manager.lockReg(reg), | 3522 | .load_symbol => mat_lhs_mcv: { |
| 3618 | else => null, | 3523 | // TODO clean this up! |
| 3619 | }; | 3524 | const addr_reg = try self.copyToTmpRegister(Type.usize, lhs_mcv.address()); |
| 3620 | defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock); | 3525 | break :mat_lhs_mcv MCValue{ .indirect = .{ .reg = addr_reg } }; |
| 3526 | }, | ||
| 3527 | else => lhs_mcv, | ||
| 3528 | }; | ||
| 3529 | const mat_lhs_lock = switch (mat_lhs_mcv) { | ||
| 3530 | .indirect => |reg_off| self.register_manager.lockReg(reg_off.reg), | ||
| 3531 | else => null, | ||
| 3532 | }; | ||
| 3533 | defer if (mat_lhs_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3534 | if (mat_lhs_mcv.isMemory()) try self.asmRegisterMemory( | ||
| 3535 | .{ ._, .mov }, | ||
| 3536 | tmp_reg, | ||
| 3537 | mat_lhs_mcv.address().offset(8).deref().mem(.qword), | ||
| 3538 | ) else try self.asmRegisterRegister( | ||
| 3539 | .{ ._, .mov }, | ||
| 3540 | tmp_reg, | ||
| 3541 | mat_lhs_mcv.register_pair[1], | ||
| 3542 | ); | ||
| 3621 | 3543 | ||
| 3622 | const limit_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp); | 3544 | const rhs_mcv = try self.resolveInst(bin_op.rhs); |
| 3623 | const limit_mcv = MCValue{ .register = limit_reg }; | 3545 | const mat_rhs_mcv = switch (rhs_mcv) { |
| 3624 | const limit_lock = self.register_manager.lockRegAssumeUnused(limit_reg); | 3546 | .load_symbol => mat_rhs_mcv: { |
| 3625 | defer self.register_manager.unlockReg(limit_lock); | 3547 | // TODO clean this up! |
| 3548 | const addr_reg = try self.copyToTmpRegister(Type.usize, rhs_mcv.address()); | ||
| 3549 | break :mat_rhs_mcv MCValue{ .indirect = .{ .reg = addr_reg } }; | ||
| 3550 | }, | ||
| 3551 | else => rhs_mcv, | ||
| 3552 | }; | ||
| 3553 | const mat_rhs_lock = switch (mat_rhs_mcv) { | ||
| 3554 | .indirect => |reg_off| self.register_manager.lockReg(reg_off.reg), | ||
| 3555 | else => null, | ||
| 3556 | }; | ||
| 3557 | defer if (mat_rhs_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3558 | if (mat_rhs_mcv.isMemory()) try self.asmRegisterMemory( | ||
| 3559 | .{ ._, .xor }, | ||
| 3560 | tmp_reg, | ||
| 3561 | mat_rhs_mcv.address().offset(8).deref().mem(.qword), | ||
| 3562 | ) else try self.asmRegisterRegister( | ||
| 3563 | .{ ._, .xor }, | ||
| 3564 | tmp_reg, | ||
| 3565 | mat_rhs_mcv.register_pair[1], | ||
| 3566 | ); | ||
| 3626 | 3567 | ||
| 3627 | const reg_bits = self.regBitSize(ty); | 3568 | try self.asmRegisterImmediate(.{ ._r, .sa }, tmp_reg, Immediate.u(63)); |
| 3628 | const cc: Condition = if (ty.isSignedInt(mod)) cc: { | 3569 | try self.asmRegister(.{ ._, .not }, tmp_reg); |
| 3629 | try self.genSetReg(limit_reg, ty, lhs_mcv); | 3570 | try self.asmMemoryImmediate(.{ ._, .cmp }, overflow.mem(.dword), Immediate.s(0)); |
| 3630 | try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv); | 3571 | try self.freeValue(overflow); |
| 3631 | try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 }); | 3572 | try self.asmCmovccRegisterRegister(.ne, dst_mcv.register_pair[0], tmp_reg); |
| 3632 | try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{ | 3573 | try self.asmRegisterImmediate(.{ ._c, .bt }, tmp_reg, Immediate.u(63)); |
| 3633 | .immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1, | 3574 | try self.asmCmovccRegisterRegister(.ne, dst_mcv.register_pair[1], tmp_reg); |
| 3634 | }); | 3575 | break :result dst_mcv; |
| 3635 | break :cc .o; | 3576 | } |
| 3636 | } else cc: { | ||
| 3637 | try self.genSetReg(limit_reg, ty, .{ | ||
| 3638 | .immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits), | ||
| 3639 | }); | ||
| 3640 | break :cc .c; | ||
| 3641 | }; | ||
| 3642 | 3577 | ||
| 3643 | const dst_mcv = try self.genMulDivBinOp(.mul, inst, ty, ty, lhs_mcv, rhs_mcv); | 3578 | if (ty.zigTypeTag(mod) == .Vector or ty.abiSize(mod) > 8) return self.fail( |
| 3644 | const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2); | 3579 | "TODO implement airMulSat for {}", |
| 3645 | try self.asmCmovccRegisterRegister( | 3580 | .{ty.fmt(mod)}, |
| 3646 | cc, | 3581 | ); |
| 3647 | registerAlias(dst_mcv.register, cmov_abi_size), | ||
| 3648 | registerAlias(limit_reg, cmov_abi_size), | ||
| 3649 | ); | ||
| 3650 | 3582 | ||
| 3651 | return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none }); | 3583 | try self.spillRegisters(&.{ .rax, .rdx }); |
| 3584 | const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx }); | ||
| 3585 | defer for (reg_locks) |reg_lock| if (reg_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3586 | |||
| 3587 | const lhs_mcv = try self.resolveInst(bin_op.lhs); | ||
| 3588 | const lhs_lock = switch (lhs_mcv) { | ||
| 3589 | .register => |reg| self.register_manager.lockRegAssumeUnused(reg), | ||
| 3590 | else => null, | ||
| 3591 | }; | ||
| 3592 | defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3593 | |||
| 3594 | const rhs_mcv = try self.resolveInst(bin_op.rhs); | ||
| 3595 | const rhs_lock = switch (rhs_mcv) { | ||
| 3596 | .register => |reg| self.register_manager.lockReg(reg), | ||
| 3597 | else => null, | ||
| 3598 | }; | ||
| 3599 | defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock); | ||
| 3600 | |||
| 3601 | const limit_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp); | ||
| 3602 | const limit_mcv = MCValue{ .register = limit_reg }; | ||
| 3603 | const limit_lock = self.register_manager.lockRegAssumeUnused(limit_reg); | ||
| 3604 | defer self.register_manager.unlockReg(limit_lock); | ||
| 3605 | |||
| 3606 | const reg_bits = self.regBitSize(ty); | ||
| 3607 | const cc: Condition = if (ty.isSignedInt(mod)) cc: { | ||
| 3608 | try self.genSetReg(limit_reg, ty, lhs_mcv); | ||
| 3609 | try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv); | ||
| 3610 | try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 }); | ||
| 3611 | try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{ | ||
| 3612 | .immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1, | ||
| 3613 | }); | ||
| 3614 | break :cc .o; | ||
| 3615 | } else cc: { | ||
| 3616 | try self.genSetReg(limit_reg, ty, .{ | ||
| 3617 | .immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits), | ||
| 3618 | }); | ||
| 3619 | break :cc .c; | ||
| 3620 | }; | ||
| 3621 | |||
| 3622 | const dst_mcv = try self.genMulDivBinOp(.mul, inst, ty, ty, lhs_mcv, rhs_mcv); | ||
| 3623 | const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2); | ||
| 3624 | try self.asmCmovccRegisterRegister( | ||
| 3625 | cc, | ||
| 3626 | registerAlias(dst_mcv.register, cmov_abi_size), | ||
| 3627 | registerAlias(limit_reg, cmov_abi_size), | ||
| 3628 | ); | ||
| 3629 | break :result dst_mcv; | ||
| 3630 | }; | ||
| 3631 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); | ||
| 3652 | } | 3632 | } |
| 3653 | 3633 | ||
| 3654 | fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void { | 3634 | fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void { |
| ... | @@ -3802,10 +3782,13 @@ fn genSetFrameTruncatedOverflowCompare( | ... | @@ -3802,10 +3782,13 @@ fn genSetFrameTruncatedOverflowCompare( |
| 3802 | const ty = tuple_ty.structFieldType(0, mod); | 3782 | const ty = tuple_ty.structFieldType(0, mod); |
| 3803 | const int_info = ty.intInfo(mod); | 3783 | const int_info = ty.intInfo(mod); |
| 3804 | 3784 | ||
| 3805 | const hi_limb_bits = (int_info.bits - 1) % 64 + 1; | 3785 | const hi_bits = (int_info.bits - 1) % 64 + 1; |
| 3806 | const hi_limb_ty = try mod.intType(int_info.signedness, hi_limb_bits); | 3786 | const hi_ty = try mod.intType(int_info.signedness, hi_bits); |
| 3787 | |||
| 3788 | const limb_bits: u16 = @intCast(if (int_info.bits <= 64) self.regBitSize(ty) else 64); | ||
| 3789 | const limb_ty = try mod.intType(int_info.signedness, limb_bits); | ||
| 3807 | 3790 | ||
| 3808 | const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_limb_bits); | 3791 | const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_bits); |
| 3809 | 3792 | ||
| 3810 | const temp_regs = | 3793 | const temp_regs = |
| 3811 | try self.register_manager.allocRegs(3, .{ null, null, null }, abi.RegisterClass.gp); | 3794 | try self.register_manager.allocRegs(3, .{ null, null, null }, abi.RegisterClass.gp); |
| ... | @@ -3821,9 +3804,9 @@ fn genSetFrameTruncatedOverflowCompare( | ... | @@ -3821,9 +3804,9 @@ fn genSetFrameTruncatedOverflowCompare( |
| 3821 | src_mcv.address().offset(int_info.bits / 64 * 8).deref() | 3804 | src_mcv.address().offset(int_info.bits / 64 * 8).deref() |
| 3822 | else | 3805 | else |
| 3823 | src_mcv; | 3806 | src_mcv; |
| 3824 | try self.genSetReg(scratch_reg, hi_limb_ty, hi_limb_mcv); | 3807 | try self.genSetReg(scratch_reg, limb_ty, hi_limb_mcv); |
| 3825 | try self.truncateRegister(hi_limb_ty, scratch_reg); | 3808 | try self.truncateRegister(hi_ty, scratch_reg); |
| 3826 | try self.genBinOpMir(.{ ._, .cmp }, hi_limb_ty, .{ .register = scratch_reg }, hi_limb_mcv); | 3809 | try self.genBinOpMir(.{ ._, .cmp }, limb_ty, .{ .register = scratch_reg }, hi_limb_mcv); |
| 3827 | 3810 | ||
| 3828 | const eq_reg = temp_regs[2]; | 3811 | const eq_reg = temp_regs[2]; |
| 3829 | if (overflow_cc) |_| { | 3812 | if (overflow_cc) |_| { |
| ... | @@ -3841,7 +3824,7 @@ fn genSetFrameTruncatedOverflowCompare( | ... | @@ -3841,7 +3824,7 @@ fn genSetFrameTruncatedOverflowCompare( |
| 3841 | try self.genSetMem( | 3824 | try self.genSetMem( |
| 3842 | .{ .frame = frame_index }, | 3825 | .{ .frame = frame_index }, |
| 3843 | payload_off + hi_limb_off, | 3826 | payload_off + hi_limb_off, |
| 3844 | hi_limb_ty, | 3827 | limb_ty, |
| 3845 | .{ .register = scratch_reg }, | 3828 | .{ .register = scratch_reg }, |
| 3846 | ); | 3829 | ); |
| 3847 | try self.genSetMem( | 3830 | try self.genSetMem( |
| ... | @@ -3891,7 +3874,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -3891,7 +3874,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void { |
| 3891 | ); | 3874 | ); |
| 3892 | try self.asmMemoryImmediate( | 3875 | try self.asmMemoryImmediate( |
| 3893 | .{ ._, .cmp }, | 3876 | .{ ._, .cmp }, |
| 3894 | overflow.mem(self.memPtrSize(Type.c_int)), | 3877 | overflow.mem(self.memSize(Type.c_int)), |
| 3895 | Immediate.s(0), | 3878 | Immediate.s(0), |
| 3896 | ); | 3879 | ); |
| 3897 | try self.genSetMem( | 3880 | try self.genSetMem( |
| ... | @@ -4123,7 +4106,7 @@ fn genIntMulDivOpMir(self: *Self, tag: Mir.Inst.FixedTag, ty: Type, lhs: MCValue | ... | @@ -4123,7 +4106,7 @@ fn genIntMulDivOpMir(self: *Self, tag: Mir.Inst.FixedTag, ty: Type, lhs: MCValue |
| 4123 | .register => |reg| try self.asmRegister(tag, registerAlias(reg, abi_size)), | 4106 | .register => |reg| try self.asmRegister(tag, registerAlias(reg, abi_size)), |
| 4124 | .memory, .indirect, .load_frame => try self.asmMemory( | 4107 | .memory, .indirect, .load_frame => try self.asmMemory( |
| 4125 | tag, | 4108 | tag, |
| 4126 | mat_rhs.mem(Memory.PtrSize.fromSize(abi_size)), | 4109 | mat_rhs.mem(Memory.Size.fromSize(abi_size)), |
| 4127 | ), | 4110 | ), |
| 4128 | else => unreachable, | 4111 | else => unreachable, |
| 4129 | } | 4112 | } |
| ... | @@ -4185,6 +4168,7 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa | ... | @@ -4185,6 +4168,7 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa |
| 4185 | } | 4168 | } |
| 4186 | 4169 | ||
| 4187 | fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void { | 4170 | fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void { |
| 4171 | const mod = self.bin_file.options.module.?; | ||
| 4188 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; | 4172 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; |
| 4189 | 4173 | ||
| 4190 | try self.spillRegisters(&.{.rcx}); | 4174 | try self.spillRegisters(&.{.rcx}); |
| ... | @@ -4196,9 +4180,38 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4196,9 +4180,38 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void { |
| 4196 | const lhs_ty = self.typeOf(bin_op.lhs); | 4180 | const lhs_ty = self.typeOf(bin_op.lhs); |
| 4197 | const rhs_ty = self.typeOf(bin_op.rhs); | 4181 | const rhs_ty = self.typeOf(bin_op.rhs); |
| 4198 | 4182 | ||
| 4199 | const result = try self.genShiftBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty); | 4183 | const dst_mcv = try self.genShiftBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty); |
| 4184 | switch (tag) { | ||
| 4185 | .shr, .shr_exact, .shl_exact => {}, | ||
| 4186 | .shl => switch (dst_mcv) { | ||
| 4187 | .register => |dst_reg| try self.truncateRegister(lhs_ty, dst_reg), | ||
| 4188 | .register_pair => |dst_regs| try self.truncateRegister(lhs_ty, dst_regs[1]), | ||
| 4189 | .load_frame => |frame_addr| { | ||
| 4190 | const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp); | ||
| 4191 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | ||
| 4192 | defer self.register_manager.unlockReg(tmp_lock); | ||
| 4200 | 4193 | ||
| 4201 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); | 4194 | const lhs_bits: u31 = @intCast(lhs_ty.bitSize(mod)); |
| 4195 | const tmp_ty = if (lhs_bits > 64) Type.usize else lhs_ty; | ||
| 4196 | const off = frame_addr.off + lhs_bits / 64 * 8; | ||
| 4197 | try self.genSetReg( | ||
| 4198 | tmp_reg, | ||
| 4199 | tmp_ty, | ||
| 4200 | .{ .load_frame = .{ .index = frame_addr.index, .off = off } }, | ||
| 4201 | ); | ||
| 4202 | try self.truncateRegister(lhs_ty, tmp_reg); | ||
| 4203 | try self.genSetMem( | ||
| 4204 | .{ .frame = frame_addr.index }, | ||
| 4205 | off, | ||
| 4206 | tmp_ty, | ||
| 4207 | .{ .register = tmp_reg }, | ||
| 4208 | ); | ||
| 4209 | }, | ||
| 4210 | else => {}, | ||
| 4211 | }, | ||
| 4212 | else => unreachable, | ||
| 4213 | } | ||
| 4214 | return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none }); | ||
| 4202 | } | 4215 | } |
| 4203 | 4216 | ||
| 4204 | fn airShlSat(self: *Self, inst: Air.Inst.Index) !void { | 4217 | fn airShlSat(self: *Self, inst: Air.Inst.Index) !void { |
| ... | @@ -4360,10 +4373,13 @@ fn airUnwrapErrUnionErrPtr(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4360,10 +4373,13 @@ fn airUnwrapErrUnionErrPtr(self: *Self, inst: Air.Inst.Index) !void { |
| 4360 | try self.asmRegisterMemory( | 4373 | try self.asmRegisterMemory( |
| 4361 | .{ ._, .mov }, | 4374 | .{ ._, .mov }, |
| 4362 | registerAlias(dst_reg, err_abi_size), | 4375 | registerAlias(dst_reg, err_abi_size), |
| 4363 | Memory.sib(Memory.PtrSize.fromSize(err_abi_size), .{ | 4376 | .{ |
| 4364 | .base = .{ .reg = src_reg }, | 4377 | .base = .{ .reg = src_reg }, |
| 4365 | .disp = err_off, | 4378 | .mod = .{ .rm = .{ |
| 4366 | }), | 4379 | .size = Memory.Size.fromSize(err_abi_size), |
| 4380 | .disp = err_off, | ||
| 4381 | } }, | ||
| 4382 | }, | ||
| 4367 | ); | 4383 | ); |
| 4368 | 4384 | ||
| 4369 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); | 4385 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); |
| ... | @@ -4398,10 +4414,13 @@ fn airErrUnionPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4398,10 +4414,13 @@ fn airErrUnionPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void { |
| 4398 | const err_abi_size: u32 = @intCast(err_ty.abiSize(mod)); | 4414 | const err_abi_size: u32 = @intCast(err_ty.abiSize(mod)); |
| 4399 | try self.asmMemoryImmediate( | 4415 | try self.asmMemoryImmediate( |
| 4400 | .{ ._, .mov }, | 4416 | .{ ._, .mov }, |
| 4401 | Memory.sib(Memory.PtrSize.fromSize(err_abi_size), .{ | 4417 | .{ |
| 4402 | .base = .{ .reg = src_reg }, | 4418 | .base = .{ .reg = src_reg }, |
| 4403 | .disp = err_off, | 4419 | .mod = .{ .rm = .{ |
| 4404 | }), | 4420 | .size = Memory.Size.fromSize(err_abi_size), |
| 4421 | .disp = err_off, | ||
| 4422 | } }, | ||
| 4423 | }, | ||
| 4405 | Immediate.u(0), | 4424 | Immediate.u(0), |
| 4406 | ); | 4425 | ); |
| 4407 | 4426 | ||
| ... | @@ -4420,7 +4439,10 @@ fn airErrUnionPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4420,7 +4439,10 @@ fn airErrUnionPayloadPtrSet(self: *Self, inst: Air.Inst.Index) !void { |
| 4420 | try self.asmRegisterMemory( | 4439 | try self.asmRegisterMemory( |
| 4421 | .{ ._, .lea }, | 4440 | .{ ._, .lea }, |
| 4422 | registerAlias(dst_reg, dst_abi_size), | 4441 | registerAlias(dst_reg, dst_abi_size), |
| 4423 | Memory.sib(.qword, .{ .base = .{ .reg = src_reg }, .disp = pl_off }), | 4442 | .{ |
| 4443 | .base = .{ .reg = src_reg }, | ||
| 4444 | .mod = .{ .rm = .{ .size = .qword, .disp = pl_off } }, | ||
| 4445 | }, | ||
| 4424 | ); | 4446 | ); |
| 4425 | break :result .{ .register = dst_reg }; | 4447 | break :result .{ .register = dst_reg }; |
| 4426 | }; | 4448 | }; |
| ... | @@ -4542,10 +4564,13 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4542,10 +4564,13 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void { |
| 4542 | 4564 | ||
| 4543 | .load_frame => |frame_addr| try self.asmMemoryImmediate( | 4565 | .load_frame => |frame_addr| try self.asmMemoryImmediate( |
| 4544 | .{ ._, .mov }, | 4566 | .{ ._, .mov }, |
| 4545 | Memory.sib(.byte, .{ | 4567 | .{ |
| 4546 | .base = .{ .frame = frame_addr.index }, | 4568 | .base = .{ .frame = frame_addr.index }, |
| 4547 | .disp = frame_addr.off + pl_abi_size, | 4569 | .mod = .{ .rm = .{ |
| 4548 | }), | 4570 | .size = .byte, |
| 4571 | .disp = frame_addr.off + pl_abi_size, | ||
| 4572 | } }, | ||
| 4573 | }, | ||
| 4549 | Immediate.u(1), | 4574 | Immediate.u(1), |
| 4550 | ), | 4575 | ), |
| 4551 | } | 4576 | } |
| ... | @@ -4618,18 +4643,24 @@ fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4618,18 +4643,24 @@ fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void { |
| 4618 | fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void { | 4643 | fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void { |
| 4619 | const ty_op = self.air.instructions.items(.data)[inst].ty_op; | 4644 | const ty_op = self.air.instructions.items(.data)[inst].ty_op; |
| 4620 | 4645 | ||
| 4621 | const operand = try self.resolveInst(ty_op.operand); | 4646 | const result: MCValue = result: { |
| 4622 | const dst_mcv: MCValue = blk: { | 4647 | const src_mcv = try self.resolveInst(ty_op.operand); |
| 4623 | switch (operand) { | 4648 | switch (src_mcv) { |
| 4624 | .load_frame => |frame_addr| break :blk .{ .load_frame = .{ | 4649 | .load_frame => |frame_addr| { |
| 4625 | .index = frame_addr.index, | 4650 | const len_mcv: MCValue = .{ .load_frame = .{ |
| 4626 | .off = frame_addr.off + 8, | 4651 | .index = frame_addr.index, |
| 4627 | } }, | 4652 | .off = frame_addr.off + 8, |
| 4628 | else => return self.fail("TODO implement slice_len for {}", .{operand}), | 4653 | } }; |
| 4654 | if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result len_mcv; | ||
| 4655 | |||
| 4656 | const dst_mcv = try self.allocRegOrMem(inst, true); | ||
| 4657 | try self.genCopy(Type.usize, dst_mcv, len_mcv); | ||
| 4658 | break :result dst_mcv; | ||
| 4659 | }, | ||
| 4660 | else => return self.fail("TODO implement slice_len for {}", .{src_mcv}), | ||
| 4629 | } | 4661 | } |
| 4630 | }; | 4662 | }; |
| 4631 | 4663 | return self.finishAir(inst, result, .{ ty_op.operand, .none, .none }); | |
| 4632 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); | ||
| 4633 | } | 4664 | } |
| 4634 | 4665 | ||
| 4635 | fn airPtrSliceLenPtr(self: *Self, inst: Air.Inst.Index) !void { | 4666 | fn airPtrSliceLenPtr(self: *Self, inst: Air.Inst.Index) !void { |
| ... | @@ -4658,10 +4689,10 @@ fn airPtrSliceLenPtr(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4658,10 +4689,10 @@ fn airPtrSliceLenPtr(self: *Self, inst: Air.Inst.Index) !void { |
| 4658 | try self.asmRegisterMemory( | 4689 | try self.asmRegisterMemory( |
| 4659 | .{ ._, .lea }, | 4690 | .{ ._, .lea }, |
| 4660 | registerAlias(dst_reg, dst_abi_size), | 4691 | registerAlias(dst_reg, dst_abi_size), |
| 4661 | Memory.sib(.qword, .{ | 4692 | .{ |
| 4662 | .base = .{ .reg = src_reg }, | 4693 | .base = .{ .reg = src_reg }, |
| 4663 | .disp = @divExact(self.target.ptrBitWidth(), 8), | 4694 | .mod = .{ .rm = .{ .size = .qword, .disp = 8 } }, |
| 4664 | }), | 4695 | }, |
| 4665 | ); | 4696 | ); |
| 4666 | 4697 | ||
| 4667 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); | 4698 | return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none }); |
| ... | @@ -4791,13 +4822,16 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -4791,13 +4822,16 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void { |
| 4791 | try self.asmRegisterMemory( | 4822 | try self.asmRegisterMemory( |
| 4792 | .{ ._, .lea }, | 4823 | .{ ._, .lea }, |
| 4793 | addr_reg, | 4824 | addr_reg, |
| 4794 | Memory.sib(.qword, .{ .base = .{ .frame = frame_index } }), | 4825 | .{ .base = .{ .frame = frame_index }, .mod = .{ .rm = .{ .size = .qword } } }, |
| 4795 | ); | 4826 | ); |
| 4796 | }, | 4827 | }, |
| 4797 | .load_frame => |frame_addr| try self.asmRegisterMemory( | 4828 | .load_frame => |frame_addr| try self.asmRegisterMemory( |
| 4798 | .{ ._, .lea }, | 4829 | .{ ._, .lea }, |
| 4799 | addr_reg, | 4830 | addr_reg, |
| 4800 | Memory.sib(.qword, .{ .base = .{ .frame = frame_addr.index }, .disp = frame_addr.off }), | 4831 | .{ |
| 4832 | .base = .{ .frame = frame_addr.index }, | ||
| 4833 | .mod = .{ .rm = .{ .size = .qword, .disp = frame_addr.off } }, | ||
| 4834 | }, | ||
| 4801 | ), | 4835 | ), |
| 4802 | .memory, | 4836 | .memory, |
| 4803 | .load_symbol, | 4837 | .load_symbol, |
| ... | @@ -5019,13 +5053,19 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -5019,13 +5053,19 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void { |
| 5019 | const has_lzcnt = self.hasFeature(.lzcnt); | 5053 | const has_lzcnt = self.hasFeature(.lzcnt); |
| 5020 | if (src_bits > 64 and !has_lzcnt) { | 5054 | if (src_bits > 64 and !has_lzcnt) { |
| 5021 | var callee_buf: ["__clz?i2".len]u8 = undefined; | 5055 | var callee_buf: ["__clz?i2".len]u8 = undefined; |
| 5022 | break :result try self.genCall(.{ .lib = .{ | 5056 | const result = try self.genCall(.{ .lib = .{ |
| 5023 | .return_type = .i32_type, | 5057 | .return_type = .i32_type, |
| 5024 | .param_types = &.{src_ty.toIntern()}, | 5058 | .param_types = &.{src_ty.toIntern()}, |
| 5025 | .callee = std.fmt.bufPrint(&callee_buf, "__clz{c}i2", .{ | 5059 | .callee = std.fmt.bufPrint(&callee_buf, "__clz{c}i2", .{ |
| 5026 | intCompilerRtAbiName(src_bits), | 5060 | intCompilerRtAbiName(src_bits), |
| 5027 | }) catch unreachable, | 5061 | }) catch unreachable, |
| 5028 | } }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }}); | 5062 | } }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }}); |
| 5063 | if (src_bits < 128) try self.asmRegisterImmediate( | ||
| 5064 | .{ ._, .sub }, | ||
| 5065 | result.register, | ||
| 5066 | Immediate.u(128 - src_bits), | ||
| 5067 | ); | ||
| 5068 | break :result result; | ||
| 5029 | } | 5069 | } |
| 5030 | 5070 | ||
| 5031 | const src_mcv = try self.resolveInst(ty_op.operand); | 5071 | const src_mcv = try self.resolveInst(ty_op.operand); |
| ... | @@ -5610,10 +5650,14 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -5610,10 +5650,14 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { |
| 5610 | try self.asmRegisterMemory( | 5650 | try self.asmRegisterMemory( |
| 5611 | .{ ._, .lea }, | 5651 | .{ ._, .lea }, |
| 5612 | if (limb_abi_size > 4) tmp.to64() else tmp.to32(), | 5652 | if (limb_abi_size > 4) tmp.to64() else tmp.to32(), |
| 5613 | Memory.sib(.qword, .{ | 5653 | .{ |
| 5614 | .base = .{ .reg = dst.to64() }, | 5654 | .base = .{ .reg = dst.to64() }, |
| 5615 | .scale_index = .{ .index = tmp.to64(), .scale = 1 << 2 }, | 5655 | .mod = .{ .rm = .{ |
| 5616 | }), | 5656 | .size = .qword, |
| 5657 | .index = tmp.to64(), | ||
| 5658 | .scale = .@"4", | ||
| 5659 | } }, | ||
| 5660 | }, | ||
| 5617 | ); | 5661 | ); |
| 5618 | // tmp = temp3 = ((temp2 >> 2) & 0x33...33) + ((temp2 & 0x33...33) << 2) | 5662 | // tmp = temp3 = ((temp2 >> 2) & 0x33...33) + ((temp2 & 0x33...33) << 2) |
| 5619 | try self.asmRegisterRegister(.{ ._, .mov }, dst, tmp); | 5663 | try self.asmRegisterRegister(.{ ._, .mov }, dst, tmp); |
| ... | @@ -5633,10 +5677,14 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -5633,10 +5677,14 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void { |
| 5633 | try self.asmRegisterMemory( | 5677 | try self.asmRegisterMemory( |
| 5634 | .{ ._, .lea }, | 5678 | .{ ._, .lea }, |
| 5635 | if (limb_abi_size > 4) dst.to64() else dst.to32(), | 5679 | if (limb_abi_size > 4) dst.to64() else dst.to32(), |
| 5636 | Memory.sib(.qword, .{ | 5680 | .{ |
| 5637 | .base = .{ .reg = tmp.to64() }, | 5681 | .base = .{ .reg = tmp.to64() }, |
| 5638 | .scale_index = .{ .index = dst.to64(), .scale = 1 << 1 }, | 5682 | .mod = .{ .rm = .{ |
| 5639 | }), | 5683 | .size = .qword, |
| 5684 | .index = dst.to64(), | ||
| 5685 | .scale = .@"2", | ||
| 5686 | } }, | ||
| 5687 | }, | ||
| 5640 | ); | 5688 | ); |
| 5641 | // dst = ((temp3 >> 1) & 0x55...55) + ((temp3 & 0x55...55) << 1) | 5689 | // dst = ((temp3 >> 1) & 0x55...55) + ((temp3 & 0x55...55) << 1) |
| 5642 | } | 5690 | } |
| ... | @@ -5668,7 +5716,7 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type) | ... | @@ -5668,7 +5716,7 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type) |
| 5668 | defer if (src_lock) |lock| self.register_manager.unlockReg(lock); | 5716 | defer if (src_lock) |lock| self.register_manager.unlockReg(lock); |
| 5669 | 5717 | ||
| 5670 | const dst_mcv: MCValue = .{ .register = .st0 }; | 5718 | const dst_mcv: MCValue = .{ .register = .st0 }; |
| 5671 | if (std.meta.eql(src_mcv, dst_mcv) and self.reuseOperand(inst, operand, 0, src_mcv)) | 5719 | if (!std.meta.eql(src_mcv, dst_mcv) or !self.reuseOperand(inst, operand, 0, src_mcv)) |
| 5672 | try self.register_manager.getReg(.st0, inst); | 5720 | try self.register_manager.getReg(.st0, inst); |
| 5673 | 5721 | ||
| 5674 | try self.genCopy(ty, dst_mcv, src_mcv); | 5722 | try self.genCopy(ty, dst_mcv, src_mcv); |
| ... | @@ -5713,12 +5761,13 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type) | ... | @@ -5713,12 +5761,13 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type) |
| 5713 | .abs => try vec_ty.maxInt(mod, vec_ty), | 5761 | .abs => try vec_ty.maxInt(mod, vec_ty), |
| 5714 | else => unreachable, | 5762 | else => unreachable, |
| 5715 | } }); | 5763 | } }); |
| 5716 | const sign_mem = if (sign_mcv.isMemory()) | 5764 | const sign_mem: Memory = if (sign_mcv.isMemory()) |
| 5717 | sign_mcv.mem(Memory.PtrSize.fromSize(abi_size)) | 5765 | sign_mcv.mem(Memory.Size.fromSize(abi_size)) |
| 5718 | else | 5766 | else |
| 5719 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ | 5767 | .{ |
| 5720 | .base = .{ .reg = try self.copyToTmpRegister(Type.usize, sign_mcv.address()) }, | 5768 | .base = .{ .reg = try self.copyToTmpRegister(Type.usize, sign_mcv.address()) }, |
| 5721 | }); | 5769 | .mod = .{ .rm = .{ .size = Memory.Size.fromSize(abi_size) } }, |
| 5770 | }; | ||
| 5722 | 5771 | ||
| 5723 | if (self.hasFeature(.avx)) try self.asmRegisterRegisterMemory( | 5772 | if (self.hasFeature(.avx)) try self.asmRegisterRegisterMemory( |
| 5724 | switch (scalar_bits) { | 5773 | switch (scalar_bits) { |
| ... | @@ -5896,7 +5945,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro | ... | @@ -5896,7 +5945,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro |
| 5896 | mir_tag, | 5945 | mir_tag, |
| 5897 | dst_alias, | 5946 | dst_alias, |
| 5898 | dst_alias, | 5947 | dst_alias, |
| 5899 | src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 5948 | src_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 5900 | Immediate.u(@as(u5, @bitCast(mode))), | 5949 | Immediate.u(@as(u5, @bitCast(mode))), |
| 5901 | ) else try self.asmRegisterRegisterRegisterImmediate( | 5950 | ) else try self.asmRegisterRegisterRegisterImmediate( |
| 5902 | mir_tag, | 5951 | mir_tag, |
| ... | @@ -5911,7 +5960,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro | ... | @@ -5911,7 +5960,7 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro |
| 5911 | else => if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate( | 5960 | else => if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate( |
| 5912 | mir_tag, | 5961 | mir_tag, |
| 5913 | dst_alias, | 5962 | dst_alias, |
| 5914 | src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 5963 | src_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 5915 | Immediate.u(@as(u5, @bitCast(mode))), | 5964 | Immediate.u(@as(u5, @bitCast(mode))), |
| 5916 | ) else try self.asmRegisterRegisterImmediate( | 5965 | ) else try self.asmRegisterRegisterImmediate( |
| 5917 | mir_tag, | 5966 | mir_tag, |
| ... | @@ -5951,7 +6000,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -5951,7 +6000,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void { |
| 5951 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( | 6000 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( |
| 5952 | .l, | 6001 | .l, |
| 5953 | registerAlias(dst_mcv.register, cmov_abi_size), | 6002 | registerAlias(dst_mcv.register, cmov_abi_size), |
| 5954 | src_mcv.mem(Memory.PtrSize.fromSize(cmov_abi_size)), | 6003 | src_mcv.mem(Memory.Size.fromSize(cmov_abi_size)), |
| 5955 | ), | 6004 | ), |
| 5956 | else => { | 6005 | else => { |
| 5957 | const val_reg = try self.copyToTmpRegister(ty, src_mcv); | 6006 | const val_reg = try self.copyToTmpRegister(ty, src_mcv); |
| ... | @@ -6051,7 +6100,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6051,7 +6100,7 @@ fn airAbs(self: *Self, inst: Air.Inst.Index) !void { |
| 6051 | if (src_mcv.isMemory()) try self.asmRegisterMemory( | 6100 | if (src_mcv.isMemory()) try self.asmRegisterMemory( |
| 6052 | mir_tag, | 6101 | mir_tag, |
| 6053 | dst_alias, | 6102 | dst_alias, |
| 6054 | src_mcv.mem(self.memPtrSize(ty)), | 6103 | src_mcv.mem(self.memSize(ty)), |
| 6055 | ) else try self.asmRegisterRegister( | 6104 | ) else try self.asmRegisterRegister( |
| 6056 | mir_tag, | 6105 | mir_tag, |
| 6057 | dst_alias, | 6106 | dst_alias, |
| ... | @@ -6157,7 +6206,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6157,7 +6206,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { |
| 6157 | if (src_mcv.isMemory()) try self.asmRegisterMemory( | 6206 | if (src_mcv.isMemory()) try self.asmRegisterMemory( |
| 6158 | .{ .v_ps, .cvtph2 }, | 6207 | .{ .v_ps, .cvtph2 }, |
| 6159 | wide_reg, | 6208 | wide_reg, |
| 6160 | src_mcv.mem(Memory.PtrSize.fromSize( | 6209 | src_mcv.mem(Memory.Size.fromSize( |
| 6161 | @intCast(@divExact(wide_reg.bitSize(), 16)), | 6210 | @intCast(@divExact(wide_reg.bitSize(), 16)), |
| 6162 | )), | 6211 | )), |
| 6163 | ) else try self.asmRegisterRegister( | 6212 | ) else try self.asmRegisterRegister( |
| ... | @@ -6205,7 +6254,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6205,7 +6254,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { |
| 6205 | mir_tag, | 6254 | mir_tag, |
| 6206 | dst_reg, | 6255 | dst_reg, |
| 6207 | dst_reg, | 6256 | dst_reg, |
| 6208 | src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 6257 | src_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 6209 | ) else try self.asmRegisterRegisterRegister( | 6258 | ) else try self.asmRegisterRegisterRegister( |
| 6210 | mir_tag, | 6259 | mir_tag, |
| 6211 | dst_reg, | 6260 | dst_reg, |
| ... | @@ -6218,7 +6267,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6218,7 +6267,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void { |
| 6218 | else => if (src_mcv.isMemory()) try self.asmRegisterMemory( | 6267 | else => if (src_mcv.isMemory()) try self.asmRegisterMemory( |
| 6219 | mir_tag, | 6268 | mir_tag, |
| 6220 | dst_reg, | 6269 | dst_reg, |
| 6221 | src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 6270 | src_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 6222 | ) else try self.asmRegisterRegister( | 6271 | ) else try self.asmRegisterRegister( |
| 6223 | mir_tag, | 6272 | mir_tag, |
| 6224 | dst_reg, | 6273 | dst_reg, |
| ... | @@ -6337,14 +6386,13 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn | ... | @@ -6337,14 +6386,13 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn |
| 6337 | if (val_bit_off < val_extra_bits) val_abi_size else val_abi_size * 2; | 6386 | if (val_bit_off < val_extra_bits) val_abi_size else val_abi_size * 2; |
| 6338 | if (load_abi_size <= 8) { | 6387 | if (load_abi_size <= 8) { |
| 6339 | const load_reg = registerAlias(dst_reg, load_abi_size); | 6388 | const load_reg = registerAlias(dst_reg, load_abi_size); |
| 6340 | try self.asmRegisterMemory( | 6389 | try self.asmRegisterMemory(.{ ._, .mov }, load_reg, .{ |
| 6341 | .{ ._, .mov }, | 6390 | .base = .{ .reg = ptr_reg }, |
| 6342 | load_reg, | 6391 | .mod = .{ .rm = .{ |
| 6343 | Memory.sib(Memory.PtrSize.fromSize(load_abi_size), .{ | 6392 | .size = Memory.Size.fromSize(load_abi_size), |
| 6344 | .base = .{ .reg = ptr_reg }, | ||
| 6345 | .disp = val_byte_off, | 6393 | .disp = val_byte_off, |
| 6346 | }), | 6394 | } }, |
| 6347 | ); | 6395 | }); |
| 6348 | try self.asmRegisterImmediate(.{ ._r, .sh }, load_reg, Immediate.u(val_bit_off)); | 6396 | try self.asmRegisterImmediate(.{ ._r, .sh }, load_reg, Immediate.u(val_bit_off)); |
| 6349 | } else { | 6397 | } else { |
| 6350 | const tmp_reg = | 6398 | const tmp_reg = |
| ... | @@ -6353,22 +6401,20 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn | ... | @@ -6353,22 +6401,20 @@ fn packedLoad(self: *Self, dst_mcv: MCValue, ptr_ty: Type, ptr_mcv: MCValue) Inn |
| 6353 | defer self.register_manager.unlockReg(tmp_lock); | 6401 | defer self.register_manager.unlockReg(tmp_lock); |
| 6354 | 6402 | ||
| 6355 | const dst_alias = registerAlias(dst_reg, val_abi_size); | 6403 | const dst_alias = registerAlias(dst_reg, val_abi_size); |
| 6356 | try self.asmRegisterMemory( | 6404 | try self.asmRegisterMemory(.{ ._, .mov }, dst_alias, .{ |
| 6357 | .{ ._, .mov }, | 6405 | .base = .{ .reg = ptr_reg }, |
| 6358 | dst_alias, | 6406 | .mod = .{ .rm = .{ |
| 6359 | Memory.sib(Memory.PtrSize.fromSize(val_abi_size), .{ | 6407 | .size = Memory.Size.fromSize(val_abi_size), |
| 6360 | .base = .{ .reg = ptr_reg }, | ||
| 6361 | .disp = val_byte_off, | 6408 | .disp = val_byte_off, |
| 6362 | }), | 6409 | } }, |
| 6363 | ); | 6410 | }); |
| 6364 | try self.asmRegisterMemory( | 6411 | try self.asmRegisterMemory(.{ ._, .mov }, tmp_reg, .{ |
| 6365 | .{ ._, .mov }, | 6412 | .base = .{ .reg = ptr_reg }, |
| 6366 | tmp_reg, | 6413 | .mod = .{ .rm = .{ |
| 6367 | Memory.sib(Memory.PtrSize.fromSize(val_abi_size), .{ | 6414 | .size = Memory.Size.fromSize(val_abi_size), |
| 6368 | .base = .{ .reg = ptr_reg }, | ||
| 6369 | .disp = val_byte_off + 1, | 6415 | .disp = val_byte_off + 1, |
| 6370 | }), | 6416 | } }, |
| 6371 | ); | 6417 | }); |
| 6372 | try self.asmRegisterRegisterImmediate( | 6418 | try self.asmRegisterRegisterImmediate( |
| 6373 | .{ ._rd, .sh }, | 6419 | .{ ._rd, .sh }, |
| 6374 | dst_alias, | 6420 | dst_alias, |
| ... | @@ -6480,10 +6526,13 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In | ... | @@ -6480,10 +6526,13 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In |
| 6480 | const part_bit_off = if (limb_i == 0) src_bit_off else 0; | 6526 | const part_bit_off = if (limb_i == 0) src_bit_off else 0; |
| 6481 | const part_bit_size = | 6527 | const part_bit_size = |
| 6482 | @min(src_bit_off + src_bit_size - limb_i * limb_abi_bits, limb_abi_bits) - part_bit_off; | 6528 | @min(src_bit_off + src_bit_size - limb_i * limb_abi_bits, limb_abi_bits) - part_bit_off; |
| 6483 | const limb_mem = Memory.sib(Memory.PtrSize.fromSize(limb_abi_size), .{ | 6529 | const limb_mem: Memory = .{ |
| 6484 | .base = .{ .reg = ptr_reg }, | 6530 | .base = .{ .reg = ptr_reg }, |
| 6485 | .disp = src_byte_off + limb_i * limb_abi_bits, | 6531 | .mod = .{ .rm = .{ |
| 6486 | }); | 6532 | .size = Memory.Size.fromSize(limb_abi_size), |
| 6533 | .disp = src_byte_off + limb_i * limb_abi_bits, | ||
| 6534 | } }, | ||
| 6535 | }; | ||
| 6487 | 6536 | ||
| 6488 | const part_mask = (@as(u64, math.maxInt(u64)) >> @intCast(64 - part_bit_size)) << | 6537 | const part_mask = (@as(u64, math.maxInt(u64)) >> @intCast(64 - part_bit_size)) << |
| 6489 | @intCast(part_bit_off); | 6538 | @intCast(part_bit_off); |
| ... | @@ -6814,7 +6863,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6814,7 +6863,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { |
| 6814 | break :result dst_mcv; | 6863 | break :result dst_mcv; |
| 6815 | } | 6864 | } |
| 6816 | 6865 | ||
| 6817 | const limb_abi_size: u32 = @min(field_abi_size, 8); | 6866 | const limb_abi_size: u31 = @min(field_abi_size, 8); |
| 6818 | const limb_abi_bits = limb_abi_size * 8; | 6867 | const limb_abi_bits = limb_abi_size * 8; |
| 6819 | const field_byte_off: i32 = @intCast(field_off / limb_abi_bits * limb_abi_size); | 6868 | const field_byte_off: i32 = @intCast(field_off / limb_abi_bits * limb_abi_size); |
| 6820 | const field_bit_off = field_off % limb_abi_bits; | 6869 | const field_bit_off = field_off % limb_abi_bits; |
| ... | @@ -6832,14 +6881,13 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6832,14 +6881,13 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { |
| 6832 | if (field_bit_off < field_extra_bits) field_abi_size else field_abi_size * 2; | 6881 | if (field_bit_off < field_extra_bits) field_abi_size else field_abi_size * 2; |
| 6833 | if (load_abi_size <= 8) { | 6882 | if (load_abi_size <= 8) { |
| 6834 | const load_reg = registerAlias(dst_reg, load_abi_size); | 6883 | const load_reg = registerAlias(dst_reg, load_abi_size); |
| 6835 | try self.asmRegisterMemory( | 6884 | try self.asmRegisterMemory(.{ ._, .mov }, load_reg, .{ |
| 6836 | .{ ._, .mov }, | 6885 | .base = .{ .frame = frame_addr.index }, |
| 6837 | load_reg, | 6886 | .mod = .{ .rm = .{ |
| 6838 | Memory.sib(Memory.PtrSize.fromSize(load_abi_size), .{ | 6887 | .size = Memory.Size.fromSize(load_abi_size), |
| 6839 | .base = .{ .frame = frame_addr.index }, | ||
| 6840 | .disp = frame_addr.off + field_byte_off, | 6888 | .disp = frame_addr.off + field_byte_off, |
| 6841 | }), | 6889 | } }, |
| 6842 | ); | 6890 | }); |
| 6843 | try self.asmRegisterImmediate(.{ ._r, .sh }, load_reg, Immediate.u(field_bit_off)); | 6891 | try self.asmRegisterImmediate(.{ ._r, .sh }, load_reg, Immediate.u(field_bit_off)); |
| 6844 | } else { | 6892 | } else { |
| 6845 | const tmp_reg = registerAlias( | 6893 | const tmp_reg = registerAlias( |
| ... | @@ -6853,19 +6901,21 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -6853,19 +6901,21 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void { |
| 6853 | try self.asmRegisterMemory( | 6901 | try self.asmRegisterMemory( |
| 6854 | .{ ._, .mov }, | 6902 | .{ ._, .mov }, |
| 6855 | dst_alias, | 6903 | dst_alias, |
| 6856 | Memory.sib(Memory.PtrSize.fromSize(field_abi_size), .{ | 6904 | .{ |
| 6857 | .base = .{ .frame = frame_addr.index }, | ||
| 6858 | .disp = frame_addr.off + field_byte_off, | ||
| 6859 | }), | ||
| 6860 | ); | ||
| 6861 | try self.asmRegisterMemory( | ||
| 6862 | .{ ._, .mov }, | ||
| 6863 | tmp_reg, | ||
| 6864 | Memory.sib(Memory.PtrSize.fromSize(field_abi_size), .{ | ||
| 6865 | .base = .{ .frame = frame_addr.index }, | 6905 | .base = .{ .frame = frame_addr.index }, |
| 6866 | .disp = frame_addr.off + field_byte_off + @as(i32, @intCast(limb_abi_size)), | 6906 | .mod = .{ .rm = .{ |
| 6867 | }), | 6907 | .size = Memory.Size.fromSize(field_abi_size), |
| 6908 | .disp = frame_addr.off + field_byte_off, | ||
| 6909 | } }, | ||
| 6910 | }, | ||
| 6868 | ); | 6911 | ); |
| 6912 | try self.asmRegisterMemory(.{ ._, .mov }, tmp_reg, .{ | ||
| 6913 | .base = .{ .frame = frame_addr.index }, | ||
| 6914 | .mod = .{ .rm = .{ | ||
| 6915 | .size = Memory.Size.fromSize(field_abi_size), | ||
| 6916 | .disp = frame_addr.off + field_byte_off + limb_abi_size, | ||
| 6917 | } }, | ||
| 6918 | }); | ||
| 6869 | try self.asmRegisterRegisterImmediate( | 6919 | try self.asmRegisterRegisterImmediate( |
| 6870 | .{ ._rd, .sh }, | 6920 | .{ ._rd, .sh }, |
| 6871 | dst_alias, | 6921 | dst_alias, |
| ... | @@ -6998,14 +7048,13 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC | ... | @@ -6998,14 +7048,13 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.FixedTag, dst_ty: Type, dst_mcv: MC |
| 6998 | defer self.register_manager.unlockReg(addr_reg_lock); | 7048 | defer self.register_manager.unlockReg(addr_reg_lock); |
| 6999 | 7049 | ||
| 7000 | try self.genSetReg(addr_reg, Type.usize, dst_mcv.address()); | 7050 | try self.genSetReg(addr_reg, Type.usize, dst_mcv.address()); |
| 7001 | try self.asmMemory( | 7051 | try self.asmMemory(mir_tag, .{ .base = .{ .reg = addr_reg }, .mod = .{ .rm = .{ |
| 7002 | mir_tag, | 7052 | .size = Memory.Size.fromSize(abi_size), |
| 7003 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = .{ .reg = addr_reg } }), | 7053 | } } }); |
| 7004 | ); | ||
| 7005 | }, | 7054 | }, |
| 7006 | .indirect, .load_frame => try self.asmMemory( | 7055 | .indirect, .load_frame => try self.asmMemory( |
| 7007 | mir_tag, | 7056 | mir_tag, |
| 7008 | dst_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 7057 | dst_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 7009 | ), | 7058 | ), |
| 7010 | } | 7059 | } |
| 7011 | } | 7060 | } |
| ... | @@ -7053,25 +7102,34 @@ fn genShiftBinOpMir( | ... | @@ -7053,25 +7102,34 @@ fn genShiftBinOpMir( |
| 7053 | }), | 7102 | }), |
| 7054 | }, | 7103 | }, |
| 7055 | .memory, .indirect, .load_frame => { | 7104 | .memory, .indirect, .load_frame => { |
| 7056 | const lhs_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (lhs_mcv) { | 7105 | const lhs_mem: Memory = switch (lhs_mcv) { |
| 7057 | .memory => |addr| .{ | 7106 | .memory => |addr| .{ |
| 7058 | .base = .{ .reg = .ds }, | 7107 | .base = .{ .reg = .ds }, |
| 7059 | .disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse | 7108 | .mod = .{ .rm = .{ |
| 7060 | return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{ | 7109 | .size = Memory.Size.fromSize(abi_size), |
| 7061 | @tagName(lhs_mcv), | 7110 | .disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse |
| 7062 | @tagName(rhs_mcv), | 7111 | return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{ |
| 7063 | }), | 7112 | @tagName(lhs_mcv), |
| 7113 | @tagName(rhs_mcv), | ||
| 7114 | }), | ||
| 7115 | } }, | ||
| 7064 | }, | 7116 | }, |
| 7065 | .indirect => |reg_off| .{ | 7117 | .indirect => |reg_off| .{ |
| 7066 | .base = .{ .reg = reg_off.reg }, | 7118 | .base = .{ .reg = reg_off.reg }, |
| 7067 | .disp = reg_off.off, | 7119 | .mod = .{ .rm = .{ |
| 7120 | .size = Memory.Size.fromSize(abi_size), | ||
| 7121 | .disp = reg_off.off, | ||
| 7122 | } }, | ||
| 7068 | }, | 7123 | }, |
| 7069 | .load_frame => |frame_addr| .{ | 7124 | .load_frame => |frame_addr| .{ |
| 7070 | .base = .{ .frame = frame_addr.index }, | 7125 | .base = .{ .frame = frame_addr.index }, |
| 7071 | .disp = frame_addr.off, | 7126 | .mod = .{ .rm = .{ |
| 7127 | .size = Memory.Size.fromSize(abi_size), | ||
| 7128 | .disp = frame_addr.off, | ||
| 7129 | } }, | ||
| 7072 | }, | 7130 | }, |
| 7073 | else => unreachable, | 7131 | else => unreachable, |
| 7074 | }); | 7132 | }; |
| 7075 | switch (rhs_mcv) { | 7133 | switch (rhs_mcv) { |
| 7076 | .immediate => |rhs_imm| try self.asmMemoryImmediate( | 7134 | .immediate => |rhs_imm| try self.asmMemoryImmediate( |
| 7077 | tag, | 7135 | tag, |
| ... | @@ -7187,26 +7245,35 @@ fn genShiftBinOpMir( | ... | @@ -7187,26 +7245,35 @@ fn genShiftBinOpMir( |
| 7187 | try self.asmRegisterMemory( | 7245 | try self.asmRegisterMemory( |
| 7188 | .{ ._, .mov }, | 7246 | .{ ._, .mov }, |
| 7189 | tmp_reg, | 7247 | tmp_reg, |
| 7190 | Memory.sib(.qword, .{ | 7248 | .{ |
| 7191 | .base = .{ .frame = dst_frame_addr.index }, | 7249 | .base = .{ .frame = dst_frame_addr.index }, |
| 7192 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7250 | .mod = .{ .rm = .{ |
| 7193 | }), | 7251 | .size = .qword, |
| 7252 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7253 | } }, | ||
| 7254 | }, | ||
| 7194 | ); | 7255 | ); |
| 7195 | try self.asmMemoryRegisterImmediate( | 7256 | try self.asmMemoryRegisterImmediate( |
| 7196 | info.double_tag, | 7257 | info.double_tag, |
| 7197 | Memory.sib(.qword, .{ | 7258 | .{ |
| 7198 | .base = .{ .frame = dst_frame_addr.index }, | 7259 | .base = .{ .frame = dst_frame_addr.index }, |
| 7199 | .disp = dst_frame_addr.off + info.indices[1] * 8, | 7260 | .mod = .{ .rm = .{ |
| 7200 | }), | 7261 | .size = .qword, |
| 7262 | .disp = dst_frame_addr.off + info.indices[1] * 8, | ||
| 7263 | } }, | ||
| 7264 | }, | ||
| 7201 | tmp_reg, | 7265 | tmp_reg, |
| 7202 | Immediate.u(rhs_imm), | 7266 | Immediate.u(rhs_imm), |
| 7203 | ); | 7267 | ); |
| 7204 | try self.asmMemoryImmediate( | 7268 | try self.asmMemoryImmediate( |
| 7205 | tag, | 7269 | tag, |
| 7206 | Memory.sib(.qword, .{ | 7270 | .{ |
| 7207 | .base = .{ .frame = dst_frame_addr.index }, | 7271 | .base = .{ .frame = dst_frame_addr.index }, |
| 7208 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7272 | .mod = .{ .rm = .{ |
| 7209 | }), | 7273 | .size = .qword, |
| 7274 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7275 | } }, | ||
| 7276 | }, | ||
| 7210 | Immediate.u(rhs_imm), | 7277 | Immediate.u(rhs_imm), |
| 7211 | ); | 7278 | ); |
| 7212 | } else { | 7279 | } else { |
| ... | @@ -7214,10 +7281,13 @@ fn genShiftBinOpMir( | ... | @@ -7214,10 +7281,13 @@ fn genShiftBinOpMir( |
| 7214 | try self.asmRegisterMemory( | 7281 | try self.asmRegisterMemory( |
| 7215 | .{ ._, .mov }, | 7282 | .{ ._, .mov }, |
| 7216 | tmp_reg, | 7283 | tmp_reg, |
| 7217 | Memory.sib(.qword, .{ | 7284 | .{ |
| 7218 | .base = .{ .frame = dst_frame_addr.index }, | 7285 | .base = .{ .frame = dst_frame_addr.index }, |
| 7219 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7286 | .mod = .{ .rm = .{ |
| 7220 | }), | 7287 | .size = .qword, |
| 7288 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7289 | } }, | ||
| 7290 | }, | ||
| 7221 | ); | 7291 | ); |
| 7222 | if (rhs_imm > 64) try self.asmRegisterImmediate( | 7292 | if (rhs_imm > 64) try self.asmRegisterImmediate( |
| 7223 | tag, | 7293 | tag, |
| ... | @@ -7226,27 +7296,36 @@ fn genShiftBinOpMir( | ... | @@ -7226,27 +7296,36 @@ fn genShiftBinOpMir( |
| 7226 | ); | 7296 | ); |
| 7227 | try self.asmMemoryRegister( | 7297 | try self.asmMemoryRegister( |
| 7228 | .{ ._, .mov }, | 7298 | .{ ._, .mov }, |
| 7229 | Memory.sib(.qword, .{ | 7299 | .{ |
| 7230 | .base = .{ .frame = dst_frame_addr.index }, | 7300 | .base = .{ .frame = dst_frame_addr.index }, |
| 7231 | .disp = dst_frame_addr.off + info.indices[1] * 8, | 7301 | .mod = .{ .rm = .{ |
| 7232 | }), | 7302 | .size = .qword, |
| 7303 | .disp = dst_frame_addr.off + info.indices[1] * 8, | ||
| 7304 | } }, | ||
| 7305 | }, | ||
| 7233 | tmp_reg, | 7306 | tmp_reg, |
| 7234 | ); | 7307 | ); |
| 7235 | if (tag[0] == ._r and tag[1] == .sa) try self.asmMemoryImmediate( | 7308 | if (tag[0] == ._r and tag[1] == .sa) try self.asmMemoryImmediate( |
| 7236 | tag, | 7309 | tag, |
| 7237 | Memory.sib(.qword, .{ | 7310 | .{ |
| 7238 | .base = .{ .frame = dst_frame_addr.index }, | 7311 | .base = .{ .frame = dst_frame_addr.index }, |
| 7239 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7312 | .mod = .{ .rm = .{ |
| 7240 | }), | 7313 | .size = .qword, |
| 7314 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7315 | } }, | ||
| 7316 | }, | ||
| 7241 | Immediate.u(63), | 7317 | Immediate.u(63), |
| 7242 | ) else { | 7318 | ) else { |
| 7243 | try self.asmRegisterRegister(.{ ._, .xor }, tmp_reg.to32(), tmp_reg.to32()); | 7319 | try self.asmRegisterRegister(.{ ._, .xor }, tmp_reg.to32(), tmp_reg.to32()); |
| 7244 | try self.asmMemoryRegister( | 7320 | try self.asmMemoryRegister( |
| 7245 | .{ ._, .mov }, | 7321 | .{ ._, .mov }, |
| 7246 | Memory.sib(.qword, .{ | 7322 | .{ |
| 7247 | .base = .{ .frame = dst_frame_addr.index }, | 7323 | .base = .{ .frame = dst_frame_addr.index }, |
| 7248 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7324 | .mod = .{ .rm = .{ |
| 7249 | }), | 7325 | .size = .qword, |
| 7326 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7327 | } }, | ||
| 7328 | }, | ||
| 7250 | tmp_reg, | 7329 | tmp_reg, |
| 7251 | ); | 7330 | ); |
| 7252 | } | 7331 | } |
| ... | @@ -7265,18 +7344,24 @@ fn genShiftBinOpMir( | ... | @@ -7265,18 +7344,24 @@ fn genShiftBinOpMir( |
| 7265 | try self.asmRegisterMemory( | 7344 | try self.asmRegisterMemory( |
| 7266 | .{ ._, .mov }, | 7345 | .{ ._, .mov }, |
| 7267 | first_reg, | 7346 | first_reg, |
| 7268 | Memory.sib(.qword, .{ | 7347 | .{ |
| 7269 | .base = .{ .frame = dst_frame_addr.index }, | 7348 | .base = .{ .frame = dst_frame_addr.index }, |
| 7270 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7349 | .mod = .{ .rm = .{ |
| 7271 | }), | 7350 | .size = .qword, |
| 7351 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7352 | } }, | ||
| 7353 | }, | ||
| 7272 | ); | 7354 | ); |
| 7273 | try self.asmRegisterMemory( | 7355 | try self.asmRegisterMemory( |
| 7274 | .{ ._, .mov }, | 7356 | .{ ._, .mov }, |
| 7275 | second_reg, | 7357 | second_reg, |
| 7276 | Memory.sib(.qword, .{ | 7358 | .{ |
| 7277 | .base = .{ .frame = dst_frame_addr.index }, | 7359 | .base = .{ .frame = dst_frame_addr.index }, |
| 7278 | .disp = dst_frame_addr.off + info.indices[1] * 8, | 7360 | .mod = .{ .rm = .{ |
| 7279 | }), | 7361 | .size = .qword, |
| 7362 | .disp = dst_frame_addr.off + info.indices[1] * 8, | ||
| 7363 | } }, | ||
| 7364 | }, | ||
| 7280 | ); | 7365 | ); |
| 7281 | if (tag[0] == ._r and tag[1] == .sa) { | 7366 | if (tag[0] == ._r and tag[1] == .sa) { |
| 7282 | try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, first_reg); | 7367 | try self.asmRegisterRegister(.{ ._, .mov }, tmp_reg, first_reg); |
| ... | @@ -7302,18 +7387,24 @@ fn genShiftBinOpMir( | ... | @@ -7302,18 +7387,24 @@ fn genShiftBinOpMir( |
| 7302 | try self.asmCmovccRegisterRegister(.ae, first_reg, tmp_reg); | 7387 | try self.asmCmovccRegisterRegister(.ae, first_reg, tmp_reg); |
| 7303 | try self.asmMemoryRegister( | 7388 | try self.asmMemoryRegister( |
| 7304 | .{ ._, .mov }, | 7389 | .{ ._, .mov }, |
| 7305 | Memory.sib(.qword, .{ | 7390 | .{ |
| 7306 | .base = .{ .frame = dst_frame_addr.index }, | 7391 | .base = .{ .frame = dst_frame_addr.index }, |
| 7307 | .disp = dst_frame_addr.off + info.indices[1] * 8, | 7392 | .mod = .{ .rm = .{ |
| 7308 | }), | 7393 | .size = .qword, |
| 7394 | .disp = dst_frame_addr.off + info.indices[1] * 8, | ||
| 7395 | } }, | ||
| 7396 | }, | ||
| 7309 | second_reg, | 7397 | second_reg, |
| 7310 | ); | 7398 | ); |
| 7311 | try self.asmMemoryRegister( | 7399 | try self.asmMemoryRegister( |
| 7312 | .{ ._, .mov }, | 7400 | .{ ._, .mov }, |
| 7313 | Memory.sib(.qword, .{ | 7401 | .{ |
| 7314 | .base = .{ .frame = dst_frame_addr.index }, | 7402 | .base = .{ .frame = dst_frame_addr.index }, |
| 7315 | .disp = dst_frame_addr.off + info.indices[0] * 8, | 7403 | .mod = .{ .rm = .{ |
| 7316 | }), | 7404 | .size = .qword, |
| 7405 | .disp = dst_frame_addr.off + info.indices[0] * 8, | ||
| 7406 | } }, | ||
| 7407 | }, | ||
| 7317 | first_reg, | 7408 | first_reg, |
| 7318 | ); | 7409 | ); |
| 7319 | }, | 7410 | }, |
| ... | @@ -7352,6 +7443,7 @@ fn genShiftBinOp( | ... | @@ -7352,6 +7443,7 @@ fn genShiftBinOp( |
| 7352 | }); | 7443 | }); |
| 7353 | 7444 | ||
| 7354 | assert(rhs_ty.abiSize(mod) == 1); | 7445 | assert(rhs_ty.abiSize(mod) == 1); |
| 7446 | try self.spillEflagsIfOccupied(); | ||
| 7355 | 7447 | ||
| 7356 | const lhs_abi_size = lhs_ty.abiSize(mod); | 7448 | const lhs_abi_size = lhs_ty.abiSize(mod); |
| 7357 | if (lhs_abi_size > 16) return self.fail("TODO implement genShiftBinOp for {}", .{ | 7449 | if (lhs_abi_size > 16) return self.fail("TODO implement genShiftBinOp for {}", .{ |
| ... | @@ -7541,22 +7633,20 @@ fn genMulDivBinOp( | ... | @@ -7541,22 +7633,20 @@ fn genMulDivBinOp( |
| 7541 | }, dst_abi_size) }; | 7633 | }, dst_abi_size) }; |
| 7542 | 7634 | ||
| 7543 | const dst_mcv = try self.allocRegOrMemAdvanced(dst_ty, maybe_inst, false); | 7635 | const dst_mcv = try self.allocRegOrMemAdvanced(dst_ty, maybe_inst, false); |
| 7544 | try self.asmMemoryRegister( | 7636 | try self.asmMemoryRegister(.{ ._, .mov }, .{ |
| 7545 | .{ ._, .mov }, | 7637 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 7546 | Memory.sib(.qword, .{ | 7638 | .mod = .{ .rm = .{ |
| 7547 | .base = .{ .frame = dst_mcv.load_frame.index }, | 7639 | .size = .qword, |
| 7548 | .disp = dst_mcv.load_frame.off, | 7640 | .disp = dst_mcv.load_frame.off, |
| 7549 | }), | 7641 | } }, |
| 7550 | .rax, | 7642 | }, .rax); |
| 7551 | ); | 7643 | try self.asmMemoryRegister(.{ ._, .mov }, .{ |
| 7552 | try self.asmMemoryRegister( | 7644 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 7553 | .{ ._, .mov }, | 7645 | .mod = .{ .rm = .{ |
| 7554 | Memory.sib(.qword, .{ | 7646 | .size = .qword, |
| 7555 | .base = .{ .frame = dst_mcv.load_frame.index }, | ||
| 7556 | .disp = dst_mcv.load_frame.off + 8, | 7647 | .disp = dst_mcv.load_frame.off + 8, |
| 7557 | }), | 7648 | } }, |
| 7558 | .rdx, | 7649 | }, .rdx); |
| 7559 | ); | ||
| 7560 | return dst_mcv; | 7650 | return dst_mcv; |
| 7561 | }, | 7651 | }, |
| 7562 | 7652 | ||
| ... | @@ -7768,7 +7858,7 @@ fn genBinOp( | ... | @@ -7768,7 +7858,7 @@ fn genBinOp( |
| 7768 | mir_tag, | 7858 | mir_tag, |
| 7769 | dst_reg, | 7859 | dst_reg, |
| 7770 | dst_reg, | 7860 | dst_reg, |
| 7771 | src_mcv.mem(Memory.PtrSize.fromBitSize(float_bits)), | 7861 | src_mcv.mem(Memory.Size.fromBitSize(float_bits)), |
| 7772 | ) else try self.asmRegisterRegisterRegister( | 7862 | ) else try self.asmRegisterRegisterRegister( |
| 7773 | mir_tag, | 7863 | mir_tag, |
| 7774 | dst_reg, | 7864 | dst_reg, |
| ... | @@ -7787,7 +7877,7 @@ fn genBinOp( | ... | @@ -7787,7 +7877,7 @@ fn genBinOp( |
| 7787 | if (src_mcv.isMemory()) try self.asmRegisterMemory( | 7877 | if (src_mcv.isMemory()) try self.asmRegisterMemory( |
| 7788 | mir_tag, | 7878 | mir_tag, |
| 7789 | dst_reg, | 7879 | dst_reg, |
| 7790 | src_mcv.mem(Memory.PtrSize.fromBitSize(float_bits)), | 7880 | src_mcv.mem(Memory.Size.fromBitSize(float_bits)), |
| 7791 | ) else try self.asmRegisterRegister( | 7881 | ) else try self.asmRegisterRegister( |
| 7792 | mir_tag, | 7882 | mir_tag, |
| 7793 | dst_reg, | 7883 | dst_reg, |
| ... | @@ -7858,7 +7948,7 @@ fn genBinOp( | ... | @@ -7858,7 +7948,7 @@ fn genBinOp( |
| 7858 | }) .{ .lhs = rhs_air, .rhs = lhs_air } else .{ .lhs = lhs_air, .rhs = rhs_air }; | 7948 | }) .{ .lhs = rhs_air, .rhs = lhs_air } else .{ .lhs = lhs_air, .rhs = rhs_air }; |
| 7859 | 7949 | ||
| 7860 | const lhs_mcv = try self.resolveInst(ordered_air.lhs); | 7950 | const lhs_mcv = try self.resolveInst(ordered_air.lhs); |
| 7861 | const rhs_mcv = try self.resolveInst(ordered_air.rhs); | 7951 | var rhs_mcv = try self.resolveInst(ordered_air.rhs); |
| 7862 | switch (lhs_mcv) { | 7952 | switch (lhs_mcv) { |
| 7863 | .immediate => |imm| switch (imm) { | 7953 | .immediate => |imm| switch (imm) { |
| 7864 | 0 => switch (air_tag) { | 7954 | 0 => switch (air_tag) { |
| ... | @@ -7930,6 +8020,7 @@ fn genBinOp( | ... | @@ -7930,6 +8020,7 @@ fn genBinOp( |
| 7930 | copied_to_dst = false | 8020 | copied_to_dst = false |
| 7931 | else | 8021 | else |
| 7932 | try self.genCopy(lhs_ty, dst_mcv, lhs_mcv); | 8022 | try self.genCopy(lhs_ty, dst_mcv, lhs_mcv); |
| 8023 | rhs_mcv = try self.resolveInst(ordered_air.rhs); | ||
| 7933 | break :dst dst_mcv; | 8024 | break :dst dst_mcv; |
| 7934 | }; | 8025 | }; |
| 7935 | const dst_locks: [2]?RegisterLock = switch (dst_mcv) { | 8026 | const dst_locks: [2]?RegisterLock = switch (dst_mcv) { |
| ... | @@ -8149,21 +8240,30 @@ fn genBinOp( | ... | @@ -8149,21 +8240,30 @@ fn genBinOp( |
| 8149 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( | 8240 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( |
| 8150 | cc, | 8241 | cc, |
| 8151 | registerAlias(tmp_reg, cmov_abi_size), | 8242 | registerAlias(tmp_reg, cmov_abi_size), |
| 8152 | Memory.sib(Memory.PtrSize.fromSize(cmov_abi_size), switch (mat_src_mcv) { | 8243 | switch (mat_src_mcv) { |
| 8153 | .memory => |addr| .{ | 8244 | .memory => |addr| .{ |
| 8154 | .base = .{ .reg = .ds }, | 8245 | .base = .{ .reg = .ds }, |
| 8155 | .disp = @intCast(@as(i64, @bitCast(addr))), | 8246 | .mod = .{ .rm = .{ |
| 8247 | .size = Memory.Size.fromSize(cmov_abi_size), | ||
| 8248 | .disp = @intCast(@as(i64, @bitCast(addr))), | ||
| 8249 | } }, | ||
| 8156 | }, | 8250 | }, |
| 8157 | .indirect => |reg_off| .{ | 8251 | .indirect => |reg_off| .{ |
| 8158 | .base = .{ .reg = reg_off.reg }, | 8252 | .base = .{ .reg = reg_off.reg }, |
| 8159 | .disp = reg_off.off, | 8253 | .mod = .{ .rm = .{ |
| 8254 | .size = Memory.Size.fromSize(cmov_abi_size), | ||
| 8255 | .disp = reg_off.off, | ||
| 8256 | } }, | ||
| 8160 | }, | 8257 | }, |
| 8161 | .load_frame => |frame_addr| .{ | 8258 | .load_frame => |frame_addr| .{ |
| 8162 | .base = .{ .frame = frame_addr.index }, | 8259 | .base = .{ .frame = frame_addr.index }, |
| 8163 | .disp = frame_addr.off, | 8260 | .mod = .{ .rm = .{ |
| 8261 | .size = Memory.Size.fromSize(cmov_abi_size), | ||
| 8262 | .disp = frame_addr.off, | ||
| 8263 | } }, | ||
| 8164 | }, | 8264 | }, |
| 8165 | else => unreachable, | 8265 | else => unreachable, |
| 8166 | }), | 8266 | }, |
| 8167 | ), | 8267 | ), |
| 8168 | } | 8268 | } |
| 8169 | try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg }); | 8269 | try self.genCopy(lhs_ty, dst_mcv, .{ .register = tmp_reg }); |
| ... | @@ -8912,8 +9012,8 @@ fn genBinOp( | ... | @@ -8912,8 +9012,8 @@ fn genBinOp( |
| 8912 | dst_reg, | 9012 | dst_reg, |
| 8913 | lhs_reg, | 9013 | lhs_reg, |
| 8914 | src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { | 9014 | src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { |
| 8915 | else => Memory.PtrSize.fromSize(abi_size), | 9015 | else => Memory.Size.fromSize(abi_size), |
| 8916 | .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()), | 9016 | .Vector => Memory.Size.fromBitSize(dst_reg.bitSize()), |
| 8917 | }), | 9017 | }), |
| 8918 | ) else try self.asmRegisterRegisterRegister( | 9018 | ) else try self.asmRegisterRegisterRegister( |
| 8919 | mir_tag, | 9019 | mir_tag, |
| ... | @@ -8930,8 +9030,8 @@ fn genBinOp( | ... | @@ -8930,8 +9030,8 @@ fn genBinOp( |
| 8930 | mir_tag, | 9030 | mir_tag, |
| 8931 | dst_reg, | 9031 | dst_reg, |
| 8932 | src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { | 9032 | src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { |
| 8933 | else => Memory.PtrSize.fromSize(abi_size), | 9033 | else => Memory.Size.fromSize(abi_size), |
| 8934 | .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()), | 9034 | .Vector => Memory.Size.fromBitSize(dst_reg.bitSize()), |
| 8935 | }), | 9035 | }), |
| 8936 | ) else try self.asmRegisterRegister( | 9036 | ) else try self.asmRegisterRegister( |
| 8937 | mir_tag, | 9037 | mir_tag, |
| ... | @@ -9202,12 +9302,12 @@ fn genBinOp( | ... | @@ -9202,12 +9302,12 @@ fn genBinOp( |
| 9202 | .ty = lhs_ty, | 9302 | .ty = lhs_ty, |
| 9203 | .val = try unsigned_ty.maxInt(mod, unsigned_ty), | 9303 | .val = try unsigned_ty.maxInt(mod, unsigned_ty), |
| 9204 | }); | 9304 | }); |
| 9205 | const not_mem = if (not_mcv.isMemory()) | 9305 | const not_mem: Memory = if (not_mcv.isMemory()) |
| 9206 | not_mcv.mem(Memory.PtrSize.fromSize(abi_size)) | 9306 | not_mcv.mem(Memory.Size.fromSize(abi_size)) |
| 9207 | else | 9307 | else |
| 9208 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = .{ | 9308 | .{ .base = .{ |
| 9209 | .reg = try self.copyToTmpRegister(Type.usize, not_mcv.address()), | 9309 | .reg = try self.copyToTmpRegister(Type.usize, not_mcv.address()), |
| 9210 | } }); | 9310 | }, .mod = .{ .rm = .{ .size = Memory.Size.fromSize(abi_size) } } }; |
| 9211 | switch (mir_tag[0]) { | 9311 | switch (mir_tag[0]) { |
| 9212 | .vp_b, .vp_d, .vp_q, .vp_w => try self.asmRegisterRegisterMemory( | 9312 | .vp_b, .vp_d, .vp_q, .vp_w => try self.asmRegisterRegisterMemory( |
| 9213 | .{ .vp_, .xor }, | 9313 | .{ .vp_, .xor }, |
| ... | @@ -9252,6 +9352,7 @@ fn genBinOpMir( | ... | @@ -9252,6 +9352,7 @@ fn genBinOpMir( |
| 9252 | ) !void { | 9352 | ) !void { |
| 9253 | const mod = self.bin_file.options.module.?; | 9353 | const mod = self.bin_file.options.module.?; |
| 9254 | const abi_size: u32 = @intCast(ty.abiSize(mod)); | 9354 | const abi_size: u32 = @intCast(ty.abiSize(mod)); |
| 9355 | try self.spillEflagsIfOccupied(); | ||
| 9255 | switch (dst_mcv) { | 9356 | switch (dst_mcv) { |
| 9256 | .none, | 9357 | .none, |
| 9257 | .unreach, | 9358 | .unreach, |
| ... | @@ -9359,25 +9460,30 @@ fn genBinOpMir( | ... | @@ -9359,25 +9460,30 @@ fn genBinOpMir( |
| 9359 | .lea_frame, | 9460 | .lea_frame, |
| 9360 | => { | 9461 | => { |
| 9361 | blk: { | 9462 | blk: { |
| 9362 | return self.asmRegisterMemory( | 9463 | return self.asmRegisterMemory(mir_limb_tag, dst_alias, switch (src_mcv) { |
| 9363 | mir_limb_tag, | 9464 | .memory => |addr| .{ |
| 9364 | dst_alias, | 9465 | .base = .{ .reg = .ds }, |
| 9365 | Memory.sib(Memory.PtrSize.fromSize(limb_abi_size), switch (src_mcv) { | 9466 | .mod = .{ .rm = .{ |
| 9366 | .memory => |addr| .{ | 9467 | .size = Memory.Size.fromSize(limb_abi_size), |
| 9367 | .base = .{ .reg = .ds }, | ||
| 9368 | .disp = math.cast(i32, addr + off) orelse break :blk, | 9468 | .disp = math.cast(i32, addr + off) orelse break :blk, |
| 9369 | }, | 9469 | } }, |
| 9370 | .indirect => |reg_off| .{ | 9470 | }, |
| 9371 | .base = .{ .reg = reg_off.reg }, | 9471 | .indirect => |reg_off| .{ |
| 9472 | .base = .{ .reg = reg_off.reg }, | ||
| 9473 | .mod = .{ .rm = .{ | ||
| 9474 | .size = Memory.Size.fromSize(limb_abi_size), | ||
| 9372 | .disp = reg_off.off + off, | 9475 | .disp = reg_off.off + off, |
| 9373 | }, | 9476 | } }, |
| 9374 | .load_frame => |frame_addr| .{ | 9477 | }, |
| 9375 | .base = .{ .frame = frame_addr.index }, | 9478 | .load_frame => |frame_addr| .{ |
| 9479 | .base = .{ .frame = frame_addr.index }, | ||
| 9480 | .mod = .{ .rm = .{ | ||
| 9481 | .size = Memory.Size.fromSize(limb_abi_size), | ||
| 9376 | .disp = frame_addr.off + off, | 9482 | .disp = frame_addr.off + off, |
| 9377 | }, | 9483 | } }, |
| 9378 | else => break :blk, | 9484 | }, |
| 9379 | }), | 9485 | else => break :blk, |
| 9380 | ); | 9486 | }); |
| 9381 | } | 9487 | } |
| 9382 | 9488 | ||
| 9383 | switch (src_mcv) { | 9489 | switch (src_mcv) { |
| ... | @@ -9510,26 +9616,35 @@ fn genBinOpMir( | ... | @@ -9510,26 +9616,35 @@ fn genBinOpMir( |
| 9510 | }), | 9616 | }), |
| 9511 | }, | 9617 | }, |
| 9512 | }; | 9618 | }; |
| 9513 | const dst_limb_mem = Memory.sib( | 9619 | const dst_limb_mem: Memory = switch (dst_mcv) { |
| 9514 | Memory.PtrSize.fromSize(limb_abi_size), | 9620 | .memory, |
| 9515 | switch (dst_mcv) { | 9621 | .load_symbol, |
| 9516 | .memory, | 9622 | .load_got, |
| 9517 | .load_symbol, | 9623 | .load_direct, |
| 9518 | .load_got, | 9624 | .load_tlv, |
| 9519 | .load_direct, | 9625 | => .{ |
| 9520 | .load_tlv, | 9626 | .base = .{ .reg = dst_info.?.addr_reg }, |
| 9521 | => .{ .base = .{ .reg = dst_info.?.addr_reg }, .disp = off }, | 9627 | .mod = .{ .rm = .{ |
| 9522 | .indirect => |reg_off| .{ | 9628 | .size = Memory.Size.fromSize(limb_abi_size), |
| 9523 | .base = .{ .reg = reg_off.reg }, | 9629 | .disp = off, |
| 9630 | } }, | ||
| 9631 | }, | ||
| 9632 | .indirect => |reg_off| .{ | ||
| 9633 | .base = .{ .reg = reg_off.reg }, | ||
| 9634 | .mod = .{ .rm = .{ | ||
| 9635 | .size = Memory.Size.fromSize(limb_abi_size), | ||
| 9524 | .disp = reg_off.off + off, | 9636 | .disp = reg_off.off + off, |
| 9525 | }, | 9637 | } }, |
| 9526 | .load_frame => |frame_addr| .{ | 9638 | }, |
| 9527 | .base = .{ .frame = frame_addr.index }, | 9639 | .load_frame => |frame_addr| .{ |
| 9640 | .base = .{ .frame = frame_addr.index }, | ||
| 9641 | .mod = .{ .rm = .{ | ||
| 9642 | .size = Memory.Size.fromSize(limb_abi_size), | ||
| 9528 | .disp = frame_addr.off + off, | 9643 | .disp = frame_addr.off + off, |
| 9529 | }, | 9644 | } }, |
| 9530 | else => unreachable, | ||
| 9531 | }, | 9645 | }, |
| 9532 | ); | 9646 | else => unreachable, |
| 9647 | }; | ||
| 9533 | switch (resolved_src_mcv) { | 9648 | switch (resolved_src_mcv) { |
| 9534 | .none, | 9649 | .none, |
| 9535 | .unreach, | 9650 | .unreach, |
| ... | @@ -9730,29 +9845,38 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M | ... | @@ -9730,29 +9845,38 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M |
| 9730 | .memory, .indirect, .load_frame => try self.asmRegisterMemory( | 9845 | .memory, .indirect, .load_frame => try self.asmRegisterMemory( |
| 9731 | .{ .i_, .mul }, | 9846 | .{ .i_, .mul }, |
| 9732 | dst_alias, | 9847 | dst_alias, |
| 9733 | Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (resolved_src_mcv) { | 9848 | switch (resolved_src_mcv) { |
| 9734 | .memory => |addr| .{ | 9849 | .memory => |addr| .{ |
| 9735 | .base = .{ .reg = .ds }, | 9850 | .base = .{ .reg = .ds }, |
| 9736 | .disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse | 9851 | .mod = .{ .rm = .{ |
| 9737 | return self.asmRegisterRegister( | 9852 | .size = Memory.Size.fromSize(abi_size), |
| 9738 | .{ .i_, .mul }, | 9853 | .disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse |
| 9739 | dst_alias, | 9854 | return self.asmRegisterRegister( |
| 9740 | registerAlias( | 9855 | .{ .i_, .mul }, |
| 9741 | try self.copyToTmpRegister(dst_ty, resolved_src_mcv), | 9856 | dst_alias, |
| 9742 | abi_size, | 9857 | registerAlias( |
| 9858 | try self.copyToTmpRegister(dst_ty, resolved_src_mcv), | ||
| 9859 | abi_size, | ||
| 9860 | ), | ||
| 9743 | ), | 9861 | ), |
| 9744 | ), | 9862 | } }, |
| 9745 | }, | 9863 | }, |
| 9746 | .indirect => |reg_off| .{ | 9864 | .indirect => |reg_off| .{ |
| 9747 | .base = .{ .reg = reg_off.reg }, | 9865 | .base = .{ .reg = reg_off.reg }, |
| 9748 | .disp = reg_off.off, | 9866 | .mod = .{ .rm = .{ |
| 9867 | .size = Memory.Size.fromSize(abi_size), | ||
| 9868 | .disp = reg_off.off, | ||
| 9869 | } }, | ||
| 9749 | }, | 9870 | }, |
| 9750 | .load_frame => |frame_addr| .{ | 9871 | .load_frame => |frame_addr| .{ |
| 9751 | .base = .{ .frame = frame_addr.index }, | 9872 | .base = .{ .frame = frame_addr.index }, |
| 9752 | .disp = frame_addr.off, | 9873 | .mod = .{ .rm = .{ |
| 9874 | .size = Memory.Size.fromSize(abi_size), | ||
| 9875 | .disp = frame_addr.off, | ||
| 9876 | } }, | ||
| 9753 | }, | 9877 | }, |
| 9754 | else => unreachable, | 9878 | else => unreachable, |
| 9755 | }), | 9879 | }, |
| 9756 | ), | 9880 | ), |
| 9757 | } | 9881 | } |
| 9758 | }, | 9882 | }, |
| ... | @@ -9857,9 +9981,14 @@ fn genVarDbgInfo( | ... | @@ -9857,9 +9981,14 @@ fn genVarDbgInfo( |
| 9857 | // .offset = -off, | 9981 | // .offset = -off, |
| 9858 | //} }, | 9982 | //} }, |
| 9859 | .memory => |address| .{ .memory = address }, | 9983 | .memory => |address| .{ .memory = address }, |
| 9860 | .load_symbol => |sym_index| .{ .linker_load = .{ .type = .direct, .sym_index = sym_index } }, // TODO | 9984 | .load_symbol => |sym_off| loc: { |
| 9985 | assert(sym_off.off == 0); | ||
| 9986 | break :loc .{ .linker_load = .{ .type = .direct, .sym_index = sym_off.sym } }; | ||
| 9987 | }, // TODO | ||
| 9861 | .load_got => |sym_index| .{ .linker_load = .{ .type = .got, .sym_index = sym_index } }, | 9988 | .load_got => |sym_index| .{ .linker_load = .{ .type = .got, .sym_index = sym_index } }, |
| 9862 | .load_direct => |sym_index| .{ .linker_load = .{ .type = .direct, .sym_index = sym_index } }, | 9989 | .load_direct => |sym_index| .{ |
| 9990 | .linker_load = .{ .type = .direct, .sym_index = sym_index }, | ||
| 9991 | }, | ||
| 9863 | .immediate => |x| .{ .immediate = x }, | 9992 | .immediate => |x| .{ .immediate = x }, |
| 9864 | .undef => .undef, | 9993 | .undef => .undef, |
| 9865 | .none => .none, | 9994 | .none => .none, |
| ... | @@ -9971,6 +10100,7 @@ fn genCall(self: *Self, info: union(enum) { | ... | @@ -9971,6 +10100,7 @@ fn genCall(self: *Self, info: union(enum) { |
| 9971 | }), | 10100 | }), |
| 9972 | }; | 10101 | }; |
| 9973 | const fn_info = mod.typeToFunc(fn_ty).?; | 10102 | const fn_info = mod.typeToFunc(fn_ty).?; |
| 10103 | const resolved_cc = abi.resolveCallingConvention(fn_info.cc, self.target.*); | ||
| 9974 | 10104 | ||
| 9975 | const ExpectedContents = extern struct { | 10105 | const ExpectedContents = extern struct { |
| 9976 | var_args: [16][@sizeOf(Type)]u8 align(@alignOf(Type)), | 10106 | var_args: [16][@sizeOf(Type)]u8 align(@alignOf(Type)), |
| ... | @@ -10012,9 +10142,7 @@ fn genCall(self: *Self, info: union(enum) { | ... | @@ -10012,9 +10142,7 @@ fn genCall(self: *Self, info: union(enum) { |
| 10012 | } | 10142 | } |
| 10013 | 10143 | ||
| 10014 | try self.spillEflagsIfOccupied(); | 10144 | try self.spillEflagsIfOccupied(); |
| 10015 | try self.spillRegisters(abi.getCallerPreservedRegs( | 10145 | try self.spillRegisters(abi.getCallerPreservedRegs(resolved_cc)); |
| 10016 | abi.resolveCallingConvention(fn_info.cc, self.target.*), | ||
| 10017 | )); | ||
| 10018 | 10146 | ||
| 10019 | // set stack arguments first because this can clobber registers | 10147 | // set stack arguments first because this can clobber registers |
| 10020 | // also clobber spill arguments as we go | 10148 | // also clobber spill arguments as we go |
| ... | @@ -10109,18 +10237,31 @@ fn genCall(self: *Self, info: union(enum) { | ... | @@ -10109,18 +10237,31 @@ fn genCall(self: *Self, info: union(enum) { |
| 10109 | const sym = elf_file.symbol(sym_index); | 10237 | const sym = elf_file.symbol(sym_index); |
| 10110 | _ = try sym.getOrCreateZigGotEntry(sym_index, elf_file); | 10238 | _ = try sym.getOrCreateZigGotEntry(sym_index, elf_file); |
| 10111 | if (self.bin_file.options.pic) { | 10239 | if (self.bin_file.options.pic) { |
| 10112 | try self.genSetReg(.rax, Type.usize, .{ .load_symbol = sym.esym_index }); | 10240 | const callee_reg: Register = switch (resolved_cc) { |
| 10113 | try self.asmRegister(.{ ._, .call }, .rax); | 10241 | .SysV => callee: { |
| 10114 | } else { | 10242 | if (!fn_info.is_var_args) break :callee .rax; |
| 10115 | _ = try self.addInst(.{ | 10243 | const param_regs = abi.getCAbiIntParamRegs(resolved_cc); |
| 10116 | .tag = .call, | 10244 | break :callee if (call_info.gp_count < param_regs.len) |
| 10117 | .ops = .linker_reloc, | 10245 | param_regs[call_info.gp_count] |
| 10118 | .data = .{ .reloc = .{ | 10246 | else |
| 10119 | .atom_index = try self.owner.getSymbolIndex(self), | 10247 | .r10; |
| 10120 | .sym_index = sym.esym_index, | 10248 | }, |
| 10121 | } }, | 10249 | .Win64 => .rax, |
| 10122 | }); | 10250 | else => unreachable, |
| 10123 | } | 10251 | }; |
| 10252 | try self.genSetReg( | ||
| 10253 | callee_reg, | ||
| 10254 | Type.usize, | ||
| 10255 | .{ .load_symbol = .{ .sym = sym.esym_index } }, | ||
| 10256 | ); | ||
| 10257 | try self.asmRegister(.{ ._, .call }, callee_reg); | ||
| 10258 | } else try self.asmMemory(.{ ._, .call }, .{ | ||
| 10259 | .base = .{ .reloc = .{ | ||
| 10260 | .atom_index = try self.owner.getSymbolIndex(self), | ||
| 10261 | .sym_index = sym.esym_index, | ||
| 10262 | } }, | ||
| 10263 | .mod = .{ .rm = .{ .size = .qword } }, | ||
| 10264 | }); | ||
| 10124 | } else if (self.bin_file.cast(link.File.Coff)) |coff_file| { | 10265 | } else if (self.bin_file.cast(link.File.Coff)) |coff_file| { |
| 10125 | const atom = try coff_file.getOrCreateAtomForDecl(func.owner_decl); | 10266 | const atom = try coff_file.getOrCreateAtomForDecl(func.owner_decl); |
| 10126 | const sym_index = coff_file.getAtom(atom).getSymbolIndex().?; | 10267 | const sym_index = coff_file.getAtom(atom).getSymbolIndex().?; |
| ... | @@ -10134,10 +10275,13 @@ fn genCall(self: *Self, info: union(enum) { | ... | @@ -10134,10 +10275,13 @@ fn genCall(self: *Self, info: union(enum) { |
| 10134 | } else if (self.bin_file.cast(link.File.Plan9)) |p9| { | 10275 | } else if (self.bin_file.cast(link.File.Plan9)) |p9| { |
| 10135 | const atom_index = try p9.seeDecl(func.owner_decl); | 10276 | const atom_index = try p9.seeDecl(func.owner_decl); |
| 10136 | const atom = p9.getAtom(atom_index); | 10277 | const atom = p9.getAtom(atom_index); |
| 10137 | try self.asmMemory(.{ ._, .call }, Memory.sib(.qword, .{ | 10278 | try self.asmMemory(.{ ._, .call }, .{ |
| 10138 | .base = .{ .reg = .ds }, | 10279 | .base = .{ .reg = .ds }, |
| 10139 | .disp = @intCast(atom.getOffsetTableAddress(p9)), | 10280 | .mod = .{ .rm = .{ |
| 10140 | })); | 10281 | .size = .qword, |
| 10282 | .disp = @intCast(atom.getOffsetTableAddress(p9)), | ||
| 10283 | } }, | ||
| 10284 | }); | ||
| 10141 | } else unreachable; | 10285 | } else unreachable; |
| 10142 | }, | 10286 | }, |
| 10143 | .extern_func => |extern_func| { | 10287 | .extern_func => |extern_func| { |
| ... | @@ -10622,7 +10766,10 @@ fn airCmpLtErrorsLen(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -10622,7 +10766,10 @@ fn airCmpLtErrorsLen(self: *Self, inst: Air.Inst.Index) !void { |
| 10622 | try self.asmRegisterMemory( | 10766 | try self.asmRegisterMemory( |
| 10623 | .{ ._, .cmp }, | 10767 | .{ ._, .cmp }, |
| 10624 | registerAlias(dst_reg, op_abi_size), | 10768 | registerAlias(dst_reg, op_abi_size), |
| 10625 | Memory.sib(Memory.PtrSize.fromSize(op_abi_size), .{ .base = .{ .reg = addr_reg } }), | 10769 | .{ |
| 10770 | .base = .{ .reg = addr_reg }, | ||
| 10771 | .mod = .{ .rm = .{ .size = Memory.Size.fromSize(op_abi_size) } }, | ||
| 10772 | }, | ||
| 10626 | ); | 10773 | ); |
| 10627 | 10774 | ||
| 10628 | self.eflags_inst = inst; | 10775 | self.eflags_inst = inst; |
| ... | @@ -10876,10 +11023,13 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC | ... | @@ -10876,10 +11023,13 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC |
| 10876 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); | 11023 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); |
| 10877 | try self.asmMemoryImmediate( | 11024 | try self.asmMemoryImmediate( |
| 10878 | .{ ._, .cmp }, | 11025 | .{ ._, .cmp }, |
| 10879 | Memory.sib(Memory.PtrSize.fromSize(some_abi_size), .{ | 11026 | .{ |
| 10880 | .base = .{ .reg = addr_reg }, | 11027 | .base = .{ .reg = addr_reg }, |
| 10881 | .disp = some_info.off, | 11028 | .mod = .{ .rm = .{ |
| 10882 | }), | 11029 | .size = Memory.Size.fromSize(some_abi_size), |
| 11030 | .disp = some_info.off, | ||
| 11031 | } }, | ||
| 11032 | }, | ||
| 10883 | Immediate.u(0), | 11033 | Immediate.u(0), |
| 10884 | ); | 11034 | ); |
| 10885 | return .{ .eflags = .e }; | 11035 | return .{ .eflags = .e }; |
| ... | @@ -10889,17 +11039,23 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC | ... | @@ -10889,17 +11039,23 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC |
| 10889 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); | 11039 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); |
| 10890 | try self.asmMemoryImmediate( | 11040 | try self.asmMemoryImmediate( |
| 10891 | .{ ._, .cmp }, | 11041 | .{ ._, .cmp }, |
| 10892 | Memory.sib(Memory.PtrSize.fromSize(some_abi_size), switch (opt_mcv) { | 11042 | switch (opt_mcv) { |
| 10893 | .indirect => |reg_off| .{ | 11043 | .indirect => |reg_off| .{ |
| 10894 | .base = .{ .reg = reg_off.reg }, | 11044 | .base = .{ .reg = reg_off.reg }, |
| 10895 | .disp = reg_off.off + some_info.off, | 11045 | .mod = .{ .rm = .{ |
| 11046 | .size = Memory.Size.fromSize(some_abi_size), | ||
| 11047 | .disp = reg_off.off + some_info.off, | ||
| 11048 | } }, | ||
| 10896 | }, | 11049 | }, |
| 10897 | .load_frame => |frame_addr| .{ | 11050 | .load_frame => |frame_addr| .{ |
| 10898 | .base = .{ .frame = frame_addr.index }, | 11051 | .base = .{ .frame = frame_addr.index }, |
| 10899 | .disp = frame_addr.off + some_info.off, | 11052 | .mod = .{ .rm = .{ |
| 11053 | .size = Memory.Size.fromSize(some_abi_size), | ||
| 11054 | .disp = frame_addr.off + some_info.off, | ||
| 11055 | } }, | ||
| 10900 | }, | 11056 | }, |
| 10901 | else => unreachable, | 11057 | else => unreachable, |
| 10902 | }), | 11058 | }, |
| 10903 | Immediate.u(0), | 11059 | Immediate.u(0), |
| 10904 | ); | 11060 | ); |
| 10905 | return .{ .eflags = .e }; | 11061 | return .{ .eflags = .e }; |
| ... | @@ -10929,10 +11085,13 @@ fn isNullPtr(self: *Self, inst: Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCValue) | ... | @@ -10929,10 +11085,13 @@ fn isNullPtr(self: *Self, inst: Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCValue) |
| 10929 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); | 11085 | const some_abi_size: u32 = @intCast(some_info.ty.abiSize(mod)); |
| 10930 | try self.asmMemoryImmediate( | 11086 | try self.asmMemoryImmediate( |
| 10931 | .{ ._, .cmp }, | 11087 | .{ ._, .cmp }, |
| 10932 | Memory.sib(Memory.PtrSize.fromSize(some_abi_size), .{ | 11088 | .{ |
| 10933 | .base = .{ .reg = ptr_reg }, | 11089 | .base = .{ .reg = ptr_reg }, |
| 10934 | .disp = some_info.off, | 11090 | .mod = .{ .rm = .{ |
| 10935 | }), | 11091 | .size = Memory.Size.fromSize(some_abi_size), |
| 11092 | .disp = some_info.off, | ||
| 11093 | } }, | ||
| 11094 | }, | ||
| 10936 | Immediate.u(0), | 11095 | Immediate.u(0), |
| 10937 | ); | 11096 | ); |
| 10938 | 11097 | ||
| ... | @@ -11005,10 +11164,13 @@ fn isErrPtr(self: *Self, maybe_inst: ?Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCV | ... | @@ -11005,10 +11164,13 @@ fn isErrPtr(self: *Self, maybe_inst: ?Air.Inst.Index, ptr_ty: Type, ptr_mcv: MCV |
| 11005 | const err_off: u31 = @intCast(errUnionErrorOffset(eu_ty.errorUnionPayload(mod), mod)); | 11164 | const err_off: u31 = @intCast(errUnionErrorOffset(eu_ty.errorUnionPayload(mod), mod)); |
| 11006 | try self.asmMemoryImmediate( | 11165 | try self.asmMemoryImmediate( |
| 11007 | .{ ._, .cmp }, | 11166 | .{ ._, .cmp }, |
| 11008 | Memory.sib(self.memPtrSize(Type.anyerror), .{ | 11167 | .{ |
| 11009 | .base = .{ .reg = ptr_reg }, | 11168 | .base = .{ .reg = ptr_reg }, |
| 11010 | .disp = err_off, | 11169 | .mod = .{ .rm = .{ |
| 11011 | }), | 11170 | .size = self.memSize(Type.anyerror), |
| 11171 | .disp = err_off, | ||
| 11172 | } }, | ||
| 11173 | }, | ||
| 11012 | Immediate.u(0), | 11174 | Immediate.u(0), |
| 11013 | ); | 11175 | ); |
| 11014 | 11176 | ||
| ... | @@ -11121,11 +11283,11 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11121,11 +11283,11 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void { |
| 11121 | const ty_pl = self.air.instructions.items(.data)[inst].ty_pl; | 11283 | const ty_pl = self.air.instructions.items(.data)[inst].ty_pl; |
| 11122 | const loop = self.air.extraData(Air.Block, ty_pl.payload); | 11284 | const loop = self.air.extraData(Air.Block, ty_pl.payload); |
| 11123 | const body = self.air.extra[loop.end..][0..loop.data.body_len]; | 11285 | const body = self.air.extra[loop.end..][0..loop.data.body_len]; |
| 11124 | const jmp_target: Mir.Inst.Index = @intCast(self.mir_instructions.len); | ||
| 11125 | 11286 | ||
| 11126 | self.scope_generation += 1; | 11287 | self.scope_generation += 1; |
| 11127 | const state = try self.saveState(); | 11288 | const state = try self.saveState(); |
| 11128 | 11289 | ||
| 11290 | const jmp_target: Mir.Inst.Index = @intCast(self.mir_instructions.len); | ||
| 11129 | try self.genBody(body); | 11291 | try self.genBody(body); |
| 11130 | try self.restoreState(state, &.{}, .{ | 11292 | try self.restoreState(state, &.{}, .{ |
| 11131 | .emit_instructions = true, | 11293 | .emit_instructions = true, |
| ... | @@ -11303,14 +11465,14 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11303,14 +11465,14 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void { |
| 11303 | .close_scope = false, | 11465 | .close_scope = false, |
| 11304 | }); | 11466 | }); |
| 11305 | 11467 | ||
| 11306 | // Stop tracking block result without forgetting tracking info | ||
| 11307 | try self.freeValue(block_tracking.short); | ||
| 11308 | |||
| 11309 | // Emit a jump with a relocation. It will be patched up after the block ends. | 11468 | // Emit a jump with a relocation. It will be patched up after the block ends. |
| 11310 | // Leave the jump offset undefined | 11469 | // Leave the jump offset undefined |
| 11311 | const jmp_reloc = try self.asmJmpReloc(undefined); | 11470 | const jmp_reloc = try self.asmJmpReloc(undefined); |
| 11312 | try block_data.relocs.append(self.gpa, jmp_reloc); | 11471 | try block_data.relocs.append(self.gpa, jmp_reloc); |
| 11313 | 11472 | ||
| 11473 | // Stop tracking block result without forgetting tracking info | ||
| 11474 | try self.freeValue(block_tracking.short); | ||
| 11475 | |||
| 11314 | self.finishAirBookkeeping(); | 11476 | self.finishAirBookkeeping(); |
| 11315 | } | 11477 | } |
| 11316 | 11478 | ||
| ... | @@ -11586,7 +11748,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11586,7 +11748,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { |
| 11586 | label_gop.value_ptr.target = @intCast(self.mir_instructions.len); | 11748 | label_gop.value_ptr.target = @intCast(self.mir_instructions.len); |
| 11587 | } else continue; | 11749 | } else continue; |
| 11588 | 11750 | ||
| 11589 | var mnem_size: ?Memory.PtrSize = null; | 11751 | var mnem_size: ?Memory.Size = null; |
| 11590 | const mnem_tag = mnem: { | 11752 | const mnem_tag = mnem: { |
| 11591 | mnem_size = if (mem.endsWith(u8, mnem_str, "b")) | 11753 | mnem_size = if (mem.endsWith(u8, mnem_str, "b")) |
| 11592 | .byte | 11754 | .byte |
| ... | @@ -11605,7 +11767,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11605,7 +11767,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { |
| 11605 | mnem_size = null; | 11767 | mnem_size = null; |
| 11606 | break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str); | 11768 | break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str); |
| 11607 | } orelse return self.fail("invalid mnemonic: '{s}'", .{mnem_str}); | 11769 | } orelse return self.fail("invalid mnemonic: '{s}'", .{mnem_str}); |
| 11608 | if (@as(?Memory.PtrSize, switch (mnem_tag) { | 11770 | if (@as(?Memory.Size, switch (mnem_tag) { |
| 11609 | .fldenv, .fnstenv, .fstenv => .none, | 11771 | .fldenv, .fnstenv, .fstenv => .none, |
| 11610 | .ldmxcsr, .stmxcsr, .vldmxcsr, .vstmxcsr => .dword, | 11772 | .ldmxcsr, .stmxcsr, .vldmxcsr, .vstmxcsr => .dword, |
| 11611 | else => null, | 11773 | else => null, |
| ... | @@ -11670,10 +11832,13 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11670,10 +11832,13 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { |
| 11670 | if (colon) |colon_pos| { | 11832 | if (colon) |colon_pos| { |
| 11671 | const disp = std.fmt.parseInt(i32, op_str[colon_pos + ":".len ..], 0) catch | 11833 | const disp = std.fmt.parseInt(i32, op_str[colon_pos + ":".len ..], 0) catch |
| 11672 | return self.fail("invalid displacement: '{s}'", .{op_str}); | 11834 | return self.fail("invalid displacement: '{s}'", .{op_str}); |
| 11673 | op.* = .{ .mem = Memory.sib( | 11835 | op.* = .{ .mem = .{ |
| 11674 | mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), | 11836 | .base = .{ .reg = reg }, |
| 11675 | .{ .base = .{ .reg = reg }, .disp = disp }, | 11837 | .mod = .{ .rm = .{ |
| 11676 | ) }; | 11838 | .size = mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), |
| 11839 | .disp = disp, | ||
| 11840 | } }, | ||
| 11841 | } }; | ||
| 11677 | } else { | 11842 | } else { |
| 11678 | if (mnem_size) |size| if (reg.bitSize() != size.bitSize()) | 11843 | if (mnem_size) |size| if (reg.bitSize() != size.bitSize()) |
| 11679 | return self.fail("invalid register size: '{s}'", .{op_str}); | 11844 | return self.fail("invalid register size: '{s}'", .{op_str}); |
| ... | @@ -11697,34 +11862,45 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11697,34 +11862,45 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { |
| 11697 | .{ .reg = reg } | 11862 | .{ .reg = reg } |
| 11698 | else | 11863 | else |
| 11699 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11864 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11700 | .memory => |addr| if (mem.eql(u8, modifier, "") or | 11865 | .memory => |addr| if (mem.eql(u8, modifier, "") or mem.eql(u8, modifier, "P")) |
| 11701 | mem.eql(u8, modifier, "P")) | 11866 | .{ .mem = .{ |
| 11702 | .{ .mem = Memory.sib( | 11867 | .base = .{ .reg = .ds }, |
| 11703 | mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), | 11868 | .mod = .{ .rm = .{ |
| 11704 | .{ .base = .{ .reg = .ds }, .disp = @intCast(@as(i64, @bitCast(addr))) }, | 11869 | .size = mnem_size orelse |
| 11705 | ) } | 11870 | return self.fail("unknown size: '{s}'", .{op_str}), |
| 11871 | .disp = @intCast(@as(i64, @bitCast(addr))), | ||
| 11872 | } }, | ||
| 11873 | } } | ||
| 11706 | else | 11874 | else |
| 11707 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11875 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11708 | .indirect => |reg_off| if (mem.eql(u8, modifier, "")) | 11876 | .indirect => |reg_off| if (mem.eql(u8, modifier, "")) |
| 11709 | .{ .mem = Memory.sib( | 11877 | .{ .mem = .{ |
| 11710 | mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), | 11878 | .base = .{ .reg = reg_off.reg }, |
| 11711 | .{ .base = .{ .reg = reg_off.reg }, .disp = reg_off.off }, | 11879 | .mod = .{ .rm = .{ |
| 11712 | ) } | 11880 | .size = mnem_size orelse |
| 11881 | return self.fail("unknown size: '{s}'", .{op_str}), | ||
| 11882 | .disp = reg_off.off, | ||
| 11883 | } }, | ||
| 11884 | } } | ||
| 11713 | else | 11885 | else |
| 11714 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11886 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11715 | .load_frame => |frame_addr| if (mem.eql(u8, modifier, "")) | 11887 | .load_frame => |frame_addr| if (mem.eql(u8, modifier, "")) |
| 11716 | .{ .mem = Memory.sib( | 11888 | .{ .mem = .{ |
| 11717 | mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), | 11889 | .base = .{ .frame = frame_addr.index }, |
| 11718 | .{ .base = .{ .frame = frame_addr.index }, .disp = frame_addr.off }, | 11890 | .mod = .{ .rm = .{ |
| 11719 | ) } | 11891 | .size = mnem_size orelse |
| 11892 | return self.fail("unknown size: '{s}'", .{op_str}), | ||
| 11893 | .disp = frame_addr.off, | ||
| 11894 | } }, | ||
| 11895 | } } | ||
| 11720 | else | 11896 | else |
| 11721 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11897 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11722 | .lea_got => |sym_index| if (mem.eql(u8, modifier, "P")) | 11898 | .lea_got => |sym_index| if (mem.eql(u8, modifier, "P")) |
| 11723 | .{ .reg = try self.copyToTmpRegister(Type.usize, .{ .lea_got = sym_index }) } | 11899 | .{ .reg = try self.copyToTmpRegister(Type.usize, .{ .lea_got = sym_index }) } |
| 11724 | else | 11900 | else |
| 11725 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11901 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11726 | .load_symbol => |sym_index| if (mem.eql(u8, modifier, "P")) | 11902 | .load_symbol => |sym_off| if (mem.eql(u8, modifier, "P")) |
| 11727 | .{ .reg = try self.copyToTmpRegister(Type.usize, .{ .load_symbol = sym_index }) } | 11903 | .{ .reg = try self.copyToTmpRegister(Type.usize, .{ .load_symbol = sym_off }) } |
| 11728 | else | 11904 | else |
| 11729 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11905 | return self.fail("invalid modifier: '{s}'", .{modifier}), |
| 11730 | else => return self.fail("invalid constraint: '{s}'", .{op_str}), | 11906 | else => return self.fail("invalid constraint: '{s}'", .{op_str}), |
| ... | @@ -11759,47 +11935,61 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -11759,47 +11935,61 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void { |
| 11759 | const scale_str = sib_it.next() orelse ""; | 11935 | const scale_str = sib_it.next() orelse ""; |
| 11760 | if (index_str.len == 0 and scale_str.len > 0) | 11936 | if (index_str.len == 0 and scale_str.len > 0) |
| 11761 | return self.fail("invalid memory operand: '{s}'", .{op_str}); | 11937 | return self.fail("invalid memory operand: '{s}'", .{op_str}); |
| 11762 | const scale = if (scale_str.len > 0) switch (std.fmt.parseInt(u4, scale_str, 10) catch | 11938 | const scale: Memory.Scale = if (scale_str.len > 0) |
| 11763 | return self.fail("invalid scale: '{s}'", .{op_str})) { | 11939 | switch (std.fmt.parseInt(u4, scale_str, 10) catch |
| 11764 | 1, 2, 4, 8 => |scale| scale, | 11940 | return self.fail("invalid scale: '{s}'", .{op_str})) { |
| 11765 | else => return self.fail("invalid scale: '{s}'", .{op_str}), | 11941 | 1 => .@"1", |
| 11766 | } else 1; | 11942 | 2 => .@"2", |
| 11943 | 4 => .@"4", | ||
| 11944 | 8 => .@"8", | ||
| 11945 | else => return self.fail("invalid scale: '{s}'", .{op_str}), | ||
| 11946 | } | ||
| 11947 | else | ||
| 11948 | .@"1"; | ||
| 11767 | if (sib_it.next()) |_| return self.fail("invalid memory operand: '{s}'", .{op_str}); | 11949 | if (sib_it.next()) |_| return self.fail("invalid memory operand: '{s}'", .{op_str}); |
| 11768 | op.* = .{ .mem = Memory.sib(mnem_size orelse | 11950 | op.* = .{ |
| 11769 | return self.fail("unknown size: '{s}'", .{op_str}), .{ | 11951 | .mem = .{ |
| 11770 | .disp = if (mem.startsWith(u8, op_str[0..open], "%[") and | 11952 | .base = if (base_str.len > 0) |
| 11771 | mem.endsWith(u8, op_str[0..open], "]")) | 11953 | .{ .reg = parseRegName(base_str["%%".len..]) orelse |
| 11772 | disp: { | 11954 | return self.fail("invalid base register: '{s}'", .{base_str}) } |
| 11773 | const colon = mem.indexOfScalarPos(u8, op_str[0..open], "%[".len, ':'); | ||
| 11774 | const modifier = if (colon) |colon_pos| | ||
| 11775 | op_str[colon_pos + ":".len .. open - "]".len] | ||
| 11776 | else | 11955 | else |
| 11777 | ""; | 11956 | .none, |
| 11778 | break :disp switch (args.items[ | 11957 | .mod = .{ .rm = .{ |
| 11779 | arg_map.get(op_str["%[".len .. colon orelse open - "]".len]) orelse | 11958 | .size = mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}), |
| 11780 | return self.fail("no matching constraint: '{s}'", .{op_str}) | 11959 | .index = if (index_str.len > 0) |
| 11781 | ]) { | 11960 | parseRegName(index_str["%%".len..]) orelse |
| 11782 | .immediate => |imm| if (mem.eql(u8, modifier, "") or | 11961 | return self.fail("invalid index register: '{s}'", .{op_str}) |
| 11783 | mem.eql(u8, modifier, "c")) | 11962 | else |
| 11784 | math.cast(i32, @as(i64, @bitCast(imm))) orelse | 11963 | .none, |
| 11964 | .scale = scale, | ||
| 11965 | .disp = if (mem.startsWith(u8, op_str[0..open], "%[") and | ||
| 11966 | mem.endsWith(u8, op_str[0..open], "]")) | ||
| 11967 | disp: { | ||
| 11968 | const colon = mem.indexOfScalarPos(u8, op_str[0..open], "%[".len, ':'); | ||
| 11969 | const modifier = if (colon) |colon_pos| | ||
| 11970 | op_str[colon_pos + ":".len .. open - "]".len] | ||
| 11971 | else | ||
| 11972 | ""; | ||
| 11973 | break :disp switch (args.items[ | ||
| 11974 | arg_map.get(op_str["%[".len .. colon orelse open - "]".len]) orelse | ||
| 11975 | return self.fail("no matching constraint: '{s}'", .{op_str}) | ||
| 11976 | ]) { | ||
| 11977 | .immediate => |imm| if (mem.eql(u8, modifier, "") or | ||
| 11978 | mem.eql(u8, modifier, "c")) | ||
| 11979 | math.cast(i32, @as(i64, @bitCast(imm))) orelse | ||
| 11980 | return self.fail("invalid displacement: '{s}'", .{op_str}) | ||
| 11981 | else | ||
| 11982 | return self.fail("invalid modifier: '{s}'", .{modifier}), | ||
| 11983 | else => return self.fail("invalid constraint: '{s}'", .{op_str}), | ||
| 11984 | }; | ||
| 11985 | } else if (open > 0) | ||
| 11986 | std.fmt.parseInt(i32, op_str[0..open], 0) catch | ||
| 11785 | return self.fail("invalid displacement: '{s}'", .{op_str}) | 11987 | return self.fail("invalid displacement: '{s}'", .{op_str}) |
| 11786 | else | 11988 | else |
| 11787 | return self.fail("invalid modifier: '{s}'", .{modifier}), | 11989 | 0, |
| 11788 | else => return self.fail("invalid constraint: '{s}'", .{op_str}), | 11990 | } }, |
| 11789 | }; | 11991 | }, |
| 11790 | } else if (open > 0) | 11992 | }; |
| 11791 | std.fmt.parseInt(i32, op_str[0..open], 0) catch | ||
| 11792 | return self.fail("invalid displacement: '{s}'", .{op_str}) | ||
| 11793 | else | ||
| 11794 | 0, | ||
| 11795 | .base = if (base_str.len > 0) .{ .reg = parseRegName(base_str["%%".len..]) orelse | ||
| 11796 | return self.fail("invalid base register: '{s}'", .{base_str}) } else .none, | ||
| 11797 | .scale_index = if (index_str.len > 0) .{ | ||
| 11798 | .index = parseRegName(index_str["%%".len..]) orelse | ||
| 11799 | return self.fail("invalid index register: '{s}'", .{op_str}), | ||
| 11800 | .scale = scale, | ||
| 11801 | } else null, | ||
| 11802 | }) }; | ||
| 11803 | } else if (Label.isValid(.reference, op_str)) { | 11993 | } else if (Label.isValid(.reference, op_str)) { |
| 11804 | const anon = std.ascii.isDigit(op_str[0]); | 11994 | const anon = std.ascii.isDigit(op_str[0]); |
| 11805 | const label_gop = try labels.getOrPut(self.gpa, op_str[0..if (anon) 1 else op_str.len]); | 11995 | const label_gop = try labels.getOrPut(self.gpa, op_str[0..if (anon) 1 else op_str.len]); |
| ... | @@ -12519,20 +12709,23 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12519,20 +12709,23 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12519 | ), | 12709 | ), |
| 12520 | .lea_frame => .{ .move = .{ ._, .lea } }, | 12710 | .lea_frame => .{ .move = .{ ._, .lea } }, |
| 12521 | else => unreachable, | 12711 | else => unreachable, |
| 12522 | }).read(self, registerAlias(dst_reg, abi_size), Memory.sib( | 12712 | }).read(self, registerAlias(dst_reg, abi_size), switch (src_mcv) { |
| 12523 | self.memPtrSize(ty), | 12713 | .register_offset, .indirect => |reg_off| .{ |
| 12524 | switch (src_mcv) { | 12714 | .base = .{ .reg = reg_off.reg }, |
| 12525 | .register_offset, .indirect => |reg_off| .{ | 12715 | .mod = .{ .rm = .{ |
| 12526 | .base = .{ .reg = reg_off.reg }, | 12716 | .size = self.memSize(ty), |
| 12527 | .disp = reg_off.off, | 12717 | .disp = reg_off.off, |
| 12528 | }, | 12718 | } }, |
| 12529 | .load_frame, .lea_frame => |frame_addr| .{ | 12719 | }, |
| 12530 | .base = .{ .frame = frame_addr.index }, | 12720 | .load_frame, .lea_frame => |frame_addr| .{ |
| 12721 | .base = .{ .frame = frame_addr.index }, | ||
| 12722 | .mod = .{ .rm = .{ | ||
| 12723 | .size = self.memSize(ty), | ||
| 12531 | .disp = frame_addr.off, | 12724 | .disp = frame_addr.off, |
| 12532 | }, | 12725 | } }, |
| 12533 | else => unreachable, | ||
| 12534 | }, | 12726 | }, |
| 12535 | )), | 12727 | else => unreachable, |
| 12728 | }), | ||
| 12536 | .memory, .load_symbol, .load_direct, .load_got, .load_tlv => { | 12729 | .memory, .load_symbol, .load_direct, .load_got, .load_tlv => { |
| 12537 | switch (src_mcv) { | 12730 | switch (src_mcv) { |
| 12538 | .memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |small_addr| | 12731 | .memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |small_addr| |
| ... | @@ -12540,20 +12733,40 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12540,20 +12733,40 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12540 | ty, | 12733 | ty, |
| 12541 | dst_reg.class(), | 12734 | dst_reg.class(), |
| 12542 | ty.abiAlignment(mod).check(@as(u32, @bitCast(small_addr))), | 12735 | ty.abiAlignment(mod).check(@as(u32, @bitCast(small_addr))), |
| 12543 | )).read(self, registerAlias(dst_reg, abi_size), Memory.sib( | 12736 | )).read(self, registerAlias(dst_reg, abi_size), .{ |
| 12544 | self.memPtrSize(ty), | 12737 | .base = .{ .reg = .ds }, |
| 12545 | .{ .base = .{ .reg = .ds }, .disp = small_addr }, | 12738 | .mod = .{ .rm = .{ |
| 12546 | )), | 12739 | .size = self.memSize(ty), |
| 12740 | .disp = small_addr, | ||
| 12741 | } }, | ||
| 12742 | }), | ||
| 12743 | .load_symbol => |sym_off| switch (dst_reg.class()) { | ||
| 12744 | .general_purpose => { | ||
| 12745 | assert(sym_off.off == 0); | ||
| 12746 | try self.asmRegisterMemory(.{ ._, .mov }, registerAlias(dst_reg, abi_size), .{ | ||
| 12747 | .base = .{ .reloc = .{ | ||
| 12748 | .atom_index = try self.owner.getSymbolIndex(self), | ||
| 12749 | .sym_index = sym_off.sym, | ||
| 12750 | } }, | ||
| 12751 | .mod = .{ .rm = .{ | ||
| 12752 | .size = self.memSize(ty), | ||
| 12753 | .disp = sym_off.off, | ||
| 12754 | } }, | ||
| 12755 | }); | ||
| 12756 | return; | ||
| 12757 | }, | ||
| 12758 | .segment, .mmx => unreachable, | ||
| 12759 | .x87, .sse => {}, | ||
| 12760 | }, | ||
| 12547 | .load_direct => |sym_index| switch (dst_reg.class()) { | 12761 | .load_direct => |sym_index| switch (dst_reg.class()) { |
| 12548 | .general_purpose => { | 12762 | .general_purpose => { |
| 12549 | const atom_index = try self.owner.getSymbolIndex(self); | ||
| 12550 | _ = try self.addInst(.{ | 12763 | _ = try self.addInst(.{ |
| 12551 | .tag = .mov, | 12764 | .tag = .mov, |
| 12552 | .ops = .direct_reloc, | 12765 | .ops = .direct_reloc, |
| 12553 | .data = .{ .rx = .{ | 12766 | .data = .{ .rx = .{ |
| 12554 | .r1 = dst_reg.to64(), | 12767 | .r1 = registerAlias(dst_reg, abi_size), |
| 12555 | .payload = try self.addExtra(Mir.Reloc{ | 12768 | .payload = try self.addExtra(bits.Symbol{ |
| 12556 | .atom_index = atom_index, | 12769 | .atom_index = try self.owner.getSymbolIndex(self), |
| 12557 | .sym_index = sym_index, | 12770 | .sym_index = sym_index, |
| 12558 | }), | 12771 | }), |
| 12559 | } }, | 12772 | } }, |
| ... | @@ -12563,7 +12776,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12563,7 +12776,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12563 | .segment, .mmx => unreachable, | 12776 | .segment, .mmx => unreachable, |
| 12564 | .x87, .sse => {}, | 12777 | .x87, .sse => {}, |
| 12565 | }, | 12778 | }, |
| 12566 | .load_symbol, .load_got, .load_tlv => {}, | 12779 | .load_got, .load_tlv => {}, |
| 12567 | else => unreachable, | 12780 | else => unreachable, |
| 12568 | } | 12781 | } |
| 12569 | 12782 | ||
| ... | @@ -12574,22 +12787,42 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12574,22 +12787,42 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12574 | try (try self.moveStrategy(ty, dst_reg.class(), false)).read( | 12787 | try (try self.moveStrategy(ty, dst_reg.class(), false)).read( |
| 12575 | self, | 12788 | self, |
| 12576 | registerAlias(dst_reg, abi_size), | 12789 | registerAlias(dst_reg, abi_size), |
| 12577 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = .{ .reg = addr_reg } }), | 12790 | .{ |
| 12791 | .base = .{ .reg = addr_reg }, | ||
| 12792 | .mod = .{ .rm = .{ .size = self.memSize(ty) } }, | ||
| 12793 | }, | ||
| 12578 | ); | 12794 | ); |
| 12579 | }, | 12795 | }, |
| 12580 | .lea_symbol, .lea_direct, .lea_got => |sym_index| { | 12796 | .lea_symbol => |sym_index| { |
| 12581 | const atom_index = try self.owner.getSymbolIndex(self); | 12797 | const atom_index = try self.owner.getSymbolIndex(self); |
| 12582 | if (self.bin_file.cast(link.File.Elf)) |_| { | 12798 | if (self.bin_file.cast(link.File.Elf)) |_| { |
| 12583 | _ = try self.addInst(.{ | 12799 | try self.asmRegisterMemory( |
| 12584 | .tag = .lea, | 12800 | .{ ._, .lea }, |
| 12585 | .ops = .linker_reloc, | 12801 | dst_reg.to64(), |
| 12586 | .data = .{ .rx = .{ | 12802 | .{ |
| 12587 | .r1 = dst_reg.to64(), | 12803 | .base = .{ .reloc = .{ |
| 12588 | .payload = try self.addExtra(Mir.Reloc{ | ||
| 12589 | .atom_index = atom_index, | 12804 | .atom_index = atom_index, |
| 12590 | .sym_index = sym_index, | 12805 | .sym_index = sym_index.sym, |
| 12591 | }), | 12806 | } }, |
| 12807 | .mod = .{ .rm = .{ | ||
| 12808 | .size = .qword, | ||
| 12809 | .disp = sym_index.off, | ||
| 12810 | } }, | ||
| 12811 | }, | ||
| 12812 | ); | ||
| 12813 | } else return self.fail("TODO emit symbol sequence on {s}", .{ | ||
| 12814 | @tagName(self.bin_file.tag), | ||
| 12815 | }); | ||
| 12816 | }, | ||
| 12817 | .lea_direct, .lea_got => |sym_index| { | ||
| 12818 | const atom_index = try self.owner.getSymbolIndex(self); | ||
| 12819 | if (self.bin_file.cast(link.File.Elf)) |_| { | ||
| 12820 | try self.asmRegisterMemory(.{ ._, .lea }, dst_reg.to64(), .{ | ||
| 12821 | .base = .{ .reloc = .{ | ||
| 12822 | .atom_index = atom_index, | ||
| 12823 | .sym_index = sym_index, | ||
| 12592 | } }, | 12824 | } }, |
| 12825 | .mod = .{ .rm = .{ .size = .qword } }, | ||
| 12593 | }); | 12826 | }); |
| 12594 | } else { | 12827 | } else { |
| 12595 | _ = try self.addInst(.{ | 12828 | _ = try self.addInst(.{ |
| ... | @@ -12605,7 +12838,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12605,7 +12838,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12605 | }, | 12838 | }, |
| 12606 | .data = .{ .rx = .{ | 12839 | .data = .{ .rx = .{ |
| 12607 | .r1 = dst_reg.to64(), | 12840 | .r1 = dst_reg.to64(), |
| 12608 | .payload = try self.addExtra(Mir.Reloc{ | 12841 | .payload = try self.addExtra(bits.Symbol{ |
| 12609 | .atom_index = atom_index, | 12842 | .atom_index = atom_index, |
| 12610 | .sym_index = sym_index, | 12843 | .sym_index = sym_index, |
| 12611 | }), | 12844 | }), |
| ... | @@ -12621,14 +12854,17 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr | ... | @@ -12621,14 +12854,17 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 12621 | .ops = .tlv_reloc, | 12854 | .ops = .tlv_reloc, |
| 12622 | .data = .{ .rx = .{ | 12855 | .data = .{ .rx = .{ |
| 12623 | .r1 = .rdi, | 12856 | .r1 = .rdi, |
| 12624 | .payload = try self.addExtra(Mir.Reloc{ | 12857 | .payload = try self.addExtra(bits.Symbol{ |
| 12625 | .atom_index = atom_index, | 12858 | .atom_index = atom_index, |
| 12626 | .sym_index = sym_index, | 12859 | .sym_index = sym_index, |
| 12627 | }), | 12860 | }), |
| 12628 | } }, | 12861 | } }, |
| 12629 | }); | 12862 | }); |
| 12630 | // TODO: spill registers before calling | 12863 | // TODO: spill registers before calling |
| 12631 | try self.asmMemory(.{ ._, .call }, Memory.sib(.qword, .{ .base = .{ .reg = .rdi } })); | 12864 | try self.asmMemory(.{ ._, .call }, .{ |
| 12865 | .base = .{ .reg = .rdi }, | ||
| 12866 | .mod = .{ .rm = .{ .size = .qword } }, | ||
| 12867 | }); | ||
| 12632 | try self.genSetReg(dst_reg.to64(), Type.usize, .{ .register = .rax }); | 12868 | try self.genSetReg(dst_reg.to64(), Type.usize, .{ .register = .rax }); |
| 12633 | } else return self.fail("TODO emit ptr to TLV sequence on {s}", .{ | 12869 | } else return self.fail("TODO emit ptr to TLV sequence on {s}", .{ |
| 12634 | @tagName(self.bin_file.tag), | 12870 | @tagName(self.bin_file.tag), |
| ... | @@ -12645,6 +12881,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal | ... | @@ -12645,6 +12881,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal |
| 12645 | .none => .{ .immediate = @bitCast(@as(i64, disp)) }, | 12881 | .none => .{ .immediate = @bitCast(@as(i64, disp)) }, |
| 12646 | .reg => |base_reg| .{ .register_offset = .{ .reg = base_reg, .off = disp } }, | 12882 | .reg => |base_reg| .{ .register_offset = .{ .reg = base_reg, .off = disp } }, |
| 12647 | .frame => |base_frame_index| .{ .lea_frame = .{ .index = base_frame_index, .off = disp } }, | 12883 | .frame => |base_frame_index| .{ .lea_frame = .{ .index = base_frame_index, .off = disp } }, |
| 12884 | .reloc => |base_symbol| .{ .lea_symbol = .{ .sym = base_symbol.sym_index, .off = disp } }, | ||
| 12648 | }; | 12885 | }; |
| 12649 | switch (src_mcv) { | 12886 | switch (src_mcv) { |
| 12650 | .none, .unreach, .dead, .reserved_frame => unreachable, | 12887 | .none, .unreach, .dead, .reserved_frame => unreachable, |
| ... | @@ -12660,7 +12897,10 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal | ... | @@ -12660,7 +12897,10 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal |
| 12660 | }; | 12897 | }; |
| 12661 | try self.asmMemoryImmediate( | 12898 | try self.asmMemoryImmediate( |
| 12662 | .{ ._, .mov }, | 12899 | .{ ._, .mov }, |
| 12663 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base, .disp = disp }), | 12900 | .{ .base = base, .mod = .{ .rm = .{ |
| 12901 | .size = Memory.Size.fromSize(abi_size), | ||
| 12902 | .disp = disp, | ||
| 12903 | } } }, | ||
| 12664 | immediate, | 12904 | immediate, |
| 12665 | ); | 12905 | ); |
| 12666 | }, | 12906 | }, |
| ... | @@ -12668,27 +12908,31 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal | ... | @@ -12668,27 +12908,31 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal |
| 12668 | else => if (math.cast(i32, @as(i64, @bitCast(imm)))) |small| { | 12908 | else => if (math.cast(i32, @as(i64, @bitCast(imm)))) |small| { |
| 12669 | try self.asmMemoryImmediate( | 12909 | try self.asmMemoryImmediate( |
| 12670 | .{ ._, .mov }, | 12910 | .{ ._, .mov }, |
| 12671 | Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base, .disp = disp }), | 12911 | .{ .base = base, .mod = .{ .rm = .{ |
| 12912 | .size = Memory.Size.fromSize(abi_size), | ||
| 12913 | .disp = disp, | ||
| 12914 | } } }, | ||
| 12672 | Immediate.s(small), | 12915 | Immediate.s(small), |
| 12673 | ); | 12916 | ); |
| 12674 | } else { | 12917 | } else { |
| 12675 | var offset: i32 = 0; | 12918 | var offset: i32 = 0; |
| 12676 | while (offset < abi_size) : (offset += 4) try self.asmMemoryImmediate( | 12919 | while (offset < abi_size) : (offset += 4) try self.asmMemoryImmediate( |
| 12677 | .{ ._, .mov }, | 12920 | .{ ._, .mov }, |
| 12678 | Memory.sib(.dword, .{ .base = base, .disp = disp + offset }), | 12921 | .{ .base = base, .mod = .{ .rm = .{ |
| 12679 | if (ty.isSignedInt(mod)) | 12922 | .size = .dword, |
| 12680 | Immediate.s( | 12923 | .disp = disp + offset, |
| 12681 | @truncate(@as(i64, @bitCast(imm)) >> (math.cast(u6, offset * 8) orelse 63)), | 12924 | } } }, |
| 12682 | ) | 12925 | if (ty.isSignedInt(mod)) Immediate.s( |
| 12683 | else | 12926 | @truncate(@as(i64, @bitCast(imm)) >> (math.cast(u6, offset * 8) orelse 63)), |
| 12684 | Immediate.u(@as( | 12927 | ) else Immediate.u( |
| 12685 | u32, | 12928 | @as(u32, @truncate(if (math.cast(u6, offset * 8)) |shift| imm >> shift else 0)), |
| 12686 | @truncate(if (math.cast(u6, offset * 8)) |shift| imm >> shift else 0), | 12929 | ), |
| 12687 | )), | ||
| 12688 | ); | 12930 | ); |
| 12689 | }, | 12931 | }, |
| 12690 | }, | 12932 | }, |
| 12691 | .eflags => |cc| try self.asmSetccMemory(cc, Memory.sib(.byte, .{ .base = base, .disp = disp })), | 12933 | .eflags => |cc| try self.asmSetccMemory(cc, .{ .base = base, .mod = .{ |
| 12934 | .rm = .{ .size = .byte, .disp = disp }, | ||
| 12935 | } }), | ||
| 12692 | .register => |src_reg| try (try self.moveStrategy(ty, src_reg.class(), switch (base) { | 12936 | .register => |src_reg| try (try self.moveStrategy(ty, src_reg.class(), switch (base) { |
| 12693 | .none => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))), | 12937 | .none => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))), |
| 12694 | .reg => |reg| switch (reg) { | 12938 | .reg => |reg| switch (reg) { |
| ... | @@ -12698,9 +12942,13 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal | ... | @@ -12698,9 +12942,13 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal |
| 12698 | .frame => |frame_index| self.getFrameAddrAlignment( | 12942 | .frame => |frame_index| self.getFrameAddrAlignment( |
| 12699 | .{ .index = frame_index, .off = disp }, | 12943 | .{ .index = frame_index, .off = disp }, |
| 12700 | ).compare(.gte, ty.abiAlignment(mod)), | 12944 | ).compare(.gte, ty.abiAlignment(mod)), |
| 12945 | .reloc => false, | ||
| 12701 | })).write( | 12946 | })).write( |
| 12702 | self, | 12947 | self, |
| 12703 | Memory.sib(self.memPtrSize(ty), .{ .base = base, .disp = disp }), | 12948 | .{ .base = base, .mod = .{ .rm = .{ |
| 12949 | .size = self.memSize(ty), | ||
| 12950 | .disp = disp, | ||
| 12951 | } } }, | ||
| 12704 | registerAlias(src_reg, abi_size), | 12952 | registerAlias(src_reg, abi_size), |
| 12705 | ), | 12953 | ), |
| 12706 | .register_pair => |src_regs| for (src_regs, 0..) |src_reg, src_reg_i| { | 12954 | .register_pair => |src_regs| for (src_regs, 0..) |src_reg, src_reg_i| { |
| ... | @@ -12717,11 +12965,12 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal | ... | @@ -12717,11 +12965,12 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal |
| 12717 | .frame => |frame_index| self.getFrameAddrAlignment( | 12965 | .frame => |frame_index| self.getFrameAddrAlignment( |
| 12718 | .{ .index = frame_index, .off = disp }, | 12966 | .{ .index = frame_index, .off = disp }, |
| 12719 | ).compare(.gte, ty.abiAlignment(mod)), | 12967 | ).compare(.gte, ty.abiAlignment(mod)), |
| 12968 | .reloc => false, | ||
| 12720 | }, | 12969 | }, |
| 12721 | )).write(self, Memory.sib( | 12970 | )).write(self, .{ .base = base, .mod = .{ .rm = .{ |
| 12722 | Memory.PtrSize.fromSize(part_size), | 12971 | .size = Memory.Size.fromSize(part_size), |
| 12723 | .{ .base = base, .disp = disp + @as(i32, @intCast(src_reg_i * 8)) }, | 12972 | .disp = disp + @as(i32, @intCast(src_reg_i * 8)), |
| 12724 | ), registerAlias(src_reg, part_size)); | 12973 | } } }, registerAlias(src_reg, part_size)); |
| 12725 | }, | 12974 | }, |
| 12726 | .register_overflow => |ro| switch (ty.zigTypeTag(mod)) { | 12975 | .register_overflow => |ro| switch (ty.zigTypeTag(mod)) { |
| 12727 | .Struct => { | 12976 | .Struct => { |
| ... | @@ -12819,7 +13068,7 @@ fn genExternSymbolRef( | ... | @@ -12819,7 +13068,7 @@ fn genExternSymbolRef( |
| 12819 | .ops = .import_reloc, | 13068 | .ops = .import_reloc, |
| 12820 | .data = .{ .rx = .{ | 13069 | .data = .{ .rx = .{ |
| 12821 | .r1 = .rax, | 13070 | .r1 = .rax, |
| 12822 | .payload = try self.addExtra(Mir.Reloc{ | 13071 | .payload = try self.addExtra(bits.Symbol{ |
| 12823 | .atom_index = atom_index, | 13072 | .atom_index = atom_index, |
| 12824 | .sym_index = try coff_file.getGlobalSymbol(callee, lib), | 13073 | .sym_index = try coff_file.getGlobalSymbol(callee, lib), |
| 12825 | }), | 13074 | }), |
| ... | @@ -12856,8 +13105,12 @@ fn genLazySymbolRef( | ... | @@ -12856,8 +13105,12 @@ fn genLazySymbolRef( |
| 12856 | 13105 | ||
| 12857 | if (self.bin_file.options.pic) { | 13106 | if (self.bin_file.options.pic) { |
| 12858 | switch (tag) { | 13107 | switch (tag) { |
| 12859 | .lea, .call => try self.genSetReg(reg, Type.usize, .{ .load_symbol = sym.esym_index }), | 13108 | .lea, .call => try self.genSetReg(reg, Type.usize, .{ |
| 12860 | .mov => try self.genSetReg(reg, Type.usize, .{ .load_symbol = sym.esym_index }), | 13109 | .load_symbol = .{ .sym = sym.esym_index }, |
| 13110 | }), | ||
| 13111 | .mov => try self.genSetReg(reg, Type.usize, .{ | ||
| 13112 | .load_symbol = .{ .sym = sym.esym_index }, | ||
| 13113 | }), | ||
| 12861 | else => unreachable, | 13114 | else => unreachable, |
| 12862 | } | 13115 | } |
| 12863 | switch (tag) { | 13116 | switch (tag) { |
| ... | @@ -12866,23 +13119,18 @@ fn genLazySymbolRef( | ... | @@ -12866,23 +13119,18 @@ fn genLazySymbolRef( |
| 12866 | else => unreachable, | 13119 | else => unreachable, |
| 12867 | } | 13120 | } |
| 12868 | } else { | 13121 | } else { |
| 12869 | const reloc = Mir.Reloc{ | 13122 | const reloc = bits.Symbol{ |
| 12870 | .atom_index = try self.owner.getSymbolIndex(self), | 13123 | .atom_index = try self.owner.getSymbolIndex(self), |
| 12871 | .sym_index = sym.esym_index, | 13124 | .sym_index = sym.esym_index, |
| 12872 | }; | 13125 | }; |
| 12873 | switch (tag) { | 13126 | switch (tag) { |
| 12874 | .lea, .mov => _ = try self.addInst(.{ | 13127 | .lea, .mov => try self.asmRegisterMemory(.{ ._, .mov }, reg.to64(), .{ |
| 12875 | .tag = .mov, | 13128 | .base = .{ .reloc = reloc }, |
| 12876 | .ops = .linker_reloc, | 13129 | .mod = .{ .rm = .{ .size = .qword } }, |
| 12877 | .data = .{ .rx = .{ | ||
| 12878 | .r1 = reg.to64(), | ||
| 12879 | .payload = try self.addExtra(reloc), | ||
| 12880 | } }, | ||
| 12881 | }), | 13130 | }), |
| 12882 | .call => _ = try self.addInst(.{ | 13131 | .call => try self.asmMemory(.{ ._, .call }, .{ |
| 12883 | .tag = .call, | 13132 | .base = .{ .reloc = reloc }, |
| 12884 | .ops = .linker_reloc, | 13133 | .mod = .{ .rm = .{ .size = .qword } }, |
| 12885 | .data = .{ .reloc = reloc }, | ||
| 12886 | }), | 13134 | }), |
| 12887 | else => unreachable, | 13135 | else => unreachable, |
| 12888 | } | 13136 | } |
| ... | @@ -12893,8 +13141,13 @@ fn genLazySymbolRef( | ... | @@ -12893,8 +13141,13 @@ fn genLazySymbolRef( |
| 12893 | var atom = p9_file.getAtom(atom_index); | 13141 | var atom = p9_file.getAtom(atom_index); |
| 12894 | _ = atom.getOrCreateOffsetTableEntry(p9_file); | 13142 | _ = atom.getOrCreateOffsetTableEntry(p9_file); |
| 12895 | const got_addr = atom.getOffsetTableAddress(p9_file); | 13143 | const got_addr = atom.getOffsetTableAddress(p9_file); |
| 12896 | const got_mem = | 13144 | const got_mem: Memory = .{ |
| 12897 | Memory.sib(.qword, .{ .base = .{ .reg = .ds }, .disp = @intCast(got_addr) }); | 13145 | .base = .{ .reg = .ds }, |
| 13146 | .mod = .{ .rm = .{ | ||
| 13147 | .size = .qword, | ||
| 13148 | .disp = @intCast(got_addr), | ||
| 13149 | } }, | ||
| 13150 | }; | ||
| 12898 | switch (tag) { | 13151 | switch (tag) { |
| 12899 | .lea, .mov => try self.asmRegisterMemory(.{ ._, .mov }, reg.to64(), got_mem), | 13152 | .lea, .mov => try self.asmRegisterMemory(.{ ._, .mov }, reg.to64(), got_mem), |
| 12900 | .call => try self.asmMemory(.{ ._, .call }, got_mem), | 13153 | .call => try self.asmMemory(.{ ._, .call }, got_mem), |
| ... | @@ -13240,19 +13493,20 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -13240,19 +13493,20 @@ fn airCmpxchg(self: *Self, inst: Air.Inst.Index) !void { |
| 13240 | defer if (new_lock) |lock| self.register_manager.unlockReg(lock); | 13493 | defer if (new_lock) |lock| self.register_manager.unlockReg(lock); |
| 13241 | 13494 | ||
| 13242 | const ptr_mcv = try self.resolveInst(extra.ptr); | 13495 | const ptr_mcv = try self.resolveInst(extra.ptr); |
| 13243 | const ptr_size = Memory.PtrSize.fromSize(val_abi_size); | 13496 | const mem_size = Memory.Size.fromSize(val_abi_size); |
| 13244 | const ptr_mem = switch (ptr_mcv) { | 13497 | const ptr_mem: Memory = switch (ptr_mcv) { |
| 13245 | .immediate, .register, .register_offset, .lea_frame => ptr_mcv.deref().mem(ptr_size), | 13498 | .immediate, .register, .register_offset, .lea_frame => ptr_mcv.deref().mem(mem_size), |
| 13246 | else => Memory.sib(ptr_size, .{ | 13499 | else => .{ |
| 13247 | .base = .{ .reg = try self.copyToTmpRegister(ptr_ty, ptr_mcv) }, | 13500 | .base = .{ .reg = try self.copyToTmpRegister(ptr_ty, ptr_mcv) }, |
| 13248 | }), | 13501 | .mod = .{ .rm = .{ .size = mem_size } }, |
| 13502 | }, | ||
| 13249 | }; | 13503 | }; |
| 13250 | switch (ptr_mem) { | 13504 | switch (ptr_mem.mod) { |
| 13251 | .sib, .rip => {}, | 13505 | .rm => {}, |
| 13252 | .moffs => return self.fail("TODO airCmpxchg with {s}", .{@tagName(ptr_mcv)}), | 13506 | .off => return self.fail("TODO airCmpxchg with {s}", .{@tagName(ptr_mcv)}), |
| 13253 | } | 13507 | } |
| 13254 | const ptr_lock = switch (ptr_mem.base()) { | 13508 | const ptr_lock = switch (ptr_mem.base) { |
| 13255 | .none, .frame => null, | 13509 | .none, .frame, .reloc => null, |
| 13256 | .reg => |reg| self.register_manager.lockReg(reg), | 13510 | .reg => |reg| self.register_manager.lockReg(reg), |
| 13257 | }; | 13511 | }; |
| 13258 | defer if (ptr_lock) |lock| self.register_manager.unlockReg(lock); | 13512 | defer if (ptr_lock) |lock| self.register_manager.unlockReg(lock); |
| ... | @@ -13305,19 +13559,20 @@ fn atomicOp( | ... | @@ -13305,19 +13559,20 @@ fn atomicOp( |
| 13305 | defer if (val_lock) |lock| self.register_manager.unlockReg(lock); | 13559 | defer if (val_lock) |lock| self.register_manager.unlockReg(lock); |
| 13306 | 13560 | ||
| 13307 | const val_abi_size: u32 = @intCast(val_ty.abiSize(mod)); | 13561 | const val_abi_size: u32 = @intCast(val_ty.abiSize(mod)); |
| 13308 | const ptr_size = Memory.PtrSize.fromSize(val_abi_size); | 13562 | const mem_size = Memory.Size.fromSize(val_abi_size); |
| 13309 | const ptr_mem = switch (ptr_mcv) { | 13563 | const ptr_mem: Memory = switch (ptr_mcv) { |
| 13310 | .immediate, .register, .register_offset, .lea_frame => ptr_mcv.deref().mem(ptr_size), | 13564 | .immediate, .register, .register_offset, .lea_frame => ptr_mcv.deref().mem(mem_size), |
| 13311 | else => Memory.sib(ptr_size, .{ | 13565 | else => .{ |
| 13312 | .base = .{ .reg = try self.copyToTmpRegister(ptr_ty, ptr_mcv) }, | 13566 | .base = .{ .reg = try self.copyToTmpRegister(ptr_ty, ptr_mcv) }, |
| 13313 | }), | 13567 | .mod = .{ .rm = .{ .size = mem_size } }, |
| 13568 | }, | ||
| 13314 | }; | 13569 | }; |
| 13315 | switch (ptr_mem) { | 13570 | switch (ptr_mem.mod) { |
| 13316 | .sib, .rip => {}, | 13571 | .rm => {}, |
| 13317 | .moffs => return self.fail("TODO airCmpxchg with {s}", .{@tagName(ptr_mcv)}), | 13572 | .off => return self.fail("TODO airCmpxchg with {s}", .{@tagName(ptr_mcv)}), |
| 13318 | } | 13573 | } |
| 13319 | const mem_lock = switch (ptr_mem.base()) { | 13574 | const mem_lock = switch (ptr_mem.base) { |
| 13320 | .none, .frame => null, | 13575 | .none, .frame, .reloc => null, |
| 13321 | .reg => |reg| self.register_manager.lockReg(reg), | 13576 | .reg => |reg| self.register_manager.lockReg(reg), |
| 13322 | }; | 13577 | }; |
| 13323 | defer if (mem_lock) |lock| self.register_manager.unlockReg(lock); | 13578 | defer if (mem_lock) |lock| self.register_manager.unlockReg(lock); |
| ... | @@ -13425,7 +13680,7 @@ fn atomicOp( | ... | @@ -13425,7 +13680,7 @@ fn atomicOp( |
| 13425 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( | 13680 | .memory, .indirect, .load_frame => try self.asmCmovccRegisterMemory( |
| 13426 | cc, | 13681 | cc, |
| 13427 | registerAlias(tmp_reg, cmov_abi_size), | 13682 | registerAlias(tmp_reg, cmov_abi_size), |
| 13428 | val_mcv.mem(Memory.PtrSize.fromSize(cmov_abi_size)), | 13683 | val_mcv.mem(Memory.Size.fromSize(cmov_abi_size)), |
| 13429 | ), | 13684 | ), |
| 13430 | else => { | 13685 | else => { |
| 13431 | const val_reg = try self.copyToTmpRegister(val_ty, val_mcv); | 13686 | const val_reg = try self.copyToTmpRegister(val_ty, val_mcv); |
| ... | @@ -13446,16 +13701,24 @@ fn atomicOp( | ... | @@ -13446,16 +13701,24 @@ fn atomicOp( |
| 13446 | _ = try self.asmJccReloc(.ne, loop); | 13701 | _ = try self.asmJccReloc(.ne, loop); |
| 13447 | return if (unused) .unreach else .{ .register = .rax }; | 13702 | return if (unused) .unreach else .{ .register = .rax }; |
| 13448 | } else { | 13703 | } else { |
| 13449 | try self.asmRegisterMemory(.{ ._, .mov }, .rax, Memory.sib(.qword, .{ | 13704 | try self.asmRegisterMemory(.{ ._, .mov }, .rax, .{ |
| 13450 | .base = ptr_mem.sib.base, | 13705 | .base = ptr_mem.base, |
| 13451 | .scale_index = ptr_mem.scaleIndex(), | 13706 | .mod = .{ .rm = .{ |
| 13452 | .disp = ptr_mem.sib.disp + 0, | 13707 | .size = .qword, |
| 13453 | })); | 13708 | .index = ptr_mem.mod.rm.index, |
| 13454 | try self.asmRegisterMemory(.{ ._, .mov }, .rdx, Memory.sib(.qword, .{ | 13709 | .scale = ptr_mem.mod.rm.scale, |
| 13455 | .base = ptr_mem.sib.base, | 13710 | .disp = ptr_mem.mod.rm.disp + 0, |
| 13456 | .scale_index = ptr_mem.scaleIndex(), | 13711 | } }, |
| 13457 | .disp = ptr_mem.sib.disp + 8, | 13712 | }); |
| 13458 | })); | 13713 | try self.asmRegisterMemory(.{ ._, .mov }, .rdx, .{ |
| 13714 | .base = ptr_mem.base, | ||
| 13715 | .mod = .{ .rm = .{ | ||
| 13716 | .size = .qword, | ||
| 13717 | .index = ptr_mem.mod.rm.index, | ||
| 13718 | .scale = ptr_mem.mod.rm.scale, | ||
| 13719 | .disp = ptr_mem.mod.rm.disp + 8, | ||
| 13720 | } }, | ||
| 13721 | }); | ||
| 13459 | const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len); | 13722 | const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len); |
| 13460 | const val_mem_mcv: MCValue = switch (val_mcv) { | 13723 | const val_mem_mcv: MCValue = switch (val_mcv) { |
| 13461 | .memory, .indirect, .load_frame => val_mcv, | 13724 | .memory, .indirect, .load_frame => val_mcv, |
| ... | @@ -13509,22 +13772,20 @@ fn atomicOp( | ... | @@ -13509,22 +13772,20 @@ fn atomicOp( |
| 13509 | 13772 | ||
| 13510 | if (unused) return .unreach; | 13773 | if (unused) return .unreach; |
| 13511 | const dst_mcv = try self.allocTempRegOrMem(val_ty, false); | 13774 | const dst_mcv = try self.allocTempRegOrMem(val_ty, false); |
| 13512 | try self.asmMemoryRegister( | 13775 | try self.asmMemoryRegister(.{ ._, .mov }, .{ |
| 13513 | .{ ._, .mov }, | 13776 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 13514 | Memory.sib(.qword, .{ | 13777 | .mod = .{ .rm = .{ |
| 13515 | .base = .{ .frame = dst_mcv.load_frame.index }, | 13778 | .size = .qword, |
| 13516 | .disp = dst_mcv.load_frame.off + 0, | 13779 | .disp = dst_mcv.load_frame.off + 0, |
| 13517 | }), | 13780 | } }, |
| 13518 | .rax, | 13781 | }, .rax); |
| 13519 | ); | 13782 | try self.asmMemoryRegister(.{ ._, .mov }, .{ |
| 13520 | try self.asmMemoryRegister( | 13783 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 13521 | .{ ._, .mov }, | 13784 | .mod = .{ .rm = .{ |
| 13522 | Memory.sib(.qword, .{ | 13785 | .size = .qword, |
| 13523 | .base = .{ .frame = dst_mcv.load_frame.index }, | ||
| 13524 | .disp = dst_mcv.load_frame.off + 8, | 13786 | .disp = dst_mcv.load_frame.off + 8, |
| 13525 | }), | 13787 | } }, |
| 13526 | .rdx, | 13788 | }, .rdx); |
| 13527 | ); | ||
| 13528 | return dst_mcv; | 13789 | return dst_mcv; |
| 13529 | }, | 13790 | }, |
| 13530 | .libcall => return self.fail("TODO implement x86 atomic libcall", .{}), | 13791 | .libcall => return self.fail("TODO implement x86 atomic libcall", .{}), |
| ... | @@ -13830,55 +14091,74 @@ fn airErrorName(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -13830,55 +14091,74 @@ fn airErrorName(self: *Self, inst: Air.Inst.Index) !void { |
| 13830 | try self.asmRegisterMemory( | 14091 | try self.asmRegisterMemory( |
| 13831 | .{ ._, .mov }, | 14092 | .{ ._, .mov }, |
| 13832 | start_reg.to32(), | 14093 | start_reg.to32(), |
| 13833 | Memory.sib(.dword, .{ | 14094 | .{ |
| 13834 | .base = .{ .reg = addr_reg.to64() }, | 14095 | .base = .{ .reg = addr_reg.to64() }, |
| 13835 | .scale_index = .{ .scale = 4, .index = err_reg.to64() }, | 14096 | .mod = .{ .rm = .{ |
| 13836 | .disp = 4, | 14097 | .size = .dword, |
| 13837 | }), | 14098 | .index = err_reg.to64(), |
| 14099 | .scale = .@"4", | ||
| 14100 | .disp = 4, | ||
| 14101 | } }, | ||
| 14102 | }, | ||
| 13838 | ); | 14103 | ); |
| 13839 | try self.asmRegisterMemory( | 14104 | try self.asmRegisterMemory( |
| 13840 | .{ ._, .mov }, | 14105 | .{ ._, .mov }, |
| 13841 | end_reg.to32(), | 14106 | end_reg.to32(), |
| 13842 | Memory.sib(.dword, .{ | 14107 | .{ |
| 13843 | .base = .{ .reg = addr_reg.to64() }, | 14108 | .base = .{ .reg = addr_reg.to64() }, |
| 13844 | .scale_index = .{ .scale = 4, .index = err_reg.to64() }, | 14109 | .mod = .{ .rm = .{ |
| 13845 | .disp = 8, | 14110 | .size = .dword, |
| 13846 | }), | 14111 | .index = err_reg.to64(), |
| 14112 | .scale = .@"4", | ||
| 14113 | .disp = 8, | ||
| 14114 | } }, | ||
| 14115 | }, | ||
| 13847 | ); | 14116 | ); |
| 13848 | try self.asmRegisterRegister(.{ ._, .sub }, end_reg.to32(), start_reg.to32()); | 14117 | try self.asmRegisterRegister(.{ ._, .sub }, end_reg.to32(), start_reg.to32()); |
| 13849 | try self.asmRegisterMemory( | 14118 | try self.asmRegisterMemory( |
| 13850 | .{ ._, .lea }, | 14119 | .{ ._, .lea }, |
| 13851 | start_reg.to64(), | 14120 | start_reg.to64(), |
| 13852 | Memory.sib(.byte, .{ | 14121 | .{ |
| 13853 | .base = .{ .reg = addr_reg.to64() }, | 14122 | .base = .{ .reg = addr_reg.to64() }, |
| 13854 | .scale_index = .{ .scale = 1, .index = start_reg.to64() }, | 14123 | .mod = .{ .rm = .{ |
| 13855 | .disp = 0, | 14124 | .size = .dword, |
| 13856 | }), | 14125 | .index = start_reg.to64(), |
| 14126 | } }, | ||
| 14127 | }, | ||
| 13857 | ); | 14128 | ); |
| 13858 | try self.asmRegisterMemory( | 14129 | try self.asmRegisterMemory( |
| 13859 | .{ ._, .lea }, | 14130 | .{ ._, .lea }, |
| 13860 | end_reg.to32(), | 14131 | end_reg.to32(), |
| 13861 | Memory.sib(.byte, .{ | 14132 | .{ |
| 13862 | .base = .{ .reg = end_reg.to64() }, | 14133 | .base = .{ .reg = end_reg.to64() }, |
| 13863 | .disp = -1, | 14134 | .mod = .{ .rm = .{ |
| 13864 | }), | 14135 | .size = .byte, |
| 14136 | .disp = -1, | ||
| 14137 | } }, | ||
| 14138 | }, | ||
| 13865 | ); | 14139 | ); |
| 13866 | 14140 | ||
| 13867 | const dst_mcv = try self.allocRegOrMem(inst, false); | 14141 | const dst_mcv = try self.allocRegOrMem(inst, false); |
| 13868 | try self.asmMemoryRegister( | 14142 | try self.asmMemoryRegister( |
| 13869 | .{ ._, .mov }, | 14143 | .{ ._, .mov }, |
| 13870 | Memory.sib(.qword, .{ | 14144 | .{ |
| 13871 | .base = .{ .frame = dst_mcv.load_frame.index }, | 14145 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 13872 | .disp = dst_mcv.load_frame.off, | 14146 | .mod = .{ .rm = .{ |
| 13873 | }), | 14147 | .size = .qword, |
| 14148 | .disp = dst_mcv.load_frame.off, | ||
| 14149 | } }, | ||
| 14150 | }, | ||
| 13874 | start_reg.to64(), | 14151 | start_reg.to64(), |
| 13875 | ); | 14152 | ); |
| 13876 | try self.asmMemoryRegister( | 14153 | try self.asmMemoryRegister( |
| 13877 | .{ ._, .mov }, | 14154 | .{ ._, .mov }, |
| 13878 | Memory.sib(.qword, .{ | 14155 | .{ |
| 13879 | .base = .{ .frame = dst_mcv.load_frame.index }, | 14156 | .base = .{ .frame = dst_mcv.load_frame.index }, |
| 13880 | .disp = dst_mcv.load_frame.off + 8, | 14157 | .mod = .{ .rm = .{ |
| 13881 | }), | 14158 | .size = .qword, |
| 14159 | .disp = dst_mcv.load_frame.off + 8, | ||
| 14160 | } }, | ||
| 14161 | }, | ||
| 13882 | end_reg.to64(), | 14162 | end_reg.to64(), |
| 13883 | ); | 14163 | ); |
| 13884 | 14164 | ||
| ... | @@ -14115,7 +14395,7 @@ fn airReduce(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -14115,7 +14395,7 @@ fn airReduce(self: *Self, inst: Air.Inst.Index) !void { |
| 14115 | .Or => { | 14395 | .Or => { |
| 14116 | if (operand_mcv.isMemory()) try self.asmMemoryImmediate( | 14396 | if (operand_mcv.isMemory()) try self.asmMemoryImmediate( |
| 14117 | .{ ._, .@"test" }, | 14397 | .{ ._, .@"test" }, |
| 14118 | operand_mcv.mem(Memory.PtrSize.fromSize(abi_size)), | 14398 | operand_mcv.mem(Memory.Size.fromSize(abi_size)), |
| 14119 | Immediate.u(mask), | 14399 | Immediate.u(mask), |
| 14120 | ) else { | 14400 | ) else { |
| 14121 | const operand_reg = registerAlias(if (operand_mcv.isRegister()) | 14401 | const operand_reg = registerAlias(if (operand_mcv.isRegister()) |
| ... | @@ -14507,7 +14787,7 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -14507,7 +14787,7 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void { |
| 14507 | mir_tag, | 14787 | mir_tag, |
| 14508 | mop1_reg, | 14788 | mop1_reg, |
| 14509 | mop2_reg, | 14789 | mop2_reg, |
| 14510 | mops[2].mem(Memory.PtrSize.fromSize(abi_size)), | 14790 | mops[2].mem(Memory.Size.fromSize(abi_size)), |
| 14511 | ); | 14791 | ); |
| 14512 | break :result mops[0]; | 14792 | break :result mops[0]; |
| 14513 | }; | 14793 | }; |
| ... | @@ -14618,24 +14898,32 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -14618,24 +14898,32 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void { |
| 14618 | const mem_reloc = try self.asmJccReloc(.ae, undefined); | 14898 | const mem_reloc = try self.asmJccReloc(.ae, undefined); |
| 14619 | 14899 | ||
| 14620 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area); | 14900 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area); |
| 14621 | if (!unused) | 14901 | if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{ |
| 14622 | try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, Memory.sib(.qword, .{ | 14902 | .base = .{ .reg = addr_reg }, |
| 14623 | .base = .{ .reg = addr_reg }, | 14903 | .mod = .{ .rm = .{ |
| 14624 | .scale_index = .{ .scale = 1, .index = offset_reg.to64() }, | 14904 | .size = .qword, |
| 14625 | })); | 14905 | .index = offset_reg.to64(), |
| 14626 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg, Memory.sib(.qword, .{ | 14906 | } }, |
| 14907 | }); | ||
| 14908 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg, .{ | ||
| 14627 | .base = .{ .reg = offset_reg.to64() }, | 14909 | .base = .{ .reg = offset_reg.to64() }, |
| 14628 | .disp = 8, | 14910 | .mod = .{ .rm = .{ |
| 14629 | })); | 14911 | .size = .qword, |
| 14912 | .disp = 8, | ||
| 14913 | } }, | ||
| 14914 | }); | ||
| 14630 | try self.genCopy(Type.c_uint, gp_offset, .{ .register = offset_reg }); | 14915 | try self.genCopy(Type.c_uint, gp_offset, .{ .register = offset_reg }); |
| 14631 | const done_reloc = try self.asmJmpReloc(undefined); | 14916 | const done_reloc = try self.asmJmpReloc(undefined); |
| 14632 | 14917 | ||
| 14633 | try self.performReloc(mem_reloc); | 14918 | try self.performReloc(mem_reloc); |
| 14634 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area); | 14919 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area); |
| 14635 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), Memory.sib(.qword, .{ | 14920 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{ |
| 14636 | .base = .{ .reg = addr_reg }, | 14921 | .base = .{ .reg = addr_reg }, |
| 14637 | .disp = @intCast(@max(promote_ty.abiSize(mod), 8)), | 14922 | .mod = .{ .rm = .{ |
| 14638 | })); | 14923 | .size = .qword, |
| 14924 | .disp = @intCast(@max(promote_ty.abiSize(mod), 8)), | ||
| 14925 | } }, | ||
| 14926 | }); | ||
| 14639 | try self.genCopy( | 14927 | try self.genCopy( |
| 14640 | ptr_anyopaque_ty, | 14928 | ptr_anyopaque_ty, |
| 14641 | overflow_arg_area, | 14929 | overflow_arg_area, |
| ... | @@ -14657,24 +14945,32 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -14657,24 +14945,32 @@ fn airVaArg(self: *Self, inst: Air.Inst.Index) !void { |
| 14657 | const mem_reloc = try self.asmJccReloc(.ae, undefined); | 14945 | const mem_reloc = try self.asmJccReloc(.ae, undefined); |
| 14658 | 14946 | ||
| 14659 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area); | 14947 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, reg_save_area); |
| 14660 | if (!unused) | 14948 | if (!unused) try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, .{ |
| 14661 | try self.asmRegisterMemory(.{ ._, .lea }, addr_reg, Memory.sib(.qword, .{ | 14949 | .base = .{ .reg = addr_reg }, |
| 14662 | .base = .{ .reg = addr_reg }, | 14950 | .mod = .{ .rm = .{ |
| 14663 | .scale_index = .{ .scale = 1, .index = offset_reg.to64() }, | 14951 | .size = .qword, |
| 14664 | })); | 14952 | .index = offset_reg.to64(), |
| 14665 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg, Memory.sib(.qword, .{ | 14953 | } }, |
| 14954 | }); | ||
| 14955 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg, .{ | ||
| 14666 | .base = .{ .reg = offset_reg.to64() }, | 14956 | .base = .{ .reg = offset_reg.to64() }, |
| 14667 | .disp = 16, | 14957 | .mod = .{ .rm = .{ |
| 14668 | })); | 14958 | .size = .qword, |
| 14959 | .disp = 16, | ||
| 14960 | } }, | ||
| 14961 | }); | ||
| 14669 | try self.genCopy(Type.c_uint, fp_offset, .{ .register = offset_reg }); | 14962 | try self.genCopy(Type.c_uint, fp_offset, .{ .register = offset_reg }); |
| 14670 | const done_reloc = try self.asmJmpReloc(undefined); | 14963 | const done_reloc = try self.asmJmpReloc(undefined); |
| 14671 | 14964 | ||
| 14672 | try self.performReloc(mem_reloc); | 14965 | try self.performReloc(mem_reloc); |
| 14673 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area); | 14966 | try self.genSetReg(addr_reg, ptr_anyopaque_ty, overflow_arg_area); |
| 14674 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), Memory.sib(.qword, .{ | 14967 | try self.asmRegisterMemory(.{ ._, .lea }, offset_reg.to64(), .{ |
| 14675 | .base = .{ .reg = addr_reg }, | 14968 | .base = .{ .reg = addr_reg }, |
| 14676 | .disp = @intCast(@max(promote_ty.abiSize(mod), 8)), | 14969 | .mod = .{ .rm = .{ |
| 14677 | })); | 14970 | .size = .qword, |
| 14971 | .disp = @intCast(@max(promote_ty.abiSize(mod), 8)), | ||
| 14972 | } }, | ||
| 14973 | }); | ||
| 14678 | try self.genCopy( | 14974 | try self.genCopy( |
| 14679 | ptr_anyopaque_ty, | 14975 | ptr_anyopaque_ty, |
| 14680 | overflow_arg_area, | 14976 | overflow_arg_area, |
| ... | @@ -14823,7 +15119,7 @@ fn genTypedValue(self: *Self, arg_tv: TypedValue) InnerError!MCValue { | ... | @@ -14823,7 +15119,7 @@ fn genTypedValue(self: *Self, arg_tv: TypedValue) InnerError!MCValue { |
| 14823 | .undef => .undef, | 15119 | .undef => .undef, |
| 14824 | .immediate => |imm| .{ .immediate = imm }, | 15120 | .immediate => |imm| .{ .immediate = imm }, |
| 14825 | .memory => |addr| .{ .memory = addr }, | 15121 | .memory => |addr| .{ .memory = addr }, |
| 14826 | .load_symbol => |sym_index| .{ .load_symbol = sym_index }, | 15122 | .load_symbol => |sym_index| .{ .load_symbol = .{ .sym = sym_index } }, |
| 14827 | .load_direct => |sym_index| .{ .load_direct = sym_index }, | 15123 | .load_direct => |sym_index| .{ .load_direct = sym_index }, |
| 14828 | .load_got => |sym_index| .{ .lea_got = sym_index }, | 15124 | .load_got => |sym_index| .{ .lea_got = sym_index }, |
| 14829 | .load_tlv => |sym_index| .{ .lea_tlv = sym_index }, | 15125 | .load_tlv => |sym_index| .{ .lea_tlv = sym_index }, |
| ... | @@ -15167,11 +15463,11 @@ fn registerAlias(reg: Register, size_bytes: u32) Register { | ... | @@ -15167,11 +15463,11 @@ fn registerAlias(reg: Register, size_bytes: u32) Register { |
| 15167 | }; | 15463 | }; |
| 15168 | } | 15464 | } |
| 15169 | 15465 | ||
| 15170 | fn memPtrSize(self: *Self, ty: Type) Memory.PtrSize { | 15466 | fn memSize(self: *Self, ty: Type) Memory.Size { |
| 15171 | const mod = self.bin_file.options.module.?; | 15467 | const mod = self.bin_file.options.module.?; |
| 15172 | return switch (ty.zigTypeTag(mod)) { | 15468 | return switch (ty.zigTypeTag(mod)) { |
| 15173 | .Float => Memory.PtrSize.fromBitSize(ty.floatBits(self.target.*)), | 15469 | .Float => Memory.Size.fromBitSize(ty.floatBits(self.target.*)), |
| 15174 | else => Memory.PtrSize.fromSize(@intCast(ty.abiSize(mod))), | 15470 | else => Memory.Size.fromSize(@intCast(ty.abiSize(mod))), |
| 15175 | }; | 15471 | }; |
| 15176 | } | 15472 | } |
| 15177 | 15473 | ||
| ... | @@ -15183,11 +15479,10 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void { | ... | @@ -15183,11 +15479,10 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void { |
| 15183 | .signedness = .unsigned, | 15479 | .signedness = .unsigned, |
| 15184 | .bits = @intCast(ty.bitSize(mod)), | 15480 | .bits = @intCast(ty.bitSize(mod)), |
| 15185 | }; | 15481 | }; |
| 15186 | const max_reg_bit_width = Register.rax.bitSize(); | 15482 | const shift = math.cast(u6, 64 - int_info.bits % 64) orelse return; |
| 15187 | try self.spillEflagsIfOccupied(); | 15483 | try self.spillEflagsIfOccupied(); |
| 15188 | switch (int_info.signedness) { | 15484 | switch (int_info.signedness) { |
| 15189 | .signed => { | 15485 | .signed => { |
| 15190 | const shift: u6 = @intCast(max_reg_bit_width - int_info.bits); | ||
| 15191 | try self.genShiftBinOpMir( | 15486 | try self.genShiftBinOpMir( |
| 15192 | .{ ._l, .sa }, | 15487 | .{ ._l, .sa }, |
| 15193 | Type.isize, | 15488 | Type.isize, |
| ... | @@ -15202,7 +15497,6 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void { | ... | @@ -15202,7 +15497,6 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void { |
| 15202 | ); | 15497 | ); |
| 15203 | }, | 15498 | }, |
| 15204 | .unsigned => { | 15499 | .unsigned => { |
| 15205 | const shift: u6 = @intCast(max_reg_bit_width - int_info.bits); | ||
| 15206 | const mask = ~@as(u64, 0) >> shift; | 15500 | const mask = ~@as(u64, 0) >> shift; |
| 15207 | if (int_info.bits <= 32) { | 15501 | if (int_info.bits <= 32) { |
| 15208 | try self.genBinOpMir( | 15502 | try self.genBinOpMir( |
src/arch/x86_64/Disassembler.zig+1-1
| ... | @@ -11,7 +11,7 @@ const Encoding = @import("Encoding.zig"); | ... | @@ -11,7 +11,7 @@ const Encoding = @import("Encoding.zig"); |
| 11 | const Immediate = bits.Immediate; | 11 | const Immediate = bits.Immediate; |
| 12 | const Instruction = encoder.Instruction; | 12 | const Instruction = encoder.Instruction; |
| 13 | const LegacyPrefixes = encoder.LegacyPrefixes; | 13 | const LegacyPrefixes = encoder.LegacyPrefixes; |
| 14 | const Memory = bits.Memory; | 14 | const Memory = Instruction.Memory; |
| 15 | const Register = bits.Register; | 15 | const Register = bits.Register; |
| 16 | const Rex = encoder.Rex; | 16 | const Rex = encoder.Rex; |
| 17 | 17 |
src/arch/x86_64/Emit.zig+15-14
| ... | @@ -1,7 +1,6 @@ | ... | @@ -1,7 +1,6 @@ |
| 1 | //! This file contains the functionality for emitting x86_64 MIR as machine code | 1 | //! This file contains the functionality for emitting x86_64 MIR as machine code |
| 2 | 2 | ||
| 3 | lower: Lower, | 3 | lower: Lower, |
| 4 | bin_file: *link.File, | ||
| 5 | debug_output: DebugInfoOutput, | 4 | debug_output: DebugInfoOutput, |
| 6 | code: *std.ArrayList(u8), | 5 | code: *std.ArrayList(u8), |
| 7 | 6 | ||
| ... | @@ -41,7 +40,7 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -41,7 +40,7 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 41 | .offset = end_offset - 4, | 40 | .offset = end_offset - 4, |
| 42 | .length = @intCast(end_offset - start_offset), | 41 | .length = @intCast(end_offset - start_offset), |
| 43 | }), | 42 | }), |
| 44 | .linker_extern_fn => |symbol| if (emit.bin_file.cast(link.File.Elf)) |elf_file| { | 43 | .linker_extern_fn => |symbol| if (emit.lower.bin_file.cast(link.File.Elf)) |elf_file| { |
| 45 | // Add relocation to the decl. | 44 | // Add relocation to the decl. |
| 46 | const atom_ptr = elf_file.symbol(symbol.atom_index).atom(elf_file).?; | 45 | const atom_ptr = elf_file.symbol(symbol.atom_index).atom(elf_file).?; |
| 47 | try atom_ptr.addReloc(elf_file, .{ | 46 | try atom_ptr.addReloc(elf_file, .{ |
| ... | @@ -49,9 +48,10 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -49,9 +48,10 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 49 | .r_info = (@as(u64, @intCast(symbol.sym_index)) << 32) | std.elf.R_X86_64_PLT32, | 48 | .r_info = (@as(u64, @intCast(symbol.sym_index)) << 32) | std.elf.R_X86_64_PLT32, |
| 50 | .r_addend = -4, | 49 | .r_addend = -4, |
| 51 | }); | 50 | }); |
| 52 | } else if (emit.bin_file.cast(link.File.MachO)) |macho_file| { | 51 | } else if (emit.lower.bin_file.cast(link.File.MachO)) |macho_file| { |
| 53 | // Add relocation to the decl. | 52 | // Add relocation to the decl. |
| 54 | const atom_index = macho_file.getAtomIndexForSymbol(.{ .sym_index = symbol.atom_index }).?; | 53 | const atom_index = |
| 54 | macho_file.getAtomIndexForSymbol(.{ .sym_index = symbol.atom_index }).?; | ||
| 55 | const target = macho_file.getGlobalByIndex(symbol.sym_index); | 55 | const target = macho_file.getGlobalByIndex(symbol.sym_index); |
| 56 | try link.File.MachO.Atom.addRelocation(macho_file, atom_index, .{ | 56 | try link.File.MachO.Atom.addRelocation(macho_file, atom_index, .{ |
| 57 | .type = .branch, | 57 | .type = .branch, |
| ... | @@ -61,7 +61,7 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -61,7 +61,7 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 61 | .pcrel = true, | 61 | .pcrel = true, |
| 62 | .length = 2, | 62 | .length = 2, |
| 63 | }); | 63 | }); |
| 64 | } else if (emit.bin_file.cast(link.File.Coff)) |coff_file| { | 64 | } else if (emit.lower.bin_file.cast(link.File.Coff)) |coff_file| { |
| 65 | // Add relocation to the decl. | 65 | // Add relocation to the decl. |
| 66 | const atom_index = coff_file.getAtomIndexForSymbol( | 66 | const atom_index = coff_file.getAtomIndexForSymbol( |
| 67 | .{ .sym_index = symbol.atom_index, .file = null }, | 67 | .{ .sym_index = symbol.atom_index, .file = null }, |
| ... | @@ -76,12 +76,12 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -76,12 +76,12 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 76 | .length = 2, | 76 | .length = 2, |
| 77 | }); | 77 | }); |
| 78 | } else return emit.fail("TODO implement extern reloc for {s}", .{ | 78 | } else return emit.fail("TODO implement extern reloc for {s}", .{ |
| 79 | @tagName(emit.bin_file.tag), | 79 | @tagName(emit.lower.bin_file.tag), |
| 80 | }), | 80 | }), |
| 81 | .linker_reloc => |data| if (emit.bin_file.cast(link.File.Elf)) |elf_file| { | 81 | .linker_reloc => |data| if (emit.lower.bin_file.cast(link.File.Elf)) |elf_file| { |
| 82 | const atom = elf_file.symbol(data.atom_index).atom(elf_file).?; | 82 | const atom = elf_file.symbol(data.atom_index).atom(elf_file).?; |
| 83 | const sym = elf_file.symbol(elf_file.zigModulePtr().symbol(data.sym_index)); | 83 | const sym = elf_file.symbol(elf_file.zigModulePtr().symbol(data.sym_index)); |
| 84 | if (emit.bin_file.options.pic) { | 84 | if (emit.lower.bin_file.options.pic) { |
| 85 | const r_type: u32 = if (sym.flags.has_zig_got) | 85 | const r_type: u32 = if (sym.flags.has_zig_got) |
| 86 | link.File.Elf.R_X86_64_ZIG_GOTPCREL | 86 | link.File.Elf.R_X86_64_ZIG_GOTPCREL |
| 87 | else if (sym.flags.needs_got) | 87 | else if (sym.flags.needs_got) |
| ... | @@ -111,10 +111,11 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -111,10 +111,11 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 111 | .linker_direct, | 111 | .linker_direct, |
| 112 | .linker_import, | 112 | .linker_import, |
| 113 | .linker_tlv, | 113 | .linker_tlv, |
| 114 | => |symbol| if (emit.bin_file.cast(link.File.Elf)) |_| { | 114 | => |symbol| if (emit.lower.bin_file.cast(link.File.Elf)) |_| { |
| 115 | unreachable; | 115 | unreachable; |
| 116 | } else if (emit.bin_file.cast(link.File.MachO)) |macho_file| { | 116 | } else if (emit.lower.bin_file.cast(link.File.MachO)) |macho_file| { |
| 117 | const atom_index = macho_file.getAtomIndexForSymbol(.{ .sym_index = symbol.atom_index }).?; | 117 | const atom_index = |
| 118 | macho_file.getAtomIndexForSymbol(.{ .sym_index = symbol.atom_index }).?; | ||
| 118 | try link.File.MachO.Atom.addRelocation(macho_file, atom_index, .{ | 119 | try link.File.MachO.Atom.addRelocation(macho_file, atom_index, .{ |
| 119 | .type = switch (lowered_relocs[0].target) { | 120 | .type = switch (lowered_relocs[0].target) { |
| 120 | .linker_got => .got, | 121 | .linker_got => .got, |
| ... | @@ -128,7 +129,7 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -128,7 +129,7 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 128 | .pcrel = true, | 129 | .pcrel = true, |
| 129 | .length = 2, | 130 | .length = 2, |
| 130 | }); | 131 | }); |
| 131 | } else if (emit.bin_file.cast(link.File.Coff)) |coff_file| { | 132 | } else if (emit.lower.bin_file.cast(link.File.Coff)) |coff_file| { |
| 132 | const atom_index = coff_file.getAtomIndexForSymbol(.{ | 133 | const atom_index = coff_file.getAtomIndexForSymbol(.{ |
| 133 | .sym_index = symbol.atom_index, | 134 | .sym_index = symbol.atom_index, |
| 134 | .file = null, | 135 | .file = null, |
| ... | @@ -152,7 +153,7 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -152,7 +153,7 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 152 | .pcrel = true, | 153 | .pcrel = true, |
| 153 | .length = 2, | 154 | .length = 2, |
| 154 | }); | 155 | }); |
| 155 | } else if (emit.bin_file.cast(link.File.Plan9)) |p9_file| { | 156 | } else if (emit.lower.bin_file.cast(link.File.Plan9)) |p9_file| { |
| 156 | const atom_index = symbol.atom_index; | 157 | const atom_index = symbol.atom_index; |
| 157 | try p9_file.addReloc(atom_index, .{ // TODO we may need to add a .type field to the relocs if they are .linker_got instead of just .linker_direct | 158 | try p9_file.addReloc(atom_index, .{ // TODO we may need to add a .type field to the relocs if they are .linker_got instead of just .linker_direct |
| 158 | .target = symbol.sym_index, // we set sym_index to just be the atom index | 159 | .target = symbol.sym_index, // we set sym_index to just be the atom index |
| ... | @@ -161,7 +162,7 @@ pub fn emitMir(emit: *Emit) Error!void { | ... | @@ -161,7 +162,7 @@ pub fn emitMir(emit: *Emit) Error!void { |
| 161 | .type = .pcrel, | 162 | .type = .pcrel, |
| 162 | }); | 163 | }); |
| 163 | } else return emit.fail("TODO implement linker reloc for {s}", .{ | 164 | } else return emit.fail("TODO implement linker reloc for {s}", .{ |
| 164 | @tagName(emit.bin_file.tag), | 165 | @tagName(emit.lower.bin_file.tag), |
| 165 | }), | 166 | }), |
| 166 | }; | 167 | }; |
| 167 | } | 168 | } |
src/arch/x86_64/Encoding.zig+4-1
| ... | @@ -803,7 +803,10 @@ fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Op | ... | @@ -803,7 +803,10 @@ fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Op |
| 803 | @memcpy(inst.ops[0..ops.len], ops); | 803 | @memcpy(inst.ops[0..ops.len], ops); |
| 804 | 804 | ||
| 805 | var cwriter = std.io.countingWriter(std.io.null_writer); | 805 | var cwriter = std.io.countingWriter(std.io.null_writer); |
| 806 | inst.encode(cwriter.writer(), .{ .allow_frame_loc = true }) catch unreachable; // Not allowed to fail here unless OOM. | 806 | inst.encode(cwriter.writer(), .{ |
| 807 | .allow_frame_locs = true, | ||
| 808 | .allow_symbols = true, | ||
| 809 | }) catch unreachable; // Not allowed to fail here unless OOM. | ||
| 807 | return @as(usize, @intCast(cwriter.bytes_written)); | 810 | return @as(usize, @intCast(cwriter.bytes_written)); |
| 808 | } | 811 | } |
| 809 | 812 |
src/arch/x86_64/Lower.zig+90-181
| ... | @@ -50,12 +50,12 @@ pub const Reloc = struct { | ... | @@ -50,12 +50,12 @@ pub const Reloc = struct { |
| 50 | 50 | ||
| 51 | const Target = union(enum) { | 51 | const Target = union(enum) { |
| 52 | inst: Mir.Inst.Index, | 52 | inst: Mir.Inst.Index, |
| 53 | linker_reloc: Mir.Reloc, | 53 | linker_reloc: bits.Symbol, |
| 54 | linker_extern_fn: Mir.Reloc, | 54 | linker_extern_fn: bits.Symbol, |
| 55 | linker_got: Mir.Reloc, | 55 | linker_got: bits.Symbol, |
| 56 | linker_direct: Mir.Reloc, | 56 | linker_direct: bits.Symbol, |
| 57 | linker_import: Mir.Reloc, | 57 | linker_import: bits.Symbol, |
| 58 | linker_tlv: Mir.Reloc, | 58 | linker_tlv: bits.Symbol, |
| 59 | }; | 59 | }; |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| ... | @@ -99,17 +99,15 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { | ... | @@ -99,17 +99,15 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { |
| 99 | .{ .reg = inst.data.rr.r2 }, | 99 | .{ .reg = inst.data.rr.r2 }, |
| 100 | }); | 100 | }); |
| 101 | }, | 101 | }, |
| 102 | .pseudo_cmov_nz_or_p_rm_sib, | 102 | .pseudo_cmov_nz_or_p_rm => { |
| 103 | .pseudo_cmov_nz_or_p_rm_rip, | ||
| 104 | => { | ||
| 105 | assert(inst.data.rx.fixes == ._); | 103 | assert(inst.data.rx.fixes == ._); |
| 106 | try lower.emit(.none, .cmovnz, &.{ | 104 | try lower.emit(.none, .cmovnz, &.{ |
| 107 | .{ .reg = inst.data.rx.r1 }, | 105 | .{ .reg = inst.data.rx.r1 }, |
| 108 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 106 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 109 | }); | 107 | }); |
| 110 | try lower.emit(.none, .cmovp, &.{ | 108 | try lower.emit(.none, .cmovp, &.{ |
| 111 | .{ .reg = inst.data.rx.r1 }, | 109 | .{ .reg = inst.data.rx.r1 }, |
| 112 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 110 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 113 | }); | 111 | }); |
| 114 | }, | 112 | }, |
| 115 | .pseudo_set_z_and_np_r => { | 113 | .pseudo_set_z_and_np_r => { |
| ... | @@ -125,18 +123,16 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { | ... | @@ -125,18 +123,16 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { |
| 125 | .{ .reg = inst.data.rr.r2 }, | 123 | .{ .reg = inst.data.rr.r2 }, |
| 126 | }); | 124 | }); |
| 127 | }, | 125 | }, |
| 128 | .pseudo_set_z_and_np_m_sib, | 126 | .pseudo_set_z_and_np_m => { |
| 129 | .pseudo_set_z_and_np_m_rip, | ||
| 130 | => { | ||
| 131 | assert(inst.data.rx.fixes == ._); | 127 | assert(inst.data.rx.fixes == ._); |
| 132 | try lower.emit(.none, .setz, &.{ | 128 | try lower.emit(.none, .setz, &.{ |
| 133 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 129 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 134 | }); | 130 | }); |
| 135 | try lower.emit(.none, .setnp, &.{ | 131 | try lower.emit(.none, .setnp, &.{ |
| 136 | .{ .reg = inst.data.rx.r1 }, | 132 | .{ .reg = inst.data.rx.r1 }, |
| 137 | }); | 133 | }); |
| 138 | try lower.emit(.none, .@"and", &.{ | 134 | try lower.emit(.none, .@"and", &.{ |
| 139 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 135 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 140 | .{ .reg = inst.data.rx.r1 }, | 136 | .{ .reg = inst.data.rx.r1 }, |
| 141 | }); | 137 | }); |
| 142 | }, | 138 | }, |
| ... | @@ -153,18 +149,16 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { | ... | @@ -153,18 +149,16 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct { |
| 153 | .{ .reg = inst.data.rr.r2 }, | 149 | .{ .reg = inst.data.rr.r2 }, |
| 154 | }); | 150 | }); |
| 155 | }, | 151 | }, |
| 156 | .pseudo_set_nz_or_p_m_sib, | 152 | .pseudo_set_nz_or_p_m => { |
| 157 | .pseudo_set_nz_or_p_m_rip, | ||
| 158 | => { | ||
| 159 | assert(inst.data.rx.fixes == ._); | 153 | assert(inst.data.rx.fixes == ._); |
| 160 | try lower.emit(.none, .setnz, &.{ | 154 | try lower.emit(.none, .setnz, &.{ |
| 161 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 155 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 162 | }); | 156 | }); |
| 163 | try lower.emit(.none, .setp, &.{ | 157 | try lower.emit(.none, .setp, &.{ |
| 164 | .{ .reg = inst.data.rx.r1 }, | 158 | .{ .reg = inst.data.rx.r1 }, |
| 165 | }); | 159 | }); |
| 166 | try lower.emit(.none, .@"or", &.{ | 160 | try lower.emit(.none, .@"or", &.{ |
| 167 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 161 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 168 | .{ .reg = inst.data.rx.r1 }, | 162 | .{ .reg = inst.data.rx.r1 }, |
| 169 | }); | 163 | }); |
| 170 | }, | 164 | }, |
| ... | @@ -289,28 +283,20 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate { | ... | @@ -289,28 +283,20 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate { |
| 289 | .rri_s, | 283 | .rri_s, |
| 290 | .ri_s, | 284 | .ri_s, |
| 291 | .i_s, | 285 | .i_s, |
| 292 | .mi_sib_s, | 286 | .mi_s, |
| 293 | .mi_rip_s, | 287 | .rmi_s, |
| 294 | .rmi_sib_s, | ||
| 295 | .rmi_rip_s, | ||
| 296 | => Immediate.s(@bitCast(i)), | 288 | => Immediate.s(@bitCast(i)), |
| 297 | 289 | ||
| 298 | .rrri, | 290 | .rrri, |
| 299 | .rri_u, | 291 | .rri_u, |
| 300 | .ri_u, | 292 | .ri_u, |
| 301 | .i_u, | 293 | .i_u, |
| 302 | .mi_sib_u, | 294 | .mi_u, |
| 303 | .mi_rip_u, | 295 | .rmi, |
| 304 | .rmi_sib, | 296 | .rmi_u, |
| 305 | .rmi_rip, | 297 | .mri, |
| 306 | .rmi_sib_u, | 298 | .rrm, |
| 307 | .rmi_rip_u, | 299 | .rrmi, |
| 308 | .mri_sib, | ||
| 309 | .mri_rip, | ||
| 310 | .rrm_sib, | ||
| 311 | .rrm_rip, | ||
| 312 | .rrmi_sib, | ||
| 313 | .rrmi_rip, | ||
| 314 | => Immediate.u(i), | 300 | => Immediate.u(i), |
| 315 | 301 | ||
| 316 | .ri64 => Immediate.u(lower.mir.extraData(Mir.Imm64, i).data.decode()), | 302 | .ri64 => Immediate.u(lower.mir.extraData(Mir.Imm64, i).data.decode()), |
| ... | @@ -319,50 +305,8 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate { | ... | @@ -319,50 +305,8 @@ fn imm(lower: Lower, ops: Mir.Inst.Ops, i: u32) Immediate { |
| 319 | }; | 305 | }; |
| 320 | } | 306 | } |
| 321 | 307 | ||
| 322 | fn mem(lower: Lower, ops: Mir.Inst.Ops, payload: u32) Memory { | 308 | fn mem(lower: Lower, payload: u32) Memory { |
| 323 | return lower.mir.resolveFrameLoc(switch (ops) { | 309 | return lower.mir.resolveFrameLoc(lower.mir.extraData(Mir.Memory, payload).data).decode(); |
| 324 | .rm_sib, | ||
| 325 | .rmi_sib, | ||
| 326 | .rmi_sib_s, | ||
| 327 | .rmi_sib_u, | ||
| 328 | .m_sib, | ||
| 329 | .mi_sib_u, | ||
| 330 | .mi_sib_s, | ||
| 331 | .mr_sib, | ||
| 332 | .mrr_sib, | ||
| 333 | .mri_sib, | ||
| 334 | .rrm_sib, | ||
| 335 | .rrmi_sib, | ||
| 336 | |||
| 337 | .pseudo_cmov_nz_or_p_rm_sib, | ||
| 338 | .pseudo_set_z_and_np_m_sib, | ||
| 339 | .pseudo_set_nz_or_p_m_sib, | ||
| 340 | => lower.mir.extraData(Mir.MemorySib, payload).data.decode(), | ||
| 341 | |||
| 342 | .rm_rip, | ||
| 343 | .rmi_rip, | ||
| 344 | .rmi_rip_s, | ||
| 345 | .rmi_rip_u, | ||
| 346 | .m_rip, | ||
| 347 | .mi_rip_u, | ||
| 348 | .mi_rip_s, | ||
| 349 | .mr_rip, | ||
| 350 | .mrr_rip, | ||
| 351 | .mri_rip, | ||
| 352 | .rrm_rip, | ||
| 353 | .rrmi_rip, | ||
| 354 | |||
| 355 | .pseudo_cmov_nz_or_p_rm_rip, | ||
| 356 | .pseudo_set_z_and_np_m_rip, | ||
| 357 | .pseudo_set_nz_or_p_m_rip, | ||
| 358 | => lower.mir.extraData(Mir.MemoryRip, payload).data.decode(), | ||
| 359 | |||
| 360 | .rax_moffs, | ||
| 361 | .moffs_rax, | ||
| 362 | => lower.mir.extraData(Mir.MemoryMoffs, payload).data.decode(), | ||
| 363 | |||
| 364 | else => unreachable, | ||
| 365 | }); | ||
| 366 | } | 310 | } |
| 367 | 311 | ||
| 368 | fn reloc(lower: *Lower, target: Reloc.Target) Immediate { | 312 | fn reloc(lower: *Lower, target: Reloc.Target) Immediate { |
| ... | @@ -375,7 +319,42 @@ fn reloc(lower: *Lower, target: Reloc.Target) Immediate { | ... | @@ -375,7 +319,42 @@ fn reloc(lower: *Lower, target: Reloc.Target) Immediate { |
| 375 | } | 319 | } |
| 376 | 320 | ||
| 377 | fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand) Error!void { | 321 | fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand) Error!void { |
| 378 | lower.result_insts[lower.result_insts_len] = try Instruction.new(prefix, mnemonic, ops); | 322 | var emit_prefix = prefix; |
| 323 | var emit_mnemonic = mnemonic; | ||
| 324 | var emit_ops_storage: [4]Operand = undefined; | ||
| 325 | const emit_ops = emit_ops_storage[0..ops.len]; | ||
| 326 | for (emit_ops, ops) |*emit_op, op| { | ||
| 327 | emit_op.* = switch (op) { | ||
| 328 | else => op, | ||
| 329 | .mem => |mem_op| switch (mem_op.base()) { | ||
| 330 | else => op, | ||
| 331 | .reloc => |sym| op: { | ||
| 332 | assert(prefix == .none); | ||
| 333 | assert(mem_op.sib.disp == 0); | ||
| 334 | assert(mem_op.sib.scale_index.scale == 0); | ||
| 335 | _ = lower.reloc(.{ .linker_reloc = sym }); | ||
| 336 | break :op if (lower.bin_file.options.pic) switch (mnemonic) { | ||
| 337 | .mov, .lea => .{ .mem = Memory.rip(mem_op.sib.ptr_size, 0) }, | ||
| 338 | else => unreachable, | ||
| 339 | } else switch (mnemonic) { | ||
| 340 | .call => .{ .mem = Memory.sib(mem_op.sib.ptr_size, .{ | ||
| 341 | .base = .{ .reg = .ds }, | ||
| 342 | }) }, | ||
| 343 | .lea => { | ||
| 344 | emit_mnemonic = .mov; | ||
| 345 | break :op .{ .imm = Immediate.s(0) }; | ||
| 346 | }, | ||
| 347 | .mov => .{ .mem = Memory.sib(mem_op.sib.ptr_size, .{ | ||
| 348 | .base = .{ .reg = .ds }, | ||
| 349 | }) }, | ||
| 350 | else => unreachable, | ||
| 351 | }; | ||
| 352 | }, | ||
| 353 | }, | ||
| 354 | }; | ||
| 355 | } | ||
| 356 | lower.result_insts[lower.result_insts_len] = | ||
| 357 | try Instruction.new(emit_prefix, emit_mnemonic, emit_ops); | ||
| 379 | lower.result_insts_len += 1; | 358 | lower.result_insts_len += 1; |
| 380 | } | 359 | } |
| 381 | 360 | ||
| ... | @@ -391,74 +370,13 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void { | ... | @@ -391,74 +370,13 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void { |
| 391 | .rrri => inst.data.rrri.fixes, | 370 | .rrri => inst.data.rrri.fixes, |
| 392 | .rri_s, .rri_u => inst.data.rri.fixes, | 371 | .rri_s, .rri_u => inst.data.rri.fixes, |
| 393 | .ri_s, .ri_u => inst.data.ri.fixes, | 372 | .ri_s, .ri_u => inst.data.ri.fixes, |
| 394 | .ri64, | 373 | .ri64, .rm, .rmi_s, .mr => inst.data.rx.fixes, |
| 395 | .rm_sib, | 374 | .mrr, .rrm => inst.data.rrx.fixes, |
| 396 | .rm_rip, | 375 | .rmi, .mri => inst.data.rix.fixes, |
| 397 | .rmi_sib_s, | 376 | .rrmi => inst.data.rrix.fixes, |
| 398 | .rmi_sib_u, | 377 | .mi_u, .mi_s => inst.data.x.fixes, |
| 399 | .rmi_rip_s, | 378 | .m => inst.data.x.fixes, |
| 400 | .rmi_rip_u, | 379 | .extern_fn_reloc, .got_reloc, .direct_reloc, .import_reloc, .tlv_reloc => ._, |
| 401 | .mr_sib, | ||
| 402 | .mr_rip, | ||
| 403 | => inst.data.rx.fixes, | ||
| 404 | .mrr_sib, .mrr_rip, .rrm_sib, .rrm_rip => inst.data.rrx.fixes, | ||
| 405 | .rmi_sib, .rmi_rip, .mri_sib, .mri_rip => inst.data.rix.fixes, | ||
| 406 | .rrmi_sib, .rrmi_rip => inst.data.rrix.fixes, | ||
| 407 | .mi_sib_u, .mi_rip_u, .mi_sib_s, .mi_rip_s => inst.data.x.fixes, | ||
| 408 | .m_sib, .m_rip, .rax_moffs, .moffs_rax => inst.data.x.fixes, | ||
| 409 | .extern_fn_reloc, | ||
| 410 | .got_reloc, | ||
| 411 | .direct_reloc, | ||
| 412 | .import_reloc, | ||
| 413 | .tlv_reloc, | ||
| 414 | => ._, | ||
| 415 | .linker_reloc => { | ||
| 416 | if (lower.bin_file.options.pic) { | ||
| 417 | assert(inst.data.rx.fixes == ._); | ||
| 418 | const reg = inst.data.rx.r1; | ||
| 419 | const extra = lower.mir.extraData(Mir.Reloc, inst.data.rx.payload).data; | ||
| 420 | _ = lower.reloc(.{ .linker_reloc = extra }); | ||
| 421 | const mnemonic: Mnemonic = switch (inst.tag) { | ||
| 422 | .mov => .mov, | ||
| 423 | .lea => .lea, | ||
| 424 | else => unreachable, | ||
| 425 | }; | ||
| 426 | try lower.emit(.none, mnemonic, &.{ | ||
| 427 | .{ .reg = reg }, | ||
| 428 | .{ .mem = Memory.rip(Memory.PtrSize.fromBitSize(reg.bitSize()), 0) }, | ||
| 429 | }); | ||
| 430 | } else { | ||
| 431 | switch (inst.tag) { | ||
| 432 | .call => { | ||
| 433 | _ = lower.reloc(.{ .linker_reloc = inst.data.reloc }); | ||
| 434 | try lower.emit(.none, .call, &.{ | ||
| 435 | .{ .mem = Memory.sib(.qword, .{ .base = .{ .reg = .ds }, .disp = 0 }) }, | ||
| 436 | }); | ||
| 437 | }, | ||
| 438 | .lea => { | ||
| 439 | assert(inst.data.rx.fixes == ._); | ||
| 440 | const reg = inst.data.rx.r1; | ||
| 441 | const extra = lower.mir.extraData(Mir.Reloc, inst.data.rx.payload).data; | ||
| 442 | try lower.emit(.none, .mov, &.{ | ||
| 443 | .{ .reg = reg }, | ||
| 444 | .{ .imm = lower.reloc(.{ .linker_reloc = extra }) }, | ||
| 445 | }); | ||
| 446 | }, | ||
| 447 | .mov => { | ||
| 448 | assert(inst.data.rx.fixes == ._); | ||
| 449 | const reg = inst.data.rx.r1; | ||
| 450 | const extra = lower.mir.extraData(Mir.Reloc, inst.data.rx.payload).data; | ||
| 451 | _ = lower.reloc(.{ .linker_reloc = extra }); | ||
| 452 | try lower.emit(.none, .mov, &.{ | ||
| 453 | .{ .reg = reg }, | ||
| 454 | .{ .mem = Memory.sib(.qword, .{ .base = .{ .reg = .ds }, .disp = 0 }) }, | ||
| 455 | }); | ||
| 456 | }, | ||
| 457 | else => return lower.fail("TODO lower {s} {s}", .{ @tagName(inst.tag), @tagName(inst.ops) }), | ||
| 458 | } | ||
| 459 | } | ||
| 460 | return; | ||
| 461 | }, | ||
| 462 | else => return lower.fail("TODO lower .{s}", .{@tagName(inst.ops)}), | 380 | else => return lower.fail("TODO lower .{s}", .{@tagName(inst.ops)}), |
| 463 | }; | 381 | }; |
| 464 | try lower.emit(switch (fixes) { | 382 | try lower.emit(switch (fixes) { |
| ... | @@ -527,73 +445,64 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void { | ... | @@ -527,73 +445,64 @@ fn generic(lower: *Lower, inst: Mir.Inst) Error!void { |
| 527 | .{ .reg = inst.data.rri.r2 }, | 445 | .{ .reg = inst.data.rri.r2 }, |
| 528 | .{ .imm = lower.imm(inst.ops, inst.data.rri.i) }, | 446 | .{ .imm = lower.imm(inst.ops, inst.data.rri.i) }, |
| 529 | }, | 447 | }, |
| 530 | .m_sib, .m_rip => &.{ | 448 | .m => &.{ |
| 531 | .{ .mem = lower.mem(inst.ops, inst.data.x.payload) }, | 449 | .{ .mem = lower.mem(inst.data.x.payload) }, |
| 532 | }, | 450 | }, |
| 533 | .mi_sib_s, .mi_sib_u, .mi_rip_s, .mi_rip_u => &.{ | 451 | .mi_s, .mi_u => &.{ |
| 534 | .{ .mem = lower.mem(inst.ops, inst.data.x.payload + 1) }, | 452 | .{ .mem = lower.mem(inst.data.x.payload + 1) }, |
| 535 | .{ .imm = lower.imm( | 453 | .{ .imm = lower.imm( |
| 536 | inst.ops, | 454 | inst.ops, |
| 537 | lower.mir.extraData(Mir.Imm32, inst.data.x.payload).data.imm, | 455 | lower.mir.extraData(Mir.Imm32, inst.data.x.payload).data.imm, |
| 538 | ) }, | 456 | ) }, |
| 539 | }, | 457 | }, |
| 540 | .rm_sib, .rm_rip => &.{ | 458 | .rm => &.{ |
| 541 | .{ .reg = inst.data.rx.r1 }, | 459 | .{ .reg = inst.data.rx.r1 }, |
| 542 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 460 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 543 | }, | 461 | }, |
| 544 | .rmi_sib, .rmi_rip => &.{ | 462 | .rmi => &.{ |
| 545 | .{ .reg = inst.data.rix.r1 }, | 463 | .{ .reg = inst.data.rix.r1 }, |
| 546 | .{ .mem = lower.mem(inst.ops, inst.data.rix.payload) }, | 464 | .{ .mem = lower.mem(inst.data.rix.payload) }, |
| 547 | .{ .imm = lower.imm(inst.ops, inst.data.rix.i) }, | 465 | .{ .imm = lower.imm(inst.ops, inst.data.rix.i) }, |
| 548 | }, | 466 | }, |
| 549 | .rmi_sib_s, .rmi_sib_u, .rmi_rip_s, .rmi_rip_u => &.{ | 467 | .rmi_s, .rmi_u => &.{ |
| 550 | .{ .reg = inst.data.rx.r1 }, | 468 | .{ .reg = inst.data.rx.r1 }, |
| 551 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload + 1) }, | 469 | .{ .mem = lower.mem(inst.data.rx.payload + 1) }, |
| 552 | .{ .imm = lower.imm( | 470 | .{ .imm = lower.imm( |
| 553 | inst.ops, | 471 | inst.ops, |
| 554 | lower.mir.extraData(Mir.Imm32, inst.data.rx.payload).data.imm, | 472 | lower.mir.extraData(Mir.Imm32, inst.data.rx.payload).data.imm, |
| 555 | ) }, | 473 | ) }, |
| 556 | }, | 474 | }, |
| 557 | .mr_sib, .mr_rip => &.{ | 475 | .mr => &.{ |
| 558 | .{ .mem = lower.mem(inst.ops, inst.data.rx.payload) }, | 476 | .{ .mem = lower.mem(inst.data.rx.payload) }, |
| 559 | .{ .reg = inst.data.rx.r1 }, | 477 | .{ .reg = inst.data.rx.r1 }, |
| 560 | }, | 478 | }, |
| 561 | .mrr_sib, .mrr_rip => &.{ | 479 | .mrr => &.{ |
| 562 | .{ .mem = lower.mem(inst.ops, inst.data.rrx.payload) }, | 480 | .{ .mem = lower.mem(inst.data.rrx.payload) }, |
| 563 | .{ .reg = inst.data.rrx.r1 }, | 481 | .{ .reg = inst.data.rrx.r1 }, |
| 564 | .{ .reg = inst.data.rrx.r2 }, | 482 | .{ .reg = inst.data.rrx.r2 }, |
| 565 | }, | 483 | }, |
| 566 | .mri_sib, .mri_rip => &.{ | 484 | .mri => &.{ |
| 567 | .{ .mem = lower.mem(inst.ops, inst.data.rix.payload) }, | 485 | .{ .mem = lower.mem(inst.data.rix.payload) }, |
| 568 | .{ .reg = inst.data.rix.r1 }, | 486 | .{ .reg = inst.data.rix.r1 }, |
| 569 | .{ .imm = lower.imm(inst.ops, inst.data.rix.i) }, | 487 | .{ .imm = lower.imm(inst.ops, inst.data.rix.i) }, |
| 570 | }, | 488 | }, |
| 571 | .rrm_sib, .rrm_rip => &.{ | 489 | .rrm => &.{ |
| 572 | .{ .reg = inst.data.rrx.r1 }, | 490 | .{ .reg = inst.data.rrx.r1 }, |
| 573 | .{ .reg = inst.data.rrx.r2 }, | 491 | .{ .reg = inst.data.rrx.r2 }, |
| 574 | .{ .mem = lower.mem(inst.ops, inst.data.rrx.payload) }, | 492 | .{ .mem = lower.mem(inst.data.rrx.payload) }, |
| 575 | }, | 493 | }, |
| 576 | .rrmi_sib, .rrmi_rip => &.{ | 494 | .rrmi => &.{ |
| 577 | .{ .reg = inst.data.rrix.r1 }, | 495 | .{ .reg = inst.data.rrix.r1 }, |
| 578 | .{ .reg = inst.data.rrix.r2 }, | 496 | .{ .reg = inst.data.rrix.r2 }, |
| 579 | .{ .mem = lower.mem(inst.ops, inst.data.rrix.payload) }, | 497 | .{ .mem = lower.mem(inst.data.rrix.payload) }, |
| 580 | .{ .imm = lower.imm(inst.ops, inst.data.rrix.i) }, | 498 | .{ .imm = lower.imm(inst.ops, inst.data.rrix.i) }, |
| 581 | }, | 499 | }, |
| 582 | .rax_moffs => &.{ | ||
| 583 | .{ .reg = .rax }, | ||
| 584 | .{ .mem = lower.mem(inst.ops, inst.data.x.payload) }, | ||
| 585 | }, | ||
| 586 | .moffs_rax => &.{ | ||
| 587 | .{ .mem = lower.mem(inst.ops, inst.data.x.payload) }, | ||
| 588 | .{ .reg = .rax }, | ||
| 589 | }, | ||
| 590 | .extern_fn_reloc => &.{ | 500 | .extern_fn_reloc => &.{ |
| 591 | .{ .imm = lower.reloc(.{ .linker_extern_fn = inst.data.reloc }) }, | 501 | .{ .imm = lower.reloc(.{ .linker_extern_fn = inst.data.reloc }) }, |
| 592 | }, | 502 | }, |
| 593 | .linker_reloc => unreachable, | ||
| 594 | .got_reloc, .direct_reloc, .import_reloc, .tlv_reloc => ops: { | 503 | .got_reloc, .direct_reloc, .import_reloc, .tlv_reloc => ops: { |
| 595 | const reg = inst.data.rx.r1; | 504 | const reg = inst.data.rx.r1; |
| 596 | const extra = lower.mir.extraData(Mir.Reloc, inst.data.rx.payload).data; | 505 | const extra = lower.mir.extraData(bits.Symbol, inst.data.rx.payload).data; |
| 597 | _ = lower.reloc(switch (inst.ops) { | 506 | _ = lower.reloc(switch (inst.ops) { |
| 598 | .got_reloc => .{ .linker_got = extra }, | 507 | .got_reloc => .{ .linker_got = extra }, |
| 599 | .direct_reloc => .{ .linker_direct = extra }, | 508 | .direct_reloc => .{ .linker_direct = extra }, |
| ... | @@ -635,7 +544,7 @@ const ErrorMsg = Module.ErrorMsg; | ... | @@ -635,7 +544,7 @@ const ErrorMsg = Module.ErrorMsg; |
| 635 | const Immediate = bits.Immediate; | 544 | const Immediate = bits.Immediate; |
| 636 | const Instruction = encoder.Instruction; | 545 | const Instruction = encoder.Instruction; |
| 637 | const Lower = @This(); | 546 | const Lower = @This(); |
| 638 | const Memory = bits.Memory; | 547 | const Memory = Instruction.Memory; |
| 639 | const Mir = @import("Mir.zig"); | 548 | const Mir = @import("Mir.zig"); |
| 640 | const Mnemonic = Instruction.Mnemonic; | 549 | const Mnemonic = Instruction.Mnemonic; |
| 641 | const Module = @import("../../Module.zig"); | 550 | const Module = @import("../../Module.zig"); |
src/arch/x86_64/Mir.zig+136-203
| ... | @@ -17,7 +17,6 @@ const encoder = @import("encoder.zig"); | ... | @@ -17,7 +17,6 @@ const encoder = @import("encoder.zig"); |
| 17 | const Air = @import("../../Air.zig"); | 17 | const Air = @import("../../Air.zig"); |
| 18 | const CodeGen = @import("CodeGen.zig"); | 18 | const CodeGen = @import("CodeGen.zig"); |
| 19 | const IntegerBitSet = std.bit_set.IntegerBitSet; | 19 | const IntegerBitSet = std.bit_set.IntegerBitSet; |
| 20 | const Memory = bits.Memory; | ||
| 21 | const Register = bits.Register; | 20 | const Register = bits.Register; |
| 22 | 21 | ||
| 23 | instructions: std.MultiArrayList(Inst).Slice, | 22 | instructions: std.MultiArrayList(Inst).Slice, |
| ... | @@ -767,84 +766,42 @@ pub const Inst = struct { | ... | @@ -767,84 +766,42 @@ pub const Inst = struct { |
| 767 | /// Relative displacement operand. | 766 | /// Relative displacement operand. |
| 768 | /// Uses `imm` payload. | 767 | /// Uses `imm` payload. |
| 769 | rel, | 768 | rel, |
| 770 | /// Register, memory (SIB) operands. | 769 | /// Register, memory operands. |
| 771 | /// Uses `rx` payload. | 770 | /// Uses `rx` payload. |
| 772 | rm_sib, | 771 | rm, |
| 773 | /// Register, memory (RIP) operands. | 772 | /// Register, memory, immediate (word) operands. |
| 774 | /// Uses `rx` payload. | 773 | /// Uses `rix` payload with extra data of type `Memory`. |
| 775 | rm_rip, | 774 | rmi, |
| 776 | /// Register, memory (SIB), immediate (word) operands. | 775 | /// Register, memory, immediate (signed) operands. |
| 777 | /// Uses `rix` payload with extra data of type `MemorySib`. | 776 | /// Uses `rx` payload with extra data of type `Imm32` followed by `Memory`. |
| 778 | rmi_sib, | 777 | rmi_s, |
| 779 | /// Register, memory (RIP), immediate (word) operands. | 778 | /// Register, memory, immediate (unsigned) operands. |
| 780 | /// Uses `rix` payload with extra data of type `MemoryRip`. | 779 | /// Uses `rx` payload with extra data of type `Imm32` followed by `Memory`. |
| 781 | rmi_rip, | 780 | rmi_u, |
| 782 | /// Register, memory (SIB), immediate (signed) operands. | 781 | /// Register, register, memory. |
| 783 | /// Uses `rx` payload with extra data of type `Imm32` followed by `MemorySib`. | 782 | /// Uses `rrix` payload with extra data of type `Memory`. |
| 784 | rmi_sib_s, | 783 | rrm, |
| 785 | /// Register, memory (SIB), immediate (unsigned) operands. | 784 | /// Register, register, memory, immediate (byte) operands. |
| 786 | /// Uses `rx` payload with extra data of type `Imm32` followed by `MemorySib`. | 785 | /// Uses `rrix` payload with extra data of type `Memory`. |
| 787 | rmi_sib_u, | 786 | rrmi, |
| 788 | /// Register, memory (RIP), immediate (signed) operands. | 787 | /// Single memory operand. |
| 789 | /// Uses `rx` payload with extra data of type `Imm32` followed by `MemoryRip`. | 788 | /// Uses `x` with extra data of type `Memory`. |
| 790 | rmi_rip_s, | 789 | m, |
| 791 | /// Register, memory (RIP), immediate (unsigned) operands. | 790 | /// Memory, immediate (sign-extend) operands. |
| 792 | /// Uses `rx` payload with extra data of type `Imm32` followed by `MemoryRip`. | 791 | /// Uses `x` payload with extra data of type `Imm32` followed by `Memory`. |
| 793 | rmi_rip_u, | 792 | mi_s, |
| 794 | /// Register, register, memory (RIP). | 793 | /// Memory, immediate (unsigned) operands. |
| 795 | /// Uses `rrix` payload with extra data of type `MemoryRip`. | 794 | /// Uses `x` payload with extra data of type `Imm32` followed by `Memory`. |
| 796 | rrm_rip, | 795 | mi_u, |
| 797 | /// Register, register, memory (SIB). | 796 | /// Memory, register operands. |
| 798 | /// Uses `rrix` payload with extra data of type `MemorySib`. | 797 | /// Uses `rx` payload with extra data of type `Memory`. |
| 799 | rrm_sib, | 798 | mr, |
| 800 | /// Register, register, memory (RIP), immediate (byte) operands. | 799 | /// Memory, register, register operands. |
| 801 | /// Uses `rrix` payload with extra data of type `MemoryRip`. | 800 | /// Uses `rrx` payload with extra data of type `Memory`. |
| 802 | rrmi_rip, | 801 | mrr, |
| 803 | /// Register, register, memory (SIB), immediate (byte) operands. | 802 | /// Memory, register, immediate (word) operands. |
| 804 | /// Uses `rrix` payload with extra data of type `MemorySib`. | 803 | /// Uses `rix` payload with extra data of type `Memory`. |
| 805 | rrmi_sib, | 804 | mri, |
| 806 | /// Single memory (SIB) operand. | ||
| 807 | /// Uses `x` with extra data of type `MemorySib`. | ||
| 808 | m_sib, | ||
| 809 | /// Single memory (RIP) operand. | ||
| 810 | /// Uses `x` with extra data of type `MemoryRip`. | ||
| 811 | m_rip, | ||
| 812 | /// Memory (SIB), immediate (sign-extend) operands. | ||
| 813 | /// Uses `x` payload with extra data of type `Imm32` followed by `MemorySib`. | ||
| 814 | mi_sib_s, | ||
| 815 | /// Memory (SIB), immediate (unsigned) operands. | ||
| 816 | /// Uses `x` payload with extra data of type `Imm32` followed by `MemorySib`. | ||
| 817 | mi_sib_u, | ||
| 818 | /// Memory (RIP), immediate (sign-extend) operands. | ||
| 819 | /// Uses `x` payload with extra data of type `Imm32` followed by `MemoryRip`. | ||
| 820 | mi_rip_s, | ||
| 821 | /// Memory (RIP), immediate (unsigned) operands. | ||
| 822 | /// Uses `x` payload with extra data of type `Imm32` followed by `MemoryRip`. | ||
| 823 | mi_rip_u, | ||
| 824 | /// Memory (SIB), register operands. | ||
| 825 | /// Uses `rx` payload with extra data of type `MemorySib`. | ||
| 826 | mr_sib, | ||
| 827 | /// Memory (RIP), register operands. | ||
| 828 | /// Uses `rx` payload with extra data of type `MemoryRip`. | ||
| 829 | mr_rip, | ||
| 830 | /// Memory (SIB), register, register operands. | ||
| 831 | /// Uses `rrx` payload with extra data of type `MemorySib`. | ||
| 832 | mrr_sib, | ||
| 833 | /// Memory (RIP), register, register operands. | ||
| 834 | /// Uses `rrx` payload with extra data of type `MemoryRip`. | ||
| 835 | mrr_rip, | ||
| 836 | /// Memory (SIB), register, immediate (word) operands. | ||
| 837 | /// Uses `rix` payload with extra data of type `MemorySib`. | ||
| 838 | mri_sib, | ||
| 839 | /// Memory (RIP), register, immediate (word) operands. | ||
| 840 | /// Uses `rix` payload with extra data of type `MemoryRip`. | ||
| 841 | mri_rip, | ||
| 842 | /// Rax, Memory moffs. | ||
| 843 | /// Uses `x` with extra data of type `MemoryMoffs`. | ||
| 844 | rax_moffs, | ||
| 845 | /// Memory moffs, rax. | ||
| 846 | /// Uses `x` with extra data of type `MemoryMoffs`. | ||
| 847 | moffs_rax, | ||
| 848 | /// References another Mir instruction directly. | 805 | /// References another Mir instruction directly. |
| 849 | /// Uses `inst` payload. | 806 | /// Uses `inst` payload. |
| 850 | inst, | 807 | inst, |
| ... | @@ -852,20 +809,17 @@ pub const Inst = struct { | ... | @@ -852,20 +809,17 @@ pub const Inst = struct { |
| 852 | /// Uses `reloc` payload. | 809 | /// Uses `reloc` payload. |
| 853 | extern_fn_reloc, | 810 | extern_fn_reloc, |
| 854 | /// Linker relocation - GOT indirection. | 811 | /// Linker relocation - GOT indirection. |
| 855 | /// Uses `rx` payload with extra data of type `Reloc`. | 812 | /// Uses `rx` payload with extra data of type `bits.Symbol`. |
| 856 | got_reloc, | 813 | got_reloc, |
| 857 | /// Linker relocation - direct reference. | 814 | /// Linker relocation - direct reference. |
| 858 | /// Uses `rx` payload with extra data of type `Reloc`. | 815 | /// Uses `rx` payload with extra data of type `bits.Symbol`. |
| 859 | direct_reloc, | 816 | direct_reloc, |
| 860 | /// Linker relocation - imports table indirection (binding). | 817 | /// Linker relocation - imports table indirection (binding). |
| 861 | /// Uses `rx` payload with extra data of type `Reloc`. | 818 | /// Uses `rx` payload with extra data of type `bits.Symbol`. |
| 862 | import_reloc, | 819 | import_reloc, |
| 863 | /// Linker relocation - threadlocal variable via GOT indirection. | 820 | /// Linker relocation - threadlocal variable via GOT indirection. |
| 864 | /// Uses `rx` payload with extra data of type `Reloc`. | 821 | /// Uses `rx` payload with extra data of type `bits.Symbol`. |
| 865 | tlv_reloc, | 822 | tlv_reloc, |
| 866 | /// Linker relocation. | ||
| 867 | /// Uses `rx` payload with extra data of type `Reloc`. | ||
| 868 | linker_reloc, | ||
| 869 | 823 | ||
| 870 | // Pseudo instructions: | 824 | // Pseudo instructions: |
| 871 | 825 | ||
| ... | @@ -878,10 +832,7 @@ pub const Inst = struct { | ... | @@ -878,10 +832,7 @@ pub const Inst = struct { |
| 878 | pseudo_cmov_nz_or_p_rr, | 832 | pseudo_cmov_nz_or_p_rr, |
| 879 | /// Conditional move if zero flag not set or parity flag set | 833 | /// Conditional move if zero flag not set or parity flag set |
| 880 | /// Uses `rx` payload. | 834 | /// Uses `rx` payload. |
| 881 | pseudo_cmov_nz_or_p_rm_sib, | 835 | pseudo_cmov_nz_or_p_rm, |
| 882 | /// Conditional move if zero flag not set or parity flag set | ||
| 883 | /// Uses `rx` payload. | ||
| 884 | pseudo_cmov_nz_or_p_rm_rip, | ||
| 885 | /// Set byte if zero flag set and parity flag not set | 836 | /// Set byte if zero flag set and parity flag not set |
| 886 | /// Requires a scratch register! | 837 | /// Requires a scratch register! |
| 887 | /// Uses `rr` payload. | 838 | /// Uses `rr` payload. |
| ... | @@ -889,11 +840,7 @@ pub const Inst = struct { | ... | @@ -889,11 +840,7 @@ pub const Inst = struct { |
| 889 | /// Set byte if zero flag set and parity flag not set | 840 | /// Set byte if zero flag set and parity flag not set |
| 890 | /// Requires a scratch register! | 841 | /// Requires a scratch register! |
| 891 | /// Uses `rx` payload. | 842 | /// Uses `rx` payload. |
| 892 | pseudo_set_z_and_np_m_sib, | 843 | pseudo_set_z_and_np_m, |
| 893 | /// Set byte if zero flag set and parity flag not set | ||
| 894 | /// Requires a scratch register! | ||
| 895 | /// Uses `rx` payload. | ||
| 896 | pseudo_set_z_and_np_m_rip, | ||
| 897 | /// Set byte if zero flag not set or parity flag set | 844 | /// Set byte if zero flag not set or parity flag set |
| 898 | /// Requires a scratch register! | 845 | /// Requires a scratch register! |
| 899 | /// Uses `rr` payload. | 846 | /// Uses `rr` payload. |
| ... | @@ -901,11 +848,7 @@ pub const Inst = struct { | ... | @@ -901,11 +848,7 @@ pub const Inst = struct { |
| 901 | /// Set byte if zero flag not set or parity flag set | 848 | /// Set byte if zero flag not set or parity flag set |
| 902 | /// Requires a scratch register! | 849 | /// Requires a scratch register! |
| 903 | /// Uses `rx` payload. | 850 | /// Uses `rx` payload. |
| 904 | pseudo_set_nz_or_p_m_sib, | 851 | pseudo_set_nz_or_p_m, |
| 905 | /// Set byte if zero flag not set or parity flag set | ||
| 906 | /// Requires a scratch register! | ||
| 907 | /// Uses `rx` payload. | ||
| 908 | pseudo_set_nz_or_p_m_rip, | ||
| 909 | /// Jump if zero flag set and parity flag not set | 852 | /// Jump if zero flag set and parity flag not set |
| 910 | /// Uses `inst` payload. | 853 | /// Uses `inst` payload. |
| 911 | pseudo_j_z_and_np_inst, | 854 | pseudo_j_z_and_np_inst, |
| ... | @@ -1036,7 +979,7 @@ pub const Inst = struct { | ... | @@ -1036,7 +979,7 @@ pub const Inst = struct { |
| 1036 | /// Relocation for the linker where: | 979 | /// Relocation for the linker where: |
| 1037 | /// * `atom_index` is the index of the source | 980 | /// * `atom_index` is the index of the source |
| 1038 | /// * `sym_index` is the index of the target | 981 | /// * `sym_index` is the index of the target |
| 1039 | reloc: Reloc, | 982 | reloc: bits.Symbol, |
| 1040 | /// Debug line and column position | 983 | /// Debug line and column position |
| 1041 | line_column: struct { | 984 | line_column: struct { |
| 1042 | line: u32, | 985 | line: u32, |
| ... | @@ -1055,14 +998,6 @@ pub const Inst = struct { | ... | @@ -1055,14 +998,6 @@ pub const Inst = struct { |
| 1055 | } | 998 | } |
| 1056 | }; | 999 | }; |
| 1057 | 1000 | ||
| 1058 | /// A linker symbol not yet allocated in VM. | ||
| 1059 | pub const Reloc = struct { | ||
| 1060 | /// Index of the containing atom. | ||
| 1061 | atom_index: u32, | ||
| 1062 | /// Index into the linker's symbol table. | ||
| 1063 | sym_index: u32, | ||
| 1064 | }; | ||
| 1065 | |||
| 1066 | /// Used in conjunction with payload to transfer a list of used registers in a compact manner. | 1001 | /// Used in conjunction with payload to transfer a list of used registers in a compact manner. |
| 1067 | pub const RegisterList = struct { | 1002 | pub const RegisterList = struct { |
| 1068 | bitset: BitSet = BitSet.initEmpty(), | 1003 | bitset: BitSet = BitSet.initEmpty(), |
| ... | @@ -1123,100 +1058,94 @@ pub const Imm64 = struct { | ... | @@ -1123,100 +1058,94 @@ pub const Imm64 = struct { |
| 1123 | } | 1058 | } |
| 1124 | }; | 1059 | }; |
| 1125 | 1060 | ||
| 1126 | // TODO this can be further compacted using packed struct | 1061 | pub const Memory = struct { |
| 1127 | pub const MemorySib = struct { | 1062 | info: Info, |
| 1128 | /// Size of the pointer. | ||
| 1129 | ptr_size: u32, | ||
| 1130 | /// Base register tag of type Memory.Base.Tag | ||
| 1131 | base_tag: u32, | ||
| 1132 | /// Base register of type Register or FrameIndex | ||
| 1133 | base: u32, | 1063 | base: u32, |
| 1134 | /// Scale starting at bit 0 and index register starting at bit 4. | 1064 | off: u32, |
| 1135 | scale_index: u32, | 1065 | extra: u32, |
| 1136 | /// Displacement value. | 1066 | |
| 1137 | disp: i32, | 1067 | pub const Info = packed struct(u32) { |
| 1068 | base: @typeInfo(bits.Memory.Base).Union.tag_type.?, | ||
| 1069 | mod: @typeInfo(bits.Memory.Mod).Union.tag_type.?, | ||
| 1070 | size: bits.Memory.Size, | ||
| 1071 | index: Register, | ||
| 1072 | scale: bits.Memory.Scale, | ||
| 1073 | _: u16 = undefined, | ||
| 1074 | }; | ||
| 1138 | 1075 | ||
| 1139 | pub fn encode(mem: Memory) MemorySib { | 1076 | pub fn encode(mem: bits.Memory) Memory { |
| 1140 | const sib = mem.sib; | 1077 | assert(mem.base != .reloc or mem.mod != .off); |
| 1141 | assert(sib.scale_index.scale == 0 or std.math.isPowerOfTwo(sib.scale_index.scale)); | ||
| 1142 | return .{ | 1078 | return .{ |
| 1143 | .ptr_size = @intFromEnum(sib.ptr_size), | 1079 | .info = .{ |
| 1144 | .base_tag = @intFromEnum(sib.base), | 1080 | .base = mem.base, |
| 1145 | .base = switch (sib.base) { | 1081 | .mod = mem.mod, |
| 1082 | .size = switch (mem.mod) { | ||
| 1083 | .rm => |rm| rm.size, | ||
| 1084 | .off => undefined, | ||
| 1085 | }, | ||
| 1086 | .index = switch (mem.mod) { | ||
| 1087 | .rm => |rm| rm.index, | ||
| 1088 | .off => undefined, | ||
| 1089 | }, | ||
| 1090 | .scale = switch (mem.mod) { | ||
| 1091 | .rm => |rm| rm.scale, | ||
| 1092 | .off => undefined, | ||
| 1093 | }, | ||
| 1094 | }, | ||
| 1095 | .base = switch (mem.base) { | ||
| 1146 | .none => undefined, | 1096 | .none => undefined, |
| 1147 | .reg => |r| @intFromEnum(r), | 1097 | .reg => |reg| @intFromEnum(reg), |
| 1148 | .frame => |fi| @intFromEnum(fi), | 1098 | .frame => |frame_index| @intFromEnum(frame_index), |
| 1099 | .reloc => |symbol| symbol.sym_index, | ||
| 1100 | }, | ||
| 1101 | .off = switch (mem.mod) { | ||
| 1102 | .rm => |rm| @bitCast(rm.disp), | ||
| 1103 | .off => |off| @truncate(off), | ||
| 1149 | }, | 1104 | }, |
| 1150 | .scale_index = @as(u32, sib.scale_index.scale) << 0 | | 1105 | .extra = if (mem.base == .reloc) |
| 1151 | @as(u32, if (sib.scale_index.scale > 0) | 1106 | mem.base.reloc.atom_index |
| 1152 | @intFromEnum(sib.scale_index.index) | 1107 | else if (mem.mod == .off) |
| 1108 | @intCast(mem.mod.off >> 32) | ||
| 1153 | else | 1109 | else |
| 1154 | undefined) << 4, | 1110 | undefined, |
| 1155 | .disp = sib.disp, | ||
| 1156 | }; | 1111 | }; |
| 1157 | } | 1112 | } |
| 1158 | 1113 | ||
| 1159 | pub fn decode(msib: MemorySib) Memory { | 1114 | pub fn decode(mem: Memory) encoder.Instruction.Memory { |
| 1160 | const scale: u4 = @truncate(msib.scale_index); | 1115 | switch (mem.info.mod) { |
| 1161 | assert(scale == 0 or std.math.isPowerOfTwo(scale)); | 1116 | .rm => { |
| 1162 | return .{ .sib = .{ | 1117 | if (mem.info.base == .reg and @as(Register, @enumFromInt(mem.base)) == .rip) { |
| 1163 | .ptr_size = @enumFromInt(msib.ptr_size), | 1118 | assert(mem.info.index == .none and mem.info.scale == .@"1"); |
| 1164 | .base = switch (@as(Memory.Base.Tag, @enumFromInt(msib.base_tag))) { | 1119 | return encoder.Instruction.Memory.rip(mem.info.size, @bitCast(mem.off)); |
| 1165 | .none => .none, | 1120 | } |
| 1166 | .reg => .{ .reg = @enumFromInt(msib.base) }, | 1121 | return encoder.Instruction.Memory.sib(mem.info.size, .{ |
| 1167 | .frame => .{ .frame = @enumFromInt(msib.base) }, | 1122 | .disp = @bitCast(mem.off), |
| 1123 | .base = switch (mem.info.base) { | ||
| 1124 | .none => .none, | ||
| 1125 | .reg => .{ .reg = @enumFromInt(mem.base) }, | ||
| 1126 | .frame => .{ .frame = @enumFromInt(mem.base) }, | ||
| 1127 | .reloc => .{ .reloc = .{ .atom_index = mem.extra, .sym_index = mem.base } }, | ||
| 1128 | }, | ||
| 1129 | .scale_index = switch (mem.info.index) { | ||
| 1130 | .none => null, | ||
| 1131 | else => |index| .{ .scale = switch (mem.info.scale) { | ||
| 1132 | inline else => |scale| comptime std.fmt.parseInt( | ||
| 1133 | u4, | ||
| 1134 | @tagName(scale), | ||
| 1135 | 10, | ||
| 1136 | ) catch unreachable, | ||
| 1137 | }, .index = index }, | ||
| 1138 | }, | ||
| 1139 | }); | ||
| 1168 | }, | 1140 | }, |
| 1169 | .scale_index = .{ | 1141 | .off => { |
| 1170 | .scale = scale, | 1142 | assert(mem.info.base == .reg); |
| 1171 | .index = if (scale > 0) @enumFromInt(msib.scale_index >> 4) else undefined, | 1143 | return encoder.Instruction.Memory.moffs( |
| 1144 | @enumFromInt(mem.base), | ||
| 1145 | @as(u64, mem.extra) << 32 | mem.off, | ||
| 1146 | ); | ||
| 1172 | }, | 1147 | }, |
| 1173 | .disp = msib.disp, | 1148 | } |
| 1174 | } }; | ||
| 1175 | } | ||
| 1176 | }; | ||
| 1177 | |||
| 1178 | pub const MemoryRip = struct { | ||
| 1179 | /// Size of the pointer. | ||
| 1180 | ptr_size: u32, | ||
| 1181 | /// Displacement value. | ||
| 1182 | disp: i32, | ||
| 1183 | |||
| 1184 | pub fn encode(mem: Memory) MemoryRip { | ||
| 1185 | return .{ | ||
| 1186 | .ptr_size = @intFromEnum(mem.rip.ptr_size), | ||
| 1187 | .disp = mem.rip.disp, | ||
| 1188 | }; | ||
| 1189 | } | ||
| 1190 | |||
| 1191 | pub fn decode(mrip: MemoryRip) Memory { | ||
| 1192 | return .{ .rip = .{ | ||
| 1193 | .ptr_size = @enumFromInt(mrip.ptr_size), | ||
| 1194 | .disp = mrip.disp, | ||
| 1195 | } }; | ||
| 1196 | } | ||
| 1197 | }; | ||
| 1198 | |||
| 1199 | pub const MemoryMoffs = struct { | ||
| 1200 | /// Segment register. | ||
| 1201 | seg: u32, | ||
| 1202 | /// Absolute offset wrt to the segment register split between MSB and LSB parts much like | ||
| 1203 | /// `Imm64` payload. | ||
| 1204 | msb: u32, | ||
| 1205 | lsb: u32, | ||
| 1206 | |||
| 1207 | pub fn encode(seg: Register, offset: u64) MemoryMoffs { | ||
| 1208 | return .{ | ||
| 1209 | .seg = @intFromEnum(seg), | ||
| 1210 | .msb = @truncate(offset >> 32), | ||
| 1211 | .lsb = @truncate(offset >> 0), | ||
| 1212 | }; | ||
| 1213 | } | ||
| 1214 | |||
| 1215 | pub fn decode(moffs: MemoryMoffs) Memory { | ||
| 1216 | return .{ .moffs = .{ | ||
| 1217 | .seg = @enumFromInt(moffs.seg), | ||
| 1218 | .offset = @as(u64, moffs.msb) << 32 | @as(u64, moffs.lsb) << 0, | ||
| 1219 | } }; | ||
| 1220 | } | 1149 | } |
| 1221 | }; | 1150 | }; |
| 1222 | 1151 | ||
| ... | @@ -1234,8 +1163,8 @@ pub fn extraData(mir: Mir, comptime T: type, index: u32) struct { data: T, end: | ... | @@ -1234,8 +1163,8 @@ pub fn extraData(mir: Mir, comptime T: type, index: u32) struct { data: T, end: |
| 1234 | inline for (fields) |field| { | 1163 | inline for (fields) |field| { |
| 1235 | @field(result, field.name) = switch (field.type) { | 1164 | @field(result, field.name) = switch (field.type) { |
| 1236 | u32 => mir.extra[i], | 1165 | u32 => mir.extra[i], |
| 1237 | i32 => @bitCast(mir.extra[i]), | 1166 | i32, Memory.Info => @bitCast(mir.extra[i]), |
| 1238 | else => @compileError("bad field type"), | 1167 | else => @compileError("bad field type: " ++ field.name ++ ": " ++ @typeName(field.type)), |
| 1239 | }; | 1168 | }; |
| 1240 | i += 1; | 1169 | i += 1; |
| 1241 | } | 1170 | } |
| ... | @@ -1251,15 +1180,19 @@ pub const FrameLoc = struct { | ... | @@ -1251,15 +1180,19 @@ pub const FrameLoc = struct { |
| 1251 | }; | 1180 | }; |
| 1252 | 1181 | ||
| 1253 | pub fn resolveFrameLoc(mir: Mir, mem: Memory) Memory { | 1182 | pub fn resolveFrameLoc(mir: Mir, mem: Memory) Memory { |
| 1254 | return switch (mem) { | 1183 | return switch (mem.info.base) { |
| 1255 | .sib => |sib| switch (sib.base) { | 1184 | .none, .reg, .reloc => mem, |
| 1256 | .none, .reg => mem, | 1185 | .frame => if (mir.frame_locs.len > 0) Memory{ |
| 1257 | .frame => |index| if (mir.frame_locs.len > 0) Memory.sib(sib.ptr_size, .{ | 1186 | .info = .{ |
| 1258 | .base = .{ .reg = mir.frame_locs.items(.base)[@intFromEnum(index)] }, | 1187 | .base = .reg, |
| 1259 | .disp = mir.frame_locs.items(.disp)[@intFromEnum(index)] + sib.disp, | 1188 | .mod = mem.info.mod, |
| 1260 | .scale_index = mem.scaleIndex(), | 1189 | .size = mem.info.size, |
| 1261 | }) else mem, | 1190 | .index = mem.info.index, |
| 1262 | }, | 1191 | .scale = mem.info.scale, |
| 1263 | .rip, .moffs => mem, | 1192 | }, |
| 1193 | .base = @intFromEnum(mir.frame_locs.items(.base)[mem.base]), | ||
| 1194 | .off = @bitCast(mir.frame_locs.items(.disp)[mem.base] + @as(i32, @bitCast(mem.off))), | ||
| 1195 | .extra = mem.extra, | ||
| 1196 | } else mem, | ||
| 1264 | }; | 1197 | }; |
| 1265 | } | 1198 | } |
src/arch/x86_64/bits.zig+43-89
| ... | @@ -181,6 +181,8 @@ pub const Register = enum(u7) { | ... | @@ -181,6 +181,8 @@ pub const Register = enum(u7) { |
| 181 | 181 | ||
| 182 | es, cs, ss, ds, fs, gs, | 182 | es, cs, ss, ds, fs, gs, |
| 183 | 183 | ||
| 184 | rip, eip, ip, | ||
| 185 | |||
| 184 | none, | 186 | none, |
| 185 | // zig fmt: on | 187 | // zig fmt: on |
| 186 | 188 | ||
| ... | @@ -442,34 +444,58 @@ pub const FrameIndex = enum(u32) { | ... | @@ -442,34 +444,58 @@ pub const FrameIndex = enum(u32) { |
| 442 | } | 444 | } |
| 443 | }; | 445 | }; |
| 444 | 446 | ||
| 445 | pub const Memory = union(enum) { | 447 | /// A linker symbol not yet allocated in VM. |
| 446 | sib: Sib, | 448 | pub const Symbol = struct { |
| 447 | rip: Rip, | 449 | /// Index of the containing atom. |
| 448 | moffs: Moffs, | 450 | atom_index: u32, |
| 451 | /// Index into the linker's symbol table. | ||
| 452 | sym_index: u32, | ||
| 453 | |||
| 454 | pub fn format( | ||
| 455 | sym: Symbol, | ||
| 456 | comptime fmt: []const u8, | ||
| 457 | options: std.fmt.FormatOptions, | ||
| 458 | writer: anytype, | ||
| 459 | ) @TypeOf(writer).Error!void { | ||
| 460 | try writer.writeAll("Symbol("); | ||
| 461 | try std.fmt.formatType(sym.atom_index, fmt, options, writer, 0); | ||
| 462 | try writer.writeAll(", "); | ||
| 463 | try std.fmt.formatType(sym.sym_index, fmt, options, writer, 0); | ||
| 464 | try writer.writeByte(')'); | ||
| 465 | } | ||
| 466 | }; | ||
| 467 | |||
| 468 | pub const Memory = struct { | ||
| 469 | base: Base, | ||
| 470 | mod: Mod, | ||
| 449 | 471 | ||
| 450 | pub const Base = union(enum) { | 472 | pub const Base = union(enum(u2)) { |
| 451 | none, | 473 | none, |
| 452 | reg: Register, | 474 | reg: Register, |
| 453 | frame: FrameIndex, | 475 | frame: FrameIndex, |
| 476 | reloc: Symbol, | ||
| 454 | 477 | ||
| 455 | pub const Tag = @typeInfo(Base).Union.tag_type.?; | 478 | pub const Tag = @typeInfo(Base).Union.tag_type.?; |
| 456 | 479 | ||
| 457 | pub fn isExtended(self: Base) bool { | 480 | pub fn isExtended(self: Base) bool { |
| 458 | return switch (self) { | 481 | return switch (self) { |
| 459 | .none, .frame => false, // neither rsp nor rbp are extended | 482 | .none, .frame, .reloc => false, // rsp, rbp, and rip are not extended |
| 460 | .reg => |reg| reg.isExtended(), | 483 | .reg => |reg| reg.isExtended(), |
| 461 | }; | 484 | }; |
| 462 | } | 485 | } |
| 463 | }; | 486 | }; |
| 464 | 487 | ||
| 465 | pub const ScaleIndex = struct { | 488 | pub const Mod = union(enum(u1)) { |
| 466 | scale: u4, | 489 | rm: struct { |
| 467 | index: Register, | 490 | size: Size, |
| 468 | 491 | index: Register = .none, | |
| 469 | const none = ScaleIndex{ .scale = 0, .index = undefined }; | 492 | scale: Scale = .@"1", |
| 493 | disp: i32 = 0, | ||
| 494 | }, | ||
| 495 | off: u64, | ||
| 470 | }; | 496 | }; |
| 471 | 497 | ||
| 472 | pub const PtrSize = enum { | 498 | pub const Size = enum(u4) { |
| 473 | none, | 499 | none, |
| 474 | byte, | 500 | byte, |
| 475 | word, | 501 | word, |
| ... | @@ -480,7 +506,7 @@ pub const Memory = union(enum) { | ... | @@ -480,7 +506,7 @@ pub const Memory = union(enum) { |
| 480 | yword, | 506 | yword, |
| 481 | zword, | 507 | zword, |
| 482 | 508 | ||
| 483 | pub fn fromSize(size: u32) PtrSize { | 509 | pub fn fromSize(size: u32) Size { |
| 484 | return switch (size) { | 510 | return switch (size) { |
| 485 | 1...1 => .byte, | 511 | 1...1 => .byte, |
| 486 | 2...2 => .word, | 512 | 2...2 => .word, |
| ... | @@ -493,7 +519,7 @@ pub const Memory = union(enum) { | ... | @@ -493,7 +519,7 @@ pub const Memory = union(enum) { |
| 493 | }; | 519 | }; |
| 494 | } | 520 | } |
| 495 | 521 | ||
| 496 | pub fn fromBitSize(bit_size: u64) PtrSize { | 522 | pub fn fromBitSize(bit_size: u64) Size { |
| 497 | return switch (bit_size) { | 523 | return switch (bit_size) { |
| 498 | 8 => .byte, | 524 | 8 => .byte, |
| 499 | 16 => .word, | 525 | 16 => .word, |
| ... | @@ -507,7 +533,7 @@ pub const Memory = union(enum) { | ... | @@ -507,7 +533,7 @@ pub const Memory = union(enum) { |
| 507 | }; | 533 | }; |
| 508 | } | 534 | } |
| 509 | 535 | ||
| 510 | pub fn bitSize(s: PtrSize) u64 { | 536 | pub fn bitSize(s: Size) u64 { |
| 511 | return switch (s) { | 537 | return switch (s) { |
| 512 | .none => 0, | 538 | .none => 0, |
| 513 | .byte => 8, | 539 | .byte => 8, |
| ... | @@ -522,7 +548,7 @@ pub const Memory = union(enum) { | ... | @@ -522,7 +548,7 @@ pub const Memory = union(enum) { |
| 522 | } | 548 | } |
| 523 | 549 | ||
| 524 | pub fn format( | 550 | pub fn format( |
| 525 | s: PtrSize, | 551 | s: Size, |
| 526 | comptime _: []const u8, | 552 | comptime _: []const u8, |
| 527 | _: std.fmt.FormatOptions, | 553 | _: std.fmt.FormatOptions, |
| 528 | writer: anytype, | 554 | writer: anytype, |
| ... | @@ -533,79 +559,7 @@ pub const Memory = union(enum) { | ... | @@ -533,79 +559,7 @@ pub const Memory = union(enum) { |
| 533 | } | 559 | } |
| 534 | }; | 560 | }; |
| 535 | 561 | ||
| 536 | pub const Sib = struct { | 562 | pub const Scale = enum(u2) { @"1", @"2", @"4", @"8" }; |
| 537 | ptr_size: PtrSize, | ||
| 538 | base: Base, | ||
| 539 | scale_index: ScaleIndex, | ||
| 540 | disp: i32, | ||
| 541 | }; | ||
| 542 | |||
| 543 | pub const Rip = struct { | ||
| 544 | ptr_size: PtrSize, | ||
| 545 | disp: i32, | ||
| 546 | }; | ||
| 547 | |||
| 548 | pub const Moffs = struct { | ||
| 549 | seg: Register, | ||
| 550 | offset: u64, | ||
| 551 | }; | ||
| 552 | |||
| 553 | pub fn moffs(reg: Register, offset: u64) Memory { | ||
| 554 | assert(reg.class() == .segment); | ||
| 555 | return .{ .moffs = .{ .seg = reg, .offset = offset } }; | ||
| 556 | } | ||
| 557 | |||
| 558 | pub fn sib(ptr_size: PtrSize, args: struct { | ||
| 559 | disp: i32 = 0, | ||
| 560 | base: Base = .none, | ||
| 561 | scale_index: ?ScaleIndex = null, | ||
| 562 | }) Memory { | ||
| 563 | if (args.scale_index) |si| assert(std.math.isPowerOfTwo(si.scale)); | ||
| 564 | return .{ .sib = .{ | ||
| 565 | .base = args.base, | ||
| 566 | .disp = args.disp, | ||
| 567 | .ptr_size = ptr_size, | ||
| 568 | .scale_index = if (args.scale_index) |si| si else ScaleIndex.none, | ||
| 569 | } }; | ||
| 570 | } | ||
| 571 | |||
| 572 | pub fn rip(ptr_size: PtrSize, disp: i32) Memory { | ||
| 573 | return .{ .rip = .{ .ptr_size = ptr_size, .disp = disp } }; | ||
| 574 | } | ||
| 575 | |||
| 576 | pub fn isSegmentRegister(mem: Memory) bool { | ||
| 577 | return switch (mem) { | ||
| 578 | .moffs => true, | ||
| 579 | .rip => false, | ||
| 580 | .sib => |s| switch (s.base) { | ||
| 581 | .none, .frame => false, | ||
| 582 | .reg => |reg| reg.class() == .segment, | ||
| 583 | }, | ||
| 584 | }; | ||
| 585 | } | ||
| 586 | |||
| 587 | pub fn base(mem: Memory) Base { | ||
| 588 | return switch (mem) { | ||
| 589 | .moffs => |m| .{ .reg = m.seg }, | ||
| 590 | .sib => |s| s.base, | ||
| 591 | .rip => .none, | ||
| 592 | }; | ||
| 593 | } | ||
| 594 | |||
| 595 | pub fn scaleIndex(mem: Memory) ?ScaleIndex { | ||
| 596 | return switch (mem) { | ||
| 597 | .moffs, .rip => null, | ||
| 598 | .sib => |s| if (s.scale_index.scale > 0) s.scale_index else null, | ||
| 599 | }; | ||
| 600 | } | ||
| 601 | |||
| 602 | pub fn bitSize(mem: Memory) u64 { | ||
| 603 | return switch (mem) { | ||
| 604 | .rip => |r| r.ptr_size.bitSize(), | ||
| 605 | .sib => |s| s.ptr_size.bitSize(), | ||
| 606 | .moffs => 64, | ||
| 607 | }; | ||
| 608 | } | ||
| 609 | }; | 563 | }; |
| 610 | 564 | ||
| 611 | pub const Immediate = union(enum) { | 565 | pub const Immediate = union(enum) { |
src/arch/x86_64/encoder.zig+181-85
| ... | @@ -6,9 +6,10 @@ const testing = std.testing; | ... | @@ -6,9 +6,10 @@ const testing = std.testing; |
| 6 | 6 | ||
| 7 | const bits = @import("bits.zig"); | 7 | const bits = @import("bits.zig"); |
| 8 | const Encoding = @import("Encoding.zig"); | 8 | const Encoding = @import("Encoding.zig"); |
| 9 | const FrameIndex = bits.FrameIndex; | ||
| 9 | const Immediate = bits.Immediate; | 10 | const Immediate = bits.Immediate; |
| 10 | const Memory = bits.Memory; | ||
| 11 | const Register = bits.Register; | 11 | const Register = bits.Register; |
| 12 | const Symbol = bits.Symbol; | ||
| 12 | 13 | ||
| 13 | pub const Instruction = struct { | 14 | pub const Instruction = struct { |
| 14 | prefix: Prefix = .none, | 15 | prefix: Prefix = .none, |
| ... | @@ -27,6 +28,97 @@ pub const Instruction = struct { | ... | @@ -27,6 +28,97 @@ pub const Instruction = struct { |
| 27 | repnz, | 28 | repnz, |
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 31 | pub const Memory = union(enum) { | ||
| 32 | sib: Sib, | ||
| 33 | rip: Rip, | ||
| 34 | moffs: Moffs, | ||
| 35 | |||
| 36 | pub const Base = bits.Memory.Base; | ||
| 37 | |||
| 38 | pub const ScaleIndex = struct { | ||
| 39 | scale: u4, | ||
| 40 | index: Register, | ||
| 41 | |||
| 42 | const none = ScaleIndex{ .scale = 0, .index = undefined }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | pub const PtrSize = bits.Memory.Size; | ||
| 46 | |||
| 47 | pub const Sib = struct { | ||
| 48 | ptr_size: PtrSize, | ||
| 49 | base: Base, | ||
| 50 | scale_index: ScaleIndex, | ||
| 51 | disp: i32, | ||
| 52 | }; | ||
| 53 | |||
| 54 | pub const Rip = struct { | ||
| 55 | ptr_size: PtrSize, | ||
| 56 | disp: i32, | ||
| 57 | }; | ||
| 58 | |||
| 59 | pub const Moffs = struct { | ||
| 60 | seg: Register, | ||
| 61 | offset: u64, | ||
| 62 | }; | ||
| 63 | |||
| 64 | pub fn moffs(reg: Register, offset: u64) Memory { | ||
| 65 | assert(reg.class() == .segment); | ||
| 66 | return .{ .moffs = .{ .seg = reg, .offset = offset } }; | ||
| 67 | } | ||
| 68 | |||
| 69 | pub fn sib(ptr_size: PtrSize, args: struct { | ||
| 70 | disp: i32 = 0, | ||
| 71 | base: Base = .none, | ||
| 72 | scale_index: ?ScaleIndex = null, | ||
| 73 | }) Memory { | ||
| 74 | if (args.scale_index) |si| assert(std.math.isPowerOfTwo(si.scale)); | ||
| 75 | return .{ .sib = .{ | ||
| 76 | .base = args.base, | ||
| 77 | .disp = args.disp, | ||
| 78 | .ptr_size = ptr_size, | ||
| 79 | .scale_index = if (args.scale_index) |si| si else ScaleIndex.none, | ||
| 80 | } }; | ||
| 81 | } | ||
| 82 | |||
| 83 | pub fn rip(ptr_size: PtrSize, disp: i32) Memory { | ||
| 84 | return .{ .rip = .{ .ptr_size = ptr_size, .disp = disp } }; | ||
| 85 | } | ||
| 86 | |||
| 87 | pub fn isSegmentRegister(mem: Memory) bool { | ||
| 88 | return switch (mem) { | ||
| 89 | .moffs => true, | ||
| 90 | .rip => false, | ||
| 91 | .sib => |s| switch (s.base) { | ||
| 92 | .none, .frame, .reloc => false, | ||
| 93 | .reg => |reg| reg.class() == .segment, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | } | ||
| 97 | |||
| 98 | pub fn base(mem: Memory) Base { | ||
| 99 | return switch (mem) { | ||
| 100 | .moffs => |m| .{ .reg = m.seg }, | ||
| 101 | .sib => |s| s.base, | ||
| 102 | .rip => .none, | ||
| 103 | }; | ||
| 104 | } | ||
| 105 | |||
| 106 | pub fn scaleIndex(mem: Memory) ?ScaleIndex { | ||
| 107 | return switch (mem) { | ||
| 108 | .moffs, .rip => null, | ||
| 109 | .sib => |s| if (s.scale_index.scale > 0) s.scale_index else null, | ||
| 110 | }; | ||
| 111 | } | ||
| 112 | |||
| 113 | pub fn bitSize(mem: Memory) u64 { | ||
| 114 | return switch (mem) { | ||
| 115 | .rip => |r| r.ptr_size.bitSize(), | ||
| 116 | .sib => |s| s.ptr_size.bitSize(), | ||
| 117 | .moffs => 64, | ||
| 118 | }; | ||
| 119 | } | ||
| 120 | }; | ||
| 121 | |||
| 30 | pub const Operand = union(enum) { | 122 | pub const Operand = union(enum) { |
| 31 | none, | 123 | none, |
| 32 | reg: Register, | 124 | reg: Register, |
| ... | @@ -125,8 +217,8 @@ pub const Instruction = struct { | ... | @@ -125,8 +217,8 @@ pub const Instruction = struct { |
| 125 | try writer.print("{s}", .{@tagName(reg)}); | 217 | try writer.print("{s}", .{@tagName(reg)}); |
| 126 | any = true; | 218 | any = true; |
| 127 | }, | 219 | }, |
| 128 | .frame => |frame| { | 220 | inline .frame, .reloc => |payload| { |
| 129 | try writer.print("{}", .{frame}); | 221 | try writer.print("{}", .{payload}); |
| 130 | any = true; | 222 | any = true; |
| 131 | }, | 223 | }, |
| 132 | } | 224 | } |
| ... | @@ -498,7 +590,11 @@ pub const Instruction = struct { | ... | @@ -498,7 +590,11 @@ pub const Instruction = struct { |
| 498 | } | 590 | } |
| 499 | } | 591 | } |
| 500 | }, | 592 | }, |
| 501 | .frame => if (@TypeOf(encoder).options.allow_frame_loc) { | 593 | .frame => if (@TypeOf(encoder).options.allow_frame_locs) { |
| 594 | try encoder.modRm_indirectDisp32(operand_enc, undefined); | ||
| 595 | try encoder.disp32(undefined); | ||
| 596 | } else return error.CannotEncode, | ||
| 597 | .reloc => if (@TypeOf(encoder).options.allow_symbols) { | ||
| 502 | try encoder.modRm_indirectDisp32(operand_enc, undefined); | 598 | try encoder.modRm_indirectDisp32(operand_enc, undefined); |
| 503 | try encoder.disp32(undefined); | 599 | try encoder.disp32(undefined); |
| 504 | } else return error.CannotEncode, | 600 | } else return error.CannotEncode, |
| ... | @@ -570,7 +666,7 @@ pub const LegacyPrefixes = packed struct { | ... | @@ -570,7 +666,7 @@ pub const LegacyPrefixes = packed struct { |
| 570 | } | 666 | } |
| 571 | }; | 667 | }; |
| 572 | 668 | ||
| 573 | pub const Options = struct { allow_frame_loc: bool = false }; | 669 | pub const Options = struct { allow_frame_locs: bool = false, allow_symbols: bool = false }; |
| 574 | 670 | ||
| 575 | fn Encoder(comptime T: type, comptime opts: Options) type { | 671 | fn Encoder(comptime T: type, comptime opts: Options) type { |
| 576 | return struct { | 672 | return struct { |
| ... | @@ -1085,7 +1181,7 @@ test "lower MI encoding" { | ... | @@ -1085,7 +1181,7 @@ test "lower MI encoding" { |
| 1085 | try expectEqualHexStrings("\x49\xC7\xC4\x00\x10\x00\x00", enc.code(), "mov r12, 0x1000"); | 1181 | try expectEqualHexStrings("\x49\xC7\xC4\x00\x10\x00\x00", enc.code(), "mov r12, 0x1000"); |
| 1086 | 1182 | ||
| 1087 | try enc.encode(.mov, &.{ | 1183 | try enc.encode(.mov, &.{ |
| 1088 | .{ .mem = Memory.sib(.byte, .{ .base = .r12 }) }, | 1184 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .r12 }) }, |
| 1089 | .{ .imm = Immediate.u(0x10) }, | 1185 | .{ .imm = Immediate.u(0x10) }, |
| 1090 | }); | 1186 | }); |
| 1091 | try expectEqualHexStrings("\x41\xC6\x04\x24\x10", enc.code(), "mov BYTE PTR [r12], 0x10"); | 1187 | try expectEqualHexStrings("\x41\xC6\x04\x24\x10", enc.code(), "mov BYTE PTR [r12], 0x10"); |
| ... | @@ -1109,13 +1205,13 @@ test "lower MI encoding" { | ... | @@ -1109,13 +1205,13 @@ test "lower MI encoding" { |
| 1109 | try expectEqualHexStrings("\x48\xc7\xc0\x10\x00\x00\x00", enc.code(), "mov rax, 0x10"); | 1205 | try expectEqualHexStrings("\x48\xc7\xc0\x10\x00\x00\x00", enc.code(), "mov rax, 0x10"); |
| 1110 | 1206 | ||
| 1111 | try enc.encode(.mov, &.{ | 1207 | try enc.encode(.mov, &.{ |
| 1112 | .{ .mem = Memory.sib(.dword, .{ .base = .r11 }) }, | 1208 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .r11 }) }, |
| 1113 | .{ .imm = Immediate.u(0x10) }, | 1209 | .{ .imm = Immediate.u(0x10) }, |
| 1114 | }); | 1210 | }); |
| 1115 | try expectEqualHexStrings("\x41\xc7\x03\x10\x00\x00\x00", enc.code(), "mov DWORD PTR [r11], 0x10"); | 1211 | try expectEqualHexStrings("\x41\xc7\x03\x10\x00\x00\x00", enc.code(), "mov DWORD PTR [r11], 0x10"); |
| 1116 | 1212 | ||
| 1117 | try enc.encode(.mov, &.{ | 1213 | try enc.encode(.mov, &.{ |
| 1118 | .{ .mem = Memory.rip(.qword, 0x10) }, | 1214 | .{ .mem = Instruction.Memory.rip(.qword, 0x10) }, |
| 1119 | .{ .imm = Immediate.u(0x10) }, | 1215 | .{ .imm = Immediate.u(0x10) }, |
| 1120 | }); | 1216 | }); |
| 1121 | try expectEqualHexStrings( | 1217 | try expectEqualHexStrings( |
| ... | @@ -1125,25 +1221,25 @@ test "lower MI encoding" { | ... | @@ -1125,25 +1221,25 @@ test "lower MI encoding" { |
| 1125 | ); | 1221 | ); |
| 1126 | 1222 | ||
| 1127 | try enc.encode(.mov, &.{ | 1223 | try enc.encode(.mov, &.{ |
| 1128 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp, .disp = -8 }) }, | 1224 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp, .disp = -8 }) }, |
| 1129 | .{ .imm = Immediate.u(0x10) }, | 1225 | .{ .imm = Immediate.u(0x10) }, |
| 1130 | }); | 1226 | }); |
| 1131 | try expectEqualHexStrings("\x48\xc7\x45\xf8\x10\x00\x00\x00", enc.code(), "mov QWORD PTR [rbp - 8], 0x10"); | 1227 | try expectEqualHexStrings("\x48\xc7\x45\xf8\x10\x00\x00\x00", enc.code(), "mov QWORD PTR [rbp - 8], 0x10"); |
| 1132 | 1228 | ||
| 1133 | try enc.encode(.mov, &.{ | 1229 | try enc.encode(.mov, &.{ |
| 1134 | .{ .mem = Memory.sib(.word, .{ .base = .rbp, .disp = -2 }) }, | 1230 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp, .disp = -2 }) }, |
| 1135 | .{ .imm = Immediate.s(-16) }, | 1231 | .{ .imm = Immediate.s(-16) }, |
| 1136 | }); | 1232 | }); |
| 1137 | try expectEqualHexStrings("\x66\xC7\x45\xFE\xF0\xFF", enc.code(), "mov WORD PTR [rbp - 2], -16"); | 1233 | try expectEqualHexStrings("\x66\xC7\x45\xFE\xF0\xFF", enc.code(), "mov WORD PTR [rbp - 2], -16"); |
| 1138 | 1234 | ||
| 1139 | try enc.encode(.mov, &.{ | 1235 | try enc.encode(.mov, &.{ |
| 1140 | .{ .mem = Memory.sib(.byte, .{ .base = .rbp, .disp = -1 }) }, | 1236 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .rbp, .disp = -1 }) }, |
| 1141 | .{ .imm = Immediate.u(0x10) }, | 1237 | .{ .imm = Immediate.u(0x10) }, |
| 1142 | }); | 1238 | }); |
| 1143 | try expectEqualHexStrings("\xC6\x45\xFF\x10", enc.code(), "mov BYTE PTR [rbp - 1], 0x10"); | 1239 | try expectEqualHexStrings("\xC6\x45\xFF\x10", enc.code(), "mov BYTE PTR [rbp - 1], 0x10"); |
| 1144 | 1240 | ||
| 1145 | try enc.encode(.mov, &.{ | 1241 | try enc.encode(.mov, &.{ |
| 1146 | .{ .mem = Memory.sib(.qword, .{ | 1242 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1147 | .base = .ds, | 1243 | .base = .ds, |
| 1148 | .disp = 0x10000000, | 1244 | .disp = 0x10000000, |
| 1149 | .scale_index = .{ .scale = 2, .index = .rcx }, | 1245 | .scale_index = .{ .scale = 2, .index = .rcx }, |
| ... | @@ -1157,13 +1253,13 @@ test "lower MI encoding" { | ... | @@ -1157,13 +1253,13 @@ test "lower MI encoding" { |
| 1157 | ); | 1253 | ); |
| 1158 | 1254 | ||
| 1159 | try enc.encode(.adc, &.{ | 1255 | try enc.encode(.adc, &.{ |
| 1160 | .{ .mem = Memory.sib(.byte, .{ .base = .rbp, .disp = -0x10 }) }, | 1256 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .rbp, .disp = -0x10 }) }, |
| 1161 | .{ .imm = Immediate.u(0x10) }, | 1257 | .{ .imm = Immediate.u(0x10) }, |
| 1162 | }); | 1258 | }); |
| 1163 | try expectEqualHexStrings("\x80\x55\xF0\x10", enc.code(), "adc BYTE PTR [rbp - 0x10], 0x10"); | 1259 | try expectEqualHexStrings("\x80\x55\xF0\x10", enc.code(), "adc BYTE PTR [rbp - 0x10], 0x10"); |
| 1164 | 1260 | ||
| 1165 | try enc.encode(.adc, &.{ | 1261 | try enc.encode(.adc, &.{ |
| 1166 | .{ .mem = Memory.rip(.qword, 0) }, | 1262 | .{ .mem = Instruction.Memory.rip(.qword, 0) }, |
| 1167 | .{ .imm = Immediate.u(0x10) }, | 1263 | .{ .imm = Immediate.u(0x10) }, |
| 1168 | }); | 1264 | }); |
| 1169 | try expectEqualHexStrings("\x48\x83\x15\x00\x00\x00\x00\x10", enc.code(), "adc QWORD PTR [rip], 0x10"); | 1265 | try expectEqualHexStrings("\x48\x83\x15\x00\x00\x00\x00\x10", enc.code(), "adc QWORD PTR [rip], 0x10"); |
| ... | @@ -1175,7 +1271,7 @@ test "lower MI encoding" { | ... | @@ -1175,7 +1271,7 @@ test "lower MI encoding" { |
| 1175 | try expectEqualHexStrings("\x48\x83\xD0\x10", enc.code(), "adc rax, 0x10"); | 1271 | try expectEqualHexStrings("\x48\x83\xD0\x10", enc.code(), "adc rax, 0x10"); |
| 1176 | 1272 | ||
| 1177 | try enc.encode(.add, &.{ | 1273 | try enc.encode(.add, &.{ |
| 1178 | .{ .mem = Memory.sib(.dword, .{ .base = .rdx, .disp = -8 }) }, | 1274 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .rdx, .disp = -8 }) }, |
| 1179 | .{ .imm = Immediate.u(0x10) }, | 1275 | .{ .imm = Immediate.u(0x10) }, |
| 1180 | }); | 1276 | }); |
| 1181 | try expectEqualHexStrings("\x83\x42\xF8\x10", enc.code(), "add DWORD PTR [rdx - 8], 0x10"); | 1277 | try expectEqualHexStrings("\x83\x42\xF8\x10", enc.code(), "add DWORD PTR [rdx - 8], 0x10"); |
| ... | @@ -1187,13 +1283,13 @@ test "lower MI encoding" { | ... | @@ -1187,13 +1283,13 @@ test "lower MI encoding" { |
| 1187 | try expectEqualHexStrings("\x48\x83\xC0\x10", enc.code(), "add rax, 0x10"); | 1283 | try expectEqualHexStrings("\x48\x83\xC0\x10", enc.code(), "add rax, 0x10"); |
| 1188 | 1284 | ||
| 1189 | try enc.encode(.add, &.{ | 1285 | try enc.encode(.add, &.{ |
| 1190 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp, .disp = -0x10 }) }, | 1286 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp, .disp = -0x10 }) }, |
| 1191 | .{ .imm = Immediate.s(-0x10) }, | 1287 | .{ .imm = Immediate.s(-0x10) }, |
| 1192 | }); | 1288 | }); |
| 1193 | try expectEqualHexStrings("\x48\x83\x45\xF0\xF0", enc.code(), "add QWORD PTR [rbp - 0x10], -0x10"); | 1289 | try expectEqualHexStrings("\x48\x83\x45\xF0\xF0", enc.code(), "add QWORD PTR [rbp - 0x10], -0x10"); |
| 1194 | 1290 | ||
| 1195 | try enc.encode(.@"and", &.{ | 1291 | try enc.encode(.@"and", &.{ |
| 1196 | .{ .mem = Memory.sib(.dword, .{ .base = .ds, .disp = 0x10000000 }) }, | 1292 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .ds, .disp = 0x10000000 }) }, |
| 1197 | .{ .imm = Immediate.u(0x10) }, | 1293 | .{ .imm = Immediate.u(0x10) }, |
| 1198 | }); | 1294 | }); |
| 1199 | try expectEqualHexStrings( | 1295 | try expectEqualHexStrings( |
| ... | @@ -1203,7 +1299,7 @@ test "lower MI encoding" { | ... | @@ -1203,7 +1299,7 @@ test "lower MI encoding" { |
| 1203 | ); | 1299 | ); |
| 1204 | 1300 | ||
| 1205 | try enc.encode(.@"and", &.{ | 1301 | try enc.encode(.@"and", &.{ |
| 1206 | .{ .mem = Memory.sib(.dword, .{ .base = .es, .disp = 0x10000000 }) }, | 1302 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .es, .disp = 0x10000000 }) }, |
| 1207 | .{ .imm = Immediate.u(0x10) }, | 1303 | .{ .imm = Immediate.u(0x10) }, |
| 1208 | }); | 1304 | }); |
| 1209 | try expectEqualHexStrings( | 1305 | try expectEqualHexStrings( |
| ... | @@ -1213,7 +1309,7 @@ test "lower MI encoding" { | ... | @@ -1213,7 +1309,7 @@ test "lower MI encoding" { |
| 1213 | ); | 1309 | ); |
| 1214 | 1310 | ||
| 1215 | try enc.encode(.@"and", &.{ | 1311 | try enc.encode(.@"and", &.{ |
| 1216 | .{ .mem = Memory.sib(.dword, .{ .base = .r12, .disp = 0x10000000 }) }, | 1312 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .r12, .disp = 0x10000000 }) }, |
| 1217 | .{ .imm = Immediate.u(0x10) }, | 1313 | .{ .imm = Immediate.u(0x10) }, |
| 1218 | }); | 1314 | }); |
| 1219 | try expectEqualHexStrings( | 1315 | try expectEqualHexStrings( |
| ... | @@ -1223,7 +1319,7 @@ test "lower MI encoding" { | ... | @@ -1223,7 +1319,7 @@ test "lower MI encoding" { |
| 1223 | ); | 1319 | ); |
| 1224 | 1320 | ||
| 1225 | try enc.encode(.sub, &.{ | 1321 | try enc.encode(.sub, &.{ |
| 1226 | .{ .mem = Memory.sib(.dword, .{ .base = .r11, .disp = 0x10000000 }) }, | 1322 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .r11, .disp = 0x10000000 }) }, |
| 1227 | .{ .imm = Immediate.u(0x10) }, | 1323 | .{ .imm = Immediate.u(0x10) }, |
| 1228 | }); | 1324 | }); |
| 1229 | try expectEqualHexStrings( | 1325 | try expectEqualHexStrings( |
| ... | @@ -1238,25 +1334,25 @@ test "lower RM encoding" { | ... | @@ -1238,25 +1334,25 @@ test "lower RM encoding" { |
| 1238 | 1334 | ||
| 1239 | try enc.encode(.mov, &.{ | 1335 | try enc.encode(.mov, &.{ |
| 1240 | .{ .reg = .rax }, | 1336 | .{ .reg = .rax }, |
| 1241 | .{ .mem = Memory.sib(.qword, .{ .base = .r11 }) }, | 1337 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .r11 }) }, |
| 1242 | }); | 1338 | }); |
| 1243 | try expectEqualHexStrings("\x49\x8b\x03", enc.code(), "mov rax, QWORD PTR [r11]"); | 1339 | try expectEqualHexStrings("\x49\x8b\x03", enc.code(), "mov rax, QWORD PTR [r11]"); |
| 1244 | 1340 | ||
| 1245 | try enc.encode(.mov, &.{ | 1341 | try enc.encode(.mov, &.{ |
| 1246 | .{ .reg = .rbx }, | 1342 | .{ .reg = .rbx }, |
| 1247 | .{ .mem = Memory.sib(.qword, .{ .base = .ds, .disp = 0x10 }) }, | 1343 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .ds, .disp = 0x10 }) }, |
| 1248 | }); | 1344 | }); |
| 1249 | try expectEqualHexStrings("\x48\x8B\x1C\x25\x10\x00\x00\x00", enc.code(), "mov rbx, QWORD PTR ds:0x10"); | 1345 | try expectEqualHexStrings("\x48\x8B\x1C\x25\x10\x00\x00\x00", enc.code(), "mov rbx, QWORD PTR ds:0x10"); |
| 1250 | 1346 | ||
| 1251 | try enc.encode(.mov, &.{ | 1347 | try enc.encode(.mov, &.{ |
| 1252 | .{ .reg = .rax }, | 1348 | .{ .reg = .rax }, |
| 1253 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp, .disp = -4 }) }, | 1349 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp, .disp = -4 }) }, |
| 1254 | }); | 1350 | }); |
| 1255 | try expectEqualHexStrings("\x48\x8B\x45\xFC", enc.code(), "mov rax, QWORD PTR [rbp - 4]"); | 1351 | try expectEqualHexStrings("\x48\x8B\x45\xFC", enc.code(), "mov rax, QWORD PTR [rbp - 4]"); |
| 1256 | 1352 | ||
| 1257 | try enc.encode(.mov, &.{ | 1353 | try enc.encode(.mov, &.{ |
| 1258 | .{ .reg = .rax }, | 1354 | .{ .reg = .rax }, |
| 1259 | .{ .mem = Memory.sib(.qword, .{ | 1355 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1260 | .base = .rbp, | 1356 | .base = .rbp, |
| 1261 | .scale_index = .{ .scale = 1, .index = .rcx }, | 1357 | .scale_index = .{ .scale = 1, .index = .rcx }, |
| 1262 | .disp = -8, | 1358 | .disp = -8, |
| ... | @@ -1266,7 +1362,7 @@ test "lower RM encoding" { | ... | @@ -1266,7 +1362,7 @@ test "lower RM encoding" { |
| 1266 | 1362 | ||
| 1267 | try enc.encode(.mov, &.{ | 1363 | try enc.encode(.mov, &.{ |
| 1268 | .{ .reg = .eax }, | 1364 | .{ .reg = .eax }, |
| 1269 | .{ .mem = Memory.sib(.dword, .{ | 1365 | .{ .mem = Instruction.Memory.sib(.dword, .{ |
| 1270 | .base = .rbp, | 1366 | .base = .rbp, |
| 1271 | .scale_index = .{ .scale = 4, .index = .rdx }, | 1367 | .scale_index = .{ .scale = 4, .index = .rdx }, |
| 1272 | .disp = -4, | 1368 | .disp = -4, |
| ... | @@ -1276,7 +1372,7 @@ test "lower RM encoding" { | ... | @@ -1276,7 +1372,7 @@ test "lower RM encoding" { |
| 1276 | 1372 | ||
| 1277 | try enc.encode(.mov, &.{ | 1373 | try enc.encode(.mov, &.{ |
| 1278 | .{ .reg = .rax }, | 1374 | .{ .reg = .rax }, |
| 1279 | .{ .mem = Memory.sib(.qword, .{ | 1375 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1280 | .base = .rbp, | 1376 | .base = .rbp, |
| 1281 | .scale_index = .{ .scale = 8, .index = .rcx }, | 1377 | .scale_index = .{ .scale = 8, .index = .rcx }, |
| 1282 | .disp = -8, | 1378 | .disp = -8, |
| ... | @@ -1286,7 +1382,7 @@ test "lower RM encoding" { | ... | @@ -1286,7 +1382,7 @@ test "lower RM encoding" { |
| 1286 | 1382 | ||
| 1287 | try enc.encode(.mov, &.{ | 1383 | try enc.encode(.mov, &.{ |
| 1288 | .{ .reg = .r8b }, | 1384 | .{ .reg = .r8b }, |
| 1289 | .{ .mem = Memory.sib(.byte, .{ | 1385 | .{ .mem = Instruction.Memory.sib(.byte, .{ |
| 1290 | .base = .rsi, | 1386 | .base = .rsi, |
| 1291 | .scale_index = .{ .scale = 1, .index = .rcx }, | 1387 | .scale_index = .{ .scale = 1, .index = .rcx }, |
| 1292 | .disp = -24, | 1388 | .disp = -24, |
| ... | @@ -1302,7 +1398,7 @@ test "lower RM encoding" { | ... | @@ -1302,7 +1398,7 @@ test "lower RM encoding" { |
| 1302 | try expectEqualHexStrings("\x48\x8C\xC8", enc.code(), "mov rax, cs"); | 1398 | try expectEqualHexStrings("\x48\x8C\xC8", enc.code(), "mov rax, cs"); |
| 1303 | 1399 | ||
| 1304 | try enc.encode(.mov, &.{ | 1400 | try enc.encode(.mov, &.{ |
| 1305 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp, .disp = -16 }) }, | 1401 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp, .disp = -16 }) }, |
| 1306 | .{ .reg = .fs }, | 1402 | .{ .reg = .fs }, |
| 1307 | }); | 1403 | }); |
| 1308 | try expectEqualHexStrings("\x48\x8C\x65\xF0", enc.code(), "mov QWORD PTR [rbp - 16], fs"); | 1404 | try expectEqualHexStrings("\x48\x8C\x65\xF0", enc.code(), "mov QWORD PTR [rbp - 16], fs"); |
| ... | @@ -1314,7 +1410,7 @@ test "lower RM encoding" { | ... | @@ -1314,7 +1410,7 @@ test "lower RM encoding" { |
| 1314 | try expectEqualHexStrings("\x66\x41\x8C\xCC", enc.code(), "mov r12w, cs"); | 1410 | try expectEqualHexStrings("\x66\x41\x8C\xCC", enc.code(), "mov r12w, cs"); |
| 1315 | 1411 | ||
| 1316 | try enc.encode(.mov, &.{ | 1412 | try enc.encode(.mov, &.{ |
| 1317 | .{ .mem = Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, | 1413 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, |
| 1318 | .{ .reg = .fs }, | 1414 | .{ .reg = .fs }, |
| 1319 | }); | 1415 | }); |
| 1320 | try expectEqualHexStrings("\x66\x8C\x65\xF0", enc.code(), "mov WORD PTR [rbp - 16], fs"); | 1416 | try expectEqualHexStrings("\x66\x8C\x65\xF0", enc.code(), "mov WORD PTR [rbp - 16], fs"); |
| ... | @@ -1339,19 +1435,19 @@ test "lower RM encoding" { | ... | @@ -1339,19 +1435,19 @@ test "lower RM encoding" { |
| 1339 | 1435 | ||
| 1340 | try enc.encode(.movsx, &.{ | 1436 | try enc.encode(.movsx, &.{ |
| 1341 | .{ .reg = .eax }, | 1437 | .{ .reg = .eax }, |
| 1342 | .{ .mem = Memory.sib(.word, .{ .base = .rbp }) }, | 1438 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp }) }, |
| 1343 | }); | 1439 | }); |
| 1344 | try expectEqualHexStrings("\x0F\xBF\x45\x00", enc.code(), "movsx eax, BYTE PTR [rbp]"); | 1440 | try expectEqualHexStrings("\x0F\xBF\x45\x00", enc.code(), "movsx eax, BYTE PTR [rbp]"); |
| 1345 | 1441 | ||
| 1346 | try enc.encode(.movsx, &.{ | 1442 | try enc.encode(.movsx, &.{ |
| 1347 | .{ .reg = .eax }, | 1443 | .{ .reg = .eax }, |
| 1348 | .{ .mem = Memory.sib(.byte, .{ .scale_index = .{ .index = .rax, .scale = 2 } }) }, | 1444 | .{ .mem = Instruction.Memory.sib(.byte, .{ .scale_index = .{ .index = .rax, .scale = 2 } }) }, |
| 1349 | }); | 1445 | }); |
| 1350 | try expectEqualHexStrings("\x0F\xBE\x04\x45\x00\x00\x00\x00", enc.code(), "movsx eax, BYTE PTR [rax * 2]"); | 1446 | try expectEqualHexStrings("\x0F\xBE\x04\x45\x00\x00\x00\x00", enc.code(), "movsx eax, BYTE PTR [rax * 2]"); |
| 1351 | 1447 | ||
| 1352 | try enc.encode(.movsx, &.{ | 1448 | try enc.encode(.movsx, &.{ |
| 1353 | .{ .reg = .ax }, | 1449 | .{ .reg = .ax }, |
| 1354 | .{ .mem = Memory.rip(.byte, 0x10) }, | 1450 | .{ .mem = Instruction.Memory.rip(.byte, 0x10) }, |
| 1355 | }); | 1451 | }); |
| 1356 | try expectEqualHexStrings("\x66\x0F\xBE\x05\x10\x00\x00\x00", enc.code(), "movsx ax, BYTE PTR [rip + 0x10]"); | 1452 | try expectEqualHexStrings("\x66\x0F\xBE\x05\x10\x00\x00\x00", enc.code(), "movsx ax, BYTE PTR [rip + 0x10]"); |
| 1357 | 1453 | ||
| ... | @@ -1369,37 +1465,37 @@ test "lower RM encoding" { | ... | @@ -1369,37 +1465,37 @@ test "lower RM encoding" { |
| 1369 | 1465 | ||
| 1370 | try enc.encode(.lea, &.{ | 1466 | try enc.encode(.lea, &.{ |
| 1371 | .{ .reg = .rax }, | 1467 | .{ .reg = .rax }, |
| 1372 | .{ .mem = Memory.rip(.qword, 0x10) }, | 1468 | .{ .mem = Instruction.Memory.rip(.qword, 0x10) }, |
| 1373 | }); | 1469 | }); |
| 1374 | try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", enc.code(), "lea rax, QWORD PTR [rip + 0x10]"); | 1470 | try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", enc.code(), "lea rax, QWORD PTR [rip + 0x10]"); |
| 1375 | 1471 | ||
| 1376 | try enc.encode(.lea, &.{ | 1472 | try enc.encode(.lea, &.{ |
| 1377 | .{ .reg = .rax }, | 1473 | .{ .reg = .rax }, |
| 1378 | .{ .mem = Memory.rip(.dword, 0x10) }, | 1474 | .{ .mem = Instruction.Memory.rip(.dword, 0x10) }, |
| 1379 | }); | 1475 | }); |
| 1380 | try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", enc.code(), "lea rax, DWORD PTR [rip + 0x10]"); | 1476 | try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", enc.code(), "lea rax, DWORD PTR [rip + 0x10]"); |
| 1381 | 1477 | ||
| 1382 | try enc.encode(.lea, &.{ | 1478 | try enc.encode(.lea, &.{ |
| 1383 | .{ .reg = .eax }, | 1479 | .{ .reg = .eax }, |
| 1384 | .{ .mem = Memory.rip(.dword, 0x10) }, | 1480 | .{ .mem = Instruction.Memory.rip(.dword, 0x10) }, |
| 1385 | }); | 1481 | }); |
| 1386 | try expectEqualHexStrings("\x8D\x05\x10\x00\x00\x00", enc.code(), "lea eax, DWORD PTR [rip + 0x10]"); | 1482 | try expectEqualHexStrings("\x8D\x05\x10\x00\x00\x00", enc.code(), "lea eax, DWORD PTR [rip + 0x10]"); |
| 1387 | 1483 | ||
| 1388 | try enc.encode(.lea, &.{ | 1484 | try enc.encode(.lea, &.{ |
| 1389 | .{ .reg = .eax }, | 1485 | .{ .reg = .eax }, |
| 1390 | .{ .mem = Memory.rip(.word, 0x10) }, | 1486 | .{ .mem = Instruction.Memory.rip(.word, 0x10) }, |
| 1391 | }); | 1487 | }); |
| 1392 | try expectEqualHexStrings("\x8D\x05\x10\x00\x00\x00", enc.code(), "lea eax, WORD PTR [rip + 0x10]"); | 1488 | try expectEqualHexStrings("\x8D\x05\x10\x00\x00\x00", enc.code(), "lea eax, WORD PTR [rip + 0x10]"); |
| 1393 | 1489 | ||
| 1394 | try enc.encode(.lea, &.{ | 1490 | try enc.encode(.lea, &.{ |
| 1395 | .{ .reg = .ax }, | 1491 | .{ .reg = .ax }, |
| 1396 | .{ .mem = Memory.rip(.byte, 0x10) }, | 1492 | .{ .mem = Instruction.Memory.rip(.byte, 0x10) }, |
| 1397 | }); | 1493 | }); |
| 1398 | try expectEqualHexStrings("\x66\x8D\x05\x10\x00\x00\x00", enc.code(), "lea ax, BYTE PTR [rip + 0x10]"); | 1494 | try expectEqualHexStrings("\x66\x8D\x05\x10\x00\x00\x00", enc.code(), "lea ax, BYTE PTR [rip + 0x10]"); |
| 1399 | 1495 | ||
| 1400 | try enc.encode(.lea, &.{ | 1496 | try enc.encode(.lea, &.{ |
| 1401 | .{ .reg = .rsi }, | 1497 | .{ .reg = .rsi }, |
| 1402 | .{ .mem = Memory.sib(.qword, .{ | 1498 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1403 | .base = .rbp, | 1499 | .base = .rbp, |
| 1404 | .scale_index = .{ .scale = 1, .index = .rcx }, | 1500 | .scale_index = .{ .scale = 1, .index = .rcx }, |
| 1405 | }) }, | 1501 | }) }, |
| ... | @@ -1408,31 +1504,31 @@ test "lower RM encoding" { | ... | @@ -1408,31 +1504,31 @@ test "lower RM encoding" { |
| 1408 | 1504 | ||
| 1409 | try enc.encode(.add, &.{ | 1505 | try enc.encode(.add, &.{ |
| 1410 | .{ .reg = .r11 }, | 1506 | .{ .reg = .r11 }, |
| 1411 | .{ .mem = Memory.sib(.qword, .{ .base = .ds, .disp = 0x10000000 }) }, | 1507 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .ds, .disp = 0x10000000 }) }, |
| 1412 | }); | 1508 | }); |
| 1413 | try expectEqualHexStrings("\x4C\x03\x1C\x25\x00\x00\x00\x10", enc.code(), "add r11, QWORD PTR ds:0x10000000"); | 1509 | try expectEqualHexStrings("\x4C\x03\x1C\x25\x00\x00\x00\x10", enc.code(), "add r11, QWORD PTR ds:0x10000000"); |
| 1414 | 1510 | ||
| 1415 | try enc.encode(.add, &.{ | 1511 | try enc.encode(.add, &.{ |
| 1416 | .{ .reg = .r12b }, | 1512 | .{ .reg = .r12b }, |
| 1417 | .{ .mem = Memory.sib(.byte, .{ .base = .ds, .disp = 0x10000000 }) }, | 1513 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .ds, .disp = 0x10000000 }) }, |
| 1418 | }); | 1514 | }); |
| 1419 | try expectEqualHexStrings("\x44\x02\x24\x25\x00\x00\x00\x10", enc.code(), "add r11b, BYTE PTR ds:0x10000000"); | 1515 | try expectEqualHexStrings("\x44\x02\x24\x25\x00\x00\x00\x10", enc.code(), "add r11b, BYTE PTR ds:0x10000000"); |
| 1420 | 1516 | ||
| 1421 | try enc.encode(.add, &.{ | 1517 | try enc.encode(.add, &.{ |
| 1422 | .{ .reg = .r12b }, | 1518 | .{ .reg = .r12b }, |
| 1423 | .{ .mem = Memory.sib(.byte, .{ .base = .fs, .disp = 0x10000000 }) }, | 1519 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .fs, .disp = 0x10000000 }) }, |
| 1424 | }); | 1520 | }); |
| 1425 | try expectEqualHexStrings("\x64\x44\x02\x24\x25\x00\x00\x00\x10", enc.code(), "add r11b, BYTE PTR fs:0x10000000"); | 1521 | try expectEqualHexStrings("\x64\x44\x02\x24\x25\x00\x00\x00\x10", enc.code(), "add r11b, BYTE PTR fs:0x10000000"); |
| 1426 | 1522 | ||
| 1427 | try enc.encode(.sub, &.{ | 1523 | try enc.encode(.sub, &.{ |
| 1428 | .{ .reg = .r11 }, | 1524 | .{ .reg = .r11 }, |
| 1429 | .{ .mem = Memory.sib(.qword, .{ .base = .r13, .disp = 0x10000000 }) }, | 1525 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .r13, .disp = 0x10000000 }) }, |
| 1430 | }); | 1526 | }); |
| 1431 | try expectEqualHexStrings("\x4D\x2B\x9D\x00\x00\x00\x10", enc.code(), "sub r11, QWORD PTR [r13 + 0x10000000]"); | 1527 | try expectEqualHexStrings("\x4D\x2B\x9D\x00\x00\x00\x10", enc.code(), "sub r11, QWORD PTR [r13 + 0x10000000]"); |
| 1432 | 1528 | ||
| 1433 | try enc.encode(.sub, &.{ | 1529 | try enc.encode(.sub, &.{ |
| 1434 | .{ .reg = .r11 }, | 1530 | .{ .reg = .r11 }, |
| 1435 | .{ .mem = Memory.sib(.qword, .{ .base = .r12, .disp = 0x10000000 }) }, | 1531 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .r12, .disp = 0x10000000 }) }, |
| 1436 | }); | 1532 | }); |
| 1437 | try expectEqualHexStrings("\x4D\x2B\x9C\x24\x00\x00\x00\x10", enc.code(), "sub r11, QWORD PTR [r12 + 0x10000000]"); | 1533 | try expectEqualHexStrings("\x4D\x2B\x9C\x24\x00\x00\x00\x10", enc.code(), "sub r11, QWORD PTR [r12 + 0x10000000]"); |
| 1438 | 1534 | ||
| ... | @@ -1455,7 +1551,7 @@ test "lower RMI encoding" { | ... | @@ -1455,7 +1551,7 @@ test "lower RMI encoding" { |
| 1455 | 1551 | ||
| 1456 | try enc.encode(.imul, &.{ | 1552 | try enc.encode(.imul, &.{ |
| 1457 | .{ .reg = .r11 }, | 1553 | .{ .reg = .r11 }, |
| 1458 | .{ .mem = Memory.rip(.qword, -16) }, | 1554 | .{ .mem = Instruction.Memory.rip(.qword, -16) }, |
| 1459 | .{ .imm = Immediate.s(-1024) }, | 1555 | .{ .imm = Immediate.s(-1024) }, |
| 1460 | }); | 1556 | }); |
| 1461 | try expectEqualHexStrings( | 1557 | try expectEqualHexStrings( |
| ... | @@ -1466,7 +1562,7 @@ test "lower RMI encoding" { | ... | @@ -1466,7 +1562,7 @@ test "lower RMI encoding" { |
| 1466 | 1562 | ||
| 1467 | try enc.encode(.imul, &.{ | 1563 | try enc.encode(.imul, &.{ |
| 1468 | .{ .reg = .bx }, | 1564 | .{ .reg = .bx }, |
| 1469 | .{ .mem = Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, | 1565 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, |
| 1470 | .{ .imm = Immediate.s(-1024) }, | 1566 | .{ .imm = Immediate.s(-1024) }, |
| 1471 | }); | 1567 | }); |
| 1472 | try expectEqualHexStrings( | 1568 | try expectEqualHexStrings( |
| ... | @@ -1477,7 +1573,7 @@ test "lower RMI encoding" { | ... | @@ -1477,7 +1573,7 @@ test "lower RMI encoding" { |
| 1477 | 1573 | ||
| 1478 | try enc.encode(.imul, &.{ | 1574 | try enc.encode(.imul, &.{ |
| 1479 | .{ .reg = .bx }, | 1575 | .{ .reg = .bx }, |
| 1480 | .{ .mem = Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, | 1576 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp, .disp = -16 }) }, |
| 1481 | .{ .imm = Immediate.u(1024) }, | 1577 | .{ .imm = Immediate.u(1024) }, |
| 1482 | }); | 1578 | }); |
| 1483 | try expectEqualHexStrings( | 1579 | try expectEqualHexStrings( |
| ... | @@ -1497,19 +1593,19 @@ test "lower MR encoding" { | ... | @@ -1497,19 +1593,19 @@ test "lower MR encoding" { |
| 1497 | try expectEqualHexStrings("\x48\x89\xD8", enc.code(), "mov rax, rbx"); | 1593 | try expectEqualHexStrings("\x48\x89\xD8", enc.code(), "mov rax, rbx"); |
| 1498 | 1594 | ||
| 1499 | try enc.encode(.mov, &.{ | 1595 | try enc.encode(.mov, &.{ |
| 1500 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp, .disp = -4 }) }, | 1596 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp, .disp = -4 }) }, |
| 1501 | .{ .reg = .r11 }, | 1597 | .{ .reg = .r11 }, |
| 1502 | }); | 1598 | }); |
| 1503 | try expectEqualHexStrings("\x4c\x89\x5d\xfc", enc.code(), "mov QWORD PTR [rbp - 4], r11"); | 1599 | try expectEqualHexStrings("\x4c\x89\x5d\xfc", enc.code(), "mov QWORD PTR [rbp - 4], r11"); |
| 1504 | 1600 | ||
| 1505 | try enc.encode(.mov, &.{ | 1601 | try enc.encode(.mov, &.{ |
| 1506 | .{ .mem = Memory.rip(.qword, 0x10) }, | 1602 | .{ .mem = Instruction.Memory.rip(.qword, 0x10) }, |
| 1507 | .{ .reg = .r12 }, | 1603 | .{ .reg = .r12 }, |
| 1508 | }); | 1604 | }); |
| 1509 | try expectEqualHexStrings("\x4C\x89\x25\x10\x00\x00\x00", enc.code(), "mov QWORD PTR [rip + 0x10], r12"); | 1605 | try expectEqualHexStrings("\x4C\x89\x25\x10\x00\x00\x00", enc.code(), "mov QWORD PTR [rip + 0x10], r12"); |
| 1510 | 1606 | ||
| 1511 | try enc.encode(.mov, &.{ | 1607 | try enc.encode(.mov, &.{ |
| 1512 | .{ .mem = Memory.sib(.qword, .{ | 1608 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1513 | .base = .r11, | 1609 | .base = .r11, |
| 1514 | .scale_index = .{ .scale = 2, .index = .r12 }, | 1610 | .scale_index = .{ .scale = 2, .index = .r12 }, |
| 1515 | .disp = 0x10, | 1611 | .disp = 0x10, |
| ... | @@ -1519,13 +1615,13 @@ test "lower MR encoding" { | ... | @@ -1519,13 +1615,13 @@ test "lower MR encoding" { |
| 1519 | try expectEqualHexStrings("\x4F\x89\x6C\x63\x10", enc.code(), "mov QWORD PTR [r11 + 2 * r12 + 0x10], r13"); | 1615 | try expectEqualHexStrings("\x4F\x89\x6C\x63\x10", enc.code(), "mov QWORD PTR [r11 + 2 * r12 + 0x10], r13"); |
| 1520 | 1616 | ||
| 1521 | try enc.encode(.mov, &.{ | 1617 | try enc.encode(.mov, &.{ |
| 1522 | .{ .mem = Memory.rip(.word, -0x10) }, | 1618 | .{ .mem = Instruction.Memory.rip(.word, -0x10) }, |
| 1523 | .{ .reg = .r12w }, | 1619 | .{ .reg = .r12w }, |
| 1524 | }); | 1620 | }); |
| 1525 | try expectEqualHexStrings("\x66\x44\x89\x25\xF0\xFF\xFF\xFF", enc.code(), "mov WORD PTR [rip - 0x10], r12w"); | 1621 | try expectEqualHexStrings("\x66\x44\x89\x25\xF0\xFF\xFF\xFF", enc.code(), "mov WORD PTR [rip - 0x10], r12w"); |
| 1526 | 1622 | ||
| 1527 | try enc.encode(.mov, &.{ | 1623 | try enc.encode(.mov, &.{ |
| 1528 | .{ .mem = Memory.sib(.byte, .{ | 1624 | .{ .mem = Instruction.Memory.sib(.byte, .{ |
| 1529 | .base = .r11, | 1625 | .base = .r11, |
| 1530 | .scale_index = .{ .scale = 2, .index = .r12 }, | 1626 | .scale_index = .{ .scale = 2, .index = .r12 }, |
| 1531 | .disp = 0x10, | 1627 | .disp = 0x10, |
| ... | @@ -1535,25 +1631,25 @@ test "lower MR encoding" { | ... | @@ -1535,25 +1631,25 @@ test "lower MR encoding" { |
| 1535 | try expectEqualHexStrings("\x47\x88\x6C\x63\x10", enc.code(), "mov BYTE PTR [r11 + 2 * r12 + 0x10], r13b"); | 1631 | try expectEqualHexStrings("\x47\x88\x6C\x63\x10", enc.code(), "mov BYTE PTR [r11 + 2 * r12 + 0x10], r13b"); |
| 1536 | 1632 | ||
| 1537 | try enc.encode(.add, &.{ | 1633 | try enc.encode(.add, &.{ |
| 1538 | .{ .mem = Memory.sib(.byte, .{ .base = .ds, .disp = 0x10000000 }) }, | 1634 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .ds, .disp = 0x10000000 }) }, |
| 1539 | .{ .reg = .r12b }, | 1635 | .{ .reg = .r12b }, |
| 1540 | }); | 1636 | }); |
| 1541 | try expectEqualHexStrings("\x44\x00\x24\x25\x00\x00\x00\x10", enc.code(), "add BYTE PTR ds:0x10000000, r12b"); | 1637 | try expectEqualHexStrings("\x44\x00\x24\x25\x00\x00\x00\x10", enc.code(), "add BYTE PTR ds:0x10000000, r12b"); |
| 1542 | 1638 | ||
| 1543 | try enc.encode(.add, &.{ | 1639 | try enc.encode(.add, &.{ |
| 1544 | .{ .mem = Memory.sib(.dword, .{ .base = .ds, .disp = 0x10000000 }) }, | 1640 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .ds, .disp = 0x10000000 }) }, |
| 1545 | .{ .reg = .r12d }, | 1641 | .{ .reg = .r12d }, |
| 1546 | }); | 1642 | }); |
| 1547 | try expectEqualHexStrings("\x44\x01\x24\x25\x00\x00\x00\x10", enc.code(), "add DWORD PTR [ds:0x10000000], r12d"); | 1643 | try expectEqualHexStrings("\x44\x01\x24\x25\x00\x00\x00\x10", enc.code(), "add DWORD PTR [ds:0x10000000], r12d"); |
| 1548 | 1644 | ||
| 1549 | try enc.encode(.add, &.{ | 1645 | try enc.encode(.add, &.{ |
| 1550 | .{ .mem = Memory.sib(.dword, .{ .base = .gs, .disp = 0x10000000 }) }, | 1646 | .{ .mem = Instruction.Memory.sib(.dword, .{ .base = .gs, .disp = 0x10000000 }) }, |
| 1551 | .{ .reg = .r12d }, | 1647 | .{ .reg = .r12d }, |
| 1552 | }); | 1648 | }); |
| 1553 | try expectEqualHexStrings("\x65\x44\x01\x24\x25\x00\x00\x00\x10", enc.code(), "add DWORD PTR [gs:0x10000000], r12d"); | 1649 | try expectEqualHexStrings("\x65\x44\x01\x24\x25\x00\x00\x00\x10", enc.code(), "add DWORD PTR [gs:0x10000000], r12d"); |
| 1554 | 1650 | ||
| 1555 | try enc.encode(.sub, &.{ | 1651 | try enc.encode(.sub, &.{ |
| 1556 | .{ .mem = Memory.sib(.qword, .{ .base = .r11, .disp = 0x10000000 }) }, | 1652 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .r11, .disp = 0x10000000 }) }, |
| 1557 | .{ .reg = .r12 }, | 1653 | .{ .reg = .r12 }, |
| 1558 | }); | 1654 | }); |
| 1559 | try expectEqualHexStrings("\x4D\x29\xA3\x00\x00\x00\x10", enc.code(), "sub QWORD PTR [r11 + 0x10000000], r12"); | 1655 | try expectEqualHexStrings("\x4D\x29\xA3\x00\x00\x00\x10", enc.code(), "sub QWORD PTR [r11 + 0x10000000], r12"); |
| ... | @@ -1568,12 +1664,12 @@ test "lower M encoding" { | ... | @@ -1568,12 +1664,12 @@ test "lower M encoding" { |
| 1568 | try expectEqualHexStrings("\x41\xFF\xD4", enc.code(), "call r12"); | 1664 | try expectEqualHexStrings("\x41\xFF\xD4", enc.code(), "call r12"); |
| 1569 | 1665 | ||
| 1570 | try enc.encode(.call, &.{ | 1666 | try enc.encode(.call, &.{ |
| 1571 | .{ .mem = Memory.sib(.qword, .{ .base = .r12 }) }, | 1667 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .r12 }) }, |
| 1572 | }); | 1668 | }); |
| 1573 | try expectEqualHexStrings("\x41\xFF\x14\x24", enc.code(), "call QWORD PTR [r12]"); | 1669 | try expectEqualHexStrings("\x41\xFF\x14\x24", enc.code(), "call QWORD PTR [r12]"); |
| 1574 | 1670 | ||
| 1575 | try enc.encode(.call, &.{ | 1671 | try enc.encode(.call, &.{ |
| 1576 | .{ .mem = Memory.sib(.qword, .{ | 1672 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1577 | .base = null, | 1673 | .base = null, |
| 1578 | .scale_index = .{ .index = .r11, .scale = 2 }, | 1674 | .scale_index = .{ .index = .r11, .scale = 2 }, |
| 1579 | }) }, | 1675 | }) }, |
| ... | @@ -1581,7 +1677,7 @@ test "lower M encoding" { | ... | @@ -1581,7 +1677,7 @@ test "lower M encoding" { |
| 1581 | try expectEqualHexStrings("\x42\xFF\x14\x5D\x00\x00\x00\x00", enc.code(), "call QWORD PTR [r11 * 2]"); | 1677 | try expectEqualHexStrings("\x42\xFF\x14\x5D\x00\x00\x00\x00", enc.code(), "call QWORD PTR [r11 * 2]"); |
| 1582 | 1678 | ||
| 1583 | try enc.encode(.call, &.{ | 1679 | try enc.encode(.call, &.{ |
| 1584 | .{ .mem = Memory.sib(.qword, .{ | 1680 | .{ .mem = Instruction.Memory.sib(.qword, .{ |
| 1585 | .base = null, | 1681 | .base = null, |
| 1586 | .scale_index = .{ .index = .r12, .scale = 2 }, | 1682 | .scale_index = .{ .index = .r12, .scale = 2 }, |
| 1587 | }) }, | 1683 | }) }, |
| ... | @@ -1589,7 +1685,7 @@ test "lower M encoding" { | ... | @@ -1589,7 +1685,7 @@ test "lower M encoding" { |
| 1589 | try expectEqualHexStrings("\x42\xFF\x14\x65\x00\x00\x00\x00", enc.code(), "call QWORD PTR [r12 * 2]"); | 1685 | try expectEqualHexStrings("\x42\xFF\x14\x65\x00\x00\x00\x00", enc.code(), "call QWORD PTR [r12 * 2]"); |
| 1590 | 1686 | ||
| 1591 | try enc.encode(.call, &.{ | 1687 | try enc.encode(.call, &.{ |
| 1592 | .{ .mem = Memory.sib(.qword, .{ .base = .gs }) }, | 1688 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .gs }) }, |
| 1593 | }); | 1689 | }); |
| 1594 | try expectEqualHexStrings("\x65\xFF\x14\x25\x00\x00\x00\x00", enc.code(), "call gs:0x0"); | 1690 | try expectEqualHexStrings("\x65\xFF\x14\x25\x00\x00\x00\x00", enc.code(), "call gs:0x0"); |
| 1595 | 1691 | ||
| ... | @@ -1599,22 +1695,22 @@ test "lower M encoding" { | ... | @@ -1599,22 +1695,22 @@ test "lower M encoding" { |
| 1599 | try expectEqualHexStrings("\xE8\x00\x00\x00\x00", enc.code(), "call 0x0"); | 1695 | try expectEqualHexStrings("\xE8\x00\x00\x00\x00", enc.code(), "call 0x0"); |
| 1600 | 1696 | ||
| 1601 | try enc.encode(.push, &.{ | 1697 | try enc.encode(.push, &.{ |
| 1602 | .{ .mem = Memory.sib(.qword, .{ .base = .rbp }) }, | 1698 | .{ .mem = Instruction.Memory.sib(.qword, .{ .base = .rbp }) }, |
| 1603 | }); | 1699 | }); |
| 1604 | try expectEqualHexStrings("\xFF\x75\x00", enc.code(), "push QWORD PTR [rbp]"); | 1700 | try expectEqualHexStrings("\xFF\x75\x00", enc.code(), "push QWORD PTR [rbp]"); |
| 1605 | 1701 | ||
| 1606 | try enc.encode(.push, &.{ | 1702 | try enc.encode(.push, &.{ |
| 1607 | .{ .mem = Memory.sib(.word, .{ .base = .rbp }) }, | 1703 | .{ .mem = Instruction.Memory.sib(.word, .{ .base = .rbp }) }, |
| 1608 | }); | 1704 | }); |
| 1609 | try expectEqualHexStrings("\x66\xFF\x75\x00", enc.code(), "push QWORD PTR [rbp]"); | 1705 | try expectEqualHexStrings("\x66\xFF\x75\x00", enc.code(), "push QWORD PTR [rbp]"); |
| 1610 | 1706 | ||
| 1611 | try enc.encode(.pop, &.{ | 1707 | try enc.encode(.pop, &.{ |
| 1612 | .{ .mem = Memory.rip(.qword, 0) }, | 1708 | .{ .mem = Instruction.Memory.rip(.qword, 0) }, |
| 1613 | }); | 1709 | }); |
| 1614 | try expectEqualHexStrings("\x8F\x05\x00\x00\x00\x00", enc.code(), "pop QWORD PTR [rip]"); | 1710 | try expectEqualHexStrings("\x8F\x05\x00\x00\x00\x00", enc.code(), "pop QWORD PTR [rip]"); |
| 1615 | 1711 | ||
| 1616 | try enc.encode(.pop, &.{ | 1712 | try enc.encode(.pop, &.{ |
| 1617 | .{ .mem = Memory.rip(.word, 0) }, | 1713 | .{ .mem = Instruction.Memory.rip(.word, 0) }, |
| 1618 | }); | 1714 | }); |
| 1619 | try expectEqualHexStrings("\x66\x8F\x05\x00\x00\x00\x00", enc.code(), "pop WORD PTR [rbp]"); | 1715 | try expectEqualHexStrings("\x66\x8F\x05\x00\x00\x00\x00", enc.code(), "pop WORD PTR [rbp]"); |
| 1620 | 1716 | ||
| ... | @@ -1695,48 +1791,48 @@ test "lower FD/TD encoding" { | ... | @@ -1695,48 +1791,48 @@ test "lower FD/TD encoding" { |
| 1695 | 1791 | ||
| 1696 | try enc.encode(.mov, &.{ | 1792 | try enc.encode(.mov, &.{ |
| 1697 | .{ .reg = .rax }, | 1793 | .{ .reg = .rax }, |
| 1698 | .{ .mem = Memory.moffs(.cs, 0x10) }, | 1794 | .{ .mem = Instruction.Memory.moffs(.cs, 0x10) }, |
| 1699 | }); | 1795 | }); |
| 1700 | try expectEqualHexStrings("\x2E\x48\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs rax, cs:0x10"); | 1796 | try expectEqualHexStrings("\x2E\x48\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs rax, cs:0x10"); |
| 1701 | 1797 | ||
| 1702 | try enc.encode(.mov, &.{ | 1798 | try enc.encode(.mov, &.{ |
| 1703 | .{ .reg = .eax }, | 1799 | .{ .reg = .eax }, |
| 1704 | .{ .mem = Memory.moffs(.fs, 0x10) }, | 1800 | .{ .mem = Instruction.Memory.moffs(.fs, 0x10) }, |
| 1705 | }); | 1801 | }); |
| 1706 | try expectEqualHexStrings("\x64\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs eax, fs:0x10"); | 1802 | try expectEqualHexStrings("\x64\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs eax, fs:0x10"); |
| 1707 | 1803 | ||
| 1708 | try enc.encode(.mov, &.{ | 1804 | try enc.encode(.mov, &.{ |
| 1709 | .{ .reg = .ax }, | 1805 | .{ .reg = .ax }, |
| 1710 | .{ .mem = Memory.moffs(.gs, 0x10) }, | 1806 | .{ .mem = Instruction.Memory.moffs(.gs, 0x10) }, |
| 1711 | }); | 1807 | }); |
| 1712 | try expectEqualHexStrings("\x65\x66\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs ax, gs:0x10"); | 1808 | try expectEqualHexStrings("\x65\x66\xA1\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs ax, gs:0x10"); |
| 1713 | 1809 | ||
| 1714 | try enc.encode(.mov, &.{ | 1810 | try enc.encode(.mov, &.{ |
| 1715 | .{ .reg = .al }, | 1811 | .{ .reg = .al }, |
| 1716 | .{ .mem = Memory.moffs(.ds, 0x10) }, | 1812 | .{ .mem = Instruction.Memory.moffs(.ds, 0x10) }, |
| 1717 | }); | 1813 | }); |
| 1718 | try expectEqualHexStrings("\xA0\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs al, ds:0x10"); | 1814 | try expectEqualHexStrings("\xA0\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs al, ds:0x10"); |
| 1719 | 1815 | ||
| 1720 | try enc.encode(.mov, &.{ | 1816 | try enc.encode(.mov, &.{ |
| 1721 | .{ .mem = Memory.moffs(.cs, 0x10) }, | 1817 | .{ .mem = Instruction.Memory.moffs(.cs, 0x10) }, |
| 1722 | .{ .reg = .rax }, | 1818 | .{ .reg = .rax }, |
| 1723 | }); | 1819 | }); |
| 1724 | try expectEqualHexStrings("\x2E\x48\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs cs:0x10, rax"); | 1820 | try expectEqualHexStrings("\x2E\x48\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs cs:0x10, rax"); |
| 1725 | 1821 | ||
| 1726 | try enc.encode(.mov, &.{ | 1822 | try enc.encode(.mov, &.{ |
| 1727 | .{ .mem = Memory.moffs(.fs, 0x10) }, | 1823 | .{ .mem = Instruction.Memory.moffs(.fs, 0x10) }, |
| 1728 | .{ .reg = .eax }, | 1824 | .{ .reg = .eax }, |
| 1729 | }); | 1825 | }); |
| 1730 | try expectEqualHexStrings("\x64\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs fs:0x10, eax"); | 1826 | try expectEqualHexStrings("\x64\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs fs:0x10, eax"); |
| 1731 | 1827 | ||
| 1732 | try enc.encode(.mov, &.{ | 1828 | try enc.encode(.mov, &.{ |
| 1733 | .{ .mem = Memory.moffs(.gs, 0x10) }, | 1829 | .{ .mem = Instruction.Memory.moffs(.gs, 0x10) }, |
| 1734 | .{ .reg = .ax }, | 1830 | .{ .reg = .ax }, |
| 1735 | }); | 1831 | }); |
| 1736 | try expectEqualHexStrings("\x65\x66\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs gs:0x10, ax"); | 1832 | try expectEqualHexStrings("\x65\x66\xA3\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs gs:0x10, ax"); |
| 1737 | 1833 | ||
| 1738 | try enc.encode(.mov, &.{ | 1834 | try enc.encode(.mov, &.{ |
| 1739 | .{ .mem = Memory.moffs(.ds, 0x10) }, | 1835 | .{ .mem = Instruction.Memory.moffs(.ds, 0x10) }, |
| 1740 | .{ .reg = .al }, | 1836 | .{ .reg = .al }, |
| 1741 | }); | 1837 | }); |
| 1742 | try expectEqualHexStrings("\xA2\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs ds:0x10, al"); | 1838 | try expectEqualHexStrings("\xA2\x10\x00\x00\x00\x00\x00\x00\x00", enc.code(), "movabs ds:0x10, al"); |
| ... | @@ -1774,16 +1870,16 @@ test "invalid instruction" { | ... | @@ -1774,16 +1870,16 @@ test "invalid instruction" { |
| 1774 | .{ .reg = .al }, | 1870 | .{ .reg = .al }, |
| 1775 | }); | 1871 | }); |
| 1776 | try invalidInstruction(.call, &.{ | 1872 | try invalidInstruction(.call, &.{ |
| 1777 | .{ .mem = Memory.rip(.dword, 0) }, | 1873 | .{ .mem = Instruction.Memory.rip(.dword, 0) }, |
| 1778 | }); | 1874 | }); |
| 1779 | try invalidInstruction(.call, &.{ | 1875 | try invalidInstruction(.call, &.{ |
| 1780 | .{ .mem = Memory.rip(.word, 0) }, | 1876 | .{ .mem = Instruction.Memory.rip(.word, 0) }, |
| 1781 | }); | 1877 | }); |
| 1782 | try invalidInstruction(.call, &.{ | 1878 | try invalidInstruction(.call, &.{ |
| 1783 | .{ .mem = Memory.rip(.byte, 0) }, | 1879 | .{ .mem = Instruction.Memory.rip(.byte, 0) }, |
| 1784 | }); | 1880 | }); |
| 1785 | try invalidInstruction(.mov, &.{ | 1881 | try invalidInstruction(.mov, &.{ |
| 1786 | .{ .mem = Memory.rip(.word, 0x10) }, | 1882 | .{ .mem = Instruction.Memory.rip(.word, 0x10) }, |
| 1787 | .{ .reg = .r12 }, | 1883 | .{ .reg = .r12 }, |
| 1788 | }); | 1884 | }); |
| 1789 | try invalidInstruction(.lea, &.{ | 1885 | try invalidInstruction(.lea, &.{ |
| ... | @@ -1792,7 +1888,7 @@ test "invalid instruction" { | ... | @@ -1792,7 +1888,7 @@ test "invalid instruction" { |
| 1792 | }); | 1888 | }); |
| 1793 | try invalidInstruction(.lea, &.{ | 1889 | try invalidInstruction(.lea, &.{ |
| 1794 | .{ .reg = .al }, | 1890 | .{ .reg = .al }, |
| 1795 | .{ .mem = Memory.rip(.byte, 0) }, | 1891 | .{ .mem = Instruction.Memory.rip(.byte, 0) }, |
| 1796 | }); | 1892 | }); |
| 1797 | try invalidInstruction(.pop, &.{ | 1893 | try invalidInstruction(.pop, &.{ |
| 1798 | .{ .reg = .r12b }, | 1894 | .{ .reg = .r12b }, |
| ... | @@ -1817,7 +1913,7 @@ fn cannotEncode(mnemonic: Instruction.Mnemonic, ops: []const Instruction.Operand | ... | @@ -1817,7 +1913,7 @@ fn cannotEncode(mnemonic: Instruction.Mnemonic, ops: []const Instruction.Operand |
| 1817 | 1913 | ||
| 1818 | test "cannot encode" { | 1914 | test "cannot encode" { |
| 1819 | try cannotEncode(.@"test", &.{ | 1915 | try cannotEncode(.@"test", &.{ |
| 1820 | .{ .mem = Memory.sib(.byte, .{ .base = .r12 }) }, | 1916 | .{ .mem = Instruction.Memory.sib(.byte, .{ .base = .r12 }) }, |
| 1821 | .{ .reg = .ah }, | 1917 | .{ .reg = .ah }, |
| 1822 | }); | 1918 | }); |
| 1823 | try cannotEncode(.@"test", &.{ | 1919 | try cannotEncode(.@"test", &.{ |
| ... | @@ -2149,8 +2245,8 @@ const Assembler = struct { | ... | @@ -2149,8 +2245,8 @@ const Assembler = struct { |
| 2149 | return null; | 2245 | return null; |
| 2150 | } | 2246 | } |
| 2151 | 2247 | ||
| 2152 | fn parseMemory(as: *Assembler) ParseError!Memory { | 2248 | fn parseMemory(as: *Assembler) ParseError!Instruction.Memory { |
| 2153 | const ptr_size: ?Memory.PtrSize = blk: { | 2249 | const ptr_size: ?Instruction.Memory.PtrSize = blk: { |
| 2154 | const pos = as.it.pos; | 2250 | const pos = as.it.pos; |
| 2155 | const ptr_size = as.parsePtrSize() catch |err| switch (err) { | 2251 | const ptr_size = as.parsePtrSize() catch |err| switch (err) { |
| 2156 | error.UnexpectedToken => { | 2252 | error.UnexpectedToken => { |
| ... | @@ -2194,7 +2290,7 @@ const Assembler = struct { | ... | @@ -2194,7 +2290,7 @@ const Assembler = struct { |
| 2194 | if (res.rip) { | 2290 | if (res.rip) { |
| 2195 | if (res.base != null or res.scale_index != null or res.offset != null) | 2291 | if (res.base != null or res.scale_index != null or res.offset != null) |
| 2196 | return error.InvalidMemoryOperand; | 2292 | return error.InvalidMemoryOperand; |
| 2197 | return Memory.rip(ptr_size orelse .qword, res.disp orelse 0); | 2293 | return Instruction.Memory.rip(ptr_size orelse .qword, res.disp orelse 0); |
| 2198 | } | 2294 | } |
| 2199 | if (res.base) |base| { | 2295 | if (res.base) |base| { |
| 2200 | if (res.rip) | 2296 | if (res.rip) |
| ... | @@ -2202,9 +2298,9 @@ const Assembler = struct { | ... | @@ -2202,9 +2298,9 @@ const Assembler = struct { |
| 2202 | if (res.offset) |offset| { | 2298 | if (res.offset) |offset| { |
| 2203 | if (res.scale_index != null or res.disp != null) | 2299 | if (res.scale_index != null or res.disp != null) |
| 2204 | return error.InvalidMemoryOperand; | 2300 | return error.InvalidMemoryOperand; |
| 2205 | return Memory.moffs(base, offset); | 2301 | return Instruction.Memory.moffs(base, offset); |
| 2206 | } | 2302 | } |
| 2207 | return Memory.sib(ptr_size orelse .qword, .{ | 2303 | return Instruction.Memory.sib(ptr_size orelse .qword, .{ |
| 2208 | .base = base, | 2304 | .base = base, |
| 2209 | .scale_index = res.scale_index, | 2305 | .scale_index = res.scale_index, |
| 2210 | .disp = res.disp orelse 0, | 2306 | .disp = res.disp orelse 0, |
| ... | @@ -2222,12 +2318,12 @@ const Assembler = struct { | ... | @@ -2222,12 +2318,12 @@ const Assembler = struct { |
| 2222 | const MemoryParseResult = struct { | 2318 | const MemoryParseResult = struct { |
| 2223 | rip: bool = false, | 2319 | rip: bool = false, |
| 2224 | base: ?Register = null, | 2320 | base: ?Register = null, |
| 2225 | scale_index: ?Memory.ScaleIndex = null, | 2321 | scale_index: ?Instruction.Memory.ScaleIndex = null, |
| 2226 | disp: ?i32 = null, | 2322 | disp: ?i32 = null, |
| 2227 | offset: ?u64 = null, | 2323 | offset: ?u64 = null, |
| 2228 | }; | 2324 | }; |
| 2229 | 2325 | ||
| 2230 | fn parseMemoryRule(as: *Assembler, rule: anytype) ParseError!MemoryParseResult { | 2326 | fn parseMemoryRule(as: *Assembler, rule: anytype) ParseError!Instruction.MemoryParseResult { |
| 2231 | var res: MemoryParseResult = .{}; | 2327 | var res: MemoryParseResult = .{}; |
| 2232 | inline for (rule, 0..) |cond, i| { | 2328 | inline for (rule, 0..) |cond, i| { |
| 2233 | if (@typeInfo(@TypeOf(cond)) != .EnumLiteral) { | 2329 | if (@typeInfo(@TypeOf(cond)) != .EnumLiteral) { |
| ... | @@ -2294,7 +2390,7 @@ const Assembler = struct { | ... | @@ -2294,7 +2390,7 @@ const Assembler = struct { |
| 2294 | return res; | 2390 | return res; |
| 2295 | } | 2391 | } |
| 2296 | 2392 | ||
| 2297 | fn parsePtrSize(as: *Assembler) ParseError!Memory.PtrSize { | 2393 | fn parsePtrSize(as: *Assembler) ParseError!Instruction.Memory.PtrSize { |
| 2298 | const size = try as.expect(.string); | 2394 | const size = try as.expect(.string); |
| 2299 | try as.skip(1, .{.space}); | 2395 | try as.skip(1, .{.space}); |
| 2300 | const ptr = try as.expect(.string); | 2396 | const ptr = try as.expect(.string); |
test/behavior/export_builtin.zig-3
| ... | @@ -4,7 +4,6 @@ const expect = std.testing.expect; | ... | @@ -4,7 +4,6 @@ const expect = std.testing.expect; |
| 4 | 4 | ||
| 5 | test "exporting enum type and value" { | 5 | test "exporting enum type and value" { |
| 6 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 6 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 7 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 8 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 7 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 9 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 8 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 10 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 9 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
| ... | @@ -21,7 +20,6 @@ test "exporting enum type and value" { | ... | @@ -21,7 +20,6 @@ test "exporting enum type and value" { |
| 21 | 20 | ||
| 22 | test "exporting with internal linkage" { | 21 | test "exporting with internal linkage" { |
| 23 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 22 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 24 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 25 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 23 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 26 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 24 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 27 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 25 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
| ... | @@ -37,7 +35,6 @@ test "exporting with internal linkage" { | ... | @@ -37,7 +35,6 @@ test "exporting with internal linkage" { |
| 37 | 35 | ||
| 38 | test "exporting using field access" { | 36 | test "exporting using field access" { |
| 39 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 37 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 40 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 41 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 38 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 42 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 39 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 43 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 40 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
test/behavior/fn.zig-1
| ... | @@ -577,7 +577,6 @@ test "pass and return comptime-only types" { | ... | @@ -577,7 +577,6 @@ test "pass and return comptime-only types" { |
| 577 | 577 | ||
| 578 | test "pointer to alias behaves same as pointer to function" { | 578 | test "pointer to alias behaves same as pointer to function" { |
| 579 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 579 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 580 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 581 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 580 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 582 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 581 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 583 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 582 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
test/behavior/globals.zig-2
| ... | @@ -6,7 +6,6 @@ var pos = [2]f32{ 0.0, 0.0 }; | ... | @@ -6,7 +6,6 @@ var pos = [2]f32{ 0.0, 0.0 }; |
| 6 | test "store to global array" { | 6 | test "store to global array" { |
| 7 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; | 7 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; |
| 8 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 8 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 9 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 10 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 9 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 11 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 10 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 12 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 11 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
| ... | @@ -20,7 +19,6 @@ var vpos = @Vector(2, f32){ 0.0, 0.0 }; | ... | @@ -20,7 +19,6 @@ var vpos = @Vector(2, f32){ 0.0, 0.0 }; |
| 20 | test "store to global vector" { | 19 | test "store to global vector" { |
| 21 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; | 20 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; |
| 22 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 21 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 23 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 24 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 22 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 25 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 23 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 26 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 24 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
test/behavior/nan.zig-1
| ... | @@ -23,7 +23,6 @@ const snan_f128: f128 = math.snan(f128); | ... | @@ -23,7 +23,6 @@ const snan_f128: f128 = math.snan(f128); |
| 23 | 23 | ||
| 24 | test "nan memory equality" { | 24 | test "nan memory equality" { |
| 25 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; | 25 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; |
| 26 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | ||
| 27 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; | 26 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 28 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; | 27 | if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; |
| 29 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; | 28 | if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; |
test/tests.zig+11-7
| ... | @@ -28,6 +28,7 @@ const TestTarget = struct { | ... | @@ -28,6 +28,7 @@ const TestTarget = struct { |
| 28 | single_threaded: ?bool = null, | 28 | single_threaded: ?bool = null, |
| 29 | use_llvm: ?bool = null, | 29 | use_llvm: ?bool = null, |
| 30 | use_lld: ?bool = null, | 30 | use_lld: ?bool = null, |
| 31 | force_pic: ?bool = null, | ||
| 31 | }; | 32 | }; |
| 32 | 33 | ||
| 33 | const test_targets = blk: { | 34 | const test_targets = blk: { |
| ... | @@ -103,6 +104,7 @@ const test_targets = blk: { | ... | @@ -103,6 +104,7 @@ const test_targets = blk: { |
| 103 | }, | 104 | }, |
| 104 | .use_llvm = false, | 105 | .use_llvm = false, |
| 105 | .use_lld = false, | 106 | .use_lld = false, |
| 107 | .force_pic = true, | ||
| 106 | }, | 108 | }, |
| 107 | .{ | 109 | .{ |
| 108 | .target = .{ | 110 | .target = .{ |
| ... | @@ -494,6 +496,7 @@ const CAbiTarget = struct { | ... | @@ -494,6 +496,7 @@ const CAbiTarget = struct { |
| 494 | target: CrossTarget = .{}, | 496 | target: CrossTarget = .{}, |
| 495 | use_llvm: ?bool = null, | 497 | use_llvm: ?bool = null, |
| 496 | use_lld: ?bool = null, | 498 | use_lld: ?bool = null, |
| 499 | force_pic: ?bool = null, | ||
| 497 | c_defines: []const []const u8 = &.{}, | 500 | c_defines: []const []const u8 = &.{}, |
| 498 | }; | 501 | }; |
| 499 | 502 | ||
| ... | @@ -536,6 +539,7 @@ const c_abi_targets = [_]CAbiTarget{ | ... | @@ -536,6 +539,7 @@ const c_abi_targets = [_]CAbiTarget{ |
| 536 | }, | 539 | }, |
| 537 | .use_llvm = false, | 540 | .use_llvm = false, |
| 538 | .use_lld = false, | 541 | .use_lld = false, |
| 542 | .force_pic = true, | ||
| 539 | .c_defines = &.{"ZIG_BACKEND_STAGE2_X86_64"}, | 543 | .c_defines = &.{"ZIG_BACKEND_STAGE2_X86_64"}, |
| 540 | }, | 544 | }, |
| 541 | .{ | 545 | .{ |
| ... | @@ -1118,6 +1122,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { | ... | @@ -1118,6 +1122,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { |
| 1118 | .use_lld = test_target.use_lld, | 1122 | .use_lld = test_target.use_lld, |
| 1119 | .zig_lib_dir = .{ .path = "lib" }, | 1123 | .zig_lib_dir = .{ .path = "lib" }, |
| 1120 | }); | 1124 | }); |
| 1125 | these_tests.force_pic = test_target.force_pic; | ||
| 1121 | const single_threaded_suffix = if (test_target.single_threaded == true) "-single" else ""; | 1126 | const single_threaded_suffix = if (test_target.single_threaded == true) "-single" else ""; |
| 1122 | const backend_suffix = if (test_target.use_llvm == true) | 1127 | const backend_suffix = if (test_target.use_llvm == true) |
| 1123 | "-llvm" | 1128 | "-llvm" |
| ... | @@ -1128,6 +1133,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { | ... | @@ -1128,6 +1133,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { |
| 1128 | else | 1133 | else |
| 1129 | ""; | 1134 | ""; |
| 1130 | const use_lld = if (test_target.use_lld == false) "-no-lld" else ""; | 1135 | const use_lld = if (test_target.use_lld == false) "-no-lld" else ""; |
| 1136 | const use_pic = if (test_target.force_pic == true) "-pic" else ""; | ||
| 1131 | 1137 | ||
| 1132 | these_tests.addIncludePath(.{ .path = "test" }); | 1138 | these_tests.addIncludePath(.{ .path = "test" }); |
| 1133 | 1139 | ||
| ... | @@ -1136,7 +1142,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { | ... | @@ -1136,7 +1142,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { |
| 1136 | these_tests.stack_size = 2 * 1024 * 1024; | 1142 | these_tests.stack_size = 2 * 1024 * 1024; |
| 1137 | } | 1143 | } |
| 1138 | 1144 | ||
| 1139 | const qualified_name = b.fmt("{s}-{s}-{s}-{s}{s}{s}{s}{s}", .{ | 1145 | const qualified_name = b.fmt("{s}-{s}-{s}-{s}{s}{s}{s}{s}{s}", .{ |
| 1140 | options.name, | 1146 | options.name, |
| 1141 | triple_txt, | 1147 | triple_txt, |
| 1142 | model_txt, | 1148 | model_txt, |
| ... | @@ -1145,6 +1151,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { | ... | @@ -1145,6 +1151,7 @@ pub fn addModuleTests(b: *std.Build, options: ModuleTestOptions) *Step { |
| 1145 | single_threaded_suffix, | 1151 | single_threaded_suffix, |
| 1146 | backend_suffix, | 1152 | backend_suffix, |
| 1147 | use_lld, | 1153 | use_lld, |
| 1154 | use_pic, | ||
| 1148 | }); | 1155 | }); |
| 1149 | 1156 | ||
| 1150 | if (test_target.target.ofmt == std.Target.ObjectFormat.c) { | 1157 | if (test_target.target.ofmt == std.Target.ObjectFormat.c) { |
| ... | @@ -1234,13 +1241,8 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S | ... | @@ -1234,13 +1241,8 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S |
| 1234 | continue; | 1241 | continue; |
| 1235 | } | 1242 | } |
| 1236 | 1243 | ||
| 1237 | if (c_abi_target.use_llvm == false and optimize_mode == .ReleaseFast) { | ||
| 1238 | // panic: unrecognized command line argument | ||
| 1239 | continue; | ||
| 1240 | } | ||
| 1241 | |||
| 1242 | const test_step = b.addTest(.{ | 1244 | const test_step = b.addTest(.{ |
| 1243 | .name = b.fmt("test-c-abi-{s}-{s}-{s}{s}{s}", .{ | 1245 | .name = b.fmt("test-c-abi-{s}-{s}-{s}{s}{s}{s}", .{ |
| 1244 | c_abi_target.target.zigTriple(b.allocator) catch @panic("OOM"), | 1246 | c_abi_target.target.zigTriple(b.allocator) catch @panic("OOM"), |
| 1245 | c_abi_target.target.getCpuModel().name, | 1247 | c_abi_target.target.getCpuModel().name, |
| 1246 | @tagName(optimize_mode), | 1248 | @tagName(optimize_mode), |
| ... | @@ -1253,6 +1255,7 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S | ... | @@ -1253,6 +1255,7 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S |
| 1253 | else | 1255 | else |
| 1254 | "", | 1256 | "", |
| 1255 | if (c_abi_target.use_lld == false) "-no-lld" else "", | 1257 | if (c_abi_target.use_lld == false) "-no-lld" else "", |
| 1258 | if (c_abi_target.force_pic == true) "-pic" else "", | ||
| 1256 | }), | 1259 | }), |
| 1257 | .root_source_file = .{ .path = "test/c_abi/main.zig" }, | 1260 | .root_source_file = .{ .path = "test/c_abi/main.zig" }, |
| 1258 | .target = c_abi_target.target, | 1261 | .target = c_abi_target.target, |
| ... | @@ -1261,6 +1264,7 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S | ... | @@ -1261,6 +1264,7 @@ pub fn addCAbiTests(b: *std.Build, skip_non_native: bool, skip_release: bool) *S |
| 1261 | .use_llvm = c_abi_target.use_llvm, | 1264 | .use_llvm = c_abi_target.use_llvm, |
| 1262 | .use_lld = c_abi_target.use_lld, | 1265 | .use_lld = c_abi_target.use_lld, |
| 1263 | }); | 1266 | }); |
| 1267 | test_step.force_pic = c_abi_target.force_pic; | ||
| 1264 | if (c_abi_target.target.abi != null and c_abi_target.target.abi.?.isMusl()) { | 1268 | if (c_abi_target.target.abi != null and c_abi_target.target.abi.?.isMusl()) { |
| 1265 | // TODO NativeTargetInfo insists on dynamically linking musl | 1269 | // TODO NativeTargetInfo insists on dynamically linking musl |
| 1266 | // for some reason? | 1270 | // for some reason? |