1/*===---- avx512vlcdintrin.h - AVX512VL and AVX512CD intrinsics ------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9#ifndef __IMMINTRIN_H
10#error "Never use <avx512vlcdintrin.h> directly; include <immintrin.h> instead."
11#endif
12
13#ifndef __AVX512VLCDINTRIN_H
14#define __AVX512VLCDINTRIN_H
15
16/* Define the default attributes for the functions in this file. */
17#if defined(__cplusplus) && (__cplusplus >= 201103L)
18#define __DEFAULT_FN_ATTRS128 \
19 __attribute__((__always_inline__, __nodebug__, \
20 __target__("avx512vl,avx512cd"), \
21 __min_vector_width__(128))) constexpr
22#define __DEFAULT_FN_ATTRS256 \
23 __attribute__((__always_inline__, __nodebug__, \
24 __target__("avx512vl,avx512cd"), \
25 __min_vector_width__(256))) constexpr
26#else
27#define __DEFAULT_FN_ATTRS128 \
28 __attribute__((__always_inline__, __nodebug__, \
29 __target__("avx512vl,avx512cd"), __min_vector_width__(128)))
30#define __DEFAULT_FN_ATTRS256 \
31 __attribute__((__always_inline__, __nodebug__, \
32 __target__("avx512vl,avx512cd"), __min_vector_width__(256)))
33#endif
34
35static __inline__ __m128i __DEFAULT_FN_ATTRS128
36_mm_broadcastmb_epi64(__mmask8 __A) {
37 return (__m128i) _mm_set1_epi64x((long long) __A);
38}
39
40static __inline__ __m256i __DEFAULT_FN_ATTRS256
41_mm256_broadcastmb_epi64(__mmask8 __A) {
42 return (__m256i)_mm256_set1_epi64x((long long)__A);
43}
44
45static __inline__ __m128i __DEFAULT_FN_ATTRS128
46_mm_broadcastmw_epi32(__mmask16 __A) {
47 return (__m128i) _mm_set1_epi32((int)__A);
48}
49
50static __inline__ __m256i __DEFAULT_FN_ATTRS256
51_mm256_broadcastmw_epi32(__mmask16 __A) {
52 return (__m256i) _mm256_set1_epi32((int)__A);
53}
54
55static __inline__ __m128i __DEFAULT_FN_ATTRS128
56_mm_conflict_epi64(__m128i __A) {
57 return (__m128i)__builtin_ia32_vpconflictdi_128((__v2di)__A);
58}
59
60static __inline__ __m128i __DEFAULT_FN_ATTRS128
61_mm_mask_conflict_epi64(__m128i __W, __mmask8 __U, __m128i __A) {
62 return (__m128i)__builtin_ia32_selectq_128(
63 (__mmask8)__U, (__v2di)_mm_conflict_epi64(__A), (__v2di)__W);
64}
65
66static __inline__ __m128i __DEFAULT_FN_ATTRS128
67_mm_maskz_conflict_epi64(__mmask8 __U, __m128i __A) {
68 return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
69 (__v2di)_mm_conflict_epi64(__A),
70 (__v2di)_mm_setzero_si128());
71}
72
73static __inline__ __m256i __DEFAULT_FN_ATTRS256
74_mm256_conflict_epi64(__m256i __A) {
75 return (__m256i)__builtin_ia32_vpconflictdi_256((__v4di)__A);
76}
77
78static __inline__ __m256i __DEFAULT_FN_ATTRS256
79_mm256_mask_conflict_epi64(__m256i __W, __mmask8 __U, __m256i __A) {
80 return (__m256i)__builtin_ia32_selectq_256(
81 (__mmask8)__U, (__v4di)_mm256_conflict_epi64(__A), (__v4di)__W);
82}
83
84static __inline__ __m256i __DEFAULT_FN_ATTRS256
85_mm256_maskz_conflict_epi64(__mmask8 __U, __m256i __A) {
86 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
87 (__v4di)_mm256_conflict_epi64(__A),
88 (__v4di)_mm256_setzero_si256());
89}
90
91static __inline__ __m128i __DEFAULT_FN_ATTRS128
92_mm_conflict_epi32(__m128i __A) {
93 return (__m128i)__builtin_ia32_vpconflictsi_128((__v4si)__A);
94}
95
96static __inline__ __m128i __DEFAULT_FN_ATTRS128
97_mm_mask_conflict_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
98 return (__m128i)__builtin_ia32_selectd_128(
99 (__mmask8)__U, (__v4si)_mm_conflict_epi32(__A), (__v4si)__W);
100}
101
102static __inline__ __m128i __DEFAULT_FN_ATTRS128
103_mm_maskz_conflict_epi32(__mmask8 __U, __m128i __A) {
104 return (__m128i)__builtin_ia32_selectd_128((__mmask8)__U,
105 (__v4si)_mm_conflict_epi32(__A),
106 (__v4si)_mm_setzero_si128());
107}
108
109static __inline__ __m256i __DEFAULT_FN_ATTRS256
110_mm256_conflict_epi32(__m256i __A) {
111 return (__m256i)__builtin_ia32_vpconflictsi_256((__v8si)__A);
112}
113
114static __inline__ __m256i __DEFAULT_FN_ATTRS256
115_mm256_mask_conflict_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
116 return (__m256i)__builtin_ia32_selectd_256(
117 (__mmask8)__U, (__v8si)_mm256_conflict_epi32(__A), (__v8si)__W);
118}
119
120static __inline__ __m256i __DEFAULT_FN_ATTRS256
121_mm256_maskz_conflict_epi32(__mmask8 __U, __m256i __A) {
122 return (__m256i)__builtin_ia32_selectd_256((__mmask8)__U,
123 (__v8si)_mm256_conflict_epi32(__A),
124 (__v8si)_mm256_setzero_si256());
125}
126
127static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_lzcnt_epi32(__m128i __A) {
128 return (__m128i)__builtin_elementwise_clzg((__v4si)__A,
129 (__v4si)_mm_set1_epi32(32));
130}
131
132static __inline__ __m128i __DEFAULT_FN_ATTRS128
133_mm_mask_lzcnt_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
134 return (__m128i)__builtin_ia32_selectd_128(
135 (__mmask8)__U, (__v4si)_mm_lzcnt_epi32(__A), (__v4si)__W);
136}
137
138static __inline__ __m128i __DEFAULT_FN_ATTRS128
139_mm_maskz_lzcnt_epi32(__mmask8 __U, __m128i __A) {
140 return (__m128i)__builtin_ia32_selectd_128(
141 (__mmask8)__U, (__v4si)_mm_lzcnt_epi32(__A), (__v4si)_mm_setzero_si128());
142}
143
144static __inline__ __m256i __DEFAULT_FN_ATTRS256
145_mm256_lzcnt_epi32(__m256i __A) {
146 return (__m256i)__builtin_elementwise_clzg((__v8si)__A,
147 (__v8si)_mm256_set1_epi32(32));
148}
149
150static __inline__ __m256i __DEFAULT_FN_ATTRS256
151_mm256_mask_lzcnt_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
152 return (__m256i)__builtin_ia32_selectd_256(
153 (__mmask8)__U, (__v8si)_mm256_lzcnt_epi32(__A), (__v8si)__W);
154}
155
156static __inline__ __m256i __DEFAULT_FN_ATTRS256
157_mm256_maskz_lzcnt_epi32(__mmask8 __U, __m256i __A) {
158 return (__m256i)__builtin_ia32_selectd_256((__mmask8)__U,
159 (__v8si)_mm256_lzcnt_epi32(__A),
160 (__v8si)_mm256_setzero_si256());
161}
162
163static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_lzcnt_epi64(__m128i __A) {
164 return (__m128i)__builtin_elementwise_clzg(
165 (__v2di)__A, (__v2di)_mm_set1_epi64x((long long)64));
166}
167
168static __inline__ __m128i __DEFAULT_FN_ATTRS128
169_mm_mask_lzcnt_epi64(__m128i __W, __mmask8 __U, __m128i __A) {
170 return (__m128i)__builtin_ia32_selectq_128(
171 (__mmask8)__U, (__v2di)_mm_lzcnt_epi64(__A), (__v2di)__W);
172}
173
174static __inline__ __m128i __DEFAULT_FN_ATTRS128
175_mm_maskz_lzcnt_epi64(__mmask8 __U, __m128i __A) {
176 return (__m128i)__builtin_ia32_selectq_128(
177 (__mmask8)__U, (__v2di)_mm_lzcnt_epi64(__A), (__v2di)_mm_setzero_si128());
178}
179
180static __inline__ __m256i __DEFAULT_FN_ATTRS256
181_mm256_lzcnt_epi64(__m256i __A) {
182 return (__m256i)__builtin_elementwise_clzg(
183 (__v4di)__A, (__v4di)_mm256_set1_epi64x((long long)64));
184}
185
186static __inline__ __m256i __DEFAULT_FN_ATTRS256
187_mm256_mask_lzcnt_epi64(__m256i __W, __mmask8 __U, __m256i __A) {
188 return (__m256i)__builtin_ia32_selectq_256(
189 (__mmask8)__U, (__v4di)_mm256_lzcnt_epi64(__A), (__v4di)__W);
190}
191
192static __inline__ __m256i __DEFAULT_FN_ATTRS256
193_mm256_maskz_lzcnt_epi64(__mmask8 __U, __m256i __A) {
194 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
195 (__v4di)_mm256_lzcnt_epi64(__A),
196 (__v4di)_mm256_setzero_si256());
197}
198
199#undef __DEFAULT_FN_ATTRS128
200#undef __DEFAULT_FN_ATTRS256
201
202#endif /* __AVX512VLCDINTRIN_H */