1/*===---- avx512vldqintrin.h - AVX512VL and AVX512DQ intrinsics ------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9
10#ifndef __IMMINTRIN_H
11#error "Never use <avx512vldqintrin.h> directly; include <immintrin.h> instead."
12#endif
13
14#ifndef __AVX512VLDQINTRIN_H
15#define __AVX512VLDQINTRIN_H
16
17/* Define the default attributes for the functions in this file. */
18#define __DEFAULT_FN_ATTRS128 \
19 __attribute__((__always_inline__, __nodebug__, \
20 __target__("avx512vl,avx512dq"), __min_vector_width__(128)))
21#define __DEFAULT_FN_ATTRS256 \
22 __attribute__((__always_inline__, __nodebug__, \
23 __target__("avx512vl,avx512dq"), __min_vector_width__(256)))
24
25#if defined(__cplusplus) && (__cplusplus >= 201103L)
26#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr
27#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr
28#else
29#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256
30#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128
31#endif
32
33static __inline__ __m256i __DEFAULT_FN_ATTRS128_CONSTEXPR
34_mm256_mullo_epi64(__m256i __A, __m256i __B) {
35 return (__m256i) ((__v4du) __A * (__v4du) __B);
36}
37
38static __inline__ __m256i __DEFAULT_FN_ATTRS128_CONSTEXPR
39_mm256_mask_mullo_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) {
40 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
41 (__v4di)_mm256_mullo_epi64(__A, __B),
42 (__v4di)__W);
43}
44
45static __inline__ __m256i __DEFAULT_FN_ATTRS128_CONSTEXPR
46_mm256_maskz_mullo_epi64(__mmask8 __U, __m256i __A, __m256i __B) {
47 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
48 (__v4di)_mm256_mullo_epi64(__A, __B),
49 (__v4di)_mm256_setzero_si256());
50}
51
52static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
53_mm_mullo_epi64(__m128i __A, __m128i __B) {
54 return (__m128i) ((__v2du) __A * (__v2du) __B);
55}
56
57static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
58_mm_mask_mullo_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
59 return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
60 (__v2di)_mm_mullo_epi64(__A, __B),
61 (__v2di)__W);
62}
63
64static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
65_mm_maskz_mullo_epi64(__mmask8 __U, __m128i __A, __m128i __B) {
66 return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
67 (__v2di)_mm_mullo_epi64(__A, __B),
68 (__v2di)_mm_setzero_si128());
69}
70
71static __inline__ __m256d __DEFAULT_FN_ATTRS256
72_mm256_mask_andnot_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
73 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
74 (__v4df)_mm256_andnot_pd(__A, __B),
75 (__v4df)__W);
76}
77
78static __inline__ __m256d __DEFAULT_FN_ATTRS256
79_mm256_maskz_andnot_pd(__mmask8 __U, __m256d __A, __m256d __B) {
80 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
81 (__v4df)_mm256_andnot_pd(__A, __B),
82 (__v4df)_mm256_setzero_pd());
83}
84
85static __inline__ __m128d __DEFAULT_FN_ATTRS128
86_mm_mask_andnot_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
87 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
88 (__v2df)_mm_andnot_pd(__A, __B),
89 (__v2df)__W);
90}
91
92static __inline__ __m128d __DEFAULT_FN_ATTRS128
93_mm_maskz_andnot_pd(__mmask8 __U, __m128d __A, __m128d __B) {
94 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
95 (__v2df)_mm_andnot_pd(__A, __B),
96 (__v2df)_mm_setzero_pd());
97}
98
99static __inline__ __m256 __DEFAULT_FN_ATTRS256
100_mm256_mask_andnot_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
101 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
102 (__v8sf)_mm256_andnot_ps(__A, __B),
103 (__v8sf)__W);
104}
105
106static __inline__ __m256 __DEFAULT_FN_ATTRS256
107_mm256_maskz_andnot_ps(__mmask8 __U, __m256 __A, __m256 __B) {
108 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
109 (__v8sf)_mm256_andnot_ps(__A, __B),
110 (__v8sf)_mm256_setzero_ps());
111}
112
113static __inline__ __m128 __DEFAULT_FN_ATTRS128
114_mm_mask_andnot_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
115 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
116 (__v4sf)_mm_andnot_ps(__A, __B),
117 (__v4sf)__W);
118}
119
120static __inline__ __m128 __DEFAULT_FN_ATTRS128
121_mm_maskz_andnot_ps(__mmask8 __U, __m128 __A, __m128 __B) {
122 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
123 (__v4sf)_mm_andnot_ps(__A, __B),
124 (__v4sf)_mm_setzero_ps());
125}
126
127static __inline__ __m256d __DEFAULT_FN_ATTRS256
128_mm256_mask_and_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
129 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
130 (__v4df)_mm256_and_pd(__A, __B),
131 (__v4df)__W);
132}
133
134static __inline__ __m256d __DEFAULT_FN_ATTRS256
135_mm256_maskz_and_pd(__mmask8 __U, __m256d __A, __m256d __B) {
136 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
137 (__v4df)_mm256_and_pd(__A, __B),
138 (__v4df)_mm256_setzero_pd());
139}
140
141static __inline__ __m128d __DEFAULT_FN_ATTRS128
142_mm_mask_and_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
143 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
144 (__v2df)_mm_and_pd(__A, __B),
145 (__v2df)__W);
146}
147
148static __inline__ __m128d __DEFAULT_FN_ATTRS128
149_mm_maskz_and_pd(__mmask8 __U, __m128d __A, __m128d __B) {
150 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
151 (__v2df)_mm_and_pd(__A, __B),
152 (__v2df)_mm_setzero_pd());
153}
154
155static __inline__ __m256 __DEFAULT_FN_ATTRS256
156_mm256_mask_and_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
157 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
158 (__v8sf)_mm256_and_ps(__A, __B),
159 (__v8sf)__W);
160}
161
162static __inline__ __m256 __DEFAULT_FN_ATTRS256
163_mm256_maskz_and_ps(__mmask8 __U, __m256 __A, __m256 __B) {
164 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
165 (__v8sf)_mm256_and_ps(__A, __B),
166 (__v8sf)_mm256_setzero_ps());
167}
168
169static __inline__ __m128 __DEFAULT_FN_ATTRS128
170_mm_mask_and_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
171 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
172 (__v4sf)_mm_and_ps(__A, __B),
173 (__v4sf)__W);
174}
175
176static __inline__ __m128 __DEFAULT_FN_ATTRS128
177_mm_maskz_and_ps(__mmask8 __U, __m128 __A, __m128 __B) {
178 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
179 (__v4sf)_mm_and_ps(__A, __B),
180 (__v4sf)_mm_setzero_ps());
181}
182
183static __inline__ __m256d __DEFAULT_FN_ATTRS256
184_mm256_mask_xor_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
185 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
186 (__v4df)_mm256_xor_pd(__A, __B),
187 (__v4df)__W);
188}
189
190static __inline__ __m256d __DEFAULT_FN_ATTRS256
191_mm256_maskz_xor_pd(__mmask8 __U, __m256d __A, __m256d __B) {
192 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
193 (__v4df)_mm256_xor_pd(__A, __B),
194 (__v4df)_mm256_setzero_pd());
195}
196
197static __inline__ __m128d __DEFAULT_FN_ATTRS128
198_mm_mask_xor_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
199 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
200 (__v2df)_mm_xor_pd(__A, __B),
201 (__v2df)__W);
202}
203
204static __inline__ __m128d __DEFAULT_FN_ATTRS128
205_mm_maskz_xor_pd (__mmask8 __U, __m128d __A, __m128d __B) {
206 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
207 (__v2df)_mm_xor_pd(__A, __B),
208 (__v2df)_mm_setzero_pd());
209}
210
211static __inline__ __m256 __DEFAULT_FN_ATTRS256
212_mm256_mask_xor_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
213 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
214 (__v8sf)_mm256_xor_ps(__A, __B),
215 (__v8sf)__W);
216}
217
218static __inline__ __m256 __DEFAULT_FN_ATTRS256
219_mm256_maskz_xor_ps(__mmask8 __U, __m256 __A, __m256 __B) {
220 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
221 (__v8sf)_mm256_xor_ps(__A, __B),
222 (__v8sf)_mm256_setzero_ps());
223}
224
225static __inline__ __m128 __DEFAULT_FN_ATTRS128
226_mm_mask_xor_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
227 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
228 (__v4sf)_mm_xor_ps(__A, __B),
229 (__v4sf)__W);
230}
231
232static __inline__ __m128 __DEFAULT_FN_ATTRS128
233_mm_maskz_xor_ps(__mmask8 __U, __m128 __A, __m128 __B) {
234 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
235 (__v4sf)_mm_xor_ps(__A, __B),
236 (__v4sf)_mm_setzero_ps());
237}
238
239static __inline__ __m256d __DEFAULT_FN_ATTRS256
240_mm256_mask_or_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
241 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
242 (__v4df)_mm256_or_pd(__A, __B),
243 (__v4df)__W);
244}
245
246static __inline__ __m256d __DEFAULT_FN_ATTRS256
247_mm256_maskz_or_pd(__mmask8 __U, __m256d __A, __m256d __B) {
248 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
249 (__v4df)_mm256_or_pd(__A, __B),
250 (__v4df)_mm256_setzero_pd());
251}
252
253static __inline__ __m128d __DEFAULT_FN_ATTRS128
254_mm_mask_or_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
255 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
256 (__v2df)_mm_or_pd(__A, __B),
257 (__v2df)__W);
258}
259
260static __inline__ __m128d __DEFAULT_FN_ATTRS128
261_mm_maskz_or_pd(__mmask8 __U, __m128d __A, __m128d __B) {
262 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
263 (__v2df)_mm_or_pd(__A, __B),
264 (__v2df)_mm_setzero_pd());
265}
266
267static __inline__ __m256 __DEFAULT_FN_ATTRS256
268_mm256_mask_or_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
269 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
270 (__v8sf)_mm256_or_ps(__A, __B),
271 (__v8sf)__W);
272}
273
274static __inline__ __m256 __DEFAULT_FN_ATTRS256
275_mm256_maskz_or_ps(__mmask8 __U, __m256 __A, __m256 __B) {
276 return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
277 (__v8sf)_mm256_or_ps(__A, __B),
278 (__v8sf)_mm256_setzero_ps());
279}
280
281static __inline__ __m128 __DEFAULT_FN_ATTRS128
282_mm_mask_or_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
283 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
284 (__v4sf)_mm_or_ps(__A, __B),
285 (__v4sf)__W);
286}
287
288static __inline__ __m128 __DEFAULT_FN_ATTRS128
289_mm_maskz_or_ps(__mmask8 __U, __m128 __A, __m128 __B) {
290 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
291 (__v4sf)_mm_or_ps(__A, __B),
292 (__v4sf)_mm_setzero_ps());
293}
294
295static __inline__ __m128i __DEFAULT_FN_ATTRS128
296_mm_cvtpd_epi64 (__m128d __A) {
297 return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
298 (__v2di) _mm_setzero_si128(),
299 (__mmask8) -1);
300}
301
302static __inline__ __m128i __DEFAULT_FN_ATTRS128
303_mm_mask_cvtpd_epi64 (__m128i __W, __mmask8 __U, __m128d __A) {
304 return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
305 (__v2di) __W,
306 (__mmask8) __U);
307}
308
309static __inline__ __m128i __DEFAULT_FN_ATTRS128
310_mm_maskz_cvtpd_epi64 (__mmask8 __U, __m128d __A) {
311 return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
312 (__v2di) _mm_setzero_si128(),
313 (__mmask8) __U);
314}
315
316static __inline__ __m256i __DEFAULT_FN_ATTRS256
317_mm256_cvtpd_epi64 (__m256d __A) {
318 return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
319 (__v4di) _mm256_setzero_si256(),
320 (__mmask8) -1);
321}
322
323static __inline__ __m256i __DEFAULT_FN_ATTRS256
324_mm256_mask_cvtpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A) {
325 return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
326 (__v4di) __W,
327 (__mmask8) __U);
328}
329
330static __inline__ __m256i __DEFAULT_FN_ATTRS256
331_mm256_maskz_cvtpd_epi64 (__mmask8 __U, __m256d __A) {
332 return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
333 (__v4di) _mm256_setzero_si256(),
334 (__mmask8) __U);
335}
336
337static __inline__ __m128i __DEFAULT_FN_ATTRS128
338_mm_cvtpd_epu64 (__m128d __A) {
339 return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
340 (__v2di) _mm_setzero_si128(),
341 (__mmask8) -1);
342}
343
344static __inline__ __m128i __DEFAULT_FN_ATTRS128
345_mm_mask_cvtpd_epu64 (__m128i __W, __mmask8 __U, __m128d __A) {
346 return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
347 (__v2di) __W,
348 (__mmask8) __U);
349}
350
351static __inline__ __m128i __DEFAULT_FN_ATTRS128
352_mm_maskz_cvtpd_epu64 (__mmask8 __U, __m128d __A) {
353 return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
354 (__v2di) _mm_setzero_si128(),
355 (__mmask8) __U);
356}
357
358static __inline__ __m256i __DEFAULT_FN_ATTRS256
359_mm256_cvtpd_epu64 (__m256d __A) {
360 return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
361 (__v4di) _mm256_setzero_si256(),
362 (__mmask8) -1);
363}
364
365static __inline__ __m256i __DEFAULT_FN_ATTRS256
366_mm256_mask_cvtpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A) {
367 return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
368 (__v4di) __W,
369 (__mmask8) __U);
370}
371
372static __inline__ __m256i __DEFAULT_FN_ATTRS256
373_mm256_maskz_cvtpd_epu64 (__mmask8 __U, __m256d __A) {
374 return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
375 (__v4di) _mm256_setzero_si256(),
376 (__mmask8) __U);
377}
378
379static __inline__ __m128i __DEFAULT_FN_ATTRS128
380_mm_cvtps_epi64 (__m128 __A) {
381 return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
382 (__v2di) _mm_setzero_si128(),
383 (__mmask8) -1);
384}
385
386static __inline__ __m128i __DEFAULT_FN_ATTRS128
387_mm_mask_cvtps_epi64 (__m128i __W, __mmask8 __U, __m128 __A) {
388 return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
389 (__v2di) __W,
390 (__mmask8) __U);
391}
392
393static __inline__ __m128i __DEFAULT_FN_ATTRS128
394_mm_maskz_cvtps_epi64 (__mmask8 __U, __m128 __A) {
395 return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
396 (__v2di) _mm_setzero_si128(),
397 (__mmask8) __U);
398}
399
400static __inline__ __m256i __DEFAULT_FN_ATTRS256
401_mm256_cvtps_epi64 (__m128 __A) {
402 return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
403 (__v4di) _mm256_setzero_si256(),
404 (__mmask8) -1);
405}
406
407static __inline__ __m256i __DEFAULT_FN_ATTRS256
408_mm256_mask_cvtps_epi64 (__m256i __W, __mmask8 __U, __m128 __A) {
409 return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
410 (__v4di) __W,
411 (__mmask8) __U);
412}
413
414static __inline__ __m256i __DEFAULT_FN_ATTRS256
415_mm256_maskz_cvtps_epi64 (__mmask8 __U, __m128 __A) {
416 return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
417 (__v4di) _mm256_setzero_si256(),
418 (__mmask8) __U);
419}
420
421static __inline__ __m128i __DEFAULT_FN_ATTRS128
422_mm_cvtps_epu64 (__m128 __A) {
423 return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
424 (__v2di) _mm_setzero_si128(),
425 (__mmask8) -1);
426}
427
428static __inline__ __m128i __DEFAULT_FN_ATTRS128
429_mm_mask_cvtps_epu64 (__m128i __W, __mmask8 __U, __m128 __A) {
430 return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
431 (__v2di) __W,
432 (__mmask8) __U);
433}
434
435static __inline__ __m128i __DEFAULT_FN_ATTRS128
436_mm_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
437 return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
438 (__v2di) _mm_setzero_si128(),
439 (__mmask8) __U);
440}
441
442static __inline__ __m256i __DEFAULT_FN_ATTRS256
443_mm256_cvtps_epu64 (__m128 __A) {
444 return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
445 (__v4di) _mm256_setzero_si256(),
446 (__mmask8) -1);
447}
448
449static __inline__ __m256i __DEFAULT_FN_ATTRS256
450_mm256_mask_cvtps_epu64 (__m256i __W, __mmask8 __U, __m128 __A) {
451 return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
452 (__v4di) __W,
453 (__mmask8) __U);
454}
455
456static __inline__ __m256i __DEFAULT_FN_ATTRS256
457_mm256_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
458 return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
459 (__v4di) _mm256_setzero_si256(),
460 (__mmask8) __U);
461}
462
463static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
464_mm_cvtepi64_pd(__m128i __A) {
465 return (__m128d)__builtin_convertvector((__v2di)__A, __v2df);
466}
467
468static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
469_mm_mask_cvtepi64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
470 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
471 (__v2df)_mm_cvtepi64_pd(__A),
472 (__v2df)__W);
473}
474
475static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
476_mm_maskz_cvtepi64_pd(__mmask8 __U, __m128i __A) {
477 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
478 (__v2df)_mm_cvtepi64_pd(__A),
479 (__v2df)_mm_setzero_pd());
480}
481
482static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
483_mm256_cvtepi64_pd(__m256i __A) {
484 return (__m256d)__builtin_convertvector((__v4di)__A, __v4df);
485}
486
487static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
488_mm256_mask_cvtepi64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
489 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
490 (__v4df)_mm256_cvtepi64_pd(__A),
491 (__v4df)__W);
492}
493
494static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
495_mm256_maskz_cvtepi64_pd(__mmask8 __U, __m256i __A) {
496 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
497 (__v4df)_mm256_cvtepi64_pd(__A),
498 (__v4df)_mm256_setzero_pd());
499}
500
501static __inline__ __m128 __DEFAULT_FN_ATTRS128
502_mm_cvtepi64_ps (__m128i __A) {
503 return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
504 (__v4sf) _mm_setzero_ps(),
505 (__mmask8) -1);
506}
507
508static __inline__ __m128 __DEFAULT_FN_ATTRS128
509_mm_mask_cvtepi64_ps (__m128 __W, __mmask8 __U, __m128i __A) {
510 return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
511 (__v4sf) __W,
512 (__mmask8) __U);
513}
514
515static __inline__ __m128 __DEFAULT_FN_ATTRS128
516_mm_maskz_cvtepi64_ps (__mmask8 __U, __m128i __A) {
517 return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
518 (__v4sf) _mm_setzero_ps(),
519 (__mmask8) __U);
520}
521
522static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
523_mm256_cvtepi64_ps(__m256i __A) {
524 return (__m128)__builtin_convertvector((__v4di)__A, __v4sf);
525}
526
527static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
528_mm256_mask_cvtepi64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
529 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
530 (__v4sf)_mm256_cvtepi64_ps(__A),
531 (__v4sf)__W);
532}
533
534static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
535_mm256_maskz_cvtepi64_ps(__mmask8 __U, __m256i __A) {
536 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
537 (__v4sf)_mm256_cvtepi64_ps(__A),
538 (__v4sf)_mm_setzero_ps());
539}
540
541static __inline__ __m128i __DEFAULT_FN_ATTRS128
542_mm_cvttpd_epi64 (__m128d __A) {
543 return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
544 (__v2di) _mm_setzero_si128(),
545 (__mmask8) -1);
546}
547
548static __inline__ __m128i __DEFAULT_FN_ATTRS128
549_mm_mask_cvttpd_epi64 (__m128i __W, __mmask8 __U, __m128d __A) {
550 return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
551 (__v2di) __W,
552 (__mmask8) __U);
553}
554
555static __inline__ __m128i __DEFAULT_FN_ATTRS128
556_mm_maskz_cvttpd_epi64 (__mmask8 __U, __m128d __A) {
557 return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
558 (__v2di) _mm_setzero_si128(),
559 (__mmask8) __U);
560}
561
562static __inline__ __m256i __DEFAULT_FN_ATTRS256
563_mm256_cvttpd_epi64 (__m256d __A) {
564 return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
565 (__v4di) _mm256_setzero_si256(),
566 (__mmask8) -1);
567}
568
569static __inline__ __m256i __DEFAULT_FN_ATTRS256
570_mm256_mask_cvttpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A) {
571 return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
572 (__v4di) __W,
573 (__mmask8) __U);
574}
575
576static __inline__ __m256i __DEFAULT_FN_ATTRS256
577_mm256_maskz_cvttpd_epi64 (__mmask8 __U, __m256d __A) {
578 return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
579 (__v4di) _mm256_setzero_si256(),
580 (__mmask8) __U);
581}
582
583static __inline__ __m128i __DEFAULT_FN_ATTRS128
584_mm_cvttpd_epu64 (__m128d __A) {
585 return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
586 (__v2di) _mm_setzero_si128(),
587 (__mmask8) -1);
588}
589
590static __inline__ __m128i __DEFAULT_FN_ATTRS128
591_mm_mask_cvttpd_epu64 (__m128i __W, __mmask8 __U, __m128d __A) {
592 return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
593 (__v2di) __W,
594 (__mmask8) __U);
595}
596
597static __inline__ __m128i __DEFAULT_FN_ATTRS128
598_mm_maskz_cvttpd_epu64 (__mmask8 __U, __m128d __A) {
599 return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
600 (__v2di) _mm_setzero_si128(),
601 (__mmask8) __U);
602}
603
604static __inline__ __m256i __DEFAULT_FN_ATTRS256
605_mm256_cvttpd_epu64 (__m256d __A) {
606 return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
607 (__v4di) _mm256_setzero_si256(),
608 (__mmask8) -1);
609}
610
611static __inline__ __m256i __DEFAULT_FN_ATTRS256
612_mm256_mask_cvttpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A) {
613 return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
614 (__v4di) __W,
615 (__mmask8) __U);
616}
617
618static __inline__ __m256i __DEFAULT_FN_ATTRS256
619_mm256_maskz_cvttpd_epu64 (__mmask8 __U, __m256d __A) {
620 return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
621 (__v4di) _mm256_setzero_si256(),
622 (__mmask8) __U);
623}
624
625static __inline__ __m128i __DEFAULT_FN_ATTRS128
626_mm_cvttps_epi64 (__m128 __A) {
627 return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
628 (__v2di) _mm_setzero_si128(),
629 (__mmask8) -1);
630}
631
632static __inline__ __m128i __DEFAULT_FN_ATTRS128
633_mm_mask_cvttps_epi64 (__m128i __W, __mmask8 __U, __m128 __A) {
634 return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
635 (__v2di) __W,
636 (__mmask8) __U);
637}
638
639static __inline__ __m128i __DEFAULT_FN_ATTRS128
640_mm_maskz_cvttps_epi64 (__mmask8 __U, __m128 __A) {
641 return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
642 (__v2di) _mm_setzero_si128(),
643 (__mmask8) __U);
644}
645
646static __inline__ __m256i __DEFAULT_FN_ATTRS256
647_mm256_cvttps_epi64 (__m128 __A) {
648 return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
649 (__v4di) _mm256_setzero_si256(),
650 (__mmask8) -1);
651}
652
653static __inline__ __m256i __DEFAULT_FN_ATTRS256
654_mm256_mask_cvttps_epi64 (__m256i __W, __mmask8 __U, __m128 __A) {
655 return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
656 (__v4di) __W,
657 (__mmask8) __U);
658}
659
660static __inline__ __m256i __DEFAULT_FN_ATTRS256
661_mm256_maskz_cvttps_epi64 (__mmask8 __U, __m128 __A) {
662 return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
663 (__v4di) _mm256_setzero_si256(),
664 (__mmask8) __U);
665}
666
667static __inline__ __m128i __DEFAULT_FN_ATTRS128
668_mm_cvttps_epu64 (__m128 __A) {
669 return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
670 (__v2di) _mm_setzero_si128(),
671 (__mmask8) -1);
672}
673
674static __inline__ __m128i __DEFAULT_FN_ATTRS128
675_mm_mask_cvttps_epu64 (__m128i __W, __mmask8 __U, __m128 __A) {
676 return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
677 (__v2di) __W,
678 (__mmask8) __U);
679}
680
681static __inline__ __m128i __DEFAULT_FN_ATTRS128
682_mm_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
683 return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
684 (__v2di) _mm_setzero_si128(),
685 (__mmask8) __U);
686}
687
688static __inline__ __m256i __DEFAULT_FN_ATTRS256
689_mm256_cvttps_epu64 (__m128 __A) {
690 return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
691 (__v4di) _mm256_setzero_si256(),
692 (__mmask8) -1);
693}
694
695static __inline__ __m256i __DEFAULT_FN_ATTRS256
696_mm256_mask_cvttps_epu64 (__m256i __W, __mmask8 __U, __m128 __A) {
697 return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
698 (__v4di) __W,
699 (__mmask8) __U);
700}
701
702static __inline__ __m256i __DEFAULT_FN_ATTRS256
703_mm256_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
704 return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
705 (__v4di) _mm256_setzero_si256(),
706 (__mmask8) __U);
707}
708
709static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
710_mm_cvtepu64_pd(__m128i __A) {
711 return (__m128d)__builtin_convertvector((__v2du)__A, __v2df);
712}
713
714static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
715_mm_mask_cvtepu64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
716 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
717 (__v2df)_mm_cvtepu64_pd(__A),
718 (__v2df)__W);
719}
720
721static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
722_mm_maskz_cvtepu64_pd(__mmask8 __U, __m128i __A) {
723 return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
724 (__v2df)_mm_cvtepu64_pd(__A),
725 (__v2df)_mm_setzero_pd());
726}
727
728static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
729_mm256_cvtepu64_pd(__m256i __A) {
730 return (__m256d)__builtin_convertvector((__v4du)__A, __v4df);
731}
732
733static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
734_mm256_mask_cvtepu64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
735 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
736 (__v4df)_mm256_cvtepu64_pd(__A),
737 (__v4df)__W);
738}
739
740static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
741_mm256_maskz_cvtepu64_pd(__mmask8 __U, __m256i __A) {
742 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
743 (__v4df)_mm256_cvtepu64_pd(__A),
744 (__v4df)_mm256_setzero_pd());
745}
746
747static __inline__ __m128 __DEFAULT_FN_ATTRS128
748_mm_cvtepu64_ps (__m128i __A) {
749 return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
750 (__v4sf) _mm_setzero_ps(),
751 (__mmask8) -1);
752}
753
754static __inline__ __m128 __DEFAULT_FN_ATTRS128
755_mm_mask_cvtepu64_ps (__m128 __W, __mmask8 __U, __m128i __A) {
756 return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
757 (__v4sf) __W,
758 (__mmask8) __U);
759}
760
761static __inline__ __m128 __DEFAULT_FN_ATTRS128
762_mm_maskz_cvtepu64_ps (__mmask8 __U, __m128i __A) {
763 return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
764 (__v4sf) _mm_setzero_ps(),
765 (__mmask8) __U);
766}
767
768static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
769_mm256_cvtepu64_ps(__m256i __A) {
770 return (__m128)__builtin_convertvector((__v4du)__A, __v4sf);
771}
772
773static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
774_mm256_mask_cvtepu64_ps(__m128 __W, __mmask8 __U, __m256i __A) {
775 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
776 (__v4sf)_mm256_cvtepu64_ps(__A),
777 (__v4sf)__W);
778}
779
780static __inline__ __m128 __DEFAULT_FN_ATTRS256_CONSTEXPR
781_mm256_maskz_cvtepu64_ps(__mmask8 __U, __m256i __A) {
782 return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
783 (__v4sf)_mm256_cvtepu64_ps(__A),
784 (__v4sf)_mm_setzero_ps());
785}
786
787#define _mm_range_pd(A, B, C) \
788 ((__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
789 (__v2df)(__m128d)(B), (int)(C), \
790 (__v2df)_mm_setzero_pd(), \
791 (__mmask8)-1))
792
793#define _mm_mask_range_pd(W, U, A, B, C) \
794 ((__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
795 (__v2df)(__m128d)(B), (int)(C), \
796 (__v2df)(__m128d)(W), \
797 (__mmask8)(U)))
798
799#define _mm_maskz_range_pd(U, A, B, C) \
800 ((__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
801 (__v2df)(__m128d)(B), (int)(C), \
802 (__v2df)_mm_setzero_pd(), \
803 (__mmask8)(U)))
804
805#define _mm256_range_pd(A, B, C) \
806 ((__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
807 (__v4df)(__m256d)(B), (int)(C), \
808 (__v4df)_mm256_setzero_pd(), \
809 (__mmask8)-1))
810
811#define _mm256_mask_range_pd(W, U, A, B, C) \
812 ((__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
813 (__v4df)(__m256d)(B), (int)(C), \
814 (__v4df)(__m256d)(W), \
815 (__mmask8)(U)))
816
817#define _mm256_maskz_range_pd(U, A, B, C) \
818 ((__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
819 (__v4df)(__m256d)(B), (int)(C), \
820 (__v4df)_mm256_setzero_pd(), \
821 (__mmask8)(U)))
822
823#define _mm_range_ps(A, B, C) \
824 ((__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
825 (__v4sf)(__m128)(B), (int)(C), \
826 (__v4sf)_mm_setzero_ps(), \
827 (__mmask8)-1))
828
829#define _mm_mask_range_ps(W, U, A, B, C) \
830 ((__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
831 (__v4sf)(__m128)(B), (int)(C), \
832 (__v4sf)(__m128)(W), (__mmask8)(U)))
833
834#define _mm_maskz_range_ps(U, A, B, C) \
835 ((__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
836 (__v4sf)(__m128)(B), (int)(C), \
837 (__v4sf)_mm_setzero_ps(), \
838 (__mmask8)(U)))
839
840#define _mm256_range_ps(A, B, C) \
841 ((__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
842 (__v8sf)(__m256)(B), (int)(C), \
843 (__v8sf)_mm256_setzero_ps(), \
844 (__mmask8)-1))
845
846#define _mm256_mask_range_ps(W, U, A, B, C) \
847 ((__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
848 (__v8sf)(__m256)(B), (int)(C), \
849 (__v8sf)(__m256)(W), (__mmask8)(U)))
850
851#define _mm256_maskz_range_ps(U, A, B, C) \
852 ((__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
853 (__v8sf)(__m256)(B), (int)(C), \
854 (__v8sf)_mm256_setzero_ps(), \
855 (__mmask8)(U)))
856
857#define _mm_reduce_pd(A, B) \
858 ((__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
859 (__v2df)_mm_setzero_pd(), \
860 (__mmask8)-1))
861
862#define _mm_mask_reduce_pd(W, U, A, B) \
863 ((__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
864 (__v2df)(__m128d)(W), \
865 (__mmask8)(U)))
866
867#define _mm_maskz_reduce_pd(U, A, B) \
868 ((__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
869 (__v2df)_mm_setzero_pd(), \
870 (__mmask8)(U)))
871
872#define _mm256_reduce_pd(A, B) \
873 ((__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
874 (__v4df)_mm256_setzero_pd(), \
875 (__mmask8)-1))
876
877#define _mm256_mask_reduce_pd(W, U, A, B) \
878 ((__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
879 (__v4df)(__m256d)(W), \
880 (__mmask8)(U)))
881
882#define _mm256_maskz_reduce_pd(U, A, B) \
883 ((__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
884 (__v4df)_mm256_setzero_pd(), \
885 (__mmask8)(U)))
886
887#define _mm_reduce_ps(A, B) \
888 ((__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
889 (__v4sf)_mm_setzero_ps(), \
890 (__mmask8)-1))
891
892#define _mm_mask_reduce_ps(W, U, A, B) \
893 ((__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
894 (__v4sf)(__m128)(W), \
895 (__mmask8)(U)))
896
897#define _mm_maskz_reduce_ps(U, A, B) \
898 ((__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
899 (__v4sf)_mm_setzero_ps(), \
900 (__mmask8)(U)))
901
902#define _mm256_reduce_ps(A, B) \
903 ((__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
904 (__v8sf)_mm256_setzero_ps(), \
905 (__mmask8)-1))
906
907#define _mm256_mask_reduce_ps(W, U, A, B) \
908 ((__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
909 (__v8sf)(__m256)(W), \
910 (__mmask8)(U)))
911
912#define _mm256_maskz_reduce_ps(U, A, B) \
913 ((__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
914 (__v8sf)_mm256_setzero_ps(), \
915 (__mmask8)(U)))
916
917static __inline__ __mmask8
918 __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_movepi32_mask(__m128i __A) {
919 return (__mmask8) __builtin_ia32_cvtd2mask128 ((__v4si) __A);
920}
921
922static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
923_mm256_movepi32_mask(__m256i __A) {
924 return (__mmask8) __builtin_ia32_cvtd2mask256 ((__v8si) __A);
925}
926
927static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
928_mm_movm_epi32(__mmask8 __A) {
929 return (__m128i) __builtin_ia32_cvtmask2d128 (__A);
930}
931
932static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
933_mm256_movm_epi32(__mmask8 __A) {
934 return (__m256i) __builtin_ia32_cvtmask2d256 (__A);
935}
936
937static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
938_mm_movm_epi64(__mmask8 __A) {
939 return (__m128i) __builtin_ia32_cvtmask2q128 (__A);
940}
941
942static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
943_mm256_movm_epi64(__mmask8 __A) {
944 return (__m256i) __builtin_ia32_cvtmask2q256 (__A);
945}
946
947static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
948_mm_movepi64_mask(__m128i __A) {
949 return (__mmask8) __builtin_ia32_cvtq2mask128 ((__v2di) __A);
950}
951
952static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
953_mm256_movepi64_mask(__m256i __A) {
954 return (__mmask8) __builtin_ia32_cvtq2mask256 ((__v4di) __A);
955}
956
957static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
958_mm256_broadcast_f32x2(__m128 __A) {
959 return (__m256)__builtin_shufflevector((__v4sf)__A, (__v4sf)__A,
960 0, 1, 0, 1, 0, 1, 0, 1);
961}
962
963static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
964_mm256_mask_broadcast_f32x2(__m256 __O, __mmask8 __M, __m128 __A) {
965 return (__m256)__builtin_ia32_selectps_256((__mmask8)__M,
966 (__v8sf)_mm256_broadcast_f32x2(__A),
967 (__v8sf)__O);
968}
969
970static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
971_mm256_maskz_broadcast_f32x2(__mmask8 __M, __m128 __A) {
972 return (__m256)__builtin_ia32_selectps_256((__mmask8)__M,
973 (__v8sf)_mm256_broadcast_f32x2(__A),
974 (__v8sf)_mm256_setzero_ps());
975}
976
977static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
978_mm256_broadcast_f64x2(__m128d __A) {
979 return (__m256d)__builtin_shufflevector((__v2df)__A, (__v2df)__A,
980 0, 1, 0, 1);
981}
982
983static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
984_mm256_mask_broadcast_f64x2(__m256d __O, __mmask8 __M, __m128d __A) {
985 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__M,
986 (__v4df)_mm256_broadcast_f64x2(__A),
987 (__v4df)__O);
988}
989
990static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
991_mm256_maskz_broadcast_f64x2(__mmask8 __M, __m128d __A) {
992 return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__M,
993 (__v4df)_mm256_broadcast_f64x2(__A),
994 (__v4df)_mm256_setzero_pd());
995}
996
997static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
998_mm_broadcast_i32x2(__m128i __A) {
999 return (__m128i)__builtin_shufflevector((__v4si)__A, (__v4si)__A,
1000 0, 1, 0, 1);
1001}
1002
1003static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
1004_mm_mask_broadcast_i32x2(__m128i __O, __mmask8 __M, __m128i __A) {
1005 return (__m128i)__builtin_ia32_selectd_128((__mmask8)__M,
1006 (__v4si)_mm_broadcast_i32x2(__A),
1007 (__v4si)__O);
1008}
1009
1010static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
1011_mm_maskz_broadcast_i32x2(__mmask8 __M, __m128i __A) {
1012 return (__m128i)__builtin_ia32_selectd_128((__mmask8)__M,
1013 (__v4si)_mm_broadcast_i32x2(__A),
1014 (__v4si)_mm_setzero_si128());
1015}
1016
1017static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1018_mm256_broadcast_i32x2(__m128i __A) {
1019 return (__m256i)__builtin_shufflevector((__v4si)__A, (__v4si)__A,
1020 0, 1, 0, 1, 0, 1, 0, 1);
1021}
1022
1023static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1024_mm256_mask_broadcast_i32x2(__m256i __O, __mmask8 __M, __m128i __A) {
1025 return (__m256i)__builtin_ia32_selectd_256((__mmask8)__M,
1026 (__v8si)_mm256_broadcast_i32x2(__A),
1027 (__v8si)__O);
1028}
1029
1030static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1031_mm256_maskz_broadcast_i32x2(__mmask8 __M, __m128i __A) {
1032 return (__m256i)__builtin_ia32_selectd_256((__mmask8)__M,
1033 (__v8si)_mm256_broadcast_i32x2(__A),
1034 (__v8si)_mm256_setzero_si256());
1035}
1036
1037static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1038_mm256_broadcast_i64x2(__m128i __A) {
1039 return (__m256i)__builtin_shufflevector((__v2di)__A, (__v2di)__A,
1040 0, 1, 0, 1);
1041}
1042
1043static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1044_mm256_mask_broadcast_i64x2(__m256i __O, __mmask8 __M, __m128i __A) {
1045 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__M,
1046 (__v4di)_mm256_broadcast_i64x2(__A),
1047 (__v4di)__O);
1048}
1049
1050static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
1051_mm256_maskz_broadcast_i64x2(__mmask8 __M, __m128i __A) {
1052 return (__m256i)__builtin_ia32_selectq_256((__mmask8)__M,
1053 (__v4di)_mm256_broadcast_i64x2(__A),
1054 (__v4di)_mm256_setzero_si256());
1055}
1056
1057#define _mm256_extractf64x2_pd(A, imm) \
1058 ((__m128d)__builtin_ia32_extractf64x2_256_mask( \
1059 (__v4df)(__m256d)(A), (int)(imm), (__v2df)_mm_setzero_pd(), \
1060 (__mmask8) - 1))
1061
1062#define _mm256_mask_extractf64x2_pd(W, U, A, imm) \
1063 ((__m128d)__builtin_ia32_extractf64x2_256_mask((__v4df)(__m256d)(A), \
1064 (int)(imm), \
1065 (__v2df)(__m128d)(W), \
1066 (__mmask8)(U)))
1067
1068#define _mm256_maskz_extractf64x2_pd(U, A, imm) \
1069 ((__m128d)__builtin_ia32_extractf64x2_256_mask((__v4df)(__m256d)(A), \
1070 (int)(imm), \
1071 (__v2df)_mm_setzero_pd(), \
1072 (__mmask8)(U)))
1073
1074#define _mm256_extracti64x2_epi64(A, imm) \
1075 ((__m128i)__builtin_ia32_extracti64x2_256_mask( \
1076 (__v4di)(__m256i)(A), (int)(imm), (__v2di)_mm_setzero_si128(), \
1077 (__mmask8) - 1))
1078
1079#define _mm256_mask_extracti64x2_epi64(W, U, A, imm) \
1080 ((__m128i)__builtin_ia32_extracti64x2_256_mask((__v4di)(__m256i)(A), \
1081 (int)(imm), \
1082 (__v2di)(__m128i)(W), \
1083 (__mmask8)(U)))
1084
1085#define _mm256_maskz_extracti64x2_epi64(U, A, imm) \
1086 ((__m128i)__builtin_ia32_extracti64x2_256_mask((__v4di)(__m256i)(A), \
1087 (int)(imm), \
1088 (__v2di)_mm_setzero_si128(), \
1089 (__mmask8)(U)))
1090
1091#define _mm256_insertf64x2(A, B, imm) \
1092 ((__m256d)__builtin_ia32_insertf64x2_256((__v4df)(__m256d)(A), \
1093 (__v2df)(__m128d)(B), (int)(imm)))
1094
1095#define _mm256_mask_insertf64x2(W, U, A, B, imm) \
1096 ((__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
1097 (__v4df)_mm256_insertf64x2((A), (B), (imm)), \
1098 (__v4df)(__m256d)(W)))
1099
1100#define _mm256_maskz_insertf64x2(U, A, B, imm) \
1101 ((__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
1102 (__v4df)_mm256_insertf64x2((A), (B), (imm)), \
1103 (__v4df)_mm256_setzero_pd()))
1104
1105#define _mm256_inserti64x2(A, B, imm) \
1106 ((__m256i)__builtin_ia32_inserti64x2_256((__v4di)(__m256i)(A), \
1107 (__v2di)(__m128i)(B), (int)(imm)))
1108
1109#define _mm256_mask_inserti64x2(W, U, A, B, imm) \
1110 ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
1111 (__v4di)_mm256_inserti64x2((A), (B), (imm)), \
1112 (__v4di)(__m256i)(W)))
1113
1114#define _mm256_maskz_inserti64x2(U, A, B, imm) \
1115 ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
1116 (__v4di)_mm256_inserti64x2((A), (B), (imm)), \
1117 (__v4di)_mm256_setzero_si256()))
1118
1119#define _mm_mask_fpclass_pd_mask(U, A, imm) \
1120 ((__mmask8)__builtin_ia32_fpclasspd128_mask((__v2df)(__m128d)(A), (int)(imm), \
1121 (__mmask8)(U)))
1122
1123#define _mm_fpclass_pd_mask(A, imm) \
1124 ((__mmask8)__builtin_ia32_fpclasspd128_mask((__v2df)(__m128d)(A), (int)(imm), \
1125 (__mmask8)-1))
1126
1127#define _mm256_mask_fpclass_pd_mask(U, A, imm) \
1128 ((__mmask8)__builtin_ia32_fpclasspd256_mask((__v4df)(__m256d)(A), (int)(imm), \
1129 (__mmask8)(U)))
1130
1131#define _mm256_fpclass_pd_mask(A, imm) \
1132 ((__mmask8)__builtin_ia32_fpclasspd256_mask((__v4df)(__m256d)(A), (int)(imm), \
1133 (__mmask8)-1))
1134
1135#define _mm_mask_fpclass_ps_mask(U, A, imm) \
1136 ((__mmask8)__builtin_ia32_fpclassps128_mask((__v4sf)(__m128)(A), (int)(imm), \
1137 (__mmask8)(U)))
1138
1139#define _mm_fpclass_ps_mask(A, imm) \
1140 ((__mmask8)__builtin_ia32_fpclassps128_mask((__v4sf)(__m128)(A), (int)(imm), \
1141 (__mmask8)-1))
1142
1143#define _mm256_mask_fpclass_ps_mask(U, A, imm) \
1144 ((__mmask8)__builtin_ia32_fpclassps256_mask((__v8sf)(__m256)(A), (int)(imm), \
1145 (__mmask8)(U)))
1146
1147#define _mm256_fpclass_ps_mask(A, imm) \
1148 ((__mmask8)__builtin_ia32_fpclassps256_mask((__v8sf)(__m256)(A), (int)(imm), \
1149 (__mmask8)-1))
1150
1151#undef __DEFAULT_FN_ATTRS128
1152#undef __DEFAULT_FN_ATTRS256
1153#undef __DEFAULT_FN_ATTRS256_CONSTEXPR
1154#undef __DEFAULT_FN_ATTRS128_CONSTEXPR
1155
1156#endif