1/*===------------- avx512vlvnniintrin.h - VNNI intrinsics ------------------===
2 *
3 *
4 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 * See https://llvm.org/LICENSE.txt for license information.
6 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *
8 *===-----------------------------------------------------------------------===
9 */
10#ifndef __IMMINTRIN_H
11#error "Never use <avx512vlvnniintrin.h> directly; include <immintrin.h> instead."
12#endif
13
14#ifndef __AVX512VLVNNIINTRIN_H
15#define __AVX512VLVNNIINTRIN_H
16
17/* Define the default attributes for the functions in this file. */
18#define __DEFAULT_FN_ATTRS128 \
19 __attribute__((__always_inline__, __nodebug__, \
20 __target__("avx512vl,avx512vnni"), \
21 __min_vector_width__(128)))
22#define __DEFAULT_FN_ATTRS256 \
23 __attribute__((__always_inline__, __nodebug__, \
24 __target__("avx512vl,avx512vnni"), \
25 __min_vector_width__(256)))
26
27/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
28/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
29/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
30/// in \a S, and store the packed 32-bit results in DST.
31///
32/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.
33///
34/// \code{.operation}
35/// FOR j := 0 to 7
36/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
37/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
38/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
39/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
40/// DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
41/// ENDFOR
42/// DST[MAX:256] := 0
43/// \endcode
44#define _mm256_dpbusd_epi32(S, A, B) \
45 ((__m256i)__builtin_ia32_vpdpbusd256((__v8si)(S), (__v32qu)(A), (__v32qi)(B)))
46
47/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
48/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
49/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
50/// in \a S using signed saturation, and store the packed 32-bit results in DST.
51///
52/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.
53///
54/// \code{.operation}
55/// FOR j := 0 to 7
56/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
57/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
58/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
59/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
60/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
61/// ENDFOR
62/// DST[MAX:256] := 0
63/// \endcode
64#define _mm256_dpbusds_epi32(S, A, B) \
65 ((__m256i)__builtin_ia32_vpdpbusds256((__v8si)(S), (__v32qu)(A), \
66 (__v32qi)(B)))
67
68/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
69/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
70/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,
71/// and store the packed 32-bit results in DST.
72///
73/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.
74///
75/// \code{.operation}
76/// FOR j := 0 to 7
77/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
78/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
79/// DST.dword[j] := S.dword[j] + tmp1 + tmp2
80/// ENDFOR
81/// DST[MAX:256] := 0
82/// \endcode
83#define _mm256_dpwssd_epi32(S, A, B) \
84 ((__m256i)__builtin_ia32_vpdpwssd256((__v8si)(S), (__v16hi)(A), (__v16hi)(B)))
85
86/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
87/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
88/// results. Sum these 2 results with the corresponding 32-bit integer in \a S
89/// using signed saturation, and store the packed 32-bit results in DST.
90///
91/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.
92///
93/// \code{.operation}
94/// FOR j := 0 to 7
95/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
96/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
97/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)
98/// ENDFOR
99/// DST[MAX:256] := 0
100/// \endcode
101#define _mm256_dpwssds_epi32(S, A, B) \
102 ((__m256i)__builtin_ia32_vpdpwssds256((__v8si)(S), (__v16hi)(A), \
103 (__v16hi)(B)))
104
105/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
106/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
107/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
108/// in \a S, and store the packed 32-bit results in DST.
109///
110/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.
111///
112/// \code{.operation}
113/// FOR j := 0 to 3
114/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
115/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
116/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
117/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
118/// DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
119/// ENDFOR
120/// DST[MAX:128] := 0
121/// \endcode
122#define _mm_dpbusd_epi32(S, A, B) \
123 ((__m128i)__builtin_ia32_vpdpbusd128((__v4si)(S), (__v16qu)(A), (__v16qi)(B)))
124
125/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
126/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
127/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
128/// in \a S using signed saturation, and store the packed 32-bit results in DST.
129///
130/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.
131///
132/// \code{.operation}
133/// FOR j := 0 to 3
134/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
135/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
136/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
137/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
138/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
139/// ENDFOR
140/// DST[MAX:128] := 0
141/// \endcode
142#define _mm_dpbusds_epi32(S, A, B) \
143 ((__m128i)__builtin_ia32_vpdpbusds128((__v4si)(S), (__v16qu)(A), \
144 (__v16qi)(B)))
145
146/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
147/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
148/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,
149/// and store the packed 32-bit results in DST.
150///
151/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.
152///
153/// \code{.operation}
154/// FOR j := 0 to 3
155/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
156/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
157/// DST.dword[j] := S.dword[j] + tmp1 + tmp2
158/// ENDFOR
159/// DST[MAX:128] := 0
160/// \endcode
161#define _mm_dpwssd_epi32(S, A, B) \
162 ((__m128i)__builtin_ia32_vpdpwssd128((__v4si)(S), (__v8hi)(A), (__v8hi)(B)))
163
164/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
165/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
166/// results. Sum these 2 results with the corresponding 32-bit integer in \a S
167/// using signed saturation, and store the packed 32-bit results in DST.
168///
169/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.
170///
171/// \code{.operation}
172/// FOR j := 0 to 3
173/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
174/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
175/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)
176/// ENDFOR
177/// DST[MAX:128] := 0
178/// \endcode
179#define _mm_dpwssds_epi32(S, A, B) \
180 ((__m128i)__builtin_ia32_vpdpwssds128((__v4si)(S), (__v8hi)(A), (__v8hi)(B)))
181
182static __inline__ __m256i __DEFAULT_FN_ATTRS256
183_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
184{
185 return (__m256i)__builtin_ia32_selectd_256(__U,
186 (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
187 (__v8si)__S);
188}
189
190static __inline__ __m256i __DEFAULT_FN_ATTRS256
191_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
192{
193 return (__m256i)__builtin_ia32_selectd_256(__U,
194 (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
195 (__v8si)_mm256_setzero_si256());
196}
197
198static __inline__ __m256i __DEFAULT_FN_ATTRS256
199_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
200{
201 return (__m256i)__builtin_ia32_selectd_256(__U,
202 (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
203 (__v8si)__S);
204}
205
206static __inline__ __m256i __DEFAULT_FN_ATTRS256
207_mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
208{
209 return (__m256i)__builtin_ia32_selectd_256(__U,
210 (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
211 (__v8si)_mm256_setzero_si256());
212}
213
214static __inline__ __m256i __DEFAULT_FN_ATTRS256
215_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
216{
217 return (__m256i)__builtin_ia32_selectd_256(__U,
218 (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
219 (__v8si)__S);
220}
221
222static __inline__ __m256i __DEFAULT_FN_ATTRS256
223_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
224{
225 return (__m256i)__builtin_ia32_selectd_256(__U,
226 (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
227 (__v8si)_mm256_setzero_si256());
228}
229
230static __inline__ __m256i __DEFAULT_FN_ATTRS256
231_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
232{
233 return (__m256i)__builtin_ia32_selectd_256(__U,
234 (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
235 (__v8si)__S);
236}
237
238static __inline__ __m256i __DEFAULT_FN_ATTRS256
239_mm256_maskz_dpwssds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
240{
241 return (__m256i)__builtin_ia32_selectd_256(__U,
242 (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
243 (__v8si)_mm256_setzero_si256());
244}
245
246static __inline__ __m128i __DEFAULT_FN_ATTRS128
247_mm_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
248{
249 return (__m128i)__builtin_ia32_selectd_128(__U,
250 (__v4si)_mm_dpbusd_epi32(__S, __A, __B),
251 (__v4si)__S);
252}
253
254static __inline__ __m128i __DEFAULT_FN_ATTRS128
255_mm_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
256{
257 return (__m128i)__builtin_ia32_selectd_128(__U,
258 (__v4si)_mm_dpbusd_epi32(__S, __A, __B),
259 (__v4si)_mm_setzero_si128());
260}
261
262static __inline__ __m128i __DEFAULT_FN_ATTRS128
263_mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
264{
265 return (__m128i)__builtin_ia32_selectd_128(__U,
266 (__v4si)_mm_dpbusds_epi32(__S, __A, __B),
267 (__v4si)__S);
268}
269
270static __inline__ __m128i __DEFAULT_FN_ATTRS128
271_mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
272{
273 return (__m128i)__builtin_ia32_selectd_128(__U,
274 (__v4si)_mm_dpbusds_epi32(__S, __A, __B),
275 (__v4si)_mm_setzero_si128());
276}
277
278static __inline__ __m128i __DEFAULT_FN_ATTRS128
279_mm_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
280{
281 return (__m128i)__builtin_ia32_selectd_128(__U,
282 (__v4si)_mm_dpwssd_epi32(__S, __A, __B),
283 (__v4si)__S);
284}
285
286static __inline__ __m128i __DEFAULT_FN_ATTRS128
287_mm_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
288{
289 return (__m128i)__builtin_ia32_selectd_128(__U,
290 (__v4si)_mm_dpwssd_epi32(__S, __A, __B),
291 (__v4si)_mm_setzero_si128());
292}
293
294static __inline__ __m128i __DEFAULT_FN_ATTRS128
295_mm_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
296{
297 return (__m128i)__builtin_ia32_selectd_128(__U,
298 (__v4si)_mm_dpwssds_epi32(__S, __A, __B),
299 (__v4si)__S);
300}
301
302static __inline__ __m128i __DEFAULT_FN_ATTRS128
303_mm_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
304{
305 return (__m128i)__builtin_ia32_selectd_128(__U,
306 (__v4si)_mm_dpwssds_epi32(__S, __A, __B),
307 (__v4si)_mm_setzero_si128());
308}
309
310#undef __DEFAULT_FN_ATTRS128
311#undef __DEFAULT_FN_ATTRS256
312
313#endif