1/*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9
10#if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED)
11#error "Never use <prfchwintrin.h> directly; include <x86intrin.h> instead."
12#endif
13
14#ifndef __PRFCHWINTRIN_H
15#define __PRFCHWINTRIN_H
16
17#if defined(__cplusplus)
18extern "C" {
19#endif
20
21/// Loads a memory sequence containing the specified memory address into
22/// all data cache levels.
23///
24/// The cache-coherency state is set to exclusive. Data can be read from
25/// and written to the cache line without additional delay.
26///
27/// \headerfile <x86intrin.h>
28///
29/// This intrinsic corresponds to the \c PREFETCHT0 instruction.
30///
31/// \param __P
32/// A pointer specifying the memory address to be prefetched.
33void _m_prefetch(void *__P);
34
35/// Loads a memory sequence containing the specified memory address into
36/// the L1 data cache and sets the cache-coherency state to modified.
37///
38/// This provides a hint to the processor that the cache line will be
39/// modified. It is intended for use when the cache line will be written to
40/// shortly after the prefetch is performed.
41///
42/// Note that the effect of this intrinsic is dependent on the processor
43/// implementation.
44///
45/// \headerfile <x86intrin.h>
46///
47/// This intrinsic corresponds to the \c PREFETCHW instruction.
48///
49/// \param __P
50/// A pointer specifying the memory address to be prefetched.
51void _m_prefetchw(volatile const void *__P);
52
53#if defined(__cplusplus)
54} // extern "C"
55#endif
56
57#endif /* __PRFCHWINTRIN_H */