| 1 | /*- |
| 2 | * Copyright (c) 2013, 2014 Andrew Turner |
| 3 | * Copyright (c) 2015,2021 The FreeBSD Foundation |
| 4 | * |
| 5 | * Portions of this software were developed by Andrew Turner |
| 6 | * under sponsorship from the FreeBSD Foundation. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifdef __arm__ |
| 31 | #include <arm/armreg.h> |
| 32 | #else /* !__arm__ */ |
| 33 | |
| 34 | #ifndef _MACHINE_ARMREG_H_ |
| 35 | #define _MACHINE_ARMREG_H_ |
| 36 | |
| 37 | #define INSN_SIZE 4 |
| 38 | |
| 39 | #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ |
| 40 | S##op0##_##op1##_C##crn##_C##crm##_##op2 |
| 41 | #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ |
| 42 | __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) |
| 43 | #define MRS_REG_ALT_NAME(reg) \ |
| 44 | _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) |
| 45 | |
| 46 | |
| 47 | #define READ_SPECIALREG(reg) \ |
| 48 | ({ uint64_t _val; \ |
| 49 | __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ |
| 50 | _val; \ |
| 51 | }) |
| 52 | #define WRITE_SPECIALREG(reg, _val) \ |
| 53 | __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) |
| 54 | |
| 55 | #define UL(x) UINT64_C(x) |
| 56 | |
| 57 | /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */ |
| 58 | #define AFSR0_EL1_REG MRS_REG_ALT_NAME(AFSR0_EL1) |
| 59 | #define AFSR0_EL1_op0 3 |
| 60 | #define AFSR0_EL1_op1 0 |
| 61 | #define AFSR0_EL1_CRn 5 |
| 62 | #define AFSR0_EL1_CRm 1 |
| 63 | #define AFSR0_EL1_op2 0 |
| 64 | |
| 65 | /* AFSR0_EL12 */ |
| 66 | #define AFSR0_EL12_REG MRS_REG_ALT_NAME(AFSR0_EL12) |
| 67 | #define AFSR0_EL12_op0 3 |
| 68 | #define AFSR0_EL12_op1 5 |
| 69 | #define AFSR0_EL12_CRn 5 |
| 70 | #define AFSR0_EL12_CRm 1 |
| 71 | #define AFSR0_EL12_op2 0 |
| 72 | |
| 73 | /* AFSR1_EL1 - Auxiliary Fault Status Register 1 */ |
| 74 | #define AFSR1_EL1_REG MRS_REG_ALT_NAME(AFSR1_EL1) |
| 75 | #define AFSR1_EL1_op0 3 |
| 76 | #define AFSR1_EL1_op1 0 |
| 77 | #define AFSR1_EL1_CRn 5 |
| 78 | #define AFSR1_EL1_CRm 1 |
| 79 | #define AFSR1_EL1_op2 1 |
| 80 | |
| 81 | /* AFSR1_EL12 */ |
| 82 | #define AFSR1_EL12_REG MRS_REG_ALT_NAME(AFSR1_EL12) |
| 83 | #define AFSR1_EL12_op0 3 |
| 84 | #define AFSR1_EL12_op1 5 |
| 85 | #define AFSR1_EL12_CRn 5 |
| 86 | #define AFSR1_EL12_CRm 1 |
| 87 | #define AFSR1_EL12_op2 1 |
| 88 | |
| 89 | /* AMAIR_EL1 - Auxiliary Memory Attribute Indirection Register */ |
| 90 | #define AMAIR_EL1_REG MRS_REG_ALT_NAME(AMAIR_EL1) |
| 91 | #define AMAIR_EL1_op0 3 |
| 92 | #define AMAIR_EL1_op1 0 |
| 93 | #define AMAIR_EL1_CRn 10 |
| 94 | #define AMAIR_EL1_CRm 3 |
| 95 | #define AMAIR_EL1_op2 0 |
| 96 | |
| 97 | /* AMAIR_EL12 */ |
| 98 | #define AMAIR_EL12_REG MRS_REG_ALT_NAME(AMAIR_EL12) |
| 99 | #define AMAIR_EL12_op0 3 |
| 100 | #define AMAIR_EL12_op1 5 |
| 101 | #define AMAIR_EL12_CRn 10 |
| 102 | #define AMAIR_EL12_CRm 3 |
| 103 | #define AMAIR_EL12_op2 0 |
| 104 | |
| 105 | /* APDAKeyHi_EL1 */ |
| 106 | #define APDAKeyHi_EL1_REG MRS_REG_ALT_NAME(APDAKeyHi_EL1) |
| 107 | #define APDAKeyHi_EL1_op0 3 |
| 108 | #define APDAKeyHi_EL1_op1 0 |
| 109 | #define APDAKeyHi_EL1_CRn 2 |
| 110 | #define APDAKeyHi_EL1_CRm 2 |
| 111 | #define APDAKeyHi_EL1_op2 1 |
| 112 | |
| 113 | /* APDAKeyLo_EL1 */ |
| 114 | #define APDAKeyLo_EL1_REG MRS_REG_ALT_NAME(APDAKeyLo_EL1) |
| 115 | #define APDAKeyLo_EL1_op0 3 |
| 116 | #define APDAKeyLo_EL1_op1 0 |
| 117 | #define APDAKeyLo_EL1_CRn 2 |
| 118 | #define APDAKeyLo_EL1_CRm 2 |
| 119 | #define APDAKeyLo_EL1_op2 0 |
| 120 | |
| 121 | /* APDBKeyHi_EL1 */ |
| 122 | #define APDBKeyHi_EL1_REG MRS_REG_ALT_NAME(APDBKeyHi_EL1) |
| 123 | #define APDBKeyHi_EL1_op0 3 |
| 124 | #define APDBKeyHi_EL1_op1 0 |
| 125 | #define APDBKeyHi_EL1_CRn 2 |
| 126 | #define APDBKeyHi_EL1_CRm 2 |
| 127 | #define APDBKeyHi_EL1_op2 3 |
| 128 | |
| 129 | /* APDBKeyLo_EL1 */ |
| 130 | #define APDBKeyLo_EL1_REG MRS_REG_ALT_NAME(APDBKeyLo_EL1) |
| 131 | #define APDBKeyLo_EL1_op0 3 |
| 132 | #define APDBKeyLo_EL1_op1 0 |
| 133 | #define APDBKeyLo_EL1_CRn 2 |
| 134 | #define APDBKeyLo_EL1_CRm 2 |
| 135 | #define APDBKeyLo_EL1_op2 2 |
| 136 | |
| 137 | /* APGAKeyHi_EL1 */ |
| 138 | #define APGAKeyHi_EL1_REG MRS_REG_ALT_NAME(APGAKeyHi_EL1) |
| 139 | #define APGAKeyHi_EL1_op0 3 |
| 140 | #define APGAKeyHi_EL1_op1 0 |
| 141 | #define APGAKeyHi_EL1_CRn 2 |
| 142 | #define APGAKeyHi_EL1_CRm 3 |
| 143 | #define APGAKeyHi_EL1_op2 1 |
| 144 | |
| 145 | /* APGAKeyLo_EL1 */ |
| 146 | #define APGAKeyLo_EL1_REG MRS_REG_ALT_NAME(APGAKeyLo_EL1) |
| 147 | #define APGAKeyLo_EL1_op0 3 |
| 148 | #define APGAKeyLo_EL1_op1 0 |
| 149 | #define APGAKeyLo_EL1_CRn 2 |
| 150 | #define APGAKeyLo_EL1_CRm 3 |
| 151 | #define APGAKeyLo_EL1_op2 0 |
| 152 | |
| 153 | /* APIAKeyHi_EL1 */ |
| 154 | #define APIAKeyHi_EL1_REG MRS_REG_ALT_NAME(APIAKeyHi_EL1) |
| 155 | #define APIAKeyHi_EL1_op0 3 |
| 156 | #define APIAKeyHi_EL1_op1 0 |
| 157 | #define APIAKeyHi_EL1_CRn 2 |
| 158 | #define APIAKeyHi_EL1_CRm 1 |
| 159 | #define APIAKeyHi_EL1_op2 1 |
| 160 | |
| 161 | /* APIAKeyLo_EL1 */ |
| 162 | #define APIAKeyLo_EL1_REG MRS_REG_ALT_NAME(APIAKeyLo_EL1) |
| 163 | #define APIAKeyLo_EL1_op0 3 |
| 164 | #define APIAKeyLo_EL1_op1 0 |
| 165 | #define APIAKeyLo_EL1_CRn 2 |
| 166 | #define APIAKeyLo_EL1_CRm 1 |
| 167 | #define APIAKeyLo_EL1_op2 0 |
| 168 | |
| 169 | /* APIBKeyHi_EL1 */ |
| 170 | #define APIBKeyHi_EL1_REG MRS_REG_ALT_NAME(APIBKeyHi_EL1) |
| 171 | #define APIBKeyHi_EL1_op0 3 |
| 172 | #define APIBKeyHi_EL1_op1 0 |
| 173 | #define APIBKeyHi_EL1_CRn 2 |
| 174 | #define APIBKeyHi_EL1_CRm 1 |
| 175 | #define APIBKeyHi_EL1_op2 3 |
| 176 | |
| 177 | /* APIBKeyLo_EL1 */ |
| 178 | #define APIBKeyLo_EL1_REG MRS_REG_ALT_NAME(APIBKeyLo_EL1) |
| 179 | #define APIBKeyLo_EL1_op0 3 |
| 180 | #define APIBKeyLo_EL1_op1 0 |
| 181 | #define APIBKeyLo_EL1_CRn 2 |
| 182 | #define APIBKeyLo_EL1_CRm 1 |
| 183 | #define APIBKeyLo_EL1_op2 2 |
| 184 | |
| 185 | /* CCSIDR_EL1 - Cache Size ID Register */ |
| 186 | #define CCSIDR_NumSets_MASK 0x0FFFE000 |
| 187 | #define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 |
| 188 | #define CCSIDR_NumSets_SHIFT 13 |
| 189 | #define CCSIDR_NumSets64_SHIFT 32 |
| 190 | #define CCSIDR_Assoc_MASK 0x00001FF8 |
| 191 | #define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 |
| 192 | #define CCSIDR_Assoc_SHIFT 3 |
| 193 | #define CCSIDR_Assoc64_SHIFT 3 |
| 194 | #define CCSIDR_LineSize_MASK 0x7 |
| 195 | #define CCSIDR_NSETS(idr) \ |
| 196 | (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) |
| 197 | #define CCSIDR_ASSOC(idr) \ |
| 198 | (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) |
| 199 | #define CCSIDR_NSETS_64(idr) \ |
| 200 | (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) |
| 201 | #define CCSIDR_ASSOC_64(idr) \ |
| 202 | (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) |
| 203 | |
| 204 | /* CLIDR_EL1 - Cache level ID register */ |
| 205 | #define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ |
| 206 | #define CLIDR_CTYPE_IO 0x1 /* Instruction only */ |
| 207 | #define CLIDR_CTYPE_DO 0x2 /* Data only */ |
| 208 | #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ |
| 209 | #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ |
| 210 | |
| 211 | /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ |
| 212 | #define CNTKCTL_EL1_op0 3 |
| 213 | #define CNTKCTL_EL1_op1 0 |
| 214 | #define CNTKCTL_EL1_CRn 14 |
| 215 | #define CNTKCTL_EL1_CRm 1 |
| 216 | #define CNTKCTL_EL1_op2 0 |
| 217 | |
| 218 | /* CNTKCTL_EL12 - Counter-timer Kernel Control Register */ |
| 219 | #define CNTKCTL_EL12_op0 3 |
| 220 | #define CNTKCTL_EL12_op1 5 |
| 221 | #define CNTKCTL_EL12_CRn 14 |
| 222 | #define CNTKCTL_EL12_CRm 1 |
| 223 | #define CNTKCTL_EL12_op2 0 |
| 224 | |
| 225 | /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ |
| 226 | #define CNTP_CTL_EL0_op0 3 |
| 227 | #define CNTP_CTL_EL0_op1 3 |
| 228 | #define CNTP_CTL_EL0_CRn 14 |
| 229 | #define CNTP_CTL_EL0_CRm 2 |
| 230 | #define CNTP_CTL_EL0_op2 1 |
| 231 | #define CNTP_CTL_ENABLE (1 << 0) |
| 232 | #define CNTP_CTL_IMASK (1 << 1) |
| 233 | #define CNTP_CTL_ISTATUS (1 << 2) |
| 234 | |
| 235 | /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */ |
| 236 | #define CNTP_CVAL_EL0_op0 3 |
| 237 | #define CNTP_CVAL_EL0_op1 3 |
| 238 | #define CNTP_CVAL_EL0_CRn 14 |
| 239 | #define CNTP_CVAL_EL0_CRm 2 |
| 240 | #define CNTP_CVAL_EL0_op2 2 |
| 241 | |
| 242 | /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */ |
| 243 | #define CNTP_TVAL_EL0_op0 3 |
| 244 | #define CNTP_TVAL_EL0_op1 3 |
| 245 | #define CNTP_TVAL_EL0_CRn 14 |
| 246 | #define CNTP_TVAL_EL0_CRm 2 |
| 247 | #define CNTP_TVAL_EL0_op2 0 |
| 248 | |
| 249 | /* CNTPCT_EL0 - Counter-timer Physical Count register */ |
| 250 | #define CNTPCT_EL0_ISS ISS_MSR_REG(CNTPCT_EL0) |
| 251 | #define CNTPCT_EL0_op0 3 |
| 252 | #define CNTPCT_EL0_op1 3 |
| 253 | #define CNTPCT_EL0_CRn 14 |
| 254 | #define CNTPCT_EL0_CRm 0 |
| 255 | #define CNTPCT_EL0_op2 1 |
| 256 | |
| 257 | /* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */ |
| 258 | #define CNTV_CTL_EL0_op0 3 |
| 259 | #define CNTV_CTL_EL0_op1 3 |
| 260 | #define CNTV_CTL_EL0_CRn 14 |
| 261 | #define CNTV_CTL_EL0_CRm 3 |
| 262 | #define CNTV_CTL_EL0_op2 1 |
| 263 | |
| 264 | /* CNTV_CTL_EL02 - Counter-timer Virtual Timer Control register */ |
| 265 | #define CNTV_CTL_EL02_op0 3 |
| 266 | #define CNTV_CTL_EL02_op1 5 |
| 267 | #define CNTV_CTL_EL02_CRn 14 |
| 268 | #define CNTV_CTL_EL02_CRm 3 |
| 269 | #define CNTV_CTL_EL02_op2 1 |
| 270 | |
| 271 | /* CNTV_CVAL_EL0 - Counter-timer Virtual Timer CompareValue register */ |
| 272 | #define CNTV_CVAL_EL0_op0 3 |
| 273 | #define CNTV_CVAL_EL0_op1 3 |
| 274 | #define CNTV_CVAL_EL0_CRn 14 |
| 275 | #define CNTV_CVAL_EL0_CRm 3 |
| 276 | #define CNTV_CVAL_EL0_op2 2 |
| 277 | |
| 278 | /* CNTV_CVAL_EL02 - Counter-timer Virtual Timer CompareValue register */ |
| 279 | #define CNTV_CVAL_EL02_op0 3 |
| 280 | #define CNTV_CVAL_EL02_op1 5 |
| 281 | #define CNTV_CVAL_EL02_CRn 14 |
| 282 | #define CNTV_CVAL_EL02_CRm 3 |
| 283 | #define CNTV_CVAL_EL02_op2 2 |
| 284 | |
| 285 | /* CONTEXTIDR_EL1 - Context ID register */ |
| 286 | #define CONTEXTIDR_EL1_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL1) |
| 287 | #define CONTEXTIDR_EL1_op0 3 |
| 288 | #define CONTEXTIDR_EL1_op1 0 |
| 289 | #define CONTEXTIDR_EL1_CRn 13 |
| 290 | #define CONTEXTIDR_EL1_CRm 0 |
| 291 | #define CONTEXTIDR_EL1_op2 1 |
| 292 | |
| 293 | /* CONTEXTIDR_EL12 */ |
| 294 | #define CONTEXTIDR_EL12_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL12) |
| 295 | #define CONTEXTIDR_EL12_op0 3 |
| 296 | #define CONTEXTIDR_EL12_op1 5 |
| 297 | #define CONTEXTIDR_EL12_CRn 13 |
| 298 | #define CONTEXTIDR_EL12_CRm 0 |
| 299 | #define CONTEXTIDR_EL12_op2 1 |
| 300 | |
| 301 | /* CPACR_EL1 */ |
| 302 | #define CPACR_EL1_REG MRS_REG_ALT_NAME(CPACR_EL1) |
| 303 | #define CPACR_EL1_op0 3 |
| 304 | #define CPACR_EL1_op1 0 |
| 305 | #define CPACR_EL1_CRn 1 |
| 306 | #define CPACR_EL1_CRm 0 |
| 307 | #define CPACR_EL1_op2 2 |
| 308 | #define CPACR_ZEN_MASK (0x3 << 16) |
| 309 | #define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ |
| 310 | #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ |
| 311 | #define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ |
| 312 | #define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ |
| 313 | #define CPACR_FPEN_MASK (0x3 << 20) |
| 314 | #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ |
| 315 | #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ |
| 316 | #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ |
| 317 | #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ |
| 318 | #define CPACR_TTA (0x1 << 28) |
| 319 | |
| 320 | /* CPACR_EL12 */ |
| 321 | #define CPACR_EL12_REG MRS_REG_ALT_NAME(CPACR_EL12) |
| 322 | #define CPACR_EL12_op0 3 |
| 323 | #define CPACR_EL12_op1 5 |
| 324 | #define CPACR_EL12_CRn 1 |
| 325 | #define CPACR_EL12_CRm 0 |
| 326 | #define CPACR_EL12_op2 2 |
| 327 | |
| 328 | /* CSSELR_EL1 - Cache size selection register */ |
| 329 | #define CSSELR_Level(i) (i << 1) |
| 330 | #define CSSELR_InD 0x00000001 |
| 331 | |
| 332 | /* CTR_EL0 - Cache Type Register */ |
| 333 | #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0) |
| 334 | #define CTR_EL0_ISS ISS_MSR_REG(CTR_EL0) |
| 335 | #define CTR_EL0_op0 3 |
| 336 | #define CTR_EL0_op1 3 |
| 337 | #define CTR_EL0_CRn 0 |
| 338 | #define CTR_EL0_CRm 0 |
| 339 | #define CTR_EL0_op2 1 |
| 340 | #define CTR_RES1 (1 << 31) |
| 341 | #define CTR_TminLine_SHIFT 32 |
| 342 | #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) |
| 343 | #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) |
| 344 | #define CTR_DIC_SHIFT 29 |
| 345 | #define CTR_DIC_WIDTH 1 |
| 346 | #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) |
| 347 | #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) |
| 348 | #define CTR_DIC_NONE (0x0 << CTR_DIC_SHIFT) |
| 349 | #define CTR_DIC_IMPL (0x1 << CTR_DIC_SHIFT) |
| 350 | #define CTR_IDC_SHIFT 28 |
| 351 | #define CTR_IDC_WIDTH 1 |
| 352 | #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) |
| 353 | #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) |
| 354 | #define CTR_IDC_NONE (0x0 << CTR_IDC_SHIFT) |
| 355 | #define CTR_IDC_IMPL (0x1 << CTR_IDC_SHIFT) |
| 356 | #define CTR_CWG_SHIFT 24 |
| 357 | #define CTR_CWG_WIDTH 4 |
| 358 | #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) |
| 359 | #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) |
| 360 | #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) |
| 361 | #define CTR_ERG_SHIFT 20 |
| 362 | #define CTR_ERG_WIDTH 4 |
| 363 | #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) |
| 364 | #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) |
| 365 | #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) |
| 366 | #define CTR_DLINE_SHIFT 16 |
| 367 | #define CTR_DLINE_WIDTH 4 |
| 368 | #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) |
| 369 | #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) |
| 370 | #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) |
| 371 | #define CTR_L1IP_SHIFT 14 |
| 372 | #define CTR_L1IP_WIDTH 2 |
| 373 | #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) |
| 374 | #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) |
| 375 | #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) |
| 376 | #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) |
| 377 | #define CTR_ILINE_SHIFT 0 |
| 378 | #define CTR_ILINE_WIDTH 4 |
| 379 | #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) |
| 380 | #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) |
| 381 | #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) |
| 382 | |
| 383 | /* CurrentEL - Current Exception Level */ |
| 384 | #define CURRENTEL_EL_SHIFT 2 |
| 385 | #define CURRENTEL_EL_MASK (0x3 << CURRENTEL_EL_SHIFT) |
| 386 | #define CURRENTEL_EL_EL0 (0x0 << CURRENTEL_EL_SHIFT) |
| 387 | #define CURRENTEL_EL_EL1 (0x1 << CURRENTEL_EL_SHIFT) |
| 388 | #define CURRENTEL_EL_EL2 (0x2 << CURRENTEL_EL_SHIFT) |
| 389 | #define CURRENTEL_EL_EL3 (0x3 << CURRENTEL_EL_SHIFT) |
| 390 | |
| 391 | /* DAIFSet/DAIFClear */ |
| 392 | #define DAIF_D (1 << 3) |
| 393 | #define DAIF_A (1 << 2) |
| 394 | #define DAIF_I (1 << 1) |
| 395 | #define DAIF_F (1 << 0) |
| 396 | #define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) |
| 397 | #define DAIF_INTR (DAIF_I | DAIF_F) /* All exceptions that pass */ |
| 398 | /* through the intr framework */ |
| 399 | |
| 400 | /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */ |
| 401 | #define DBGBCR_EL1_op0 2 |
| 402 | #define DBGBCR_EL1_op1 0 |
| 403 | #define DBGBCR_EL1_CRn 0 |
| 404 | /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */ |
| 405 | #define DBGBCR_EL1_op2 5 |
| 406 | #define DBGBCR_EN 0x1 |
| 407 | #define DBGBCR_PMC_SHIFT 1 |
| 408 | #define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT) |
| 409 | #define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT) |
| 410 | #define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT) |
| 411 | #define DBGBCR_BAS_SHIFT 5 |
| 412 | #define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT) |
| 413 | #define DBGBCR_HMC_SHIFT 13 |
| 414 | #define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT) |
| 415 | #define DBGBCR_SSC_SHIFT 14 |
| 416 | #define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT) |
| 417 | #define DBGBCR_LBN_SHIFT 16 |
| 418 | #define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT) |
| 419 | #define DBGBCR_BT_SHIFT 20 |
| 420 | #define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT) |
| 421 | |
| 422 | /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */ |
| 423 | #define DBGBVR_EL1_op0 2 |
| 424 | #define DBGBVR_EL1_op1 0 |
| 425 | #define DBGBVR_EL1_CRn 0 |
| 426 | /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */ |
| 427 | #define DBGBVR_EL1_op2 4 |
| 428 | |
| 429 | /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */ |
| 430 | #define DBGWCR_EL1_op0 2 |
| 431 | #define DBGWCR_EL1_op1 0 |
| 432 | #define DBGWCR_EL1_CRn 0 |
| 433 | /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */ |
| 434 | #define DBGWCR_EL1_op2 7 |
| 435 | #define DBGWCR_EN 0x1 |
| 436 | #define DBGWCR_PAC_SHIFT 1 |
| 437 | #define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT) |
| 438 | #define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT) |
| 439 | #define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT) |
| 440 | #define DBGWCR_LSC_SHIFT 3 |
| 441 | #define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT) |
| 442 | #define DBGWCR_BAS_SHIFT 5 |
| 443 | #define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT) |
| 444 | #define DBGWCR_HMC_SHIFT 13 |
| 445 | #define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT) |
| 446 | #define DBGWCR_SSC_SHIFT 14 |
| 447 | #define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT) |
| 448 | #define DBGWCR_LBN_SHIFT 16 |
| 449 | #define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT) |
| 450 | #define DBGWCR_WT_SHIFT 20 |
| 451 | #define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT) |
| 452 | #define DBGWCR_MASK_SHIFT 24 |
| 453 | #define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT) |
| 454 | |
| 455 | /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */ |
| 456 | #define DBGWVR_EL1_op0 2 |
| 457 | #define DBGWVR_EL1_op1 0 |
| 458 | #define DBGWVR_EL1_CRn 0 |
| 459 | /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */ |
| 460 | #define DBGWVR_EL1_op2 6 |
| 461 | |
| 462 | /* DCZID_EL0 - Data Cache Zero ID register */ |
| 463 | #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ |
| 464 | #define DCZID_BS_SHIFT 0 |
| 465 | #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) |
| 466 | #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) |
| 467 | |
| 468 | /* DBGAUTHSTATUS_EL1 */ |
| 469 | #define DBGAUTHSTATUS_EL1_op0 2 |
| 470 | #define DBGAUTHSTATUS_EL1_op1 0 |
| 471 | #define DBGAUTHSTATUS_EL1_CRn 7 |
| 472 | #define DBGAUTHSTATUS_EL1_CRm 14 |
| 473 | #define DBGAUTHSTATUS_EL1_op2 6 |
| 474 | |
| 475 | /* DBGCLAIMCLR_EL1 */ |
| 476 | #define DBGCLAIMCLR_EL1_op0 2 |
| 477 | #define DBGCLAIMCLR_EL1_op1 0 |
| 478 | #define DBGCLAIMCLR_EL1_CRn 7 |
| 479 | #define DBGCLAIMCLR_EL1_CRm 9 |
| 480 | #define DBGCLAIMCLR_EL1_op2 6 |
| 481 | |
| 482 | /* DBGCLAIMSET_EL1 */ |
| 483 | #define DBGCLAIMSET_EL1_op0 2 |
| 484 | #define DBGCLAIMSET_EL1_op1 0 |
| 485 | #define DBGCLAIMSET_EL1_CRn 7 |
| 486 | #define DBGCLAIMSET_EL1_CRm 8 |
| 487 | #define DBGCLAIMSET_EL1_op2 6 |
| 488 | |
| 489 | /* DBGPRCR_EL1 */ |
| 490 | #define DBGPRCR_EL1_op0 2 |
| 491 | #define DBGPRCR_EL1_op1 0 |
| 492 | #define DBGPRCR_EL1_CRn 1 |
| 493 | #define DBGPRCR_EL1_CRm 4 |
| 494 | #define DBGPRCR_EL1_op2 4 |
| 495 | |
| 496 | /* ELR_EL1 */ |
| 497 | #define ELR_EL1_REG MRS_REG_ALT_NAME(ELR_EL1) |
| 498 | #define ELR_EL1_op0 3 |
| 499 | #define ELR_EL1_op1 0 |
| 500 | #define ELR_EL1_CRn 4 |
| 501 | #define ELR_EL1_CRm 0 |
| 502 | #define ELR_EL1_op2 1 |
| 503 | |
| 504 | /* ELR_EL12 */ |
| 505 | #define ELR_EL12_REG MRS_REG_ALT_NAME(ELR_EL12) |
| 506 | #define ELR_EL12_op0 3 |
| 507 | #define ELR_EL12_op1 5 |
| 508 | #define ELR_EL12_CRn 4 |
| 509 | #define ELR_EL12_CRm 0 |
| 510 | #define ELR_EL12_op2 1 |
| 511 | |
| 512 | /* ESR_ELx */ |
| 513 | #define ESR_ELx_ISS_MASK 0x01ffffff |
| 514 | #define ISS_FP_TFV_SHIFT 23 |
| 515 | #define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT) |
| 516 | #define ISS_FP_IOF 0x01 |
| 517 | #define ISS_FP_DZF 0x02 |
| 518 | #define ISS_FP_OFF 0x04 |
| 519 | #define ISS_FP_UFF 0x08 |
| 520 | #define ISS_FP_IXF 0x10 |
| 521 | #define ISS_FP_IDF 0x80 |
| 522 | #define ISS_INSN_FnV (0x01 << 10) |
| 523 | #define ISS_INSN_EA (0x01 << 9) |
| 524 | #define ISS_INSN_S1PTW (0x01 << 7) |
| 525 | #define ISS_INSN_IFSC_MASK (0x1f << 0) |
| 526 | |
| 527 | #define ISS_WFx_TI_SHIFT 0 |
| 528 | #define ISS_WFx_TI_MASK (0x03 << ISS_WFx_TI_SHIFT) |
| 529 | #define ISS_WFx_TI_WFI (0x00 << ISS_WFx_TI_SHIFT) |
| 530 | #define ISS_WFx_TI_WFE (0x01 << ISS_WFx_TI_SHIFT) |
| 531 | #define ISS_WFx_TI_WFIT (0x02 << ISS_WFx_TI_SHIFT) |
| 532 | #define ISS_WFx_TI_WFET (0x03 << ISS_WFx_TI_SHIFT) |
| 533 | #define ISS_WFx_RV_SHIFT 2 |
| 534 | #define ISS_WFx_RV_MASK (0x01 << ISS_WFx_RV_SHIFT) |
| 535 | #define ISS_WFx_RV_INVALID (0x00 << ISS_WFx_RV_SHIFT) |
| 536 | #define ISS_WFx_RV_VALID (0x01 << ISS_WFx_RV_SHIFT) |
| 537 | #define ISS_WFx_RN_SHIFT 5 |
| 538 | #define ISS_WFx_RN_MASK (0x1f << ISS_WFx_RN_SHIFT) |
| 539 | #define ISS_WFx_RN(x) (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT) |
| 540 | #define ISS_WFx_COND_SHIFT 20 |
| 541 | #define ISS_WFx_COND_MASK (0x0f << ISS_WFx_COND_SHIFT) |
| 542 | #define ISS_WFx_CV_SHIFT 24 |
| 543 | #define ISS_WFx_CV_MASK (0x01 << ISS_WFx_CV_SHIFT) |
| 544 | #define ISS_WFx_CV_INVALID (0x00 << ISS_WFx_CV_SHIFT) |
| 545 | #define ISS_WFx_CV_VALID (0x01 << ISS_WFx_CV_SHIFT) |
| 546 | |
| 547 | #define ISS_MSR_DIR_SHIFT 0 |
| 548 | #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) |
| 549 | #define ISS_MSR_Rt_SHIFT 5 |
| 550 | #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) |
| 551 | #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) |
| 552 | #define ISS_MSR_CRm_SHIFT 1 |
| 553 | #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) |
| 554 | #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) |
| 555 | #define ISS_MSR_CRn_SHIFT 10 |
| 556 | #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) |
| 557 | #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) |
| 558 | #define ISS_MSR_OP1_SHIFT 14 |
| 559 | #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) |
| 560 | #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) |
| 561 | #define ISS_MSR_OP2_SHIFT 17 |
| 562 | #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) |
| 563 | #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) |
| 564 | #define ISS_MSR_OP0_SHIFT 20 |
| 565 | #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) |
| 566 | #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) |
| 567 | #define ISS_MSR_REG_MASK \ |
| 568 | (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ |
| 569 | ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) |
| 570 | #define __ISS_MSR_REG(op0, op1, crn, crm, op2) \ |
| 571 | (((op0) << ISS_MSR_OP0_SHIFT) | \ |
| 572 | ((op1) << ISS_MSR_OP1_SHIFT) | \ |
| 573 | ((crn) << ISS_MSR_CRn_SHIFT) | \ |
| 574 | ((crm) << ISS_MSR_CRm_SHIFT) | \ |
| 575 | ((op2) << ISS_MSR_OP2_SHIFT)) |
| 576 | #define ISS_MSR_REG(reg) \ |
| 577 | __ISS_MSR_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) |
| 578 | |
| 579 | #define ISS_DATA_ISV_SHIFT 24 |
| 580 | #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) |
| 581 | #define ISS_DATA_SAS_SHIFT 22 |
| 582 | #define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) |
| 583 | #define ISS_DATA_SSE_SHIFT 21 |
| 584 | #define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) |
| 585 | #define ISS_DATA_SRT_SHIFT 16 |
| 586 | #define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) |
| 587 | #define ISS_DATA_SF (0x01 << 15) |
| 588 | #define ISS_DATA_AR (0x01 << 14) |
| 589 | #define ISS_DATA_FnV (0x01 << 10) |
| 590 | #define ISS_DATA_EA (0x01 << 9) |
| 591 | #define ISS_DATA_CM (0x01 << 8) |
| 592 | #define ISS_DATA_S1PTW (0x01 << 7) |
| 593 | #define ISS_DATA_WnR_SHIFT 6 |
| 594 | #define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) |
| 595 | #define ISS_DATA_DFSC_MASK (0x3f << 0) |
| 596 | #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) |
| 597 | #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) |
| 598 | #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) |
| 599 | #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) |
| 600 | #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) |
| 601 | #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) |
| 602 | #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) |
| 603 | #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) |
| 604 | #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) |
| 605 | #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) |
| 606 | #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) |
| 607 | #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) |
| 608 | #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) |
| 609 | #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) |
| 610 | #define ISS_DATA_DFSC_EXT (0x10 << 0) |
| 611 | #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) |
| 612 | #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) |
| 613 | #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) |
| 614 | #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) |
| 615 | #define ISS_DATA_DFSC_ECC (0x18 << 0) |
| 616 | #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) |
| 617 | #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) |
| 618 | #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) |
| 619 | #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) |
| 620 | #define ISS_DATA_DFSC_ALIGN (0x21 << 0) |
| 621 | #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) |
| 622 | #define ESR_ELx_IL (0x01 << 25) |
| 623 | #define ESR_ELx_EC_SHIFT 26 |
| 624 | #define ESR_ELx_EC_MASK (0x3f << 26) |
| 625 | #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) |
| 626 | #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ |
| 627 | #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ |
| 628 | #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ |
| 629 | #define EXCP_BTI 0x0d /* Branch Target Exception */ |
| 630 | #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ |
| 631 | #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ |
| 632 | #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ |
| 633 | #define EXCP_HVC 0x16 /* HVC trap */ |
| 634 | #define EXCP_MSR 0x18 /* MSR/MRS trap */ |
| 635 | #define EXCP_SVE 0x19 /* SVE trap */ |
| 636 | #define EXCP_FPAC 0x1c /* Faulting PAC trap */ |
| 637 | #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ |
| 638 | #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ |
| 639 | #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ |
| 640 | #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ |
| 641 | #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ |
| 642 | #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ |
| 643 | #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ |
| 644 | #define EXCP_SERROR 0x2f /* SError interrupt */ |
| 645 | #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ |
| 646 | #define EXCP_BRKPT_EL1 0x31 /* Hardware breakpoint, from same EL */ |
| 647 | #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ |
| 648 | #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ |
| 649 | #define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ |
| 650 | #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ |
| 651 | #define EXCP_BRKPT_32 0x38 /* 32bits breakpoint */ |
| 652 | #define EXCP_BRK 0x3c /* Breakpoint */ |
| 653 | |
| 654 | /* ESR_EL1 */ |
| 655 | #define ESR_EL1_REG MRS_REG_ALT_NAME(ESR_EL1) |
| 656 | #define ESR_EL1_op0 3 |
| 657 | #define ESR_EL1_op1 0 |
| 658 | #define ESR_EL1_CRn 5 |
| 659 | #define ESR_EL1_CRm 2 |
| 660 | #define ESR_EL1_op2 0 |
| 661 | |
| 662 | /* ESR_EL12 */ |
| 663 | #define ESR_EL12_REG MRS_REG_ALT_NAME(ESR_EL12) |
| 664 | #define ESR_EL12_op0 3 |
| 665 | #define ESR_EL12_op1 5 |
| 666 | #define ESR_EL12_CRn 5 |
| 667 | #define ESR_EL12_CRm 2 |
| 668 | #define ESR_EL12_op2 0 |
| 669 | |
| 670 | /* FAR_EL1 */ |
| 671 | #define FAR_EL1_REG MRS_REG_ALT_NAME(FAR_EL1) |
| 672 | #define FAR_EL1_op0 3 |
| 673 | #define FAR_EL1_op1 0 |
| 674 | #define FAR_EL1_CRn 6 |
| 675 | #define FAR_EL1_CRm 0 |
| 676 | #define FAR_EL1_op2 0 |
| 677 | |
| 678 | /* FAR_EL12 */ |
| 679 | #define FAR_EL12_REG MRS_REG_ALT_NAME(FAR_EL12) |
| 680 | #define FAR_EL12_op0 3 |
| 681 | #define FAR_EL12_op1 5 |
| 682 | #define FAR_EL12_CRn 6 |
| 683 | #define FAR_EL12_CRm 0 |
| 684 | #define FAR_EL12_op2 0 |
| 685 | |
| 686 | /* ICC_CTLR_EL1 */ |
| 687 | #define ICC_CTLR_EL1_EOIMODE (1U << 1) |
| 688 | |
| 689 | /* ICC_IAR1_EL1 */ |
| 690 | #define ICC_IAR1_EL1_SPUR (0x03ff) |
| 691 | |
| 692 | /* ICC_IGRPEN0_EL1 */ |
| 693 | #define ICC_IGRPEN0_EL1_EN (1U << 0) |
| 694 | |
| 695 | /* ICC_PMR_EL1 */ |
| 696 | #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) |
| 697 | |
| 698 | /* ICC_SGI1R_EL1 */ |
| 699 | #define ICC_SGI1R_EL1_op0 3 |
| 700 | #define ICC_SGI1R_EL1_op1 0 |
| 701 | #define ICC_SGI1R_EL1_CRn 12 |
| 702 | #define ICC_SGI1R_EL1_CRm 11 |
| 703 | #define ICC_SGI1R_EL1_op2 5 |
| 704 | #define ICC_SGI1R_EL1_TL_SHIFT 0 |
| 705 | #define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) |
| 706 | #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) |
| 707 | #define ICC_SGI1R_EL1_AFF1_SHIFT 16 |
| 708 | #define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) |
| 709 | #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) |
| 710 | #define ICC_SGI1R_EL1_SGIID_SHIFT 24 |
| 711 | #define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) |
| 712 | #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) |
| 713 | #define ICC_SGI1R_EL1_AFF2_SHIFT 32 |
| 714 | #define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) |
| 715 | #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) |
| 716 | #define ICC_SGI1R_EL1_RS_SHIFT 44 |
| 717 | #define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) |
| 718 | #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) |
| 719 | #define ICC_SGI1R_EL1_AFF3_SHIFT 48 |
| 720 | #define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) |
| 721 | #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) |
| 722 | #define ICC_SGI1R_EL1_IRM (0x1UL << 40) |
| 723 | |
| 724 | /* ICC_SRE_EL1 */ |
| 725 | #define ICC_SRE_EL1_SRE (1U << 0) |
| 726 | |
| 727 | /* ID_AA64AFR0_EL1 */ |
| 728 | #define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1) |
| 729 | #define ID_AA64AFR0_EL1_ISS ISS_MSR_REG(ID_AA64AFR0_EL1) |
| 730 | #define ID_AA64AFR0_EL1_op0 3 |
| 731 | #define ID_AA64AFR0_EL1_op1 0 |
| 732 | #define ID_AA64AFR0_EL1_CRn 0 |
| 733 | #define ID_AA64AFR0_EL1_CRm 5 |
| 734 | #define ID_AA64AFR0_EL1_op2 4 |
| 735 | |
| 736 | /* ID_AA64AFR1_EL1 */ |
| 737 | #define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1) |
| 738 | #define ID_AA64AFR1_EL1_ISS ISS_MSR_REG(ID_AA64AFR1_EL1) |
| 739 | #define ID_AA64AFR1_EL1_op0 3 |
| 740 | #define ID_AA64AFR1_EL1_op1 0 |
| 741 | #define ID_AA64AFR1_EL1_CRn 0 |
| 742 | #define ID_AA64AFR1_EL1_CRm 5 |
| 743 | #define ID_AA64AFR1_EL1_op2 5 |
| 744 | |
| 745 | /* ID_AA64DFR0_EL1 */ |
| 746 | #define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1) |
| 747 | #define ID_AA64DFR0_EL1_ISS ISS_MSR_REG(ID_AA64DFR0_EL1) |
| 748 | #define ID_AA64DFR0_EL1_op0 3 |
| 749 | #define ID_AA64DFR0_EL1_op1 0 |
| 750 | #define ID_AA64DFR0_EL1_CRn 0 |
| 751 | #define ID_AA64DFR0_EL1_CRm 5 |
| 752 | #define ID_AA64DFR0_EL1_op2 0 |
| 753 | #define ID_AA64DFR0_DebugVer_SHIFT 0 |
| 754 | #define ID_AA64DFR0_DebugVer_WIDTH 4 |
| 755 | #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) |
| 756 | #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) |
| 757 | #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) |
| 758 | #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) |
| 759 | #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) |
| 760 | #define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) |
| 761 | #define ID_AA64DFR0_DebugVer_8_8 (UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT) |
| 762 | #define ID_AA64DFR0_DebugVer_8_9 (UL(0xb) << ID_AA64DFR0_DebugVer_SHIFT) |
| 763 | #define ID_AA64DFR0_TraceVer_SHIFT 4 |
| 764 | #define ID_AA64DFR0_TraceVer_WIDTH 4 |
| 765 | #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) |
| 766 | #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) |
| 767 | #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) |
| 768 | #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) |
| 769 | #define ID_AA64DFR0_PMUVer_SHIFT 8 |
| 770 | #define ID_AA64DFR0_PMUVer_WIDTH 4 |
| 771 | #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) |
| 772 | #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) |
| 773 | #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) |
| 774 | #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) |
| 775 | #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) |
| 776 | #define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) |
| 777 | #define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) |
| 778 | #define ID_AA64DFR0_PMUVer_3_7 (UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT) |
| 779 | #define ID_AA64DFR0_PMUVer_3_8 (UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT) |
| 780 | #define ID_AA64DFR0_PMUVer_3_9 (UL(0x9) << ID_AA64DFR0_PMUVer_SHIFT) |
| 781 | #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) |
| 782 | #define ID_AA64DFR0_BRPs_SHIFT 12 |
| 783 | #define ID_AA64DFR0_BRPs_WIDTH 4 |
| 784 | #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) |
| 785 | #define ID_AA64DFR0_BRPs_VAL(x) \ |
| 786 | ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) |
| 787 | #define ID_AA64DFR0_PMSS_SHIFT 16 |
| 788 | #define ID_AA64DFR0_PMSS_WIDTH 4 |
| 789 | #define ID_AA64DFR0_PMSS_MASK (UL(0xf) << ID_AA64DFR0_PMSS_SHIFT) |
| 790 | #define ID_AA64DFR0_PMSS_VAL(x) ((x) & ID_AA64DFR0_PMSS_MASK) |
| 791 | #define ID_AA64DFR0_PMSS_NONE (UL(0x0) << ID_AA64DFR0_PMSS_SHIFT) |
| 792 | #define ID_AA64DFR0_PMSS_IMPL (UL(0x1) << ID_AA64DFR0_PMSS_SHIFT) |
| 793 | #define ID_AA64DFR0_WRPs_SHIFT 20 |
| 794 | #define ID_AA64DFR0_WRPs_WIDTH 4 |
| 795 | #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) |
| 796 | #define ID_AA64DFR0_WRPs_VAL(x) \ |
| 797 | ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) |
| 798 | #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 |
| 799 | #define ID_AA64DFR0_CTX_CMPs_WIDTH 4 |
| 800 | #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) |
| 801 | #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ |
| 802 | ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) |
| 803 | #define ID_AA64DFR0_PMSVer_SHIFT 32 |
| 804 | #define ID_AA64DFR0_PMSVer_WIDTH 4 |
| 805 | #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) |
| 806 | #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) |
| 807 | #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) |
| 808 | #define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) |
| 809 | #define ID_AA64DFR0_PMSVer_SPE_1_1 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) |
| 810 | #define ID_AA64DFR0_PMSVer_SPE_1_2 (UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT) |
| 811 | #define ID_AA64DFR0_PMSVer_SPE_1_3 (UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT) |
| 812 | #define ID_AA64DFR0_PMSVer_SPE_1_4 (UL(0x5) << ID_AA64DFR0_PMSVer_SHIFT) |
| 813 | #define ID_AA64DFR0_DoubleLock_SHIFT 36 |
| 814 | #define ID_AA64DFR0_DoubleLock_WIDTH 4 |
| 815 | #define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) |
| 816 | #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) |
| 817 | #define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) |
| 818 | #define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) |
| 819 | #define ID_AA64DFR0_TraceFilt_SHIFT 40 |
| 820 | #define ID_AA64DFR0_TraceFilt_WIDTH 4 |
| 821 | #define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) |
| 822 | #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) |
| 823 | #define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) |
| 824 | #define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) |
| 825 | #define ID_AA64DFR0_TraceBuffer_SHIFT 44 |
| 826 | #define ID_AA64DFR0_TraceBuffer_WIDTH 4 |
| 827 | #define ID_AA64DFR0_TraceBuffer_MASK (UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT) |
| 828 | #define ID_AA64DFR0_TraceBuffer_VAL(x) ((x) & ID_AA64DFR0_TraceBuffer_MASK) |
| 829 | #define ID_AA64DFR0_TraceBuffer_NONE (UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT) |
| 830 | #define ID_AA64DFR0_TraceBuffer_IMPL (UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT) |
| 831 | #define ID_AA64DFR0_MTPMU_SHIFT 48 |
| 832 | #define ID_AA64DFR0_MTPMU_WIDTH 4 |
| 833 | #define ID_AA64DFR0_MTPMU_MASK (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) |
| 834 | #define ID_AA64DFR0_MTPMU_VAL(x) ((x) & ID_AA64DFR0_MTPMU_MASK) |
| 835 | #define ID_AA64DFR0_MTPMU_NONE (UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT) |
| 836 | #define ID_AA64DFR0_MTPMU_IMPL (UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT) |
| 837 | #define ID_AA64DFR0_MTPMU_NONE_MT_RES0 (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) |
| 838 | #define ID_AA64DFR0_BRBE_SHIFT 52 |
| 839 | #define ID_AA64DFR0_BRBE_WIDTH 4 |
| 840 | #define ID_AA64DFR0_BRBE_MASK (UL(0xf) << ID_AA64DFR0_BRBE_SHIFT) |
| 841 | #define ID_AA64DFR0_BRBE_VAL(x) ((x) & ID_AA64DFR0_BRBE_MASK) |
| 842 | #define ID_AA64DFR0_BRBE_NONE (UL(0x0) << ID_AA64DFR0_BRBE_SHIFT) |
| 843 | #define ID_AA64DFR0_BRBE_IMPL (UL(0x1) << ID_AA64DFR0_BRBE_SHIFT) |
| 844 | #define ID_AA64DFR0_BRBE_EL3 (UL(0x2) << ID_AA64DFR0_BRBE_SHIFT) |
| 845 | #define ID_AA64DFR0_HPMN0_SHIFT 60 |
| 846 | #define ID_AA64DFR0_HPMN0_WIDTH 4 |
| 847 | #define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT) |
| 848 | #define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK) |
| 849 | #define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT) |
| 850 | #define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT) |
| 851 | |
| 852 | /* ID_AA64DFR1_EL1 */ |
| 853 | #define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1) |
| 854 | #define ID_AA64DFR1_EL1_ISS ISS_MSR_REG(ID_AA64DFR1_EL1) |
| 855 | #define ID_AA64DFR1_EL1_op0 3 |
| 856 | #define ID_AA64DFR1_EL1_op1 0 |
| 857 | #define ID_AA64DFR1_EL1_CRn 0 |
| 858 | #define ID_AA64DFR1_EL1_CRm 5 |
| 859 | #define ID_AA64DFR1_EL1_op2 1 |
| 860 | #define ID_AA64DFR1_SPMU_SHIFT 32 |
| 861 | #define ID_AA64DFR1_SPMU_WIDTH 4 |
| 862 | #define ID_AA64DFR1_SPMU_MASK (UL(0xf) << ID_AA64DFR1_SPMU_SHIFT) |
| 863 | #define ID_AA64DFR1_SPMU_VAL(x) ((x) & ID_AA64DFR1_SPMU_MASK) |
| 864 | #define ID_AA64DFR1_SPMU_NONE (UL(0x0) << ID_AA64DFR1_SPMU_SHIFT) |
| 865 | #define ID_AA64DFR1_SPMU_IMPL (UL(0x1) << ID_AA64DFR1_SPMU_SHIFT) |
| 866 | #define ID_AA64DFR1_PMICNTR_SHIFT 36 |
| 867 | #define ID_AA64DFR1_PMICNTR_WIDTH 4 |
| 868 | #define ID_AA64DFR1_PMICNTR_MASK (UL(0xf) << ID_AA64DFR1_PMICNTR_SHIFT) |
| 869 | #define ID_AA64DFR1_PMICNTR_VAL(x) ((x) & ID_AA64DFR1_PMICNTR_MASK) |
| 870 | #define ID_AA64DFR1_PMICNTR_NONE (UL(0x0) << ID_AA64DFR1_PMICNTR_SHIFT) |
| 871 | #define ID_AA64DFR1_PMICNTR_IMPL (UL(0x1) << ID_AA64DFR1_PMICNTR_SHIFT) |
| 872 | #define ID_AA64DFR1_DPFZS_SHIFT 52 |
| 873 | #define ID_AA64DFR1_DPFZS_WIDTH 4 |
| 874 | #define ID_AA64DFR1_DPFZS_MASK (UL(0xf) << ID_AA64DFR1_DPFZS_SHIFT) |
| 875 | #define ID_AA64DFR1_DPFZS_VAL(x) ((x) & ID_AA64DFR1_DPFZS_MASK) |
| 876 | #define ID_AA64DFR1_DPFZS_NONE (UL(0x0) << ID_AA64DFR1_DPFZS_SHIFT) |
| 877 | #define ID_AA64DFR1_DPFZS_IMPL (UL(0x1) << ID_AA64DFR1_DPFZS_SHIFT) |
| 878 | |
| 879 | /* ID_AA64ISAR0_EL1 */ |
| 880 | #define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) |
| 881 | #define ID_AA64ISAR0_EL1_ISS ISS_MSR_REG(ID_AA64ISAR0_EL1) |
| 882 | #define ID_AA64ISAR0_EL1_op0 3 |
| 883 | #define ID_AA64ISAR0_EL1_op1 0 |
| 884 | #define ID_AA64ISAR0_EL1_CRn 0 |
| 885 | #define ID_AA64ISAR0_EL1_CRm 6 |
| 886 | #define ID_AA64ISAR0_EL1_op2 0 |
| 887 | #define ID_AA64ISAR0_AES_SHIFT 4 |
| 888 | #define ID_AA64ISAR0_AES_WIDTH 4 |
| 889 | #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) |
| 890 | #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) |
| 891 | #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) |
| 892 | #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) |
| 893 | #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) |
| 894 | #define ID_AA64ISAR0_SHA1_SHIFT 8 |
| 895 | #define ID_AA64ISAR0_SHA1_WIDTH 4 |
| 896 | #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) |
| 897 | #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) |
| 898 | #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) |
| 899 | #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) |
| 900 | #define ID_AA64ISAR0_SHA2_SHIFT 12 |
| 901 | #define ID_AA64ISAR0_SHA2_WIDTH 4 |
| 902 | #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) |
| 903 | #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) |
| 904 | #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) |
| 905 | #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) |
| 906 | #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) |
| 907 | #define ID_AA64ISAR0_CRC32_SHIFT 16 |
| 908 | #define ID_AA64ISAR0_CRC32_WIDTH 4 |
| 909 | #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) |
| 910 | #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) |
| 911 | #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) |
| 912 | #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) |
| 913 | #define ID_AA64ISAR0_Atomic_SHIFT 20 |
| 914 | #define ID_AA64ISAR0_Atomic_WIDTH 4 |
| 915 | #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) |
| 916 | #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) |
| 917 | #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) |
| 918 | #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) |
| 919 | #define ID_AA64ISAR0_TME_SHIFT 24 |
| 920 | #define ID_AA64ISAR0_TME_WIDTH 4 |
| 921 | #define ID_AA64ISAR0_TME_MASK (UL(0xf) << ID_AA64ISAR0_TME_SHIFT) |
| 922 | #define ID_AA64ISAR0_TME_NONE (UL(0x0) << ID_AA64ISAR0_TME_SHIFT) |
| 923 | #define ID_AA64ISAR0_TME_IMPL (UL(0x1) << ID_AA64ISAR0_TME_SHIFT) |
| 924 | #define ID_AA64ISAR0_RDM_SHIFT 28 |
| 925 | #define ID_AA64ISAR0_RDM_WIDTH 4 |
| 926 | #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) |
| 927 | #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) |
| 928 | #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) |
| 929 | #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) |
| 930 | #define ID_AA64ISAR0_SHA3_SHIFT 32 |
| 931 | #define ID_AA64ISAR0_SHA3_WIDTH 4 |
| 932 | #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) |
| 933 | #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) |
| 934 | #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) |
| 935 | #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) |
| 936 | #define ID_AA64ISAR0_SM3_SHIFT 36 |
| 937 | #define ID_AA64ISAR0_SM3_WIDTH 4 |
| 938 | #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) |
| 939 | #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) |
| 940 | #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) |
| 941 | #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) |
| 942 | #define ID_AA64ISAR0_SM4_SHIFT 40 |
| 943 | #define ID_AA64ISAR0_SM4_WIDTH 4 |
| 944 | #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) |
| 945 | #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) |
| 946 | #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) |
| 947 | #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) |
| 948 | #define ID_AA64ISAR0_DP_SHIFT 44 |
| 949 | #define ID_AA64ISAR0_DP_WIDTH 4 |
| 950 | #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) |
| 951 | #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) |
| 952 | #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) |
| 953 | #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) |
| 954 | #define ID_AA64ISAR0_FHM_SHIFT 48 |
| 955 | #define ID_AA64ISAR0_FHM_WIDTH 4 |
| 956 | #define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) |
| 957 | #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) |
| 958 | #define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) |
| 959 | #define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) |
| 960 | #define ID_AA64ISAR0_TS_SHIFT 52 |
| 961 | #define ID_AA64ISAR0_TS_WIDTH 4 |
| 962 | #define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) |
| 963 | #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) |
| 964 | #define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) |
| 965 | #define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) |
| 966 | #define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) |
| 967 | #define ID_AA64ISAR0_TLB_SHIFT 56 |
| 968 | #define ID_AA64ISAR0_TLB_WIDTH 4 |
| 969 | #define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) |
| 970 | #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) |
| 971 | #define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) |
| 972 | #define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) |
| 973 | #define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) |
| 974 | #define ID_AA64ISAR0_RNDR_SHIFT 60 |
| 975 | #define ID_AA64ISAR0_RNDR_WIDTH 4 |
| 976 | #define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) |
| 977 | #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) |
| 978 | #define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) |
| 979 | #define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) |
| 980 | |
| 981 | /* ID_AA64ISAR1_EL1 */ |
| 982 | #define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1) |
| 983 | #define ID_AA64ISAR1_EL1_ISS ISS_MSR_REG(ID_AA64ISAR1_EL1) |
| 984 | #define ID_AA64ISAR1_EL1_op0 3 |
| 985 | #define ID_AA64ISAR1_EL1_op1 0 |
| 986 | #define ID_AA64ISAR1_EL1_CRn 0 |
| 987 | #define ID_AA64ISAR1_EL1_CRm 6 |
| 988 | #define ID_AA64ISAR1_EL1_op2 1 |
| 989 | #define ID_AA64ISAR1_DPB_SHIFT 0 |
| 990 | #define ID_AA64ISAR1_DPB_WIDTH 4 |
| 991 | #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) |
| 992 | #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) |
| 993 | #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) |
| 994 | #define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) |
| 995 | #define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) |
| 996 | #define ID_AA64ISAR1_APA_SHIFT 4 |
| 997 | #define ID_AA64ISAR1_APA_WIDTH 4 |
| 998 | #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) |
| 999 | #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) |
| 1000 | #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) |
| 1001 | #define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) |
| 1002 | #define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) |
| 1003 | #define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT) |
| 1004 | #define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT) |
| 1005 | #define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT) |
| 1006 | #define ID_AA64ISAR1_API_SHIFT 8 |
| 1007 | #define ID_AA64ISAR1_API_WIDTH 4 |
| 1008 | #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) |
| 1009 | #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) |
| 1010 | #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) |
| 1011 | #define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) |
| 1012 | #define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) |
| 1013 | #define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT) |
| 1014 | #define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT) |
| 1015 | #define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT) |
| 1016 | #define ID_AA64ISAR1_JSCVT_SHIFT 12 |
| 1017 | #define ID_AA64ISAR1_JSCVT_WIDTH 4 |
| 1018 | #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) |
| 1019 | #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) |
| 1020 | #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) |
| 1021 | #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) |
| 1022 | #define ID_AA64ISAR1_FCMA_SHIFT 16 |
| 1023 | #define ID_AA64ISAR1_FCMA_WIDTH 4 |
| 1024 | #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) |
| 1025 | #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) |
| 1026 | #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) |
| 1027 | #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) |
| 1028 | #define ID_AA64ISAR1_LRCPC_SHIFT 20 |
| 1029 | #define ID_AA64ISAR1_LRCPC_WIDTH 4 |
| 1030 | #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) |
| 1031 | #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) |
| 1032 | #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) |
| 1033 | #define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) |
| 1034 | #define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) |
| 1035 | #define ID_AA64ISAR1_GPA_SHIFT 24 |
| 1036 | #define ID_AA64ISAR1_GPA_WIDTH 4 |
| 1037 | #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) |
| 1038 | #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) |
| 1039 | #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) |
| 1040 | #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) |
| 1041 | #define ID_AA64ISAR1_GPI_SHIFT 28 |
| 1042 | #define ID_AA64ISAR1_GPI_WIDTH 4 |
| 1043 | #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) |
| 1044 | #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) |
| 1045 | #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) |
| 1046 | #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) |
| 1047 | #define ID_AA64ISAR1_FRINTTS_SHIFT 32 |
| 1048 | #define ID_AA64ISAR1_FRINTTS_WIDTH 4 |
| 1049 | #define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 1050 | #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) |
| 1051 | #define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 1052 | #define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 1053 | #define ID_AA64ISAR1_SB_SHIFT 36 |
| 1054 | #define ID_AA64ISAR1_SB_WIDTH 4 |
| 1055 | #define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) |
| 1056 | #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) |
| 1057 | #define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) |
| 1058 | #define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) |
| 1059 | #define ID_AA64ISAR1_SPECRES_SHIFT 40 |
| 1060 | #define ID_AA64ISAR1_SPECRES_WIDTH 4 |
| 1061 | #define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) |
| 1062 | #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) |
| 1063 | #define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) |
| 1064 | #define ID_AA64ISAR1_SPECRES_8_5 (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) |
| 1065 | #define ID_AA64ISAR1_SPECRES_8_9 (UL(0x2) << ID_AA64ISAR1_SPECRES_SHIFT) |
| 1066 | #define ID_AA64ISAR1_BF16_SHIFT 44 |
| 1067 | #define ID_AA64ISAR1_BF16_WIDTH 4 |
| 1068 | #define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) |
| 1069 | #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) |
| 1070 | #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) |
| 1071 | #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) |
| 1072 | #define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT) |
| 1073 | #define ID_AA64ISAR1_DGH_SHIFT 48 |
| 1074 | #define ID_AA64ISAR1_DGH_WIDTH 4 |
| 1075 | #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) |
| 1076 | #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) |
| 1077 | #define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) |
| 1078 | #define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) |
| 1079 | #define ID_AA64ISAR1_I8MM_SHIFT 52 |
| 1080 | #define ID_AA64ISAR1_I8MM_WIDTH 4 |
| 1081 | #define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) |
| 1082 | #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) |
| 1083 | #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) |
| 1084 | #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) |
| 1085 | #define ID_AA64ISAR1_XS_SHIFT 56 |
| 1086 | #define ID_AA64ISAR1_XS_WIDTH 4 |
| 1087 | #define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT) |
| 1088 | #define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) |
| 1089 | #define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT) |
| 1090 | #define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT) |
| 1091 | #define ID_AA64ISAR1_LS64_SHIFT 60 |
| 1092 | #define ID_AA64ISAR1_LS64_WIDTH 4 |
| 1093 | #define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT) |
| 1094 | #define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) |
| 1095 | #define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT) |
| 1096 | #define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT) |
| 1097 | #define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT) |
| 1098 | #define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT) |
| 1099 | |
| 1100 | /* ID_AA64ISAR2_EL1 */ |
| 1101 | #define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1) |
| 1102 | #define ID_AA64ISAR2_EL1_ISS ISS_MSR_REG(ID_AA64ISAR2_EL1) |
| 1103 | #define ID_AA64ISAR2_EL1_op0 3 |
| 1104 | #define ID_AA64ISAR2_EL1_op1 0 |
| 1105 | #define ID_AA64ISAR2_EL1_CRn 0 |
| 1106 | #define ID_AA64ISAR2_EL1_CRm 6 |
| 1107 | #define ID_AA64ISAR2_EL1_op2 2 |
| 1108 | #define ID_AA64ISAR2_WFxT_SHIFT 0 |
| 1109 | #define ID_AA64ISAR2_WFxT_WIDTH 4 |
| 1110 | #define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) |
| 1111 | #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) |
| 1112 | #define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) |
| 1113 | #define ID_AA64ISAR2_WFxT_IMPL (UL(0x2) << ID_AA64ISAR2_WFxT_SHIFT) |
| 1114 | #define ID_AA64ISAR2_RPRES_SHIFT 4 |
| 1115 | #define ID_AA64ISAR2_RPRES_WIDTH 4 |
| 1116 | #define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) |
| 1117 | #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) |
| 1118 | #define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) |
| 1119 | #define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) |
| 1120 | #define ID_AA64ISAR2_GPA3_SHIFT 8 |
| 1121 | #define ID_AA64ISAR2_GPA3_WIDTH 4 |
| 1122 | #define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) |
| 1123 | #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) |
| 1124 | #define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) |
| 1125 | #define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) |
| 1126 | #define ID_AA64ISAR2_APA3_SHIFT 12 |
| 1127 | #define ID_AA64ISAR2_APA3_WIDTH 4 |
| 1128 | #define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) |
| 1129 | #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) |
| 1130 | #define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) |
| 1131 | #define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) |
| 1132 | #define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) |
| 1133 | #define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) |
| 1134 | #define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) |
| 1135 | #define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) |
| 1136 | #define ID_AA64ISAR2_MOPS_SHIFT 16 |
| 1137 | #define ID_AA64ISAR2_MOPS_WIDTH 4 |
| 1138 | #define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) |
| 1139 | #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) |
| 1140 | #define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) |
| 1141 | #define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) |
| 1142 | #define ID_AA64ISAR2_BC_SHIFT 20 |
| 1143 | #define ID_AA64ISAR2_BC_WIDTH 4 |
| 1144 | #define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) |
| 1145 | #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) |
| 1146 | #define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) |
| 1147 | #define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) |
| 1148 | #define ID_AA64ISAR2_PAC_frac_SHIFT 24 |
| 1149 | #define ID_AA64ISAR2_PAC_frac_WIDTH 4 |
| 1150 | #define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) |
| 1151 | #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) |
| 1152 | #define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) |
| 1153 | #define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) |
| 1154 | #define ID_AA64ISAR2_CLRBHB_SHIFT 28 |
| 1155 | #define ID_AA64ISAR2_CLRBHB_WIDTH 4 |
| 1156 | #define ID_AA64ISAR2_CLRBHB_MASK (UL(0xf) << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 1157 | #define ID_AA64ISAR2_CLRBHB_VAL(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) |
| 1158 | #define ID_AA64ISAR2_CLRBHB_NONE (UL(0x0) << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 1159 | #define ID_AA64ISAR2_CLRBHB_IMPL (UL(0x1) << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 1160 | #define ID_AA64ISAR2_PRFMSLC_SHIFT 40 |
| 1161 | #define ID_AA64ISAR2_PRFMSLC_WIDTH 4 |
| 1162 | #define ID_AA64ISAR2_PRFMSLC_MASK (UL(0xf) << ID_AA64ISAR2_PRFMSLC_SHIFT) |
| 1163 | #define ID_AA64ISAR2_PRFMSLC_VAL(x) ((x) & ID_AA64ISAR2_PRFMSLC_MASK) |
| 1164 | #define ID_AA64ISAR2_PRFMSLC_NONE (UL(0x0) << ID_AA64ISAR2_PRFMSLC_SHIFT) |
| 1165 | #define ID_AA64ISAR2_PRFMSLC_IMPL (UL(0x1) << ID_AA64ISAR2_PRFMSLC_SHIFT) |
| 1166 | #define ID_AA64ISAR2_RPRFM_SHIFT 48 |
| 1167 | #define ID_AA64ISAR2_RPRFM_WIDTH 4 |
| 1168 | #define ID_AA64ISAR2_RPRFM_MASK (UL(0xf) << ID_AA64ISAR2_RPRFM_SHIFT) |
| 1169 | #define ID_AA64ISAR2_RPRFM_VAL(x) ((x) & ID_AA64ISAR2_RPRFM_MASK) |
| 1170 | #define ID_AA64ISAR2_RPRFM_NONE (UL(0x0) << ID_AA64ISAR2_RPRFM_SHIFT) |
| 1171 | #define ID_AA64ISAR2_RPRFM_IMPL (UL(0x1) << ID_AA64ISAR2_RPRFM_SHIFT) |
| 1172 | #define ID_AA64ISAR2_CSSC_SHIFT 52 |
| 1173 | #define ID_AA64ISAR2_CSSC_WIDTH 4 |
| 1174 | #define ID_AA64ISAR2_CSSC_MASK (UL(0xf) << ID_AA64ISAR2_CSSC_SHIFT) |
| 1175 | #define ID_AA64ISAR2_CSSC_VAL(x) ((x) & ID_AA64ISAR2_CSSC_MASK) |
| 1176 | #define ID_AA64ISAR2_CSSC_NONE (UL(0x0) << ID_AA64ISAR2_CSSC_SHIFT) |
| 1177 | #define ID_AA64ISAR2_CSSC_IMPL (UL(0x1) << ID_AA64ISAR2_CSSC_SHIFT) |
| 1178 | #define ID_AA64ISAR2_ATS1A_SHIFT 60 |
| 1179 | #define ID_AA64ISAR2_ATS1A_WIDTH 4 |
| 1180 | #define ID_AA64ISAR2_ATS1A_MASK (UL(0xf) << ID_AA64ISAR2_ATS1A_SHIFT) |
| 1181 | #define ID_AA64ISAR2_ATS1A_VAL(x) ((x) & ID_AA64ISAR2_ATS1A_MASK) |
| 1182 | #define ID_AA64ISAR2_ATS1A_NONE (UL(0x0) << ID_AA64ISAR2_ATS1A_SHIFT) |
| 1183 | #define ID_AA64ISAR2_ATS1A_IMPL (UL(0x1) << ID_AA64ISAR2_ATS1A_SHIFT) |
| 1184 | |
| 1185 | /* ID_AA64MMFR0_EL1 */ |
| 1186 | #define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) |
| 1187 | #define ID_AA64MMFR0_EL1_ISS ISS_MSR_REG(ID_AA64MMFR0_EL1) |
| 1188 | #define ID_AA64MMFR0_EL1_op0 3 |
| 1189 | #define ID_AA64MMFR0_EL1_op1 0 |
| 1190 | #define ID_AA64MMFR0_EL1_CRn 0 |
| 1191 | #define ID_AA64MMFR0_EL1_CRm 7 |
| 1192 | #define ID_AA64MMFR0_EL1_op2 0 |
| 1193 | #define ID_AA64MMFR0_PARange_SHIFT 0 |
| 1194 | #define ID_AA64MMFR0_PARange_WIDTH 4 |
| 1195 | #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) |
| 1196 | #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) |
| 1197 | #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) |
| 1198 | #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) |
| 1199 | #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) |
| 1200 | #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) |
| 1201 | #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) |
| 1202 | #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) |
| 1203 | #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) |
| 1204 | #define ID_AA64MMFR0_ASIDBits_SHIFT 4 |
| 1205 | #define ID_AA64MMFR0_ASIDBits_WIDTH 4 |
| 1206 | #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) |
| 1207 | #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) |
| 1208 | #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) |
| 1209 | #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) |
| 1210 | #define ID_AA64MMFR0_BigEnd_SHIFT 8 |
| 1211 | #define ID_AA64MMFR0_BigEnd_WIDTH 4 |
| 1212 | #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) |
| 1213 | #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) |
| 1214 | #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) |
| 1215 | #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) |
| 1216 | #define ID_AA64MMFR0_SNSMem_SHIFT 12 |
| 1217 | #define ID_AA64MMFR0_SNSMem_WIDTH 4 |
| 1218 | #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) |
| 1219 | #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) |
| 1220 | #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) |
| 1221 | #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) |
| 1222 | #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 |
| 1223 | #define ID_AA64MMFR0_BigEndEL0_WIDTH 4 |
| 1224 | #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) |
| 1225 | #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) |
| 1226 | #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) |
| 1227 | #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) |
| 1228 | #define ID_AA64MMFR0_TGran16_SHIFT 20 |
| 1229 | #define ID_AA64MMFR0_TGran16_WIDTH 4 |
| 1230 | #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) |
| 1231 | #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) |
| 1232 | #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) |
| 1233 | #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) |
| 1234 | #define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT) |
| 1235 | #define ID_AA64MMFR0_TGran64_SHIFT 24 |
| 1236 | #define ID_AA64MMFR0_TGran64_WIDTH 4 |
| 1237 | #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) |
| 1238 | #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) |
| 1239 | #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) |
| 1240 | #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) |
| 1241 | #define ID_AA64MMFR0_TGran4_SHIFT 28 |
| 1242 | #define ID_AA64MMFR0_TGran4_WIDTH 4 |
| 1243 | #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) |
| 1244 | #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) |
| 1245 | #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) |
| 1246 | #define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT) |
| 1247 | #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) |
| 1248 | #define ID_AA64MMFR0_TGran16_2_SHIFT 32 |
| 1249 | #define ID_AA64MMFR0_TGran16_2_WIDTH 4 |
| 1250 | #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) |
| 1251 | #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) |
| 1252 | #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) |
| 1253 | #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) |
| 1254 | #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) |
| 1255 | #define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT) |
| 1256 | #define ID_AA64MMFR0_TGran64_2_SHIFT 36 |
| 1257 | #define ID_AA64MMFR0_TGran64_2_WIDTH 4 |
| 1258 | #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) |
| 1259 | #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) |
| 1260 | #define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) |
| 1261 | #define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) |
| 1262 | #define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) |
| 1263 | #define ID_AA64MMFR0_TGran4_2_SHIFT 40 |
| 1264 | #define ID_AA64MMFR0_TGran4_2_WIDTH 4 |
| 1265 | #define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) |
| 1266 | #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) |
| 1267 | #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) |
| 1268 | #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) |
| 1269 | #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) |
| 1270 | #define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT) |
| 1271 | #define ID_AA64MMFR0_ExS_SHIFT 44 |
| 1272 | #define ID_AA64MMFR0_ExS_WIDTH 4 |
| 1273 | #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) |
| 1274 | #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) |
| 1275 | #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) |
| 1276 | #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) |
| 1277 | #define ID_AA64MMFR0_FGT_SHIFT 56 |
| 1278 | #define ID_AA64MMFR0_FGT_WIDTH 4 |
| 1279 | #define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT) |
| 1280 | #define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) |
| 1281 | #define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT) |
| 1282 | #define ID_AA64MMFR0_FGT_8_6 (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT) |
| 1283 | #define ID_AA64MMFR0_FGT_8_9 (UL(0x2) << ID_AA64MMFR0_FGT_SHIFT) |
| 1284 | #define ID_AA64MMFR0_ECV_SHIFT 60 |
| 1285 | #define ID_AA64MMFR0_ECV_WIDTH 4 |
| 1286 | #define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT) |
| 1287 | #define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) |
| 1288 | #define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT) |
| 1289 | #define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT) |
| 1290 | #define ID_AA64MMFR0_ECV_POFF (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT) |
| 1291 | |
| 1292 | /* ID_AA64MMFR1_EL1 */ |
| 1293 | #define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1) |
| 1294 | #define ID_AA64MMFR1_EL1_ISS ISS_MSR_REG(ID_AA64MMFR1_EL1) |
| 1295 | #define ID_AA64MMFR1_EL1_op0 3 |
| 1296 | #define ID_AA64MMFR1_EL1_op1 0 |
| 1297 | #define ID_AA64MMFR1_EL1_CRn 0 |
| 1298 | #define ID_AA64MMFR1_EL1_CRm 7 |
| 1299 | #define ID_AA64MMFR1_EL1_op2 1 |
| 1300 | #define ID_AA64MMFR1_HAFDBS_SHIFT 0 |
| 1301 | #define ID_AA64MMFR1_HAFDBS_WIDTH 4 |
| 1302 | #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 1303 | #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) |
| 1304 | #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 1305 | #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 1306 | #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 1307 | #define ID_AA64MMFR1_VMIDBits_SHIFT 4 |
| 1308 | #define ID_AA64MMFR1_VMIDBits_WIDTH 4 |
| 1309 | #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) |
| 1310 | #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) |
| 1311 | #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) |
| 1312 | #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) |
| 1313 | #define ID_AA64MMFR1_VH_SHIFT 8 |
| 1314 | #define ID_AA64MMFR1_VH_WIDTH 4 |
| 1315 | #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) |
| 1316 | #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) |
| 1317 | #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) |
| 1318 | #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) |
| 1319 | #define ID_AA64MMFR1_HPDS_SHIFT 12 |
| 1320 | #define ID_AA64MMFR1_HPDS_WIDTH 4 |
| 1321 | #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) |
| 1322 | #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) |
| 1323 | #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) |
| 1324 | #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) |
| 1325 | #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) |
| 1326 | #define ID_AA64MMFR1_LO_SHIFT 16 |
| 1327 | #define ID_AA64MMFR1_LO_WIDTH 4 |
| 1328 | #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) |
| 1329 | #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) |
| 1330 | #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) |
| 1331 | #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) |
| 1332 | #define ID_AA64MMFR1_PAN_SHIFT 20 |
| 1333 | #define ID_AA64MMFR1_PAN_WIDTH 4 |
| 1334 | #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) |
| 1335 | #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) |
| 1336 | #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) |
| 1337 | #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) |
| 1338 | #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) |
| 1339 | #define ID_AA64MMFR1_PAN_EPAN (UL(0x3) << ID_AA64MMFR1_PAN_SHIFT) |
| 1340 | #define ID_AA64MMFR1_SpecSEI_SHIFT 24 |
| 1341 | #define ID_AA64MMFR1_SpecSEI_WIDTH 4 |
| 1342 | #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) |
| 1343 | #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) |
| 1344 | #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) |
| 1345 | #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) |
| 1346 | #define ID_AA64MMFR1_XNX_SHIFT 28 |
| 1347 | #define ID_AA64MMFR1_XNX_WIDTH 4 |
| 1348 | #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) |
| 1349 | #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) |
| 1350 | #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) |
| 1351 | #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) |
| 1352 | #define ID_AA64MMFR1_TWED_SHIFT 32 |
| 1353 | #define ID_AA64MMFR1_TWED_WIDTH 4 |
| 1354 | #define ID_AA64MMFR1_TWED_MASK (UL(0xf) << ID_AA64MMFR1_TWED_SHIFT) |
| 1355 | #define ID_AA64MMFR1_TWED_VAL(x) ((x) & ID_AA64MMFR1_TWED_MASK) |
| 1356 | #define ID_AA64MMFR1_TWED_NONE (UL(0x0) << ID_AA64MMFR1_TWED_SHIFT) |
| 1357 | #define ID_AA64MMFR1_TWED_IMPL (UL(0x1) << ID_AA64MMFR1_TWED_SHIFT) |
| 1358 | #define ID_AA64MMFR1_ETS_SHIFT 36 |
| 1359 | #define ID_AA64MMFR1_ETS_WIDTH 4 |
| 1360 | #define ID_AA64MMFR1_ETS_MASK (UL(0xf) << ID_AA64MMFR1_ETS_SHIFT) |
| 1361 | #define ID_AA64MMFR1_ETS_VAL(x) ((x) & ID_AA64MMFR1_ETS_MASK) |
| 1362 | #define ID_AA64MMFR1_ETS_NONE (UL(0x0) << ID_AA64MMFR1_ETS_SHIFT) |
| 1363 | #define ID_AA64MMFR1_ETS_NONE2 (UL(0x1) << ID_AA64MMFR1_ETS_SHIFT) |
| 1364 | #define ID_AA64MMFR1_ETS_IMPL (UL(0x2) << ID_AA64MMFR1_ETS_SHIFT) |
| 1365 | #define ID_AA64MMFR1_HCX_SHIFT 40 |
| 1366 | #define ID_AA64MMFR1_HCX_WIDTH 4 |
| 1367 | #define ID_AA64MMFR1_HCX_MASK (UL(0xf) << ID_AA64MMFR1_HCX_SHIFT) |
| 1368 | #define ID_AA64MMFR1_HCX_VAL(x) ((x) & ID_AA64MMFR1_HCX_MASK) |
| 1369 | #define ID_AA64MMFR1_HCX_NONE (UL(0x0) << ID_AA64MMFR1_HCX_SHIFT) |
| 1370 | #define ID_AA64MMFR1_HCX_IMPL (UL(0x1) << ID_AA64MMFR1_HCX_SHIFT) |
| 1371 | #define ID_AA64MMFR1_AFP_SHIFT 44 |
| 1372 | #define ID_AA64MMFR1_AFP_WIDTH 4 |
| 1373 | #define ID_AA64MMFR1_AFP_MASK (UL(0xf) << ID_AA64MMFR1_AFP_SHIFT) |
| 1374 | #define ID_AA64MMFR1_AFP_VAL(x) ((x) & ID_AA64MMFR1_AFP_MASK) |
| 1375 | #define ID_AA64MMFR1_AFP_NONE (UL(0x0) << ID_AA64MMFR1_AFP_SHIFT) |
| 1376 | #define ID_AA64MMFR1_AFP_IMPL (UL(0x1) << ID_AA64MMFR1_AFP_SHIFT) |
| 1377 | #define ID_AA64MMFR1_nTLBPA_SHIFT 48 |
| 1378 | #define ID_AA64MMFR1_nTLBPA_WIDTH 4 |
| 1379 | #define ID_AA64MMFR1_nTLBPA_MASK (UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT) |
| 1380 | #define ID_AA64MMFR1_nTLBPA_VAL(x) ((x) & ID_AA64MMFR1_nTLBPA_MASK) |
| 1381 | #define ID_AA64MMFR1_nTLBPA_NONE (UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT) |
| 1382 | #define ID_AA64MMFR1_nTLBPA_IMPL (UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT) |
| 1383 | #define ID_AA64MMFR1_TIDCP1_SHIFT 52 |
| 1384 | #define ID_AA64MMFR1_TIDCP1_WIDTH 4 |
| 1385 | #define ID_AA64MMFR1_TIDCP1_MASK (UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT) |
| 1386 | #define ID_AA64MMFR1_TIDCP1_VAL(x) ((x) & ID_AA64MMFR1_TIDCP1_MASK) |
| 1387 | #define ID_AA64MMFR1_TIDCP1_NONE (UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT) |
| 1388 | #define ID_AA64MMFR1_TIDCP1_IMPL (UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT) |
| 1389 | #define ID_AA64MMFR1_CMOVW_SHIFT 56 |
| 1390 | #define ID_AA64MMFR1_CMOVW_WIDTH 4 |
| 1391 | #define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT) |
| 1392 | #define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK) |
| 1393 | #define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT) |
| 1394 | #define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT) |
| 1395 | #define ID_AA64MMFR1_ECBHB_SHIFT 60 |
| 1396 | #define ID_AA64MMFR1_ECBHB_WIDTH 4 |
| 1397 | #define ID_AA64MMFR1_ECBHB_MASK (UL(0xf) << ID_AA64MMFR1_ECBHB_SHIFT) |
| 1398 | #define ID_AA64MMFR1_ECBHB_VAL(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) |
| 1399 | #define ID_AA64MMFR1_ECBHB_NONE (UL(0x0) << ID_AA64MMFR1_ECBHB_SHIFT) |
| 1400 | #define ID_AA64MMFR1_ECBHB_IMPL (UL(0x1) << ID_AA64MMFR1_ECBHB_SHIFT) |
| 1401 | |
| 1402 | /* ID_AA64MMFR2_EL1 */ |
| 1403 | #define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1) |
| 1404 | #define ID_AA64MMFR2_EL1_ISS ISS_MSR_REG(ID_AA64MMFR2_EL1) |
| 1405 | #define ID_AA64MMFR2_EL1_op0 3 |
| 1406 | #define ID_AA64MMFR2_EL1_op1 0 |
| 1407 | #define ID_AA64MMFR2_EL1_CRn 0 |
| 1408 | #define ID_AA64MMFR2_EL1_CRm 7 |
| 1409 | #define ID_AA64MMFR2_EL1_op2 2 |
| 1410 | #define ID_AA64MMFR2_CnP_SHIFT 0 |
| 1411 | #define ID_AA64MMFR2_CnP_WIDTH 4 |
| 1412 | #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) |
| 1413 | #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) |
| 1414 | #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) |
| 1415 | #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) |
| 1416 | #define ID_AA64MMFR2_UAO_SHIFT 4 |
| 1417 | #define ID_AA64MMFR2_UAO_WIDTH 4 |
| 1418 | #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) |
| 1419 | #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) |
| 1420 | #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) |
| 1421 | #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) |
| 1422 | #define ID_AA64MMFR2_LSM_SHIFT 8 |
| 1423 | #define ID_AA64MMFR2_LSM_WIDTH 4 |
| 1424 | #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) |
| 1425 | #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) |
| 1426 | #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) |
| 1427 | #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) |
| 1428 | #define ID_AA64MMFR2_IESB_SHIFT 12 |
| 1429 | #define ID_AA64MMFR2_IESB_WIDTH 4 |
| 1430 | #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) |
| 1431 | #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) |
| 1432 | #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) |
| 1433 | #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) |
| 1434 | #define ID_AA64MMFR2_VARange_SHIFT 16 |
| 1435 | #define ID_AA64MMFR2_VARange_WIDTH 4 |
| 1436 | #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) |
| 1437 | #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) |
| 1438 | #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) |
| 1439 | #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) |
| 1440 | #define ID_AA64MMFR2_CCIDX_SHIFT 20 |
| 1441 | #define ID_AA64MMFR2_CCIDX_WIDTH 4 |
| 1442 | #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) |
| 1443 | #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) |
| 1444 | #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) |
| 1445 | #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) |
| 1446 | #define ID_AA64MMFR2_NV_SHIFT 24 |
| 1447 | #define ID_AA64MMFR2_NV_WIDTH 4 |
| 1448 | #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) |
| 1449 | #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) |
| 1450 | #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) |
| 1451 | #define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) |
| 1452 | #define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) |
| 1453 | #define ID_AA64MMFR2_ST_SHIFT 28 |
| 1454 | #define ID_AA64MMFR2_ST_WIDTH 4 |
| 1455 | #define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) |
| 1456 | #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) |
| 1457 | #define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) |
| 1458 | #define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) |
| 1459 | #define ID_AA64MMFR2_AT_SHIFT 32 |
| 1460 | #define ID_AA64MMFR2_AT_WIDTH 4 |
| 1461 | #define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) |
| 1462 | #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) |
| 1463 | #define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) |
| 1464 | #define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) |
| 1465 | #define ID_AA64MMFR2_IDS_SHIFT 36 |
| 1466 | #define ID_AA64MMFR2_IDS_WIDTH 4 |
| 1467 | #define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) |
| 1468 | #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) |
| 1469 | #define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) |
| 1470 | #define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) |
| 1471 | #define ID_AA64MMFR2_FWB_SHIFT 40 |
| 1472 | #define ID_AA64MMFR2_FWB_WIDTH 4 |
| 1473 | #define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) |
| 1474 | #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) |
| 1475 | #define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) |
| 1476 | #define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) |
| 1477 | #define ID_AA64MMFR2_TTL_SHIFT 48 |
| 1478 | #define ID_AA64MMFR2_TTL_WIDTH 4 |
| 1479 | #define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) |
| 1480 | #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) |
| 1481 | #define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) |
| 1482 | #define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) |
| 1483 | #define ID_AA64MMFR2_BBM_SHIFT 52 |
| 1484 | #define ID_AA64MMFR2_BBM_WIDTH 4 |
| 1485 | #define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) |
| 1486 | #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) |
| 1487 | #define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) |
| 1488 | #define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) |
| 1489 | #define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) |
| 1490 | #define ID_AA64MMFR2_EVT_SHIFT 56 |
| 1491 | #define ID_AA64MMFR2_EVT_WIDTH 4 |
| 1492 | #define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) |
| 1493 | #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) |
| 1494 | #define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) |
| 1495 | #define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) |
| 1496 | #define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) |
| 1497 | #define ID_AA64MMFR2_E0PD_SHIFT 60 |
| 1498 | #define ID_AA64MMFR2_E0PD_WIDTH 4 |
| 1499 | #define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) |
| 1500 | #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) |
| 1501 | #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) |
| 1502 | #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) |
| 1503 | |
| 1504 | /* ID_AA64MMFR3_EL1 */ |
| 1505 | #define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1) |
| 1506 | #define ID_AA64MMFR3_EL1_ISS ISS_MSR_REG(ID_AA64MMFR3_EL1) |
| 1507 | #define ID_AA64MMFR3_EL1_op0 3 |
| 1508 | #define ID_AA64MMFR3_EL1_op1 0 |
| 1509 | #define ID_AA64MMFR3_EL1_CRn 0 |
| 1510 | #define ID_AA64MMFR3_EL1_CRm 7 |
| 1511 | #define ID_AA64MMFR3_EL1_op2 3 |
| 1512 | #define ID_AA64MMFR3_TCRX_SHIFT 0 |
| 1513 | #define ID_AA64MMFR3_TCRX_WIDTH 4 |
| 1514 | #define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT) |
| 1515 | #define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) |
| 1516 | #define ID_AA64MMFR3_TCRX_NONE (UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT) |
| 1517 | #define ID_AA64MMFR3_TCRX_IMPL (UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT) |
| 1518 | #define ID_AA64MMFR3_SCTLRX_SHIFT 4 |
| 1519 | #define ID_AA64MMFR3_SCTLRX_WIDTH 4 |
| 1520 | #define ID_AA64MMFR3_SCTLRX_MASK (UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT) |
| 1521 | #define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) |
| 1522 | #define ID_AA64MMFR3_SCTLRX_NONE (UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT) |
| 1523 | #define ID_AA64MMFR3_SCTLRX_IMPL (UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT) |
| 1524 | #define ID_AA64MMFR3_S1PIE_SHIFT 8 |
| 1525 | #define ID_AA64MMFR3_S1PIE_WIDTH 4 |
| 1526 | #define ID_AA64MMFR3_S1PIE_MASK (UL(0xf) << ID_AA64MMFR3_S1PIE_SHIFT) |
| 1527 | #define ID_AA64MMFR3_S1PIE_VAL(x) ((x) & ID_AA64MMFR3_S1PIE_MASK) |
| 1528 | #define ID_AA64MMFR3_S1PIE_NONE (UL(0x0) << ID_AA64MMFR3_S1PIE_SHIFT) |
| 1529 | #define ID_AA64MMFR3_S1PIE_IMPL (UL(0x1) << ID_AA64MMFR3_S1PIE_SHIFT) |
| 1530 | #define ID_AA64MMFR3_S2PIE_SHIFT 12 |
| 1531 | #define ID_AA64MMFR3_S2PIE_WIDTH 4 |
| 1532 | #define ID_AA64MMFR3_S2PIE_MASK (UL(0xf) << ID_AA64MMFR3_S2PIE_SHIFT) |
| 1533 | #define ID_AA64MMFR3_S2PIE_VAL(x) ((x) & ID_AA64MMFR3_S2PIE_MASK) |
| 1534 | #define ID_AA64MMFR3_S2PIE_NONE (UL(0x0) << ID_AA64MMFR3_S2PIE_SHIFT) |
| 1535 | #define ID_AA64MMFR3_S2PIE_IMPL (UL(0x1) << ID_AA64MMFR3_S2PIE_SHIFT) |
| 1536 | #define ID_AA64MMFR3_S1POE_SHIFT 16 |
| 1537 | #define ID_AA64MMFR3_S1POE_WIDTH 4 |
| 1538 | #define ID_AA64MMFR3_S1POE_MASK (UL(0xf) << ID_AA64MMFR3_S1POE_SHIFT) |
| 1539 | #define ID_AA64MMFR3_S1POE_VAL(x) ((x) & ID_AA64MMFR3_S1POE_MASK) |
| 1540 | #define ID_AA64MMFR3_S1POE_NONE (UL(0x0) << ID_AA64MMFR3_S1POE_SHIFT) |
| 1541 | #define ID_AA64MMFR3_S1POE_IMPL (UL(0x1) << ID_AA64MMFR3_S1POE_SHIFT) |
| 1542 | #define ID_AA64MMFR3_S2POE_SHIFT 20 |
| 1543 | #define ID_AA64MMFR3_S2POE_WIDTH 4 |
| 1544 | #define ID_AA64MMFR3_S2POE_MASK (UL(0xf) << ID_AA64MMFR3_S2POE_SHIFT) |
| 1545 | #define ID_AA64MMFR3_S2POE_VAL(x) ((x) & ID_AA64MMFR3_S2POE_MASK) |
| 1546 | #define ID_AA64MMFR3_S2POE_NONE (UL(0x0) << ID_AA64MMFR3_S2POE_SHIFT) |
| 1547 | #define ID_AA64MMFR3_S2POE_IMPL (UL(0x1) << ID_AA64MMFR3_S2POE_SHIFT) |
| 1548 | #define ID_AA64MMFR3_AIE_SHIFT 24 |
| 1549 | #define ID_AA64MMFR3_AIE_WIDTH 4 |
| 1550 | #define ID_AA64MMFR3_AIE_MASK (UL(0xf) << ID_AA64MMFR3_AIE_SHIFT) |
| 1551 | #define ID_AA64MMFR3_AIE_VAL(x) ((x) & ID_AA64MMFR3_AIE_MASK) |
| 1552 | #define ID_AA64MMFR3_AIE_NONE (UL(0x0) << ID_AA64MMFR3_AIE_SHIFT) |
| 1553 | #define ID_AA64MMFR3_AIE_IMPL (UL(0x1) << ID_AA64MMFR3_AIE_SHIFT) |
| 1554 | #define ID_AA64MMFR3_MEC_SHIFT 28 |
| 1555 | #define ID_AA64MMFR3_MEC_WIDTH 4 |
| 1556 | #define ID_AA64MMFR3_MEC_MASK (UL(0xf) << ID_AA64MMFR3_MEC_SHIFT) |
| 1557 | #define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) |
| 1558 | #define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT) |
| 1559 | #define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT) |
| 1560 | #define ID_AA64MMFR3_SNERR_SHIFT 40 |
| 1561 | #define ID_AA64MMFR3_SNERR_WIDTH 4 |
| 1562 | #define ID_AA64MMFR3_SNERR_MASK (UL(0xf) << ID_AA64MMFR3_SNERR_SHIFT) |
| 1563 | #define ID_AA64MMFR3_SNERR_VAL(x) ((x) & ID_AA64MMFR3_SNERR_MASK) |
| 1564 | #define ID_AA64MMFR3_SNERR_NONE (UL(0x0) << ID_AA64MMFR3_SNERR_SHIFT) |
| 1565 | #define ID_AA64MMFR3_SNERR_ALL (UL(0x1) << ID_AA64MMFR3_SNERR_SHIFT) |
| 1566 | #define ID_AA64MMFR3_ANERR_SHIFT 44 |
| 1567 | #define ID_AA64MMFR3_ANERR_WIDTH 4 |
| 1568 | #define ID_AA64MMFR3_ANERR_MASK (UL(0xf) << ID_AA64MMFR3_ANERR_SHIFT) |
| 1569 | #define ID_AA64MMFR3_ANERR_VAL(x) ((x) & ID_AA64MMFR3_ANERR_MASK) |
| 1570 | #define ID_AA64MMFR3_ANERR_NONE (UL(0x0) << ID_AA64MMFR3_ANERR_SHIFT) |
| 1571 | #define ID_AA64MMFR3_ANERR_SOME (UL(0x1) << ID_AA64MMFR3_ANERR_SHIFT) |
| 1572 | #define ID_AA64MMFR3_SDERR_SHIFT 52 |
| 1573 | #define ID_AA64MMFR3_SDERR_WIDTH 4 |
| 1574 | #define ID_AA64MMFR3_SDERR_MASK (UL(0xf) << ID_AA64MMFR3_SDERR_SHIFT) |
| 1575 | #define ID_AA64MMFR3_SDERR_VAL(x) ((x) & ID_AA64MMFR3_SDERR_MASK) |
| 1576 | #define ID_AA64MMFR3_SDERR_NONE (UL(0x0) << ID_AA64MMFR3_SDERR_SHIFT) |
| 1577 | #define ID_AA64MMFR3_SDERR_ALL (UL(0x1) << ID_AA64MMFR3_SDERR_SHIFT) |
| 1578 | #define ID_AA64MMFR3_ADERR_SHIFT 56 |
| 1579 | #define ID_AA64MMFR3_ADERR_WIDTH 4 |
| 1580 | #define ID_AA64MMFR3_ADERR_MASK (UL(0xf) << ID_AA64MMFR3_ADERR_SHIFT) |
| 1581 | #define ID_AA64MMFR3_ADERR_VAL(x) ((x) & ID_AA64MMFR3_ADERR_MASK) |
| 1582 | #define ID_AA64MMFR3_ADERR_NONE (UL(0x0) << ID_AA64MMFR3_ADERR_SHIFT) |
| 1583 | #define ID_AA64MMFR3_ADERR_SOME (UL(0x1) << ID_AA64MMFR3_ADERR_SHIFT) |
| 1584 | #define ID_AA64MMFR3_Spec_FPACC_SHIFT 60 |
| 1585 | #define ID_AA64MMFR3_Spec_FPACC_WIDTH 4 |
| 1586 | #define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT) |
| 1587 | #define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) |
| 1588 | #define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT) |
| 1589 | #define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT) |
| 1590 | |
| 1591 | /* ID_AA64MMFR4_EL1 */ |
| 1592 | #define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1) |
| 1593 | #define ID_AA64MMFR4_EL1_ISS ISS_MSR_REG(ID_AA64MMFR4_EL1) |
| 1594 | #define ID_AA64MMFR4_EL1_op0 3 |
| 1595 | #define ID_AA64MMFR4_EL1_op1 0 |
| 1596 | #define ID_AA64MMFR4_EL1_CRn 0 |
| 1597 | #define ID_AA64MMFR4_EL1_CRm 7 |
| 1598 | #define ID_AA64MMFR4_EL1_op2 4 |
| 1599 | |
| 1600 | /* ID_AA64PFR0_EL1 */ |
| 1601 | #define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1) |
| 1602 | #define ID_AA64PFR0_EL1_ISS ISS_MSR_REG(ID_AA64PFR0_EL1) |
| 1603 | #define ID_AA64PFR0_EL1_op0 3 |
| 1604 | #define ID_AA64PFR0_EL1_op1 0 |
| 1605 | #define ID_AA64PFR0_EL1_CRn 0 |
| 1606 | #define ID_AA64PFR0_EL1_CRm 4 |
| 1607 | #define ID_AA64PFR0_EL1_op2 0 |
| 1608 | #define ID_AA64PFR0_EL0_SHIFT 0 |
| 1609 | #define ID_AA64PFR0_EL0_WIDTH 4 |
| 1610 | #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) |
| 1611 | #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) |
| 1612 | #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) |
| 1613 | #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) |
| 1614 | #define ID_AA64PFR0_EL1_SHIFT 4 |
| 1615 | #define ID_AA64PFR0_EL1_WIDTH 4 |
| 1616 | #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) |
| 1617 | #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) |
| 1618 | #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) |
| 1619 | #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) |
| 1620 | #define ID_AA64PFR0_EL2_SHIFT 8 |
| 1621 | #define ID_AA64PFR0_EL2_WIDTH 4 |
| 1622 | #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) |
| 1623 | #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) |
| 1624 | #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) |
| 1625 | #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) |
| 1626 | #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) |
| 1627 | #define ID_AA64PFR0_EL3_SHIFT 12 |
| 1628 | #define ID_AA64PFR0_EL3_WIDTH 4 |
| 1629 | #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) |
| 1630 | #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) |
| 1631 | #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) |
| 1632 | #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) |
| 1633 | #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) |
| 1634 | #define ID_AA64PFR0_FP_SHIFT 16 |
| 1635 | #define ID_AA64PFR0_FP_WIDTH 4 |
| 1636 | #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) |
| 1637 | #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) |
| 1638 | #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) |
| 1639 | #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) |
| 1640 | #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) |
| 1641 | #define ID_AA64PFR0_AdvSIMD_SHIFT 20 |
| 1642 | #define ID_AA64PFR0_AdvSIMD_WIDTH 4 |
| 1643 | #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) |
| 1644 | #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) |
| 1645 | #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) |
| 1646 | #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) |
| 1647 | #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) |
| 1648 | #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ |
| 1649 | #define ID_AA64PFR0_GIC_SHIFT 24 |
| 1650 | #define ID_AA64PFR0_GIC_WIDTH 4 |
| 1651 | #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) |
| 1652 | #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) |
| 1653 | #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) |
| 1654 | #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) |
| 1655 | #define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) |
| 1656 | #define ID_AA64PFR0_RAS_SHIFT 28 |
| 1657 | #define ID_AA64PFR0_RAS_WIDTH 4 |
| 1658 | #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) |
| 1659 | #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) |
| 1660 | #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) |
| 1661 | #define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) |
| 1662 | #define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) |
| 1663 | #define ID_AA64PFR0_RAS_8_9 (UL(0x3) << ID_AA64PFR0_RAS_SHIFT) |
| 1664 | #define ID_AA64PFR0_SVE_SHIFT 32 |
| 1665 | #define ID_AA64PFR0_SVE_WIDTH 4 |
| 1666 | #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) |
| 1667 | #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) |
| 1668 | #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) |
| 1669 | #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) |
| 1670 | #define ID_AA64PFR0_SEL2_SHIFT 36 |
| 1671 | #define ID_AA64PFR0_SEL2_WIDTH 4 |
| 1672 | #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) |
| 1673 | #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) |
| 1674 | #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) |
| 1675 | #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) |
| 1676 | #define ID_AA64PFR0_MPAM_SHIFT 40 |
| 1677 | #define ID_AA64PFR0_MPAM_WIDTH 4 |
| 1678 | #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) |
| 1679 | #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) |
| 1680 | #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) |
| 1681 | #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) |
| 1682 | #define ID_AA64PFR0_AMU_SHIFT 44 |
| 1683 | #define ID_AA64PFR0_AMU_WIDTH 4 |
| 1684 | #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) |
| 1685 | #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) |
| 1686 | #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) |
| 1687 | #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) |
| 1688 | #define ID_AA64PFR0_AMU_V1_1 (UL(0x2) << ID_AA64PFR0_AMU_SHIFT) |
| 1689 | #define ID_AA64PFR0_DIT_SHIFT 48 |
| 1690 | #define ID_AA64PFR0_DIT_WIDTH 4 |
| 1691 | #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) |
| 1692 | #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) |
| 1693 | #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) |
| 1694 | #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) |
| 1695 | #define ID_AA64PFR0_RME_SHIFT 52 |
| 1696 | #define ID_AA64PFR0_RME_WIDTH 4 |
| 1697 | #define ID_AA64PFR0_RME_MASK (UL(0xf) << ID_AA64PFR0_RME_SHIFT) |
| 1698 | #define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK) |
| 1699 | #define ID_AA64PFR0_RME_NONE (UL(0x0) << ID_AA64PFR0_RME_SHIFT) |
| 1700 | #define ID_AA64PFR0_RME_IMPL (UL(0x1) << ID_AA64PFR0_RME_SHIFT) |
| 1701 | #define ID_AA64PFR0_CSV2_SHIFT 56 |
| 1702 | #define ID_AA64PFR0_CSV2_WIDTH 4 |
| 1703 | #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) |
| 1704 | #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) |
| 1705 | #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) |
| 1706 | #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) |
| 1707 | #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) |
| 1708 | #define ID_AA64PFR0_CSV2_3 (UL(0x3) << ID_AA64PFR0_CSV2_SHIFT) |
| 1709 | #define ID_AA64PFR0_CSV3_SHIFT 60 |
| 1710 | #define ID_AA64PFR0_CSV3_WIDTH 4 |
| 1711 | #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) |
| 1712 | #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) |
| 1713 | #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) |
| 1714 | #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) |
| 1715 | |
| 1716 | /* ID_AA64PFR1_EL1 */ |
| 1717 | #define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1) |
| 1718 | #define ID_AA64PFR1_EL1_ISS ISS_MSR_REG(ID_AA64PFR1_EL1) |
| 1719 | #define ID_AA64PFR1_EL1_op0 3 |
| 1720 | #define ID_AA64PFR1_EL1_op1 0 |
| 1721 | #define ID_AA64PFR1_EL1_CRn 0 |
| 1722 | #define ID_AA64PFR1_EL1_CRm 4 |
| 1723 | #define ID_AA64PFR1_EL1_op2 1 |
| 1724 | #define ID_AA64PFR1_BT_SHIFT 0 |
| 1725 | #define ID_AA64PFR1_BT_WIDTH 4 |
| 1726 | #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) |
| 1727 | #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) |
| 1728 | #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) |
| 1729 | #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) |
| 1730 | #define ID_AA64PFR1_SSBS_SHIFT 4 |
| 1731 | #define ID_AA64PFR1_SSBS_WIDTH 4 |
| 1732 | #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) |
| 1733 | #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) |
| 1734 | #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) |
| 1735 | #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) |
| 1736 | #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) |
| 1737 | #define ID_AA64PFR1_MTE_SHIFT 8 |
| 1738 | #define ID_AA64PFR1_MTE_WIDTH 4 |
| 1739 | #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) |
| 1740 | #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) |
| 1741 | #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) |
| 1742 | #define ID_AA64PFR1_MTE_MTE (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) |
| 1743 | #define ID_AA64PFR1_MTE_MTE2 (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) |
| 1744 | #define ID_AA64PFR1_MTE_MTE3 (UL(0x3) << ID_AA64PFR1_MTE_SHIFT) |
| 1745 | #define ID_AA64PFR1_RAS_frac_SHIFT 12 |
| 1746 | #define ID_AA64PFR1_RAS_frac_WIDTH 4 |
| 1747 | #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) |
| 1748 | #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) |
| 1749 | #define ID_AA64PFR1_RAS_frac_p0 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) |
| 1750 | #define ID_AA64PFR1_RAS_frac_p1 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) |
| 1751 | #define ID_AA64PFR1_MPAM_frac_SHIFT 16 |
| 1752 | #define ID_AA64PFR1_MPAM_frac_WIDTH 4 |
| 1753 | #define ID_AA64PFR1_MPAM_frac_MASK (UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT) |
| 1754 | #define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK) |
| 1755 | #define ID_AA64PFR1_MPAM_frac_p0 (UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT) |
| 1756 | #define ID_AA64PFR1_MPAM_frac_p1 (UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT) |
| 1757 | #define ID_AA64PFR1_SME_SHIFT 24 |
| 1758 | #define ID_AA64PFR1_SME_WIDTH 4 |
| 1759 | #define ID_AA64PFR1_SME_MASK (UL(0xf) << ID_AA64PFR1_SME_SHIFT) |
| 1760 | #define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK) |
| 1761 | #define ID_AA64PFR1_SME_NONE (UL(0x0) << ID_AA64PFR1_SME_SHIFT) |
| 1762 | #define ID_AA64PFR1_SME_SME (UL(0x1) << ID_AA64PFR1_SME_SHIFT) |
| 1763 | #define ID_AA64PFR1_SME_SME2 (UL(0x2) << ID_AA64PFR1_SME_SHIFT) |
| 1764 | #define ID_AA64PFR1_RNDR_trap_SHIFT 28 |
| 1765 | #define ID_AA64PFR1_RNDR_trap_WIDTH 4 |
| 1766 | #define ID_AA64PFR1_RNDR_trap_MASK (UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT) |
| 1767 | #define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK) |
| 1768 | #define ID_AA64PFR1_RNDR_trap_NONE (UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT) |
| 1769 | #define ID_AA64PFR1_RNDR_trap_IMPL (UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT) |
| 1770 | #define ID_AA64PFR1_CSV2_frac_SHIFT 32 |
| 1771 | #define ID_AA64PFR1_CSV2_frac_WIDTH 4 |
| 1772 | #define ID_AA64PFR1_CSV2_frac_MASK (UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT) |
| 1773 | #define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK) |
| 1774 | #define ID_AA64PFR1_CSV2_frac_p0 (UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT) |
| 1775 | #define ID_AA64PFR1_CSV2_frac_p1 (UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT) |
| 1776 | #define ID_AA64PFR1_CSV2_frac_p2 (UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT) |
| 1777 | #define ID_AA64PFR1_NMI_SHIFT 36 |
| 1778 | #define ID_AA64PFR1_NMI_WIDTH 4 |
| 1779 | #define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT) |
| 1780 | #define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK) |
| 1781 | #define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT) |
| 1782 | #define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT) |
| 1783 | #define ID_AA64PFR1_MTE_frac_SHIFT 40 |
| 1784 | #define ID_AA64PFR1_MTE_frac_WIDTH 4 |
| 1785 | #define ID_AA64PFR1_MTE_frac_MASK (UL(0xf) << ID_AA64PFR1_MTE_frac_SHIFT) |
| 1786 | #define ID_AA64PFR1_MTE_frac_VAL(x) ((x) & ID_AA64PFR1_MTE_frac_MASK) |
| 1787 | #define ID_AA64PFR1_MTE_frac_IMPL (UL(0x0) << ID_AA64PFR1_MTE_frac_SHIFT) |
| 1788 | #define ID_AA64PFR1_MTE_frac_NONE (UL(0xf) << ID_AA64PFR1_MTE_frac_SHIFT) |
| 1789 | #define ID_AA64PFR1_THE_SHIFT 48 |
| 1790 | #define ID_AA64PFR1_THE_WIDTH 4 |
| 1791 | #define ID_AA64PFR1_THE_MASK (UL(0xf) << ID_AA64PFR1_THE_SHIFT) |
| 1792 | #define ID_AA64PFR1_THE_VAL(x) ((x) & ID_AA64PFR1_THE_MASK) |
| 1793 | #define ID_AA64PFR1_THE_NONE (UL(0x0) << ID_AA64PFR1_THE_SHIFT) |
| 1794 | #define ID_AA64PFR1_THE_IMPL (UL(0x1) << ID_AA64PFR1_THE_SHIFT) |
| 1795 | #define ID_AA64PFR1_MTEX_SHIFT 52 |
| 1796 | #define ID_AA64PFR1_MTEX_WIDTH 4 |
| 1797 | #define ID_AA64PFR1_MTEX_MASK (UL(0xf) << ID_AA64PFR1_MTEX_SHIFT) |
| 1798 | #define ID_AA64PFR1_MTEX_VAL(x) ((x) & ID_AA64PFR1_MTEX_MASK) |
| 1799 | #define ID_AA64PFR1_MTEX_NONE (UL(0x0) << ID_AA64PFR1_MTEX_SHIFT) |
| 1800 | #define ID_AA64PFR1_MTEX_IMPL (UL(0x1) << ID_AA64PFR1_MTEX_SHIFT) |
| 1801 | #define ID_AA64PFR1_DF2_SHIFT 56 |
| 1802 | #define ID_AA64PFR1_DF2_WIDTH 4 |
| 1803 | #define ID_AA64PFR1_DF2_MASK (UL(0xf) << ID_AA64PFR1_DF2_SHIFT) |
| 1804 | #define ID_AA64PFR1_DF2_VAL(x) ((x) & ID_AA64PFR1_DF2_MASK) |
| 1805 | #define ID_AA64PFR1_DF2_NONE (UL(0x0) << ID_AA64PFR1_DF2_SHIFT) |
| 1806 | #define ID_AA64PFR1_DF2_IMPL (UL(0x1) << ID_AA64PFR1_DF2_SHIFT) |
| 1807 | #define ID_AA64PFR1_PFAR_SHIFT 60 |
| 1808 | #define ID_AA64PFR1_PFAR_WIDTH 4 |
| 1809 | #define ID_AA64PFR1_PFAR_MASK (UL(0xf) << ID_AA64PFR1_PFAR_SHIFT) |
| 1810 | #define ID_AA64PFR1_PFAR_VAL(x) ((x) & ID_AA64PFR1_PFAR_MASK) |
| 1811 | #define ID_AA64PFR1_PFAR_NONE (UL(0x0) << ID_AA64PFR1_PFAR_SHIFT) |
| 1812 | #define ID_AA64PFR1_PFAR_IMPL (UL(0x1) << ID_AA64PFR1_PFAR_SHIFT) |
| 1813 | |
| 1814 | /* ID_AA64PFR2_EL1 */ |
| 1815 | #define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1) |
| 1816 | #define ID_AA64PFR2_EL1_ISS ISS_MSR_REG(ID_AA64PFR2_EL1) |
| 1817 | #define ID_AA64PFR2_EL1_op0 3 |
| 1818 | #define ID_AA64PFR2_EL1_op1 0 |
| 1819 | #define ID_AA64PFR2_EL1_CRn 0 |
| 1820 | #define ID_AA64PFR2_EL1_CRm 4 |
| 1821 | #define ID_AA64PFR2_EL1_op2 2 |
| 1822 | |
| 1823 | /* ID_AA64ZFR0_EL1 */ |
| 1824 | #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) |
| 1825 | #define ID_AA64ZFR0_EL1_ISS ISS_MSR_REG(ID_AA64ZFR0_EL1) |
| 1826 | #define ID_AA64ZFR0_EL1_op0 3 |
| 1827 | #define ID_AA64ZFR0_EL1_op1 0 |
| 1828 | #define ID_AA64ZFR0_EL1_CRn 0 |
| 1829 | #define ID_AA64ZFR0_EL1_CRm 4 |
| 1830 | #define ID_AA64ZFR0_EL1_op2 4 |
| 1831 | #define ID_AA64ZFR0_SVEver_SHIFT 0 |
| 1832 | #define ID_AA64ZFR0_SVEver_WIDTH 4 |
| 1833 | #define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT) |
| 1834 | #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK) |
| 1835 | #define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT) |
| 1836 | #define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT) |
| 1837 | #define ID_AA64ZFR0_SVEver_SVE2P1 (UL(0x2) << ID_AA64ZFR0_SVEver_SHIFT) |
| 1838 | #define ID_AA64ZFR0_AES_SHIFT 4 |
| 1839 | #define ID_AA64ZFR0_AES_WIDTH 4 |
| 1840 | #define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT) |
| 1841 | #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK) |
| 1842 | #define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) |
| 1843 | #define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) |
| 1844 | #define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) |
| 1845 | #define ID_AA64ZFR0_BitPerm_SHIFT 16 |
| 1846 | #define ID_AA64ZFR0_BitPerm_WIDTH 4 |
| 1847 | #define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) |
| 1848 | #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK) |
| 1849 | #define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT) |
| 1850 | #define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT) |
| 1851 | #define ID_AA64ZFR0_BF16_SHIFT 20 |
| 1852 | #define ID_AA64ZFR0_BF16_WIDTH 4 |
| 1853 | #define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT) |
| 1854 | #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK) |
| 1855 | #define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) |
| 1856 | #define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) |
| 1857 | #define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) |
| 1858 | #define ID_AA64ZFR0_SHA3_SHIFT 32 |
| 1859 | #define ID_AA64ZFR0_SHA3_WIDTH 4 |
| 1860 | #define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) |
| 1861 | #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK) |
| 1862 | #define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT) |
| 1863 | #define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT) |
| 1864 | #define ID_AA64ZFR0_SM4_SHIFT 40 |
| 1865 | #define ID_AA64ZFR0_SM4_WIDTH 4 |
| 1866 | #define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT) |
| 1867 | #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK) |
| 1868 | #define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT) |
| 1869 | #define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT) |
| 1870 | #define ID_AA64ZFR0_I8MM_SHIFT 44 |
| 1871 | #define ID_AA64ZFR0_I8MM_WIDTH 4 |
| 1872 | #define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT) |
| 1873 | #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK) |
| 1874 | #define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT) |
| 1875 | #define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT) |
| 1876 | #define ID_AA64ZFR0_F32MM_SHIFT 52 |
| 1877 | #define ID_AA64ZFR0_F32MM_WIDTH 4 |
| 1878 | #define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT) |
| 1879 | #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK) |
| 1880 | #define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT) |
| 1881 | #define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT) |
| 1882 | #define ID_AA64ZFR0_F64MM_SHIFT 56 |
| 1883 | #define ID_AA64ZFR0_F64MM_WIDTH 4 |
| 1884 | #define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT) |
| 1885 | #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK) |
| 1886 | #define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) |
| 1887 | #define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) |
| 1888 | |
| 1889 | /* ID_ISAR5_EL1 */ |
| 1890 | #define ID_ISAR5_EL1_ISS ISS_MSR_REG(ID_ISAR5_EL1) |
| 1891 | #define ID_ISAR5_EL1_op0 0x3 |
| 1892 | #define ID_ISAR5_EL1_op1 0x0 |
| 1893 | #define ID_ISAR5_EL1_CRn 0x0 |
| 1894 | #define ID_ISAR5_EL1_CRm 0x2 |
| 1895 | #define ID_ISAR5_EL1_op2 0x5 |
| 1896 | #define ID_ISAR5_SEVL_SHIFT 0 |
| 1897 | #define ID_ISAR5_SEVL_WIDTH 4 |
| 1898 | #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) |
| 1899 | #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) |
| 1900 | #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) |
| 1901 | #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) |
| 1902 | #define ID_ISAR5_AES_SHIFT 4 |
| 1903 | #define ID_ISAR5_AES_WIDTH 4 |
| 1904 | #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) |
| 1905 | #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) |
| 1906 | #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) |
| 1907 | #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) |
| 1908 | #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) |
| 1909 | #define ID_ISAR5_SHA1_SHIFT 8 |
| 1910 | #define ID_ISAR5_SHA1_WIDTH 4 |
| 1911 | #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) |
| 1912 | #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) |
| 1913 | #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) |
| 1914 | #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) |
| 1915 | #define ID_ISAR5_SHA2_SHIFT 12 |
| 1916 | #define ID_ISAR5_SHA2_WIDTH 4 |
| 1917 | #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) |
| 1918 | #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) |
| 1919 | #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) |
| 1920 | #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) |
| 1921 | #define ID_ISAR5_CRC32_SHIFT 16 |
| 1922 | #define ID_ISAR5_CRC32_WIDTH 4 |
| 1923 | #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) |
| 1924 | #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) |
| 1925 | #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) |
| 1926 | #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) |
| 1927 | #define ID_ISAR5_RDM_SHIFT 24 |
| 1928 | #define ID_ISAR5_RDM_WIDTH 4 |
| 1929 | #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) |
| 1930 | #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) |
| 1931 | #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) |
| 1932 | #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) |
| 1933 | #define ID_ISAR5_VCMA_SHIFT 28 |
| 1934 | #define ID_ISAR5_VCMA_WIDTH 4 |
| 1935 | #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) |
| 1936 | #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) |
| 1937 | #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) |
| 1938 | #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) |
| 1939 | |
| 1940 | /* MAIR_EL1 - Memory Attribute Indirection Register */ |
| 1941 | #define MAIR_EL1_REG MRS_REG_ALT_NAME(MAIR_EL1) |
| 1942 | #define MAIR_EL1_op0 3 |
| 1943 | #define MAIR_EL1_op1 0 |
| 1944 | #define MAIR_EL1_CRn 10 |
| 1945 | #define MAIR_EL1_CRm 2 |
| 1946 | #define MAIR_EL1_op2 0 |
| 1947 | #define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) |
| 1948 | #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) |
| 1949 | #define MAIR_DEVICE_nGnRnE UL(0x00) |
| 1950 | #define MAIR_DEVICE_nGnRE UL(0x04) |
| 1951 | #define MAIR_NORMAL_NC UL(0x44) |
| 1952 | #define MAIR_NORMAL_WT UL(0xbb) |
| 1953 | #define MAIR_NORMAL_WB UL(0xff) |
| 1954 | |
| 1955 | /* MAIR_EL12 */ |
| 1956 | #define MAIR_EL12_REG MRS_REG_ALT_NAME(MAIR_EL12) |
| 1957 | #define MAIR_EL12_op0 3 |
| 1958 | #define MAIR_EL12_op1 5 |
| 1959 | #define MAIR_EL12_CRn 10 |
| 1960 | #define MAIR_EL12_CRm 2 |
| 1961 | #define MAIR_EL12_op2 0 |
| 1962 | |
| 1963 | /* MDCCINT_EL1 */ |
| 1964 | #define MDCCINT_EL1_op0 2 |
| 1965 | #define MDCCINT_EL1_op1 0 |
| 1966 | #define MDCCINT_EL1_CRn 0 |
| 1967 | #define MDCCINT_EL1_CRm 2 |
| 1968 | #define MDCCINT_EL1_op2 0 |
| 1969 | |
| 1970 | /* MDCCSR_EL0 */ |
| 1971 | #define MDCCSR_EL0_op0 2 |
| 1972 | #define MDCCSR_EL0_op1 3 |
| 1973 | #define MDCCSR_EL0_CRn 0 |
| 1974 | #define MDCCSR_EL0_CRm 1 |
| 1975 | #define MDCCSR_EL0_op2 0 |
| 1976 | |
| 1977 | /* MDSCR_EL1 - Monitor Debug System Control Register */ |
| 1978 | #define MDSCR_EL1_op0 2 |
| 1979 | #define MDSCR_EL1_op1 0 |
| 1980 | #define MDSCR_EL1_CRn 0 |
| 1981 | #define MDSCR_EL1_CRm 2 |
| 1982 | #define MDSCR_EL1_op2 2 |
| 1983 | #define MDSCR_SS_SHIFT 0 |
| 1984 | #define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT) |
| 1985 | #define MDSCR_KDE_SHIFT 13 |
| 1986 | #define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT) |
| 1987 | #define MDSCR_MDE_SHIFT 15 |
| 1988 | #define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) |
| 1989 | |
| 1990 | /* MIDR_EL1 - Main ID Register */ |
| 1991 | #define MIDR_EL1_op0 3 |
| 1992 | #define MIDR_EL1_op1 0 |
| 1993 | #define MIDR_EL1_CRn 0 |
| 1994 | #define MIDR_EL1_CRm 0 |
| 1995 | #define MIDR_EL1_op2 0 |
| 1996 | |
| 1997 | /* MPIDR_EL1 - Multiprocessor Affinity Register */ |
| 1998 | #define MPIDR_EL1_op0 3 |
| 1999 | #define MPIDR_EL1_op1 0 |
| 2000 | #define MPIDR_EL1_CRn 0 |
| 2001 | #define MPIDR_EL1_CRm 0 |
| 2002 | #define MPIDR_EL1_op2 5 |
| 2003 | #define MPIDR_AFF0_SHIFT 0 |
| 2004 | #define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) |
| 2005 | #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) |
| 2006 | #define MPIDR_AFF1_SHIFT 8 |
| 2007 | #define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) |
| 2008 | #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) |
| 2009 | #define MPIDR_AFF2_SHIFT 16 |
| 2010 | #define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) |
| 2011 | #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) |
| 2012 | #define MPIDR_MT_SHIFT 24 |
| 2013 | #define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) |
| 2014 | #define MPIDR_U_SHIFT 30 |
| 2015 | #define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) |
| 2016 | #define MPIDR_AFF3_SHIFT 32 |
| 2017 | #define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) |
| 2018 | #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) |
| 2019 | |
| 2020 | /* MVFR0_EL1 */ |
| 2021 | #define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1) |
| 2022 | #define MVFR0_EL1_op0 0x3 |
| 2023 | #define MVFR0_EL1_op1 0x0 |
| 2024 | #define MVFR0_EL1_CRn 0x0 |
| 2025 | #define MVFR0_EL1_CRm 0x3 |
| 2026 | #define MVFR0_EL1_op2 0x0 |
| 2027 | #define MVFR0_SIMDReg_SHIFT 0 |
| 2028 | #define MVFR0_SIMDReg_WIDTH 4 |
| 2029 | #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) |
| 2030 | #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) |
| 2031 | #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) |
| 2032 | #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) |
| 2033 | #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) |
| 2034 | #define MVFR0_FPSP_SHIFT 4 |
| 2035 | #define MVFR0_FPSP_WIDTH 4 |
| 2036 | #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) |
| 2037 | #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) |
| 2038 | #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) |
| 2039 | #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) |
| 2040 | #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) |
| 2041 | #define MVFR0_FPDP_SHIFT 8 |
| 2042 | #define MVFR0_FPDP_WIDTH 4 |
| 2043 | #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) |
| 2044 | #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) |
| 2045 | #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) |
| 2046 | #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) |
| 2047 | #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) |
| 2048 | #define MVFR0_FPTrap_SHIFT 12 |
| 2049 | #define MVFR0_FPTrap_WIDTH 4 |
| 2050 | #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) |
| 2051 | #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) |
| 2052 | #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) |
| 2053 | #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) |
| 2054 | #define MVFR0_FPDivide_SHIFT 16 |
| 2055 | #define MVFR0_FPDivide_WIDTH 4 |
| 2056 | #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) |
| 2057 | #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) |
| 2058 | #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) |
| 2059 | #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) |
| 2060 | #define MVFR0_FPSqrt_SHIFT 20 |
| 2061 | #define MVFR0_FPSqrt_WIDTH 4 |
| 2062 | #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) |
| 2063 | #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) |
| 2064 | #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) |
| 2065 | #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) |
| 2066 | #define MVFR0_FPShVec_SHIFT 24 |
| 2067 | #define MVFR0_FPShVec_WIDTH 4 |
| 2068 | #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) |
| 2069 | #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) |
| 2070 | #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) |
| 2071 | #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) |
| 2072 | #define MVFR0_FPRound_SHIFT 28 |
| 2073 | #define MVFR0_FPRound_WIDTH 4 |
| 2074 | #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) |
| 2075 | #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) |
| 2076 | #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) |
| 2077 | #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) |
| 2078 | |
| 2079 | /* MVFR1_EL1 */ |
| 2080 | #define MVFR1_EL1_ISS ISS_MSR_REG(MVFR1_EL1) |
| 2081 | #define MVFR1_EL1_op0 0x3 |
| 2082 | #define MVFR1_EL1_op1 0x0 |
| 2083 | #define MVFR1_EL1_CRn 0x0 |
| 2084 | #define MVFR1_EL1_CRm 0x3 |
| 2085 | #define MVFR1_EL1_op2 0x1 |
| 2086 | #define MVFR1_FPFtZ_SHIFT 0 |
| 2087 | #define MVFR1_FPFtZ_WIDTH 4 |
| 2088 | #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) |
| 2089 | #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) |
| 2090 | #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) |
| 2091 | #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) |
| 2092 | #define MVFR1_FPDNaN_SHIFT 4 |
| 2093 | #define MVFR1_FPDNaN_WIDTH 4 |
| 2094 | #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) |
| 2095 | #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) |
| 2096 | #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) |
| 2097 | #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) |
| 2098 | #define MVFR1_SIMDLS_SHIFT 8 |
| 2099 | #define MVFR1_SIMDLS_WIDTH 4 |
| 2100 | #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) |
| 2101 | #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) |
| 2102 | #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) |
| 2103 | #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) |
| 2104 | #define MVFR1_SIMDInt_SHIFT 12 |
| 2105 | #define MVFR1_SIMDInt_WIDTH 4 |
| 2106 | #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) |
| 2107 | #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) |
| 2108 | #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) |
| 2109 | #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) |
| 2110 | #define MVFR1_SIMDSP_SHIFT 16 |
| 2111 | #define MVFR1_SIMDSP_WIDTH 4 |
| 2112 | #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) |
| 2113 | #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) |
| 2114 | #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) |
| 2115 | #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) |
| 2116 | #define MVFR1_SIMDHP_SHIFT 20 |
| 2117 | #define MVFR1_SIMDHP_WIDTH 4 |
| 2118 | #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) |
| 2119 | #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) |
| 2120 | #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) |
| 2121 | #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) |
| 2122 | #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) |
| 2123 | #define MVFR1_FPHP_SHIFT 24 |
| 2124 | #define MVFR1_FPHP_WIDTH 4 |
| 2125 | #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) |
| 2126 | #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) |
| 2127 | #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) |
| 2128 | #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) |
| 2129 | #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) |
| 2130 | #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) |
| 2131 | #define MVFR1_SIMDFMAC_SHIFT 28 |
| 2132 | #define MVFR1_SIMDFMAC_WIDTH 4 |
| 2133 | #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) |
| 2134 | #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) |
| 2135 | #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) |
| 2136 | #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) |
| 2137 | |
| 2138 | /* OSDLR_EL1 */ |
| 2139 | #define OSDLR_EL1_op0 2 |
| 2140 | #define OSDLR_EL1_op1 0 |
| 2141 | #define OSDLR_EL1_CRn 1 |
| 2142 | #define OSDLR_EL1_CRm 3 |
| 2143 | #define OSDLR_EL1_op2 4 |
| 2144 | |
| 2145 | /* OSLAR_EL1 */ |
| 2146 | #define OSLAR_EL1_op0 2 |
| 2147 | #define OSLAR_EL1_op1 0 |
| 2148 | #define OSLAR_EL1_CRn 1 |
| 2149 | #define OSLAR_EL1_CRm 0 |
| 2150 | #define OSLAR_EL1_op2 4 |
| 2151 | #define OSLAR_OSLK (0x1ul << 0) |
| 2152 | |
| 2153 | /* OSLSR_EL1 */ |
| 2154 | #define OSLSR_EL1_op0 2 |
| 2155 | #define OSLSR_EL1_op1 0 |
| 2156 | #define OSLSR_EL1_CRn 1 |
| 2157 | #define OSLSR_EL1_CRm 1 |
| 2158 | #define OSLSR_EL1_op2 4 |
| 2159 | #define OSLSR_OSLM_1 (0x1ul << 3) |
| 2160 | #define OSLSR_nTT (0x1ul << 2) |
| 2161 | #define OSLSR_OSLK (0x1ul << 1) |
| 2162 | #define OSLSR_OSLM_0 (0x1ul << 0) |
| 2163 | |
| 2164 | /* PAR_EL1 - Physical Address Register */ |
| 2165 | #define PAR_F_SHIFT 0 |
| 2166 | #define PAR_F (0x1 << PAR_F_SHIFT) |
| 2167 | #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) |
| 2168 | /* When PAR_F == 0 (success) */ |
| 2169 | #define PAR_LOW_MASK 0xfff |
| 2170 | #define PAR_SH_SHIFT 7 |
| 2171 | #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) |
| 2172 | #define PAR_NS_SHIFT 9 |
| 2173 | #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) |
| 2174 | #define PAR_PA_SHIFT 12 |
| 2175 | #define PAR_PA_MASK 0x000ffffffffff000 |
| 2176 | #define PAR_ATTR_SHIFT 56 |
| 2177 | #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) |
| 2178 | /* When PAR_F == 1 (aborted) */ |
| 2179 | #define PAR_FST_SHIFT 1 |
| 2180 | #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) |
| 2181 | #define PAR_PTW_SHIFT 8 |
| 2182 | #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) |
| 2183 | #define PAR_S_SHIFT 9 |
| 2184 | #define PAR_S_MASK (0x1 << PAR_S_SHIFT) |
| 2185 | |
| 2186 | /* PMBIDR_EL1 */ |
| 2187 | #define PMBIDR_EL1_REG MRS_REG_ALT_NAME(PMBIDR_EL1) |
| 2188 | #define PMBIDR_EL1_op0 3 |
| 2189 | #define PMBIDR_EL1_op1 0 |
| 2190 | #define PMBIDR_EL1_CRn 9 |
| 2191 | #define PMBIDR_EL1_CRm 10 |
| 2192 | #define PMBIDR_EL1_op2 7 |
| 2193 | #define PMBIDR_Align_SHIFT 0 |
| 2194 | #define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) |
| 2195 | #define PMBIDR_P_SHIFT 4 |
| 2196 | #define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT) |
| 2197 | #define PMBIDR_F_SHIFT 5 |
| 2198 | #define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT) |
| 2199 | |
| 2200 | /* PMBLIMITR_EL1 */ |
| 2201 | #define PMBLIMITR_EL1_REG MRS_REG_ALT_NAME(PMBLIMITR_EL1) |
| 2202 | #define PMBLIMITR_EL1_op0 3 |
| 2203 | #define PMBLIMITR_EL1_op1 0 |
| 2204 | #define PMBLIMITR_EL1_CRn 9 |
| 2205 | #define PMBLIMITR_EL1_CRm 10 |
| 2206 | #define PMBLIMITR_EL1_op2 0 |
| 2207 | #define PMBLIMITR_E_SHIFT 0 |
| 2208 | #define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) |
| 2209 | #define PMBLIMITR_FM_SHIFT 1 |
| 2210 | #define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT) |
| 2211 | #define PMBLIMITR_PMFZ_SHIFT 5 |
| 2212 | #define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT) |
| 2213 | #define PMBLIMITR_LIMIT_SHIFT 12 |
| 2214 | #define PMBLIMITR_LIMIT_MASK \ |
| 2215 | (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT) |
| 2216 | |
| 2217 | /* PMBPTR_EL1 */ |
| 2218 | #define PMBPTR_EL1_REG MRS_REG_ALT_NAME(PMBPTR_EL1) |
| 2219 | #define PMBPTR_EL1_op0 3 |
| 2220 | #define PMBPTR_EL1_op1 0 |
| 2221 | #define PMBPTR_EL1_CRn 9 |
| 2222 | #define PMBPTR_EL1_CRm 10 |
| 2223 | #define PMBPTR_EL1_op2 1 |
| 2224 | #define PMBPTR_PTR_SHIFT 0 |
| 2225 | #define PMBPTR_PTR_MASK \ |
| 2226 | (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) |
| 2227 | |
| 2228 | /* PMBSR_EL1 */ |
| 2229 | #define PMBSR_EL1_REG MRS_REG_ALT_NAME(PMBSR_EL1) |
| 2230 | #define PMBSR_EL1_op0 3 |
| 2231 | #define PMBSR_EL1_op1 0 |
| 2232 | #define PMBSR_EL1_CRn 9 |
| 2233 | #define PMBSR_EL1_CRm 10 |
| 2234 | #define PMBSR_EL1_op2 3 |
| 2235 | #define PMBSR_MSS_SHIFT 0 |
| 2236 | #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) |
| 2237 | #define PMBSR_MSS_BSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) |
| 2238 | #define PMBSR_MSS_FSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) |
| 2239 | #define PMBSR_COLL_SHIFT 16 |
| 2240 | #define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) |
| 2241 | #define PMBSR_S_SHIFT 17 |
| 2242 | #define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT) |
| 2243 | #define PMBSR_EA_SHIFT 18 |
| 2244 | #define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT) |
| 2245 | #define PMBSR_DL_SHIFT 19 |
| 2246 | #define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT) |
| 2247 | #define PMBSR_EC_SHIFT 26 |
| 2248 | #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) |
| 2249 | |
| 2250 | /* PMCCFILTR_EL0 */ |
| 2251 | #define PMCCFILTR_EL0_op0 3 |
| 2252 | #define PMCCFILTR_EL0_op1 3 |
| 2253 | #define PMCCFILTR_EL0_CRn 14 |
| 2254 | #define PMCCFILTR_EL0_CRm 15 |
| 2255 | #define PMCCFILTR_EL0_op2 7 |
| 2256 | |
| 2257 | /* PMCCNTR_EL0 */ |
| 2258 | #define PMCCNTR_EL0_op0 3 |
| 2259 | #define PMCCNTR_EL0_op1 3 |
| 2260 | #define PMCCNTR_EL0_CRn 9 |
| 2261 | #define PMCCNTR_EL0_CRm 13 |
| 2262 | #define PMCCNTR_EL0_op2 0 |
| 2263 | |
| 2264 | /* PMCEID0_EL0 */ |
| 2265 | #define PMCEID0_EL0_op0 3 |
| 2266 | #define PMCEID0_EL0_op1 3 |
| 2267 | #define PMCEID0_EL0_CRn 9 |
| 2268 | #define PMCEID0_EL0_CRm 12 |
| 2269 | #define PMCEID0_EL0_op2 6 |
| 2270 | |
| 2271 | /* PMCEID1_EL0 */ |
| 2272 | #define PMCEID1_EL0_op0 3 |
| 2273 | #define PMCEID1_EL0_op1 3 |
| 2274 | #define PMCEID1_EL0_CRn 9 |
| 2275 | #define PMCEID1_EL0_CRm 12 |
| 2276 | #define PMCEID1_EL0_op2 7 |
| 2277 | |
| 2278 | /* PMCNTENCLR_EL0 */ |
| 2279 | #define PMCNTENCLR_EL0_op0 3 |
| 2280 | #define PMCNTENCLR_EL0_op1 3 |
| 2281 | #define PMCNTENCLR_EL0_CRn 9 |
| 2282 | #define PMCNTENCLR_EL0_CRm 12 |
| 2283 | #define PMCNTENCLR_EL0_op2 2 |
| 2284 | |
| 2285 | /* PMCNTENSET_EL0 */ |
| 2286 | #define PMCNTENSET_EL0_op0 3 |
| 2287 | #define PMCNTENSET_EL0_op1 3 |
| 2288 | #define PMCNTENSET_EL0_CRn 9 |
| 2289 | #define PMCNTENSET_EL0_CRm 12 |
| 2290 | #define PMCNTENSET_EL0_op2 1 |
| 2291 | |
| 2292 | /* PMCR_EL0 - Perfomance Monitoring Counters */ |
| 2293 | #define PMCR_EL0_op0 3 |
| 2294 | #define PMCR_EL0_op1 3 |
| 2295 | #define PMCR_EL0_CRn 9 |
| 2296 | #define PMCR_EL0_CRm 12 |
| 2297 | #define PMCR_EL0_op2 0 |
| 2298 | #define PMCR_E (1ul << 0) /* Enable all counters */ |
| 2299 | #define PMCR_P (1ul << 1) /* Reset all counters */ |
| 2300 | #define PMCR_C (1ul << 2) /* Clock counter reset */ |
| 2301 | #define PMCR_D (1ul << 3) /* CNTR counts every 64 clk cycles */ |
| 2302 | #define PMCR_X (1ul << 4) /* Export to ext. monitoring (ETM) */ |
| 2303 | #define PMCR_DP (1ul << 5) /* Disable CCNT if non-invasive debug*/ |
| 2304 | #define PMCR_LC (1ul << 6) /* Long cycle count enable */ |
| 2305 | #define PMCR_LP (1ul << 7) /* Long event count enable */ |
| 2306 | #define PMCR_FZO (1ul << 9) /* Freeze-on-overflow */ |
| 2307 | #define PMCR_N_SHIFT 11 /* Number of counters implemented */ |
| 2308 | #define PMCR_N_MASK (0x1ful << PMCR_N_SHIFT) |
| 2309 | #define PMCR_IDCODE_SHIFT 16 /* Identification code */ |
| 2310 | #define PMCR_IDCODE_MASK (0xfful << PMCR_IDCODE_SHIFT) |
| 2311 | #define PMCR_IDCODE_CORTEX_A57 0x01 |
| 2312 | #define PMCR_IDCODE_CORTEX_A72 0x02 |
| 2313 | #define PMCR_IDCODE_CORTEX_A53 0x03 |
| 2314 | #define PMCR_IDCODE_CORTEX_A73 0x04 |
| 2315 | #define PMCR_IDCODE_CORTEX_A35 0x0a |
| 2316 | #define PMCR_IDCODE_CORTEX_A76 0x0b |
| 2317 | #define PMCR_IDCODE_NEOVERSE_N1 0x0c |
| 2318 | #define PMCR_IDCODE_CORTEX_A77 0x10 |
| 2319 | #define PMCR_IDCODE_CORTEX_A55 0x45 |
| 2320 | #define PMCR_IDCODE_NEOVERSE_E1 0x46 |
| 2321 | #define PMCR_IDCODE_CORTEX_A75 0x4a |
| 2322 | #define PMCR_IMP_SHIFT 24 /* Implementer code */ |
| 2323 | #define PMCR_IMP_MASK (0xfful << PMCR_IMP_SHIFT) |
| 2324 | #define PMCR_IMP_ARM 0x41 |
| 2325 | #define PMCR_FZS (1ul << 32) /* Freeze-on-SPE event */ |
| 2326 | |
| 2327 | /* PMEVCNTR<n>_EL0 */ |
| 2328 | #define PMEVCNTR_EL0_op0 3 |
| 2329 | #define PMEVCNTR_EL0_op1 3 |
| 2330 | #define PMEVCNTR_EL0_CRn 14 |
| 2331 | #define PMEVCNTR_EL0_CRm 8 |
| 2332 | /* |
| 2333 | * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n' |
| 2334 | * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n' |
| 2335 | */ |
| 2336 | |
| 2337 | /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */ |
| 2338 | #define PMEVTYPER_EL0_op0 3 |
| 2339 | #define PMEVTYPER_EL0_op1 3 |
| 2340 | #define PMEVTYPER_EL0_CRn 14 |
| 2341 | #define PMEVTYPER_EL0_CRm 12 |
| 2342 | /* |
| 2343 | * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n' |
| 2344 | * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n' |
| 2345 | */ |
| 2346 | #define PMEVTYPER_EVTCOUNT_MASK 0x000003ff /* ARMv8.0 */ |
| 2347 | #define PMEVTYPER_EVTCOUNT_8_1_MASK 0x0000ffff /* ARMv8.1+ */ |
| 2348 | #define PMEVTYPER_MT (1 << 25) /* Multithreading */ |
| 2349 | #define PMEVTYPER_M (1 << 26) /* Secure EL3 filtering */ |
| 2350 | #define PMEVTYPER_NSH (1 << 27) /* Non-secure hypervisor filtering */ |
| 2351 | #define PMEVTYPER_NSU (1 << 28) /* Non-secure user filtering */ |
| 2352 | #define PMEVTYPER_NSK (1 << 29) /* Non-secure kernel filtering */ |
| 2353 | #define PMEVTYPER_U (1 << 30) /* User filtering */ |
| 2354 | #define PMEVTYPER_P (1 << 31) /* Privileged filtering */ |
| 2355 | |
| 2356 | /* PMINTENCLR_EL1 */ |
| 2357 | #define PMINTENCLR_EL1_op0 3 |
| 2358 | #define PMINTENCLR_EL1_op1 0 |
| 2359 | #define PMINTENCLR_EL1_CRn 9 |
| 2360 | #define PMINTENCLR_EL1_CRm 14 |
| 2361 | #define PMINTENCLR_EL1_op2 2 |
| 2362 | |
| 2363 | /* PMINTENSET_EL1 */ |
| 2364 | #define PMINTENSET_EL1_op0 3 |
| 2365 | #define PMINTENSET_EL1_op1 0 |
| 2366 | #define PMINTENSET_EL1_CRn 9 |
| 2367 | #define PMINTENSET_EL1_CRm 14 |
| 2368 | #define PMINTENSET_EL1_op2 1 |
| 2369 | |
| 2370 | /* PMMIR_EL1 */ |
| 2371 | #define PMMIR_EL1_op0 3 |
| 2372 | #define PMMIR_EL1_op1 0 |
| 2373 | #define PMMIR_EL1_CRn 9 |
| 2374 | #define PMMIR_EL1_CRm 14 |
| 2375 | #define PMMIR_EL1_op2 6 |
| 2376 | |
| 2377 | /* PMOVSCLR_EL0 */ |
| 2378 | #define PMOVSCLR_EL0_op0 3 |
| 2379 | #define PMOVSCLR_EL0_op1 3 |
| 2380 | #define PMOVSCLR_EL0_CRn 9 |
| 2381 | #define PMOVSCLR_EL0_CRm 12 |
| 2382 | #define PMOVSCLR_EL0_op2 3 |
| 2383 | |
| 2384 | /* PMOVSSET_EL0 */ |
| 2385 | #define PMOVSSET_EL0_op0 3 |
| 2386 | #define PMOVSSET_EL0_op1 3 |
| 2387 | #define PMOVSSET_EL0_CRn 9 |
| 2388 | #define PMOVSSET_EL0_CRm 14 |
| 2389 | #define PMOVSSET_EL0_op2 3 |
| 2390 | |
| 2391 | /* PMSCR_EL1 */ |
| 2392 | #define PMSCR_EL1_REG MRS_REG_ALT_NAME(PMSCR_EL1) |
| 2393 | #define PMSCR_EL1_op0 3 |
| 2394 | #define PMSCR_EL1_op1 0 |
| 2395 | #define PMSCR_EL1_CRn 9 |
| 2396 | #define PMSCR_EL1_CRm 9 |
| 2397 | #define PMSCR_EL1_op2 0 |
| 2398 | #define PMSCR_E0SPE_SHIFT 0 |
| 2399 | #define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) |
| 2400 | #define PMSCR_E1SPE_SHIFT 1 |
| 2401 | #define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT) |
| 2402 | #define PMSCR_CX_SHIFT 3 |
| 2403 | #define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT) |
| 2404 | #define PMSCR_PA_SHIFT 4 |
| 2405 | #define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT) |
| 2406 | #define PMSCR_TS_SHIFT 5 |
| 2407 | #define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT) |
| 2408 | #define PMSCR_PCT_SHIFT 6 |
| 2409 | #define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT) |
| 2410 | |
| 2411 | /* PMSELR_EL0 */ |
| 2412 | #define PMSELR_EL0_op0 3 |
| 2413 | #define PMSELR_EL0_op1 3 |
| 2414 | #define PMSELR_EL0_CRn 9 |
| 2415 | #define PMSELR_EL0_CRm 12 |
| 2416 | #define PMSELR_EL0_op2 5 |
| 2417 | #define PMSELR_SEL_MASK 0x1f |
| 2418 | |
| 2419 | /* PMSEVFR_EL1 */ |
| 2420 | #define PMSEVFR_EL1_REG MRS_REG_ALT_NAME(PMSEVFR_EL1) |
| 2421 | #define PMSEVFR_EL1_op0 3 |
| 2422 | #define PMSEVFR_EL1_op1 0 |
| 2423 | #define PMSEVFR_EL1_CRn 9 |
| 2424 | #define PMSEVFR_EL1_CRm 9 |
| 2425 | #define PMSEVFR_EL1_op2 5 |
| 2426 | |
| 2427 | /* PMSFCR_EL1 */ |
| 2428 | #define PMSFCR_EL1_REG MRS_REG_ALT_NAME(PMSFCR_EL1) |
| 2429 | #define PMSFCR_EL1_op0 3 |
| 2430 | #define PMSFCR_EL1_op1 0 |
| 2431 | #define PMSFCR_EL1_CRn 9 |
| 2432 | #define PMSFCR_EL1_CRm 9 |
| 2433 | #define PMSFCR_EL1_op2 4 |
| 2434 | #define PMSFCR_FE_SHIFT 0 |
| 2435 | #define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) |
| 2436 | #define PMSFCR_FT_SHIFT 1 |
| 2437 | #define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT) |
| 2438 | #define PMSFCR_FL_SHIFT 2 |
| 2439 | #define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT) |
| 2440 | #define PMSFCR_FnE_SHIFT 3 |
| 2441 | #define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT) |
| 2442 | #define PMSFCR_B_SHIFT 16 |
| 2443 | #define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT) |
| 2444 | #define PMSFCR_LD_SHIFT 17 |
| 2445 | #define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT) |
| 2446 | #define PMSFCR_ST_SHIFT 18 |
| 2447 | #define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT) |
| 2448 | |
| 2449 | /* PMSICR_EL1 */ |
| 2450 | #define PMSICR_EL1_REG MRS_REG_ALT_NAME(PMSICR_EL1) |
| 2451 | #define PMSICR_EL1_op0 3 |
| 2452 | #define PMSICR_EL1_op1 0 |
| 2453 | #define PMSICR_EL1_CRn 9 |
| 2454 | #define PMSICR_EL1_CRm 9 |
| 2455 | #define PMSICR_EL1_op2 2 |
| 2456 | #define PMSICR_COUNT_SHIFT 0 |
| 2457 | #define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) |
| 2458 | #define PMSICR_ECOUNT_SHIFT 56 |
| 2459 | #define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT) |
| 2460 | |
| 2461 | /* PMSIDR_EL1 */ |
| 2462 | #define PMSIDR_EL1_REG MRS_REG_ALT_NAME(PMSIDR_EL1) |
| 2463 | #define PMSIDR_EL1_op0 3 |
| 2464 | #define PMSIDR_EL1_op1 0 |
| 2465 | #define PMSIDR_EL1_CRn 9 |
| 2466 | #define PMSIDR_EL1_CRm 9 |
| 2467 | #define PMSIDR_EL1_op2 7 |
| 2468 | #define PMSIDR_FE_SHIFT 0 |
| 2469 | #define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) |
| 2470 | #define PMSIDR_FT_SHIFT 1 |
| 2471 | #define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT) |
| 2472 | #define PMSIDR_FL_SHIFT 2 |
| 2473 | #define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT) |
| 2474 | #define PMSIDR_ArchInst_SHIFT 3 |
| 2475 | #define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT) |
| 2476 | #define PMSIDR_LDS_SHIFT 4 |
| 2477 | #define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT) |
| 2478 | #define PMSIDR_ERnd_SHIFT 5 |
| 2479 | #define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT) |
| 2480 | #define PMSIDR_FnE_SHIFT 6 |
| 2481 | #define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT) |
| 2482 | #define PMSIDR_Interval_SHIFT 8 |
| 2483 | #define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT) |
| 2484 | #define PMSIDR_MaxSize_SHIFT 12 |
| 2485 | #define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT) |
| 2486 | #define PMSIDR_CountSize_SHIFT 16 |
| 2487 | #define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT) |
| 2488 | #define PMSIDR_Format_SHIFT 20 |
| 2489 | #define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT) |
| 2490 | #define PMSIDR_PBT_SHIFT 24 |
| 2491 | #define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT) |
| 2492 | |
| 2493 | /* PMSIRR_EL1 */ |
| 2494 | #define PMSIRR_EL1_REG MRS_REG_ALT_NAME(PMSIRR_EL1) |
| 2495 | #define PMSIRR_EL1_op0 3 |
| 2496 | #define PMSIRR_EL1_op1 0 |
| 2497 | #define PMSIRR_EL1_CRn 9 |
| 2498 | #define PMSIRR_EL1_CRm 9 |
| 2499 | #define PMSIRR_EL1_op2 3 |
| 2500 | #define PMSIRR_RND_SHIFT 0 |
| 2501 | #define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) |
| 2502 | #define PMSIRR_INTERVAL_SHIFT 8 |
| 2503 | #define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT) |
| 2504 | |
| 2505 | /* PMSLATFR_EL1 */ |
| 2506 | #define PMSLATFR_EL1_REG MRS_REG_ALT_NAME(PMSLATFR_EL1) |
| 2507 | #define PMSLATFR_EL1_op0 3 |
| 2508 | #define PMSLATFR_EL1_op1 0 |
| 2509 | #define PMSLATFR_EL1_CRn 9 |
| 2510 | #define PMSLATFR_EL1_CRm 9 |
| 2511 | #define PMSLATFR_EL1_op2 6 |
| 2512 | #define PMSLATFR_MINLAT_SHIFT 0 |
| 2513 | #define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) |
| 2514 | |
| 2515 | /* PMSNEVFR_EL1 */ |
| 2516 | #define PMSNEVFR_EL1_REG MRS_REG_ALT_NAME(PMSNEVFR_EL1) |
| 2517 | #define PMSNEVFR_EL1_op0 3 |
| 2518 | #define PMSNEVFR_EL1_op1 0 |
| 2519 | #define PMSNEVFR_EL1_CRn 9 |
| 2520 | #define PMSNEVFR_EL1_CRm 9 |
| 2521 | #define PMSNEVFR_EL1_op2 1 |
| 2522 | |
| 2523 | /* PMSWINC_EL0 */ |
| 2524 | #define PMSWINC_EL0_op0 3 |
| 2525 | #define PMSWINC_EL0_op1 3 |
| 2526 | #define PMSWINC_EL0_CRn 9 |
| 2527 | #define PMSWINC_EL0_CRm 12 |
| 2528 | #define PMSWINC_EL0_op2 4 |
| 2529 | |
| 2530 | /* PMUSERENR_EL0 */ |
| 2531 | #define PMUSERENR_EL0_op0 3 |
| 2532 | #define PMUSERENR_EL0_op1 3 |
| 2533 | #define PMUSERENR_EL0_CRn 9 |
| 2534 | #define PMUSERENR_EL0_CRm 14 |
| 2535 | #define PMUSERENR_EL0_op2 0 |
| 2536 | |
| 2537 | /* PMXEVCNTR_EL0 */ |
| 2538 | #define PMXEVCNTR_EL0_op0 3 |
| 2539 | #define PMXEVCNTR_EL0_op1 3 |
| 2540 | #define PMXEVCNTR_EL0_CRn 9 |
| 2541 | #define PMXEVCNTR_EL0_CRm 13 |
| 2542 | #define PMXEVCNTR_EL0_op2 2 |
| 2543 | |
| 2544 | /* PMXEVTYPER_EL0 */ |
| 2545 | #define PMXEVTYPER_EL0_op0 3 |
| 2546 | #define PMXEVTYPER_EL0_op1 3 |
| 2547 | #define PMXEVTYPER_EL0_CRn 9 |
| 2548 | #define PMXEVTYPER_EL0_CRm 13 |
| 2549 | #define PMXEVTYPER_EL0_op2 1 |
| 2550 | |
| 2551 | /* RNDRRS */ |
| 2552 | #define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS) |
| 2553 | #define RNDRRS_op0 3 |
| 2554 | #define RNDRRS_op1 3 |
| 2555 | #define RNDRRS_CRn 2 |
| 2556 | #define RNDRRS_CRm 4 |
| 2557 | #define RNDRRS_op2 1 |
| 2558 | |
| 2559 | /* SCTLR_EL1 - System Control Register */ |
| 2560 | #define SCTLR_EL1_REG MRS_REG_ALT_NAME(SCTLR_EL1) |
| 2561 | #define SCTLR_EL1_op0 3 |
| 2562 | #define SCTLR_EL1_op1 0 |
| 2563 | #define SCTLR_EL1_CRn 1 |
| 2564 | #define SCTLR_EL1_CRm 0 |
| 2565 | #define SCTLR_EL1_op2 0 |
| 2566 | #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ |
| 2567 | #define SCTLR_M (UL(0x1) << 0) |
| 2568 | #define SCTLR_A (UL(0x1) << 1) |
| 2569 | #define SCTLR_C (UL(0x1) << 2) |
| 2570 | #define SCTLR_SA (UL(0x1) << 3) |
| 2571 | #define SCTLR_SA0 (UL(0x1) << 4) |
| 2572 | #define SCTLR_CP15BEN (UL(0x1) << 5) |
| 2573 | #define SCTLR_nAA (UL(0x1) << 6) |
| 2574 | #define SCTLR_ITD (UL(0x1) << 7) |
| 2575 | #define SCTLR_SED (UL(0x1) << 8) |
| 2576 | #define SCTLR_UMA (UL(0x1) << 9) |
| 2577 | #define SCTLR_EnRCTX (UL(0x1) << 10) |
| 2578 | #define SCTLR_EOS (UL(0x1) << 11) |
| 2579 | #define SCTLR_I (UL(0x1) << 12) |
| 2580 | #define SCTLR_EnDB (UL(0x1) << 13) |
| 2581 | #define SCTLR_DZE (UL(0x1) << 14) |
| 2582 | #define SCTLR_UCT (UL(0x1) << 15) |
| 2583 | #define SCTLR_nTWI (UL(0x1) << 16) |
| 2584 | /* Bit 17 is reserved */ |
| 2585 | #define SCTLR_nTWE (UL(0x1) << 18) |
| 2586 | #define SCTLR_WXN (UL(0x1) << 19) |
| 2587 | #define SCTLR_TSCXT (UL(0x1) << 20) |
| 2588 | #define SCTLR_IESB (UL(0x1) << 21) |
| 2589 | #define SCTLR_EIS (UL(0x1) << 22) |
| 2590 | #define SCTLR_SPAN (UL(0x1) << 23) |
| 2591 | #define SCTLR_E0E (UL(0x1) << 24) |
| 2592 | #define SCTLR_EE (UL(0x1) << 25) |
| 2593 | #define SCTLR_UCI (UL(0x1) << 26) |
| 2594 | #define SCTLR_EnDA (UL(0x1) << 27) |
| 2595 | #define SCTLR_nTLSMD (UL(0x1) << 28) |
| 2596 | #define SCTLR_LSMAOE (UL(0x1) << 29) |
| 2597 | #define SCTLR_EnIB (UL(0x1) << 30) |
| 2598 | #define SCTLR_EnIA (UL(0x1) << 31) |
| 2599 | /* Bits 34:32 are reserved */ |
| 2600 | #define SCTLR_BT0 (UL(0x1) << 35) |
| 2601 | #define SCTLR_BT1 (UL(0x1) << 36) |
| 2602 | #define SCTLR_ITFSB (UL(0x1) << 37) |
| 2603 | #define SCTLR_TCF0_MASK (UL(0x3) << 38) |
| 2604 | #define SCTLR_TCF_MASK (UL(0x3) << 40) |
| 2605 | #define SCTLR_ATA0 (UL(0x1) << 42) |
| 2606 | #define SCTLR_ATA (UL(0x1) << 43) |
| 2607 | #define SCTLR_DSSBS (UL(0x1) << 44) |
| 2608 | #define SCTLR_TWEDEn (UL(0x1) << 45) |
| 2609 | #define SCTLR_TWEDEL_MASK (UL(0xf) << 46) |
| 2610 | /* Bits 53:50 are reserved */ |
| 2611 | #define SCTLR_EnASR (UL(0x1) << 54) |
| 2612 | #define SCTLR_EnAS0 (UL(0x1) << 55) |
| 2613 | #define SCTLR_EnALS (UL(0x1) << 56) |
| 2614 | #define SCTLR_EPAN (UL(0x1) << 57) |
| 2615 | |
| 2616 | #define SCTLR_MMU_OFF \ |
| 2617 | (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | SCTLR_TSCXT | SCTLR_EOS) |
| 2618 | #define SCTLR_MMU_ON \ |
| 2619 | (SCTLR_MMU_OFF | \ |
| 2620 | SCTLR_BT1 | \ |
| 2621 | SCTLR_BT0 | \ |
| 2622 | SCTLR_UCI | \ |
| 2623 | SCTLR_SPAN | \ |
| 2624 | SCTLR_nTWE | \ |
| 2625 | SCTLR_nTWI | \ |
| 2626 | SCTLR_UCT | \ |
| 2627 | SCTLR_DZE | \ |
| 2628 | SCTLR_I | \ |
| 2629 | SCTLR_SED | \ |
| 2630 | SCTLR_CP15BEN | \ |
| 2631 | SCTLR_SA0 | \ |
| 2632 | SCTLR_SA | \ |
| 2633 | SCTLR_C | \ |
| 2634 | SCTLR_M) |
| 2635 | |
| 2636 | /* SCTLR_EL12 */ |
| 2637 | #define SCTLR_EL12_REG MRS_REG_ALT_NAME(SCTLR_EL12) |
| 2638 | #define SCTLR_EL12_op0 3 |
| 2639 | #define SCTLR_EL12_op1 5 |
| 2640 | #define SCTLR_EL12_CRn 1 |
| 2641 | #define SCTLR_EL12_CRm 0 |
| 2642 | #define SCTLR_EL12_op2 0 |
| 2643 | |
| 2644 | /* SPSR_EL1 */ |
| 2645 | #define SPSR_EL1_REG MRS_REG_ALT_NAME(SPSR_EL1) |
| 2646 | #define SPSR_EL1_op0 3 |
| 2647 | #define SPSR_EL1_op1 0 |
| 2648 | #define SPSR_EL1_CRn 4 |
| 2649 | #define SPSR_EL1_CRm 0 |
| 2650 | #define SPSR_EL1_op2 0 |
| 2651 | /* |
| 2652 | * When the exception is taken in AArch64: |
| 2653 | * M[3:2] is the exception level |
| 2654 | * M[1] is unused |
| 2655 | * M[0] is the SP select: |
| 2656 | * 0: always SP0 |
| 2657 | * 1: current ELs SP |
| 2658 | */ |
| 2659 | #define PSR_M_EL0t 0x00000000UL |
| 2660 | #define PSR_M_EL1t 0x00000004UL |
| 2661 | #define PSR_M_EL1h 0x00000005UL |
| 2662 | #define PSR_M_EL2t 0x00000008UL |
| 2663 | #define PSR_M_EL2h 0x00000009UL |
| 2664 | #define PSR_M_64 0x00000000UL |
| 2665 | #define PSR_M_32 0x00000010UL |
| 2666 | #define PSR_M_MASK 0x0000000fUL |
| 2667 | |
| 2668 | #define PSR_T 0x00000020UL |
| 2669 | |
| 2670 | #define PSR_AARCH32 0x00000010UL |
| 2671 | #define PSR_F 0x00000040UL |
| 2672 | #define PSR_I 0x00000080UL |
| 2673 | #define PSR_A 0x00000100UL |
| 2674 | #define PSR_D 0x00000200UL |
| 2675 | #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) |
| 2676 | /* The default DAIF mask. These bits are valid in spsr_el1 and daif */ |
| 2677 | #define PSR_DAIF_DEFAULT (0) |
| 2678 | #define PSR_DAIF_INTR (PSR_I | PSR_F) |
| 2679 | #define PSR_BTYPE 0x00000c00UL |
| 2680 | #define PSR_SSBS 0x00001000UL |
| 2681 | #define PSR_ALLINT 0x00002000UL |
| 2682 | #define PSR_IL 0x00100000UL |
| 2683 | #define PSR_SS 0x00200000UL |
| 2684 | #define PSR_PAN 0x00400000UL |
| 2685 | #define PSR_UAO 0x00800000UL |
| 2686 | #define PSR_DIT 0x01000000UL |
| 2687 | #define PSR_TCO 0x02000000UL |
| 2688 | #define PSR_V 0x10000000UL |
| 2689 | #define PSR_C 0x20000000UL |
| 2690 | #define PSR_Z 0x40000000UL |
| 2691 | #define PSR_N 0x80000000UL |
| 2692 | #define PSR_FLAGS 0xf0000000UL |
| 2693 | /* PSR fields that can be set from 32-bit and 64-bit processes */ |
| 2694 | #define PSR_SETTABLE_32 PSR_FLAGS |
| 2695 | #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) |
| 2696 | |
| 2697 | /* SPSR_EL12 */ |
| 2698 | #define SPSR_EL12_REG MRS_REG_ALT_NAME(SPSR_EL12) |
| 2699 | #define SPSR_EL12_op0 3 |
| 2700 | #define SPSR_EL12_op1 5 |
| 2701 | #define SPSR_EL12_CRn 4 |
| 2702 | #define SPSR_EL12_CRm 0 |
| 2703 | #define SPSR_EL12_op2 0 |
| 2704 | |
| 2705 | /* REVIDR_EL1 - Revision ID Register */ |
| 2706 | #define REVIDR_EL1_op0 3 |
| 2707 | #define REVIDR_EL1_op1 0 |
| 2708 | #define REVIDR_EL1_CRn 0 |
| 2709 | #define REVIDR_EL1_CRm 0 |
| 2710 | #define REVIDR_EL1_op2 6 |
| 2711 | |
| 2712 | /* TCR_EL1 - Translation Control Register */ |
| 2713 | #define TCR_EL1_REG MRS_REG_ALT_NAME(TCR_EL1) |
| 2714 | #define TCR_EL1_op0 3 |
| 2715 | #define TCR_EL1_op1 0 |
| 2716 | #define TCR_EL1_CRn 2 |
| 2717 | #define TCR_EL1_CRm 0 |
| 2718 | #define TCR_EL1_op2 2 |
| 2719 | /* Bits 63:59 are reserved */ |
| 2720 | #define TCR_DS_SHIFT 59 |
| 2721 | #define TCR_DS (UL(1) << TCR_DS_SHIFT) |
| 2722 | #define TCR_TCMA1_SHIFT 58 |
| 2723 | #define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT) |
| 2724 | #define TCR_TCMA0_SHIFT 57 |
| 2725 | #define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT) |
| 2726 | #define TCR_E0PD1_SHIFT 56 |
| 2727 | #define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT) |
| 2728 | #define TCR_E0PD0_SHIFT 55 |
| 2729 | #define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT) |
| 2730 | #define TCR_NFD1_SHIFT 54 |
| 2731 | #define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT) |
| 2732 | #define TCR_NFD0_SHIFT 53 |
| 2733 | #define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT) |
| 2734 | #define TCR_TBID1_SHIFT 52 |
| 2735 | #define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT) |
| 2736 | #define TCR_TBID0_SHIFT 51 |
| 2737 | #define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT) |
| 2738 | #define TCR_HWU162_SHIFT 50 |
| 2739 | #define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT) |
| 2740 | #define TCR_HWU161_SHIFT 49 |
| 2741 | #define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT) |
| 2742 | #define TCR_HWU160_SHIFT 48 |
| 2743 | #define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT) |
| 2744 | #define TCR_HWU159_SHIFT 47 |
| 2745 | #define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT) |
| 2746 | #define TCR_HWU1 \ |
| 2747 | (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) |
| 2748 | #define TCR_HWU062_SHIFT 46 |
| 2749 | #define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT) |
| 2750 | #define TCR_HWU061_SHIFT 45 |
| 2751 | #define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT) |
| 2752 | #define TCR_HWU060_SHIFT 44 |
| 2753 | #define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT) |
| 2754 | #define TCR_HWU059_SHIFT 43 |
| 2755 | #define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT) |
| 2756 | #define TCR_HWU0 \ |
| 2757 | (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) |
| 2758 | #define TCR_HPD1_SHIFT 42 |
| 2759 | #define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT) |
| 2760 | #define TCR_HPD0_SHIFT 41 |
| 2761 | #define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT) |
| 2762 | #define TCR_HD_SHIFT 40 |
| 2763 | #define TCR_HD (UL(1) << TCR_HD_SHIFT) |
| 2764 | #define TCR_HA_SHIFT 39 |
| 2765 | #define TCR_HA (UL(1) << TCR_HA_SHIFT) |
| 2766 | #define TCR_TBI1_SHIFT 38 |
| 2767 | #define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT) |
| 2768 | #define TCR_TBI0_SHIFT 37 |
| 2769 | #define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT) |
| 2770 | #define TCR_ASID_SHIFT 36 |
| 2771 | #define TCR_ASID_WIDTH 1 |
| 2772 | #define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT) |
| 2773 | /* Bit 35 is reserved */ |
| 2774 | #define TCR_IPS_SHIFT 32 |
| 2775 | #define TCR_IPS_WIDTH 3 |
| 2776 | #define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT) |
| 2777 | #define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT) |
| 2778 | #define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT) |
| 2779 | #define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT) |
| 2780 | #define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT) |
| 2781 | #define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT) |
| 2782 | #define TCR_TG1_SHIFT 30 |
| 2783 | #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) |
| 2784 | #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) |
| 2785 | #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) |
| 2786 | #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) |
| 2787 | #define TCR_SH1_SHIFT 28 |
| 2788 | #define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT) |
| 2789 | #define TCR_ORGN1_SHIFT 26 |
| 2790 | #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) |
| 2791 | #define TCR_IRGN1_SHIFT 24 |
| 2792 | #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) |
| 2793 | #define TCR_EPD1_SHIFT 23 |
| 2794 | #define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT) |
| 2795 | #define TCR_A1_SHIFT 22 |
| 2796 | #define TCR_A1 (UL(1) << TCR_A1_SHIFT) |
| 2797 | #define TCR_T1SZ_SHIFT 16 |
| 2798 | #define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT) |
| 2799 | #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) |
| 2800 | #define TCR_TG0_SHIFT 14 |
| 2801 | #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) |
| 2802 | #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) |
| 2803 | #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) |
| 2804 | #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) |
| 2805 | #define TCR_SH0_SHIFT 12 |
| 2806 | #define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT) |
| 2807 | #define TCR_ORGN0_SHIFT 10 |
| 2808 | #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) |
| 2809 | #define TCR_IRGN0_SHIFT 8 |
| 2810 | #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) |
| 2811 | #define TCR_EPD0_SHIFT 7 |
| 2812 | #define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT) |
| 2813 | /* Bit 6 is reserved */ |
| 2814 | #define TCR_T0SZ_SHIFT 0 |
| 2815 | #define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT) |
| 2816 | #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) |
| 2817 | #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) |
| 2818 | |
| 2819 | /* TCR_EL12 */ |
| 2820 | #define TCR_EL12_REG MRS_REG_ALT_NAME(TCR_EL12) |
| 2821 | #define TCR_EL12_op0 3 |
| 2822 | #define TCR_EL12_op1 5 |
| 2823 | #define TCR_EL12_CRn 2 |
| 2824 | #define TCR_EL12_CRm 0 |
| 2825 | #define TCR_EL12_op2 2 |
| 2826 | |
| 2827 | /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ |
| 2828 | #define TTBR_ASID_SHIFT 48 |
| 2829 | #define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) |
| 2830 | #define TTBR_BADDR 0x0000fffffffffffeul |
| 2831 | #define TTBR_CnP_SHIFT 0 |
| 2832 | #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) |
| 2833 | |
| 2834 | /* TTBR0_EL1 */ |
| 2835 | #define TTBR0_EL1_REG MRS_REG_ALT_NAME(TTBR0_EL1) |
| 2836 | #define TTBR0_EL1_op0 3 |
| 2837 | #define TTBR0_EL1_op1 0 |
| 2838 | #define TTBR0_EL1_CRn 2 |
| 2839 | #define TTBR0_EL1_CRm 0 |
| 2840 | #define TTBR0_EL1_op2 0 |
| 2841 | |
| 2842 | /* TTBR0_EL12 */ |
| 2843 | #define TTBR0_EL12_REG MRS_REG_ALT_NAME(TTBR0_EL12) |
| 2844 | #define TTBR0_EL12_op0 3 |
| 2845 | #define TTBR0_EL12_op1 5 |
| 2846 | #define TTBR0_EL12_CRn 2 |
| 2847 | #define TTBR0_EL12_CRm 0 |
| 2848 | #define TTBR0_EL12_op2 0 |
| 2849 | |
| 2850 | /* TTBR1_EL1 */ |
| 2851 | #define TTBR1_EL1_REG MRS_REG_ALT_NAME(TTBR1_EL1) |
| 2852 | #define TTBR1_EL1_op0 3 |
| 2853 | #define TTBR1_EL1_op1 0 |
| 2854 | #define TTBR1_EL1_CRn 2 |
| 2855 | #define TTBR1_EL1_CRm 0 |
| 2856 | #define TTBR1_EL1_op2 1 |
| 2857 | |
| 2858 | /* TTBR1_EL12 */ |
| 2859 | #define TTBR1_EL12_REG MRS_REG_ALT_NAME(TTBR1_EL12) |
| 2860 | #define TTBR1_EL12_op0 3 |
| 2861 | #define TTBR1_EL12_op1 5 |
| 2862 | #define TTBR1_EL12_CRn 2 |
| 2863 | #define TTBR1_EL12_CRm 0 |
| 2864 | #define TTBR1_EL12_op2 1 |
| 2865 | |
| 2866 | /* VBAR_EL1 */ |
| 2867 | #define VBAR_EL1_REG MRS_REG_ALT_NAME(VBAR_EL1) |
| 2868 | #define VBAR_EL1_op0 3 |
| 2869 | #define VBAR_EL1_op1 0 |
| 2870 | #define VBAR_EL1_CRn 12 |
| 2871 | #define VBAR_EL1_CRm 0 |
| 2872 | #define VBAR_EL1_op2 0 |
| 2873 | |
| 2874 | /* VBAR_EL12 */ |
| 2875 | #define VBAR_EL12_REG MRS_REG_ALT_NAME(VBAR_EL12) |
| 2876 | #define VBAR_EL12_op0 3 |
| 2877 | #define VBAR_EL12_op1 5 |
| 2878 | #define VBAR_EL12_CRn 12 |
| 2879 | #define VBAR_EL12_CRm 0 |
| 2880 | #define VBAR_EL12_op2 0 |
| 2881 | |
| 2882 | /* ZCR_EL1 - SVE Control Register */ |
| 2883 | #define ZCR_EL1_REG MRS_REG_ALT_NAME(ZCR_EL1) |
| 2884 | #define ZCR_EL1_op0 3 |
| 2885 | #define ZCR_EL1_op1 0 |
| 2886 | #define ZCR_EL1_CRn 1 |
| 2887 | #define ZCR_EL1_CRm 2 |
| 2888 | #define ZCR_EL1_op2 0 |
| 2889 | #define ZCR_LEN_SHIFT 0 |
| 2890 | #define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) |
| 2891 | #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) |
| 2892 | |
| 2893 | #endif /* !_MACHINE_ARMREG_H_ */ |
| 2894 | |
| 2895 | #endif /* !__arm__ */ |