1/* $OpenBSD: pte.h,v 1.10 2024/10/14 12:02:16 jsg Exp $ */
2/*
3 * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17#ifndef _ARM_PTE_H_
18#define _ARM_PTE_H_
19
20/* level X descriptor */
21#define Lx_TYPE_MASK (0x00000003) /* mask of type bits */
22#define Lx_TYPE_S (0x00000001)
23#define Lx_TYPE_PT (0x00000003)
24// XXX need to investigate use of these
25#define Lx_PT_NS (1ULL<<63)
26#define Lx_PT_AP00 (0ULL<<61)
27#define Lx_PT_AP01 (1ULL<<61)
28#define Lx_PT_AP10 (2ULL<<61)
29#define Lx_PT_AP11 (3ULL<<61)
30#define Lx_PT_XN (1ULL<<60)
31#define Lx_PT_PXN (1ULL<<59)
32#define Lx_TABLE_ALIGN (4096)
33
34/* Block and Page attributes */
35/* TODO: Add the upper attributes */
36#define ATTR_MASK_H (0xfff0000000000000ULL)
37#define ATTR_MASK_L (0x0000000000000fffULL)
38#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
39/* Bits 58:55 are reserved for software */
40#define ATTR_SW_MANAGED (1UL << 56)
41#define ATTR_SW_WIRED (1UL << 55)
42#define ATTR_UXN (1UL << 54)
43#define ATTR_PXN (1UL << 53)
44#define ATTR_GP (1UL << 50)
45#define ATTR_nG (1 << 11)
46#define ATTR_AF (1 << 10)
47#define ATTR_SH(x) ((x) << 8)
48#define ATTR_AP_RW_BIT (1 << 7)
49#define ATTR_AP(x) ((x) << 6)
50#define ATTR_AP_MASK ATTR_AP(3)
51#define ATTR_NS (1 << 5)
52#define ATTR_IDX(x) ((x) << 2)
53#define ATTR_IDX_MASK (7 << 2)
54
55#define PTE_ATTR_DEV_NGNRNE 0
56#define PTE_ATTR_DEV_NGNRE 1
57#define PTE_ATTR_CI 2
58#define PTE_ATTR_WB 3
59#define PTE_ATTR_WT 4
60
61#define PTE_MEMATTR_DEV_NGNRNE 0x0
62#define PTE_MEMATTR_DEV_NGNRE 0x1
63#define PTE_MEMATTR_CI 0x5
64#define PTE_MEMATTR_WB 0xf
65#define PTE_MEMATTR_WT 0xa
66
67#define SH_INNER 3
68#define SH_OUTER 2
69#define SH_NONE 0
70
71/* Level 0 table, 512GiB per entry */
72#define L0_SHIFT 39
73#define L0_INVAL 0x0 /* An invalid address */
74#define L0_BLOCK 0x1 /* A block */
75 /* 0x2 also marks an invalid address */
76#define L0_TABLE 0x3 /* A next-level table */
77
78/* Level 1 table, 1GiB per entry */
79#define L1_SHIFT 30
80#define L1_SIZE (1 << L1_SHIFT)
81#define L1_OFFSET (L1_SIZE - 1)
82#define L1_INVAL L0_INVAL
83#define L1_BLOCK L0_BLOCK
84#define L1_TABLE L0_TABLE
85
86/* Level 2 table, 2MiB per entry */
87#define L2_SHIFT 21
88#define L2_SIZE (1 << L2_SHIFT)
89#define L2_OFFSET (L2_SIZE - 1)
90#define L2_INVAL L0_INVAL
91#define L2_BLOCK L0_BLOCK
92#define L2_TABLE L0_TABLE
93
94/* page mapping */
95#define L3_P 0x3
96
97#define Ln_ENTRIES (1 << 9)
98#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
99#define Ln_TABLE_MASK ((1 << 12) - 1)
100
101/* physical page mask */
102#define PTE_RPGN (((1ULL << 48) - 1) & ~PAGE_MASK)
103
104#endif /* _ARM_PTE_H_ */