| 1 | /* $OpenBSD: armreg.h,v 1.44 2025/07/22 09:20:41 kettenis Exp $ */ |
| 2 | /*- |
| 3 | * Copyright (c) 2013, 2014 Andrew Turner |
| 4 | * Copyright (c) 2015 The FreeBSD Foundation |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This software was developed by Andrew Turner under |
| 8 | * sponsorship from the FreeBSD Foundation. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | * |
| 31 | * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ |
| 32 | */ |
| 33 | |
| 34 | #ifndef _MACHINE_ARMREG_H_ |
| 35 | #define _MACHINE_ARMREG_H_ |
| 36 | |
| 37 | #define INSN_SIZE 4 |
| 38 | |
| 39 | #define READ_SPECIALREG(reg) \ |
| 40 | ({ uint64_t val; \ |
| 41 | __asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ |
| 42 | val; \ |
| 43 | }) |
| 44 | #define WRITE_SPECIALREG(reg, val) \ |
| 45 | __asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) |
| 46 | |
| 47 | /* CCSIDR_EL1 - Current Cache Size ID Register */ |
| 48 | #define CCSIDR_SETS_MASK 0x0fffe000 |
| 49 | #define CCSIDR_SETS_SHIFT 13 |
| 50 | #define CCSIDR_SETS(reg) \ |
| 51 | ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) |
| 52 | #define CCSIDR_WAYS_MASK 0x00001ff8 |
| 53 | #define CCSIDR_WAYS_SHIFT 3 |
| 54 | #define CCSIDR_WAYS(reg) \ |
| 55 | ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) |
| 56 | #define CCSIDR_LINE_MASK 0x00000007 |
| 57 | #define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) |
| 58 | |
| 59 | #define CCSIDR_CCIDX_SETS_MASK 0x00ffffff00000000ULL |
| 60 | #define CCSIDR_CCIDX_SETS_SHIFT 32 |
| 61 | #define CCSIDR_CCIDX_SETS(reg) \ |
| 62 | ((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1) |
| 63 | #define CCSIDR_CCIDX_WAYS_MASK 0x0000000000fffff8ULL |
| 64 | #define CCSIDR_CCIDX_WAYS_SHIFT 3 |
| 65 | #define CCSIDR_CCIDX_WAYS(reg) \ |
| 66 | ((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1) |
| 67 | #define CCSIDR_CCIDX_LINE_MASK 0x0000000000000007ULL |
| 68 | #define CCSIDR_CCIDX_LINE_SIZE(reg) \ |
| 69 | (1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4)) |
| 70 | |
| 71 | /* CLIDR_EL1 - Cache Level ID Register */ |
| 72 | #define CLIDR_CTYPE_MASK 0x7 |
| 73 | #define CLIDR_CTYPE_INSN 0x1 |
| 74 | #define CLIDR_CTYPE_DATA 0x2 |
| 75 | #define CLIDR_CTYPE_UNIFIED 0x4 |
| 76 | |
| 77 | /* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ |
| 78 | #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ |
| 79 | #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ |
| 80 | #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ |
| 81 | #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ |
| 82 | #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ |
| 83 | |
| 84 | /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ |
| 85 | #define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ |
| 86 | |
| 87 | /* CNTV_CTL_EL0 */ |
| 88 | #define CNTV_CTL_ENABLE (1 << 0) |
| 89 | #define CNTV_CTL_IMASK (1 << 1) |
| 90 | #define CNTV_CTL_ISTATUS (1 << 2) |
| 91 | |
| 92 | /* CPACR_EL1 */ |
| 93 | #define CPACR_ZEN_MASK (0x3 << 16) |
| 94 | #define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ |
| 95 | #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ |
| 96 | #define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ |
| 97 | #define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ |
| 98 | #define CPACR_FPEN_MASK (0x3 << 20) |
| 99 | #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ |
| 100 | #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ |
| 101 | #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ |
| 102 | #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ |
| 103 | #define CPACR_TTA (0x1 << 28) |
| 104 | |
| 105 | /* CSSELR_EL1 - Cache Size Selection Register */ |
| 106 | #define CSSELR_IND (1 << 0) |
| 107 | #define CSSELR_LEVEL_SHIFT 1 |
| 108 | |
| 109 | /* CTR_EL0 - Cache Type Register */ |
| 110 | #define CTR_DLINE_SHIFT 16 |
| 111 | #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) |
| 112 | #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) |
| 113 | #define CTR_IL1P_SHIFT 14 |
| 114 | #define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) |
| 115 | #define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) |
| 116 | #define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) |
| 117 | #define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) |
| 118 | #define CTR_ILINE_SHIFT 0 |
| 119 | #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) |
| 120 | #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) |
| 121 | |
| 122 | /* MPIDR_EL1 - Multiprocessor Affinity Register */ |
| 123 | #define MPIDR_AFF3 (0xFFULL << 32) |
| 124 | #define MPIDR_AFF2 (0xFFULL << 16) |
| 125 | #define MPIDR_AFF1 (0xFFULL << 8) |
| 126 | #define MPIDR_AFF0 (0xFFULL << 0) |
| 127 | #define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) |
| 128 | |
| 129 | /* DCZID_EL0 - Data Cache Zero ID register */ |
| 130 | #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ |
| 131 | #define DCZID_BS_SHIFT 0 |
| 132 | #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) |
| 133 | #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) |
| 134 | |
| 135 | /* ESR_ELx */ |
| 136 | #define ESR_ELx_ISS_MASK 0x00ffffff |
| 137 | #define ISS_INSN_FnV (0x01 << 10) |
| 138 | #define ISS_INSN_EA (0x01 << 9) |
| 139 | #define ISS_INSN_S1PTW (0x01 << 7) |
| 140 | #define ISS_INSN_IFSC_MASK (0x1f << 0) |
| 141 | #define ISS_DATA_ISV (0x01 << 24) |
| 142 | #define ISS_DATA_SAS_MASK (0x03 << 22) |
| 143 | #define ISS_DATA_SSE (0x01 << 21) |
| 144 | #define ISS_DATA_SRT_MASK (0x1f << 16) |
| 145 | #define ISS_DATA_SF (0x01 << 15) |
| 146 | #define ISS_DATA_AR (0x01 << 14) |
| 147 | #define ISS_DATA_FnV (0x01 << 10) |
| 148 | #define ISS_DATA_EA (0x01 << 9) |
| 149 | #define ISS_DATA_CM (0x01 << 8) |
| 150 | #define ISS_DATA_S1PTW (0x01 << 7) |
| 151 | #define ISS_DATA_WnR (0x01 << 6) |
| 152 | #define ISS_DATA_DFSC_MASK (0x3f << 0) |
| 153 | #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) |
| 154 | #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) |
| 155 | #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) |
| 156 | #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) |
| 157 | #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) |
| 158 | #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) |
| 159 | #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) |
| 160 | #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) |
| 161 | #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) |
| 162 | #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) |
| 163 | #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) |
| 164 | #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) |
| 165 | #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) |
| 166 | #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) |
| 167 | #define ISS_DATA_DFSC_EXT (0x10 << 0) |
| 168 | #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) |
| 169 | #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) |
| 170 | #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) |
| 171 | #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) |
| 172 | #define ISS_DATA_DFSC_ECC (0x18 << 0) |
| 173 | #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) |
| 174 | #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) |
| 175 | #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) |
| 176 | #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) |
| 177 | #define ISS_DATA_DFSC_ALIGN (0x21 << 0) |
| 178 | #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) |
| 179 | #define ISS_MSR_DIR_SHIFT 0 |
| 180 | #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) |
| 181 | #define ISS_MSR_Rt_SHIFT 5 |
| 182 | #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) |
| 183 | #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) |
| 184 | #define ISS_MSR_CRm_SHIFT 1 |
| 185 | #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) |
| 186 | #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) |
| 187 | #define ISS_MSR_CRn_SHIFT 10 |
| 188 | #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) |
| 189 | #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) |
| 190 | #define ISS_MSR_OP1_SHIFT 14 |
| 191 | #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) |
| 192 | #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) |
| 193 | #define ISS_MSR_OP2_SHIFT 17 |
| 194 | #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) |
| 195 | #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) |
| 196 | #define ISS_MSR_OP0_SHIFT 20 |
| 197 | #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) |
| 198 | #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) |
| 199 | #define ISS_BRK_COMMENT_MASK 0xffff |
| 200 | #define ESR_ELx_IL (0x01 << 25) |
| 201 | #define ESR_ELx_EC_SHIFT 26 |
| 202 | #define ESR_ELx_EC_MASK (0x3f << 26) |
| 203 | #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) |
| 204 | #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ |
| 205 | #define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */ |
| 206 | #define EXCP_BRANCH_TGT 0x0d /* Branch target exception */ |
| 207 | #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ |
| 208 | #define EXCP_SVC 0x15 /* SVC trap */ |
| 209 | #define EXCP_MSR 0x18 /* MSR/MRS trap */ |
| 210 | #define EXCP_SVE 0x19 /* SVE trap */ |
| 211 | #define EXCP_FPAC 0x1c /* Faulting PAC trap */ |
| 212 | #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ |
| 213 | #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ |
| 214 | #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ |
| 215 | #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ |
| 216 | #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ |
| 217 | #define EXCP_SP_ALIGN 0x26 /* SP alignment fault */ |
| 218 | #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ |
| 219 | #define EXCP_SERROR 0x2f /* SError interrupt */ |
| 220 | #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ |
| 221 | #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ |
| 222 | #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ |
| 223 | #define EXCP_BRK 0x3c /* Breakpoint */ |
| 224 | |
| 225 | /* ICC_CTLR_EL1 */ |
| 226 | #define ICC_CTLR_EL1_EOIMODE (1U << 1) |
| 227 | #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 |
| 228 | #define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8) |
| 229 | #define ICC_CTLR_EL1_PRIBITS(reg) \ |
| 230 | (((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) |
| 231 | |
| 232 | /* ICC_IAR1_EL1 */ |
| 233 | #define ICC_IAR1_EL1_SPUR (0x03ff) |
| 234 | |
| 235 | /* ICC_IGRPEN0_EL1 */ |
| 236 | #define ICC_IGRPEN0_EL1_EN (1U << 0) |
| 237 | |
| 238 | /* ICC_PMR_EL1 */ |
| 239 | #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) |
| 240 | |
| 241 | /* ICC_SGI1R_EL1 */ |
| 242 | #define ICC_SGI1R_EL1_TL_MASK 0xffffUL |
| 243 | #define ICC_SGI1R_EL1_AFF1_SHIFT 16 |
| 244 | #define ICC_SGI1R_EL1_SGIID_SHIFT 24 |
| 245 | #define ICC_SGI1R_EL1_AFF2_SHIFT 32 |
| 246 | #define ICC_SGI1R_EL1_AFF3_SHIFT 48 |
| 247 | #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL |
| 248 | #define ICC_SGI1R_EL1_IRM (0x1UL << 40) |
| 249 | |
| 250 | /* ICC_SRE_EL1 */ |
| 251 | #define ICC_SRE_EL1_SRE (1U << 0) |
| 252 | |
| 253 | /* ICC_SRE_EL2 */ |
| 254 | #define ICC_SRE_EL2_SRE (1U << 0) |
| 255 | #define ICC_SRE_EL2_EN (1U << 3) |
| 256 | |
| 257 | /* ID_AA64DFR0_EL1 */ |
| 258 | #define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL |
| 259 | #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 |
| 260 | #define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT) |
| 261 | #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) |
| 262 | #define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) |
| 263 | #define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) |
| 264 | #define ID_AA64DFR0_TRACE_VER_SHIFT 4 |
| 265 | #define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT) |
| 266 | #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) |
| 267 | #define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT) |
| 268 | #define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT) |
| 269 | #define ID_AA64DFR0_PMU_VER_SHIFT 8 |
| 270 | #define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) |
| 271 | #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) |
| 272 | #define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT) |
| 273 | #define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT) |
| 274 | #define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT) |
| 275 | #define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) |
| 276 | #define ID_AA64DFR0_BRPS_SHIFT 12 |
| 277 | #define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT) |
| 278 | #define ID_AA64DFR0_BRPS(x) \ |
| 279 | ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) |
| 280 | #define ID_AA64DFR0_WRPS_SHIFT 20 |
| 281 | #define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT) |
| 282 | #define ID_AA64DFR0_WRPS(x) \ |
| 283 | ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) |
| 284 | #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 |
| 285 | #define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT) |
| 286 | #define ID_AA64DFR0_CTX_CMPS(x) \ |
| 287 | ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) |
| 288 | |
| 289 | /* ID_AA64ISAR0_EL1 */ |
| 290 | #define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL |
| 291 | #define ID_AA64ISAR0_AES_SHIFT 4 |
| 292 | #define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT) |
| 293 | #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) |
| 294 | #define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT) |
| 295 | #define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT) |
| 296 | #define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT) |
| 297 | #define ID_AA64ISAR0_SHA1_SHIFT 8 |
| 298 | #define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT) |
| 299 | #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) |
| 300 | #define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT) |
| 301 | #define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT) |
| 302 | #define ID_AA64ISAR0_SHA2_SHIFT 12 |
| 303 | #define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT) |
| 304 | #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) |
| 305 | #define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT) |
| 306 | #define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT) |
| 307 | #define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT) |
| 308 | #define ID_AA64ISAR0_CRC32_SHIFT 16 |
| 309 | #define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT) |
| 310 | #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) |
| 311 | #define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT) |
| 312 | #define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT) |
| 313 | #define ID_AA64ISAR0_ATOMIC_SHIFT 20 |
| 314 | #define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT) |
| 315 | #define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) |
| 316 | #define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT) |
| 317 | #define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT) |
| 318 | #define ID_AA64ISAR0_RDM_SHIFT 28 |
| 319 | #define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT) |
| 320 | #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) |
| 321 | #define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT) |
| 322 | #define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT) |
| 323 | #define ID_AA64ISAR0_SHA3_SHIFT 32 |
| 324 | #define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) |
| 325 | #define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) |
| 326 | #define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT) |
| 327 | #define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT) |
| 328 | #define ID_AA64ISAR0_SM3_SHIFT 36 |
| 329 | #define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT) |
| 330 | #define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) |
| 331 | #define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT) |
| 332 | #define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT) |
| 333 | #define ID_AA64ISAR0_SM4_SHIFT 40 |
| 334 | #define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT) |
| 335 | #define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) |
| 336 | #define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT) |
| 337 | #define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT) |
| 338 | #define ID_AA64ISAR0_DP_SHIFT 44 |
| 339 | #define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT) |
| 340 | #define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) |
| 341 | #define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT) |
| 342 | #define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT) |
| 343 | #define ID_AA64ISAR0_FHM_SHIFT 48 |
| 344 | #define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT) |
| 345 | #define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK) |
| 346 | #define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT) |
| 347 | #define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT) |
| 348 | #define ID_AA64ISAR0_TS_SHIFT 52 |
| 349 | #define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT) |
| 350 | #define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK) |
| 351 | #define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT) |
| 352 | #define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT) |
| 353 | #define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT) |
| 354 | #define ID_AA64ISAR0_TLB_SHIFT 56 |
| 355 | #define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT) |
| 356 | #define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK) |
| 357 | #define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT) |
| 358 | #define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT) |
| 359 | #define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT) |
| 360 | #define ID_AA64ISAR0_RNDR_SHIFT 60 |
| 361 | #define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT) |
| 362 | #define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK) |
| 363 | #define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT) |
| 364 | #define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT) |
| 365 | |
| 366 | /* ID_AA64ISAR1_EL1 */ |
| 367 | #define ID_AA64ISAR1_MASK 0xffffffffffffffffULL |
| 368 | #define ID_AA64ISAR1_DPB_SHIFT 0 |
| 369 | #define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT) |
| 370 | #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) |
| 371 | #define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT) |
| 372 | #define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT) |
| 373 | #define ID_AA64ISAR1_DPB_DCCVADP (0x2ULL << ID_AA64ISAR1_DPB_SHIFT) |
| 374 | #define ID_AA64ISAR1_APA_SHIFT 4 |
| 375 | #define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT) |
| 376 | #define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) |
| 377 | #define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT) |
| 378 | #define ID_AA64ISAR1_APA_PAC (0x1ULL << ID_AA64ISAR1_APA_SHIFT) |
| 379 | #define ID_AA64ISAR1_APA_EPAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT) |
| 380 | #define ID_AA64ISAR1_APA_EPAC2 (0x3ULL << ID_AA64ISAR1_APA_SHIFT) |
| 381 | #define ID_AA64ISAR1_APA_FPAC (0x4ULL << ID_AA64ISAR1_APA_SHIFT) |
| 382 | #define ID_AA64ISAR1_APA_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_APA_SHIFT) |
| 383 | #define ID_AA64ISAR1_API_SHIFT 8 |
| 384 | #define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT) |
| 385 | #define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) |
| 386 | #define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT) |
| 387 | #define ID_AA64ISAR1_API_PAC (0x1ULL << ID_AA64ISAR1_API_SHIFT) |
| 388 | #define ID_AA64ISAR1_API_EPAC (0x2ULL << ID_AA64ISAR1_API_SHIFT) |
| 389 | #define ID_AA64ISAR1_API_EPAC2 (0x3ULL << ID_AA64ISAR1_API_SHIFT) |
| 390 | #define ID_AA64ISAR1_API_FPAC (0x4ULL << ID_AA64ISAR1_API_SHIFT) |
| 391 | #define ID_AA64ISAR1_API_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_API_SHIFT) |
| 392 | #define ID_AA64ISAR1_JSCVT_SHIFT 12 |
| 393 | #define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT) |
| 394 | #define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) |
| 395 | #define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT) |
| 396 | #define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT) |
| 397 | #define ID_AA64ISAR1_FCMA_SHIFT 16 |
| 398 | #define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT) |
| 399 | #define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) |
| 400 | #define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT) |
| 401 | #define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT) |
| 402 | #define ID_AA64ISAR1_LRCPC_SHIFT 20 |
| 403 | #define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT) |
| 404 | #define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) |
| 405 | #define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT) |
| 406 | #define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT) |
| 407 | #define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT) |
| 408 | #define ID_AA64ISAR1_GPA_SHIFT 24 |
| 409 | #define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT) |
| 410 | #define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) |
| 411 | #define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT) |
| 412 | #define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT) |
| 413 | #define ID_AA64ISAR1_GPI_SHIFT 28 |
| 414 | #define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT) |
| 415 | #define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) |
| 416 | #define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT) |
| 417 | #define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT) |
| 418 | #define ID_AA64ISAR1_FRINTTS_SHIFT 32 |
| 419 | #define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 420 | #define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) |
| 421 | #define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 422 | #define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT) |
| 423 | #define ID_AA64ISAR1_SB_SHIFT 36 |
| 424 | #define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT) |
| 425 | #define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK) |
| 426 | #define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT) |
| 427 | #define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT) |
| 428 | #define ID_AA64ISAR1_SPECRES_SHIFT 40 |
| 429 | #define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT) |
| 430 | #define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) |
| 431 | #define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT) |
| 432 | #define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT) |
| 433 | #define ID_AA64ISAR1_BF16_SHIFT 44 |
| 434 | #define ID_AA64ISAR1_BF16_MASK (0xfULL << ID_AA64ISAR1_BF16_SHIFT) |
| 435 | #define ID_AA64ISAR1_BF16(x) ((x) & ID_AA64ISAR1_BF16_MASK) |
| 436 | #define ID_AA64ISAR1_BF16_NONE (0x0ULL << ID_AA64ISAR1_BF16_SHIFT) |
| 437 | #define ID_AA64ISAR1_BF16_BASE (0x1ULL << ID_AA64ISAR1_BF16_SHIFT) |
| 438 | #define ID_AA64ISAR1_BF16_EBF (0x2ULL << ID_AA64ISAR1_BF16_SHIFT) |
| 439 | #define ID_AA64ISAR1_DGH_SHIFT 48 |
| 440 | #define ID_AA64ISAR1_DGH_MASK (0xfULL << ID_AA64ISAR1_DGH_SHIFT) |
| 441 | #define ID_AA64ISAR1_DGH(x) ((x) & ID_AA64ISAR1_DGH_MASK) |
| 442 | #define ID_AA64ISAR1_DGH_NONE (0x0ULL << ID_AA64ISAR1_DGH_SHIFT) |
| 443 | #define ID_AA64ISAR1_DGH_IMPL (0x1ULL << ID_AA64ISAR1_DGH_SHIFT) |
| 444 | #define ID_AA64ISAR1_I8MM_SHIFT 52 |
| 445 | #define ID_AA64ISAR1_I8MM_MASK (0xfULL << ID_AA64ISAR1_I8MM_SHIFT) |
| 446 | #define ID_AA64ISAR1_I8MM(x) ((x) & ID_AA64ISAR1_I8MM_MASK) |
| 447 | #define ID_AA64ISAR1_I8MM_NONE (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT) |
| 448 | #define ID_AA64ISAR1_I8MM_IMPL (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT) |
| 449 | #define ID_AA64ISAR1_XS_SHIFT 56 |
| 450 | #define ID_AA64ISAR1_XS_MASK (0xfULL << ID_AA64ISAR1_XS_SHIFT) |
| 451 | #define ID_AA64ISAR1_XS(x) ((x) & ID_AA64ISAR1_XS_MASK) |
| 452 | #define ID_AA64ISAR1_XS_NONE (0x0ULL << ID_AA64ISAR1_XS_SHIFT) |
| 453 | #define ID_AA64ISAR1_XS_IMPL (0x1ULL << ID_AA64ISAR1_XS_SHIFT) |
| 454 | #define ID_AA64ISAR1_LS64_SHIFT 60 |
| 455 | #define ID_AA64ISAR1_LS64_MASK (0xfULL << ID_AA64ISAR1_LS64_SHIFT) |
| 456 | #define ID_AA64ISAR1_LS64(x) ((x) & ID_AA64ISAR1_LS64_MASK) |
| 457 | #define ID_AA64ISAR1_LS64_NONE (0x0ULL << ID_AA64ISAR1_LS64_SHIFT) |
| 458 | #define ID_AA64ISAR1_LS64_BASE (0x1ULL << ID_AA64ISAR1_LS64_SHIFT) |
| 459 | #define ID_AA64ISAR1_LS64_V (0x2ULL << ID_AA64ISAR1_LS64_SHIFT) |
| 460 | #define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT) |
| 461 | |
| 462 | /* ID_AA64ISAR2_EL1 */ |
| 463 | #define ID_AA64ISAR2_MASK 0x00ff0000f0ffffffULL |
| 464 | #define ID_AA64ISAR2_WFXT_SHIFT 0 |
| 465 | #define ID_AA64ISAR2_WFXT_MASK (0xfULL << ID_AA64ISAR2_WFXT_SHIFT) |
| 466 | #define ID_AA64ISAR2_WFXT(x) ((x) & ID_AA64ISAR2_WFXT_MASK) |
| 467 | #define ID_AA64ISAR2_WFXT_NONE (0x0ULL << ID_AA64ISAR2_WFXT_SHIFT) |
| 468 | #define ID_AA64ISAR2_WFXT_IMPL (0x2ULL << ID_AA64ISAR2_WFXT_SHIFT) |
| 469 | #define ID_AA64ISAR2_RPRES_SHIFT 4 |
| 470 | #define ID_AA64ISAR2_RPRES_MASK (0xfULL << ID_AA64ISAR2_RPRES_SHIFT) |
| 471 | #define ID_AA64ISAR2_RPRES(x) ((x) & ID_AA64ISAR2_RPRES_MASK) |
| 472 | #define ID_AA64ISAR2_RPRES_NONE (0x0ULL << ID_AA64ISAR2_RPRES_SHIFT) |
| 473 | #define ID_AA64ISAR2_RPRES_IMPL (0x1ULL << ID_AA64ISAR2_RPRES_SHIFT) |
| 474 | #define ID_AA64ISAR2_GPA3_SHIFT 8 |
| 475 | #define ID_AA64ISAR2_GPA3_WIDTH 4 |
| 476 | #define ID_AA64ISAR2_GPA3_MASK (0xfULL << ID_AA64ISAR2_GPA3_SHIFT) |
| 477 | #define ID_AA64ISAR2_GPA3(x) ((x) & ID_AA64ISAR2_GPA3_MASK) |
| 478 | #define ID_AA64ISAR2_GPA3_NONE (0x0ULL << ID_AA64ISAR2_GPA3_SHIFT) |
| 479 | #define ID_AA64ISAR2_GPA3_IMPL (0x1ULL << ID_AA64ISAR2_GPA3_SHIFT) |
| 480 | #define ID_AA64ISAR2_APA3_SHIFT 12 |
| 481 | #define ID_AA64ISAR2_APA3_WIDTH 4 |
| 482 | #define ID_AA64ISAR2_APA3_MASK (0xfULL << ID_AA64ISAR2_APA3_SHIFT) |
| 483 | #define ID_AA64ISAR2_APA3(x) ((x) & ID_AA64ISAR2_APA3_MASK) |
| 484 | #define ID_AA64ISAR2_APA3_NONE (0x0ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 485 | #define ID_AA64ISAR2_APA3_PAC (0x1ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 486 | #define ID_AA64ISAR2_APA3_EPAC (0x2ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 487 | #define ID_AA64ISAR2_APA3_EPAC2 (0x3ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 488 | #define ID_AA64ISAR2_APA3_FPAC (0x4ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 489 | #define ID_AA64ISAR2_APA3_FPAC_COMBINED (0x5ULL << ID_AA64ISAR2_APA3_SHIFT) |
| 490 | #define ID_AA64ISAR2_MOPS_SHIFT 16 |
| 491 | #define ID_AA64ISAR2_MOPS_MASK (0xfULL << ID_AA64ISAR2_MOPS_SHIFT) |
| 492 | #define ID_AA64ISAR2_MOPS(x) ((x) & ID_AA64ISAR2_MOPS_MASK) |
| 493 | #define ID_AA64ISAR2_MOPS_NONE (0x0ULL << ID_AA64ISAR2_MOPS_SHIFT) |
| 494 | #define ID_AA64ISAR2_MOPS_IMPL (0x1ULL << ID_AA64ISAR2_MOPS_SHIFT) |
| 495 | #define ID_AA64ISAR2_BC_SHIFT 20 |
| 496 | #define ID_AA64ISAR2_BC_MASK (0xfULL << ID_AA64ISAR2_BC_SHIFT) |
| 497 | #define ID_AA64ISAR2_BC(x) ((x) & ID_AA64ISAR2_BC_MASK) |
| 498 | #define ID_AA64ISAR2_BC_NONE (0x0ULL << ID_AA64ISAR2_BC_SHIFT) |
| 499 | #define ID_AA64ISAR2_BC_IMPL (0x1ULL << ID_AA64ISAR2_BC_SHIFT) |
| 500 | #define ID_AA64ISAR2_CLRBHB_SHIFT 28 |
| 501 | #define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 502 | #define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) |
| 503 | #define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 504 | #define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT) |
| 505 | #define ID_AA64ISAR2_RPRFM_SHIFT 48 |
| 506 | #define ID_AA64ISAR2_RPRFM_MASK (0xfULL << ID_AA64ISAR2_RPRFM_SHIFT) |
| 507 | #define ID_AA64ISAR2_RPRFM(x) ((x) & ID_AA64ISAR2_RPRFM_MASK) |
| 508 | #define ID_AA64ISAR2_RPRFM_NONE (0x0ULL << ID_AA64ISAR2_RPRFM_SHIFT) |
| 509 | #define ID_AA64ISAR2_RPRFM_IMPL (0x1ULL << ID_AA64ISAR2_RPRFM_SHIFT) |
| 510 | #define ID_AA64ISAR2_CSSC_SHIFT 52 |
| 511 | #define ID_AA64ISAR2_CSSC_MASK (0xfULL << ID_AA64ISAR2_CSSC_SHIFT) |
| 512 | #define ID_AA64ISAR2_CSSC(x) ((x) & ID_AA64ISAR2_CSSC_MASK) |
| 513 | #define ID_AA64ISAR2_CSSC_NONE (0x0ULL << ID_AA64ISAR2_CSSC_SHIFT) |
| 514 | #define ID_AA64ISAR2_CSSC_IMPL (0x1ULL << ID_AA64ISAR2_CSSC_SHIFT) |
| 515 | |
| 516 | /* ID_AA64MMFR0_EL1 */ |
| 517 | #define ID_AA64MMFR0_MASK 0xf0000000ffffffffULL |
| 518 | #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 |
| 519 | #define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 520 | #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) |
| 521 | #define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 522 | #define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 523 | #define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 524 | #define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 525 | #define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 526 | #define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) |
| 527 | #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 |
| 528 | #define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT) |
| 529 | #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) |
| 530 | #define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) |
| 531 | #define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) |
| 532 | #define ID_AA64MMFR0_BIGEND_SHIFT 8 |
| 533 | #define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT) |
| 534 | #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) |
| 535 | #define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT) |
| 536 | #define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT) |
| 537 | #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 |
| 538 | #define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) |
| 539 | #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) |
| 540 | #define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) |
| 541 | #define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) |
| 542 | #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 |
| 543 | #define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) |
| 544 | #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) |
| 545 | #define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) |
| 546 | #define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) |
| 547 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 |
| 548 | #define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT) |
| 549 | #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) |
| 550 | #define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT) |
| 551 | #define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT) |
| 552 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 |
| 553 | #define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) |
| 554 | #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) |
| 555 | #define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT) |
| 556 | #define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) |
| 557 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 |
| 558 | #define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) |
| 559 | #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) |
| 560 | #define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT) |
| 561 | #define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) |
| 562 | #define ID_AA64MMFR0_ECV_SHIFT 60 |
| 563 | #define ID_AA64MMFR0_ECV_MASK (0xfULL << ID_AA64MMFR0_ECV_SHIFT) |
| 564 | #define ID_AA64MMFR0_ECV(x) ((x) & ID_AA64MMFR0_ECV_MASK) |
| 565 | #define ID_AA64MMFR0_ECV_NONE (0x0ULL << ID_AA64MMFR0_ECV_SHIFT) |
| 566 | #define ID_AA64MMFR0_ECV_IMPL (0x1ULL << ID_AA64MMFR0_ECV_SHIFT) |
| 567 | #define ID_AA64MMFR0_ECV_CNTHCTL (0x2ULL << ID_AA64MMFR0_ECV_SHIFT) |
| 568 | |
| 569 | /* ID_AA64MMFR1_EL1 */ |
| 570 | #define ID_AA64MMFR1_MASK 0xf000f000ffffffffULL |
| 571 | #define ID_AA64MMFR1_HAFDBS_SHIFT 0 |
| 572 | #define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 573 | #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) |
| 574 | #define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 575 | #define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 576 | #define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT) |
| 577 | #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 |
| 578 | #define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT) |
| 579 | #define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) |
| 580 | #define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) |
| 581 | #define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) |
| 582 | #define ID_AA64MMFR1_VH_SHIFT 8 |
| 583 | #define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT) |
| 584 | #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) |
| 585 | #define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT) |
| 586 | #define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT) |
| 587 | #define ID_AA64MMFR1_HPDS_SHIFT 12 |
| 588 | #define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT) |
| 589 | #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) |
| 590 | #define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT) |
| 591 | #define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT) |
| 592 | #define ID_AA64MMFR1_LO_SHIFT 16 |
| 593 | #define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT) |
| 594 | #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) |
| 595 | #define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT) |
| 596 | #define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT) |
| 597 | #define ID_AA64MMFR1_PAN_SHIFT 20 |
| 598 | #define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT) |
| 599 | #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) |
| 600 | #define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT) |
| 601 | #define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT) |
| 602 | #define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT) |
| 603 | #define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT) |
| 604 | #define ID_AA64MMFR1_SPECSEI_SHIFT 24 |
| 605 | #define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT) |
| 606 | #define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) |
| 607 | #define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT) |
| 608 | #define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT) |
| 609 | #define ID_AA64MMFR1_XNX_SHIFT 28 |
| 610 | #define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT) |
| 611 | #define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) |
| 612 | #define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT) |
| 613 | #define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT) |
| 614 | #define ID_AA64MMFR1_AFP_SHIFT 44 |
| 615 | #define ID_AA64MMFR1_AFP_MASK (0xfULL << ID_AA64MMFR1_AFP_SHIFT) |
| 616 | #define ID_AA64MMFR1_AFP(x) ((x) & ID_AA64MMFR1_AFP_MASK) |
| 617 | #define ID_AA64MMFR1_AFP_NONE (0x0ULL << ID_AA64MMFR1_AFP_SHIFT) |
| 618 | #define ID_AA64MMFR1_AFP_IMPL (0x1ULL << ID_AA64MMFR1_AFP_SHIFT) |
| 619 | #define ID_AA64MMFR1_ECBHB_SHIFT 60 |
| 620 | #define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT) |
| 621 | #define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) |
| 622 | #define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT) |
| 623 | #define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT) |
| 624 | |
| 625 | /* ID_AA64MMFR2_EL1 */ |
| 626 | #define ID_AA64MMFR2_MASK 0xffff0fffffffffffULL |
| 627 | #define ID_AA64MMFR2_CCIDX_SHIFT 20 |
| 628 | #define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT) |
| 629 | #define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) |
| 630 | #define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT) |
| 631 | #define ID_AA64MMFR2_AT_SHIFT 32 |
| 632 | #define ID_AA64MMFR2_AT_MASK (0xfULL << ID_AA64MMFR2_AT_SHIFT) |
| 633 | #define ID_AA64MMFR2_AT(x) ((x) & ID_AA64MMFR2_AT_MASK) |
| 634 | #define ID_AA64MMFR2_AT_NONE (0x0ULL << ID_AA64MMFR2_AT_SHIFT) |
| 635 | #define ID_AA64MMFR2_AT_IMPL (0x1ULL << ID_AA64MMFR2_AT_SHIFT) |
| 636 | #define ID_AA64MMFR2_IDS_SHIFT 36 |
| 637 | #define ID_AA64MMFR2_IDS_MASK (0xfULL << ID_AA64MMFR2_IDS_SHIFT) |
| 638 | #define ID_AA64MMFR2_IDS(x) ((x) & ID_AA64MMFR2_IDS_MASK) |
| 639 | #define ID_AA64MMFR2_IDS_NONE (0x0ULL << ID_AA64MMFR2_IDS_SHIFT) |
| 640 | #define ID_AA64MMFR2_IDS_IMPL (0x1ULL << ID_AA64MMFR2_IDS_SHIFT) |
| 641 | |
| 642 | /* ID_AA64PFR0_EL1 */ |
| 643 | #define ID_AA64PFR0_MASK 0xff0fffffffffffffULL |
| 644 | #define ID_AA64PFR0_EL0_SHIFT 0 |
| 645 | #define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT) |
| 646 | #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) |
| 647 | #define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT) |
| 648 | #define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT) |
| 649 | #define ID_AA64PFR0_EL1_SHIFT 4 |
| 650 | #define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT) |
| 651 | #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) |
| 652 | #define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT) |
| 653 | #define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT) |
| 654 | #define ID_AA64PFR0_EL2_SHIFT 8 |
| 655 | #define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT) |
| 656 | #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) |
| 657 | #define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT) |
| 658 | #define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT) |
| 659 | #define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT) |
| 660 | #define ID_AA64PFR0_EL3_SHIFT 12 |
| 661 | #define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT) |
| 662 | #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) |
| 663 | #define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT) |
| 664 | #define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT) |
| 665 | #define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT) |
| 666 | #define ID_AA64PFR0_FP_SHIFT 16 |
| 667 | #define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT) |
| 668 | #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) |
| 669 | #define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT) |
| 670 | #define ID_AA64PFR0_FP_HP (0x1ULL << ID_AA64PFR0_FP_SHIFT) |
| 671 | #define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT) |
| 672 | #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 |
| 673 | #define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) |
| 674 | #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) |
| 675 | #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) |
| 676 | #define ID_AA64PFR0_ADV_SIMD_HP (0x1ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) |
| 677 | #define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) |
| 678 | #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ |
| 679 | #define ID_AA64PFR0_GIC_SHIFT 24 |
| 680 | #define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT) |
| 681 | #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) |
| 682 | #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT) |
| 683 | #define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT) |
| 684 | #define ID_AA64PFR0_RAS_SHIFT 28 |
| 685 | #define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT) |
| 686 | #define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) |
| 687 | #define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT) |
| 688 | #define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT) |
| 689 | #define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT) |
| 690 | #define ID_AA64PFR0_SVE_SHIFT 32 |
| 691 | #define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT) |
| 692 | #define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) |
| 693 | #define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT) |
| 694 | #define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT) |
| 695 | #define ID_AA64PFR0_SEL2_SHIFT 36 |
| 696 | #define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT) |
| 697 | #define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK) |
| 698 | #define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT) |
| 699 | #define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT) |
| 700 | #define ID_AA64PFR0_MPAM_SHIFT 40 |
| 701 | #define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT) |
| 702 | #define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK) |
| 703 | #define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT) |
| 704 | #define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT) |
| 705 | #define ID_AA64PFR0_AMU_SHIFT 44 |
| 706 | #define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT) |
| 707 | #define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK) |
| 708 | #define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT) |
| 709 | #define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT) |
| 710 | #define ID_AA64PFR0_AMU_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_AMU_SHIFT) |
| 711 | #define ID_AA64PFR0_DIT_SHIFT 48 |
| 712 | #define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT) |
| 713 | #define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK) |
| 714 | #define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT) |
| 715 | #define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT) |
| 716 | #define ID_AA64PFR0_CSV2_SHIFT 56 |
| 717 | #define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT) |
| 718 | #define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK) |
| 719 | #define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT) |
| 720 | #define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT) |
| 721 | #define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT) |
| 722 | #define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT) |
| 723 | #define ID_AA64PFR0_CSV3_SHIFT 60 |
| 724 | #define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT) |
| 725 | #define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK) |
| 726 | #define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT) |
| 727 | #define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT) |
| 728 | |
| 729 | /* ID_AA64PFR1_EL1 */ |
| 730 | #define ID_AA64PFR1_MASK 0x000000000000ffffULL |
| 731 | #define ID_AA64PFR1_BT_SHIFT 0 |
| 732 | #define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT) |
| 733 | #define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK) |
| 734 | #define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT) |
| 735 | #define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT) |
| 736 | #define ID_AA64PFR1_SSBS_SHIFT 4 |
| 737 | #define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT) |
| 738 | #define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK) |
| 739 | #define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT) |
| 740 | #define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT) |
| 741 | #define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT) |
| 742 | #define ID_AA64PFR1_MTE_SHIFT 8 |
| 743 | #define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT) |
| 744 | #define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK) |
| 745 | #define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT) |
| 746 | #define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT) |
| 747 | #define ID_AA64PFR1_RAS_FRAC_SHIFT 12 |
| 748 | #define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT) |
| 749 | #define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK) |
| 750 | #define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) |
| 751 | #define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) |
| 752 | |
| 753 | /* ID_AA64ZFR0_EL1 */ |
| 754 | #define ID_AA64ZFR0_MASK 0x0ff0ff0f00ff00ffULL |
| 755 | #define ID_AA64ZFR0_SVEVER_SHIFT 0 |
| 756 | #define ID_AA64ZFR0_SVEVER_MASK (0xfULL << ID_AA64ZFR0_SVEVER_SHIFT) |
| 757 | #define ID_AA64ZFR0_SVEVER(x) ((x) & ID_AA64ZFR0_SVEVER_MASK) |
| 758 | #define ID_AA64ZFR0_SVEVER_SVE1 (0x0ULL << ID_AA64ZFR0_SVEVER_SHIFT) |
| 759 | #define ID_AA64ZFR0_SVEVER_SVE2 (0x1ULL << ID_AA64ZFR0_SVEVER_SHIFT) |
| 760 | #define ID_AA64ZFR0_SVEVER_SVE2P1 (0x2ULL << ID_AA64ZFR0_SVEVER_SHIFT) |
| 761 | #define ID_AA64ZFR0_AES_SHIFT 4 |
| 762 | #define ID_AA64ZFR0_AES_MASK (0xfULL << ID_AA64ZFR0_AES_SHIFT) |
| 763 | #define ID_AA64ZFR0_AES(x) ((x) & ID_AA64ZFR0_AES_MASK) |
| 764 | #define ID_AA64ZFR0_AES_NONE (0x0ULL << ID_AA64ZFR0_AES_SHIFT) |
| 765 | #define ID_AA64ZFR0_AES_BASE (0x1ULL << ID_AA64ZFR0_AES_SHIFT) |
| 766 | #define ID_AA64ZFR0_AES_PMULL (0x2ULL << ID_AA64ZFR0_AES_SHIFT) |
| 767 | #define ID_AA64ZFR0_BITPERM_SHIFT 16 |
| 768 | #define ID_AA64ZFR0_BITPERM_MASK (0xfULL << ID_AA64ZFR0_BITPERM_SHIFT) |
| 769 | #define ID_AA64ZFR0_BITPERM(x) ((x) & ID_AA64ZFR0_BITPERM_MASK) |
| 770 | #define ID_AA64ZFR0_BITPERM_NONE (0x0ULL << ID_AA64ZFR0_BITPERM_SHIFT) |
| 771 | #define ID_AA64ZFR0_BITPERM_IMPL (0x1ULL << ID_AA64ZFR0_BITPERM_SHIFT) |
| 772 | #define ID_AA64ZFR0_BF16_SHIFT 20 |
| 773 | #define ID_AA64ZFR0_BF16_MASK (0xfULL << ID_AA64ZFR0_BF16_SHIFT) |
| 774 | #define ID_AA64ZFR0_BF16(x) ((x) & ID_AA64ZFR0_BF16_MASK) |
| 775 | #define ID_AA64ZFR0_BF16_NONE (0x0ULL << ID_AA64ZFR0_BF16_SHIFT) |
| 776 | #define ID_AA64ZFR0_BF16_BASE (0x1ULL << ID_AA64ZFR0_BF16_SHIFT) |
| 777 | #define ID_AA64ZFR0_BF16_EBF (0x2ULL << ID_AA64ZFR0_BF16_SHIFT) |
| 778 | #define ID_AA64ZFR0_SHA3_SHIFT 32 |
| 779 | #define ID_AA64ZFR0_SHA3_MASK (0xfULL << ID_AA64ZFR0_SHA3_SHIFT) |
| 780 | #define ID_AA64ZFR0_SHA3(x) ((x) & ID_AA64ZFR0_SHA3_MASK) |
| 781 | #define ID_AA64ZFR0_SHA3_NONE (0x0ULL << ID_AA64ZFR0_SHA3_SHIFT) |
| 782 | #define ID_AA64ZFR0_SHA3_IMPL (0x1ULL << ID_AA64ZFR0_SHA3_SHIFT) |
| 783 | #define ID_AA64ZFR0_SM4_SHIFT 40 |
| 784 | #define ID_AA64ZFR0_SM4_MASK (0xfULL << ID_AA64ZFR0_SM4_SHIFT) |
| 785 | #define ID_AA64ZFR0_SM4(x) ((x) & ID_AA64ZFR0_SM4_MASK) |
| 786 | #define ID_AA64ZFR0_SM4_NONE (0x0ULL << ID_AA64ZFR0_SM4_SHIFT) |
| 787 | #define ID_AA64ZFR0_SM4_IMPL (0x1ULL << ID_AA64ZFR0_SM4_SHIFT) |
| 788 | #define ID_AA64ZFR0_I8MM_SHIFT 44 |
| 789 | #define ID_AA64ZFR0_I8MM_MASK (0xfULL << ID_AA64ZFR0_I8MM_SHIFT) |
| 790 | #define ID_AA64ZFR0_I8MM(x) ((x) & ID_AA64ZFR0_I8MM_MASK) |
| 791 | #define ID_AA64ZFR0_I8MM_NONE (0x0ULL << ID_AA64ZFR0_I8MM_SHIFT) |
| 792 | #define ID_AA64ZFR0_I8MM_IMPL (0x1ULL << ID_AA64ZFR0_I8MM_SHIFT) |
| 793 | #define ID_AA64ZFR0_F32MM_SHIFT 52 |
| 794 | #define ID_AA64ZFR0_F32MM_MASK (0xfULL << ID_AA64ZFR0_F32MM_SHIFT) |
| 795 | #define ID_AA64ZFR0_F32MM(x) ((x) & ID_AA64ZFR0_F32MM_MASK) |
| 796 | #define ID_AA64ZFR0_F32MM_NONE (0x0ULL << ID_AA64ZFR0_F32MM_SHIFT) |
| 797 | #define ID_AA64ZFR0_F32MM_IMPL (0x1ULL << ID_AA64ZFR0_F32MM_SHIFT) |
| 798 | #define ID_AA64ZFR0_F64MM_SHIFT 56 |
| 799 | #define ID_AA64ZFR0_F64MM_MASK (0xfULL << ID_AA64ZFR0_F64MM_SHIFT) |
| 800 | #define ID_AA64ZFR0_F64MM(x) ((x) & ID_AA64ZFR0_F64MM_MASK) |
| 801 | #define ID_AA64ZFR0_F64MM_NONE (0x0ULL << ID_AA64ZFR0_F64MM_SHIFT) |
| 802 | #define ID_AA64ZFR0_F64MM_IMPL (0x1ULL << ID_AA64ZFR0_F64MM_SHIFT) |
| 803 | |
| 804 | /* MAIR_EL1 - Memory Attribute Indirection Register */ |
| 805 | #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) |
| 806 | #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) |
| 807 | #define MAIR_DEVICE_nGnRnE 0x00 |
| 808 | #define MAIR_NORMAL_NC 0x44 |
| 809 | #define MAIR_NORMAL_WT 0x88 |
| 810 | #define MAIR_NORMAL_WB 0xff |
| 811 | |
| 812 | /* PAR_EL1 - Physical Address Register */ |
| 813 | #define PAR_F_SHIFT 0 |
| 814 | #define PAR_F (0x1 << PAR_F_SHIFT) |
| 815 | #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) |
| 816 | /* When PAR_F == 0 (success) */ |
| 817 | #define PAR_SH_SHIFT 7 |
| 818 | #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) |
| 819 | #define PAR_NS_SHIFT 9 |
| 820 | #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) |
| 821 | #define PAR_PA_SHIFT 12 |
| 822 | #define PAR_PA_MASK 0x0000fffffffff000 |
| 823 | #define PAR_ATTR_SHIFT 56 |
| 824 | #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) |
| 825 | /* When PAR_F == 1 (aborted) */ |
| 826 | #define PAR_FST_SHIFT 1 |
| 827 | #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) |
| 828 | #define PAR_PTW_SHIFT 8 |
| 829 | #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) |
| 830 | #define PAR_S_SHIFT 9 |
| 831 | #define PAR_S_MASK (0x1 << PAR_S_SHIFT) |
| 832 | |
| 833 | /* SCTLR_EL1 - System Control Register */ |
| 834 | #define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ |
| 835 | #define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ |
| 836 | |
| 837 | #define SCTLR_M 0x0000000000000001 |
| 838 | #define SCTLR_A 0x0000000000000002 |
| 839 | #define SCTLR_C 0x0000000000000004 |
| 840 | #define SCTLR_SA 0x0000000000000008 |
| 841 | #define SCTLR_SA0 0x0000000000000010 |
| 842 | #define SCTLR_CP15BEN 0x0000000000000020 |
| 843 | #define SCTLR_THEE 0x0000000000000040 |
| 844 | #define SCTLR_ITD 0x0000000000000080 |
| 845 | #define SCTLR_SED 0x0000000000000100 |
| 846 | #define SCTLR_UMA 0x0000000000000200 |
| 847 | #define SCTLR_I 0x0000000000001000 |
| 848 | #define SCTLR_EnDB 0x0000000000002000 |
| 849 | #define SCTLR_DZE 0x0000000000004000 |
| 850 | #define SCTLR_UCT 0x0000000000008000 |
| 851 | #define SCTLR_nTWI 0x0000000000010000 |
| 852 | #define SCTLR_nTWE 0x0000000000040000 |
| 853 | #define SCTLR_WXN 0x0000000000080000 |
| 854 | #define SCTLR_SPAN 0x0000000000800000 |
| 855 | #define SCTLR_EOE 0x0000000001000000 |
| 856 | #define SCTLR_EE 0x0000000002000000 |
| 857 | #define SCTLR_UCI 0x0000000004000000 |
| 858 | #define SCTLR_EnDA 0x0000000008000000 |
| 859 | #define SCTLR_EnIB 0x0000000040000000 |
| 860 | #define SCTLR_EnIA 0x0000000080000000 |
| 861 | #define SCTLR_BT0 0x0000000800000000 |
| 862 | #define SCTLR_BT1 0x0000001000000000 |
| 863 | #define SCTLR_EPAN 0x0200000000000000 |
| 864 | |
| 865 | /* SPSR_EL1 */ |
| 866 | /* |
| 867 | * When the exception is taken in AArch64: |
| 868 | * M[4] is 0 for AArch64 mode |
| 869 | * M[3:2] is the exception level |
| 870 | * M[1] is unused |
| 871 | * M[0] is the SP select: |
| 872 | * 0: always SP0 |
| 873 | * 1: current ELs SP |
| 874 | */ |
| 875 | #define PSR_M_EL0t 0x00000000 |
| 876 | #define PSR_M_EL1t 0x00000004 |
| 877 | #define PSR_M_EL1h 0x00000005 |
| 878 | #define PSR_M_EL2t 0x00000008 |
| 879 | #define PSR_M_EL2h 0x00000009 |
| 880 | #define PSR_M_MASK 0x0000001f |
| 881 | |
| 882 | #define PSR_F 0x00000040 |
| 883 | #define PSR_I 0x00000080 |
| 884 | #define PSR_A 0x00000100 |
| 885 | #define PSR_D 0x00000200 |
| 886 | #define PSR_BTYPE 0x00000c00 |
| 887 | #define PSR_SSBS 0x00001000 |
| 888 | #define PSR_IL 0x00100000 |
| 889 | #define PSR_SS 0x00200000 |
| 890 | #define PSR_PAN 0x00400000 |
| 891 | #define PSR_UAO 0x00800000 |
| 892 | #define PSR_DIT 0x01000000 |
| 893 | #define PSR_TCO 0x02000000 |
| 894 | #define PSR_V 0x10000000 |
| 895 | #define PSR_C 0x20000000 |
| 896 | #define PSR_Z 0x40000000 |
| 897 | #define PSR_N 0x80000000 |
| 898 | |
| 899 | /* TCR_EL1 - Translation Control Register */ |
| 900 | #define TCR_AS (1UL << 36) |
| 901 | |
| 902 | #define TCR_IPS_SHIFT 32 |
| 903 | #define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) |
| 904 | #define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) |
| 905 | #define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) |
| 906 | #define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) |
| 907 | #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) |
| 908 | #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) |
| 909 | |
| 910 | #define TCR_TG1_SHIFT 30 |
| 911 | #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) |
| 912 | #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) |
| 913 | #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) |
| 914 | |
| 915 | #define TCR_SH1_SHIFT 28 |
| 916 | #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) |
| 917 | #define TCR_ORGN1_SHIFT 26 |
| 918 | #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) |
| 919 | #define TCR_IRGN1_SHIFT 24 |
| 920 | #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) |
| 921 | |
| 922 | #define TCR_A1 (1UL << 22) |
| 923 | |
| 924 | #define TCR_TG0_SHIFT 14 |
| 925 | #define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) |
| 926 | #define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) |
| 927 | #define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) |
| 928 | |
| 929 | #define TCR_SH0_SHIFT 12 |
| 930 | #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) |
| 931 | #define TCR_ORGN0_SHIFT 10 |
| 932 | #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) |
| 933 | #define TCR_IRGN0_SHIFT 8 |
| 934 | #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) |
| 935 | |
| 936 | #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ |
| 937 | (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) |
| 938 | #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) |
| 939 | |
| 940 | #define TCR_T1SZ_SHIFT 16 |
| 941 | #define TCR_T0SZ_SHIFT 0 |
| 942 | #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) |
| 943 | #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) |
| 944 | #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) |
| 945 | |
| 946 | /* Monitor Debug System Control Register */ |
| 947 | #define DBG_MDSCR_SS (0x1 << 0) |
| 948 | #define DBG_MDSCR_TDCC (0x1 << 12) |
| 949 | #define DBG_MDSCR_KDE (0x1 << 13) |
| 950 | #define DBG_MDSCR_MDE (0x1 << 15) |
| 951 | |
| 952 | /* Performance Monitoring Counters */ |
| 953 | #define PMCR_E (1 << 0) /* Enable all counters */ |
| 954 | #define PMCR_P (1 << 1) /* Reset all counters */ |
| 955 | #define PMCR_C (1 << 2) /* Clock counter reset */ |
| 956 | #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ |
| 957 | #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ |
| 958 | #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ |
| 959 | #define PMCR_LC (1 << 6) /* Long cycle count enable */ |
| 960 | #define PMCR_IMP_SHIFT 24 /* Implementer code */ |
| 961 | #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) |
| 962 | #define PMCR_IDCODE_SHIFT 16 /* Identification code */ |
| 963 | #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) |
| 964 | #define PMCR_IDCODE_CORTEX_A57 0x01 |
| 965 | #define PMCR_IDCODE_CORTEX_A72 0x02 |
| 966 | #define PMCR_IDCODE_CORTEX_A53 0x03 |
| 967 | #define PMCR_N_SHIFT 11 /* Number of counters implemented */ |
| 968 | #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) |
| 969 | |
| 970 | #define I_bit (1 << 7) /* IRQ disable */ |
| 971 | #define F_bit 0 /* FIQ disable - not actually used */ |
| 972 | |
| 973 | #endif /* !_MACHINE_ARMREG_H_ */ |