1/* SPDX-License-Identifier: MIT */
2/* Copyright (c) 2012-2020 NVIDIA Corporation */
3
4#ifndef _TEGRA_DRM_H_
5#define _TEGRA_DRM_H_
6
7#include "drm.h"
8
9#if defined(__cplusplus)
10extern "C" {
11#endif
12
13/* Tegra DRM legacy UAPI. Only enabled with STAGING */
14
15#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
16#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
17
18/**
19 * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
20 */
21struct drm_tegra_gem_create {
22 /**
23 * @size:
24 *
25 * The size, in bytes, of the buffer object to be created.
26 */
27 __u64 size;
28
29 /**
30 * @flags:
31 *
32 * A bitmask of flags that influence the creation of GEM objects:
33 *
34 * DRM_TEGRA_GEM_CREATE_TILED
35 * Use the 16x16 tiling format for this buffer.
36 *
37 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
38 * The buffer has a bottom-up layout.
39 */
40 __u32 flags;
41
42 /**
43 * @handle:
44 *
45 * The handle of the created GEM object. Set by the kernel upon
46 * successful completion of the IOCTL.
47 */
48 __u32 handle;
49};
50
51/**
52 * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
53 */
54struct drm_tegra_gem_mmap {
55 /**
56 * @handle:
57 *
58 * Handle of the GEM object to obtain an mmap offset for.
59 */
60 __u32 handle;
61
62 /**
63 * @pad:
64 *
65 * Structure padding that may be used in the future. Must be 0.
66 */
67 __u32 pad;
68
69 /**
70 * @offset:
71 *
72 * The mmap offset for the given GEM object. Set by the kernel upon
73 * successful completion of the IOCTL.
74 */
75 __u64 offset;
76};
77
78/**
79 * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
80 */
81struct drm_tegra_syncpt_read {
82 /**
83 * @id:
84 *
85 * ID of the syncpoint to read the current value from.
86 */
87 __u32 id;
88
89 /**
90 * @value:
91 *
92 * The current syncpoint value. Set by the kernel upon successful
93 * completion of the IOCTL.
94 */
95 __u32 value;
96};
97
98/**
99 * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
100 */
101struct drm_tegra_syncpt_incr {
102 /**
103 * @id:
104 *
105 * ID of the syncpoint to increment.
106 */
107 __u32 id;
108
109 /**
110 * @pad:
111 *
112 * Structure padding that may be used in the future. Must be 0.
113 */
114 __u32 pad;
115};
116
117/**
118 * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
119 */
120struct drm_tegra_syncpt_wait {
121 /**
122 * @id:
123 *
124 * ID of the syncpoint to wait on.
125 */
126 __u32 id;
127
128 /**
129 * @thresh:
130 *
131 * Threshold value for which to wait.
132 */
133 __u32 thresh;
134
135 /**
136 * @timeout:
137 *
138 * Timeout, in milliseconds, to wait.
139 */
140 __u32 timeout;
141
142 /**
143 * @value:
144 *
145 * The new syncpoint value after the wait. Set by the kernel upon
146 * successful completion of the IOCTL.
147 */
148 __u32 value;
149};
150
151#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
152
153/**
154 * struct drm_tegra_open_channel - parameters for the open channel IOCTL
155 */
156struct drm_tegra_open_channel {
157 /**
158 * @client:
159 *
160 * The client ID for this channel.
161 */
162 __u32 client;
163
164 /**
165 * @pad:
166 *
167 * Structure padding that may be used in the future. Must be 0.
168 */
169 __u32 pad;
170
171 /**
172 * @context:
173 *
174 * The application context of this channel. Set by the kernel upon
175 * successful completion of the IOCTL. This context needs to be passed
176 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
177 */
178 __u64 context;
179};
180
181/**
182 * struct drm_tegra_close_channel - parameters for the close channel IOCTL
183 */
184struct drm_tegra_close_channel {
185 /**
186 * @context:
187 *
188 * The application context of this channel. This is obtained from the
189 * DRM_TEGRA_OPEN_CHANNEL IOCTL.
190 */
191 __u64 context;
192};
193
194/**
195 * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
196 */
197struct drm_tegra_get_syncpt {
198 /**
199 * @context:
200 *
201 * The application context identifying the channel for which to obtain
202 * the syncpoint ID.
203 */
204 __u64 context;
205
206 /**
207 * @index:
208 *
209 * Index of the client syncpoint for which to obtain the ID.
210 */
211 __u32 index;
212
213 /**
214 * @id:
215 *
216 * The ID of the given syncpoint. Set by the kernel upon successful
217 * completion of the IOCTL.
218 */
219 __u32 id;
220};
221
222/**
223 * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
224 */
225struct drm_tegra_get_syncpt_base {
226 /**
227 * @context:
228 *
229 * The application context identifying for which channel to obtain the
230 * wait base.
231 */
232 __u64 context;
233
234 /**
235 * @syncpt:
236 *
237 * ID of the syncpoint for which to obtain the wait base.
238 */
239 __u32 syncpt;
240
241 /**
242 * @id:
243 *
244 * The ID of the wait base corresponding to the client syncpoint. Set
245 * by the kernel upon successful completion of the IOCTL.
246 */
247 __u32 id;
248};
249
250/**
251 * struct drm_tegra_syncpt - syncpoint increment operation
252 */
253struct drm_tegra_syncpt {
254 /**
255 * @id:
256 *
257 * ID of the syncpoint to operate on.
258 */
259 __u32 id;
260
261 /**
262 * @incrs:
263 *
264 * Number of increments to perform for the syncpoint.
265 */
266 __u32 incrs;
267};
268
269/**
270 * struct drm_tegra_cmdbuf - structure describing a command buffer
271 */
272struct drm_tegra_cmdbuf {
273 /**
274 * @handle:
275 *
276 * Handle to a GEM object containing the command buffer.
277 */
278 __u32 handle;
279
280 /**
281 * @offset:
282 *
283 * Offset, in bytes, into the GEM object identified by @handle at
284 * which the command buffer starts.
285 */
286 __u32 offset;
287
288 /**
289 * @words:
290 *
291 * Number of 32-bit words in this command buffer.
292 */
293 __u32 words;
294
295 /**
296 * @pad:
297 *
298 * Structure padding that may be used in the future. Must be 0.
299 */
300 __u32 pad;
301};
302
303/**
304 * struct drm_tegra_reloc - GEM object relocation structure
305 */
306struct drm_tegra_reloc {
307 /** @cmdbuf: cmd information */
308 struct {
309 /**
310 * @cmdbuf.handle:
311 *
312 * Handle to the GEM object containing the command buffer for
313 * which to perform this GEM object relocation.
314 */
315 __u32 handle;
316
317 /**
318 * @cmdbuf.offset:
319 *
320 * Offset, in bytes, into the command buffer at which to
321 * insert the relocated address.
322 */
323 __u32 offset;
324 } cmdbuf;
325 /** @target: relocate target information */
326 struct {
327 /**
328 * @target.handle:
329 *
330 * Handle to the GEM object to be relocated.
331 */
332 __u32 handle;
333
334 /**
335 * @target.offset:
336 *
337 * Offset, in bytes, into the target GEM object at which the
338 * relocated data starts.
339 */
340 __u32 offset;
341 } target;
342
343 /**
344 * @shift:
345 *
346 * The number of bits by which to shift relocated addresses.
347 */
348 __u32 shift;
349
350 /**
351 * @pad:
352 *
353 * Structure padding that may be used in the future. Must be 0.
354 */
355 __u32 pad;
356};
357
358/**
359 * struct drm_tegra_waitchk - wait check structure
360 */
361struct drm_tegra_waitchk {
362 /**
363 * @handle:
364 *
365 * Handle to the GEM object containing a command stream on which to
366 * perform the wait check.
367 */
368 __u32 handle;
369
370 /**
371 * @offset:
372 *
373 * Offset, in bytes, of the location in the command stream to perform
374 * the wait check on.
375 */
376 __u32 offset;
377
378 /**
379 * @syncpt:
380 *
381 * ID of the syncpoint to wait check.
382 */
383 __u32 syncpt;
384
385 /**
386 * @thresh:
387 *
388 * Threshold value for which to check.
389 */
390 __u32 thresh;
391};
392
393/**
394 * struct drm_tegra_submit - job submission structure
395 */
396struct drm_tegra_submit {
397 /**
398 * @context:
399 *
400 * The application context identifying the channel to use for the
401 * execution of this job.
402 */
403 __u64 context;
404
405 /**
406 * @num_syncpts:
407 *
408 * The number of syncpoints operated on by this job. This defines the
409 * length of the array pointed to by @syncpts.
410 */
411 __u32 num_syncpts;
412
413 /**
414 * @num_cmdbufs:
415 *
416 * The number of command buffers to execute as part of this job. This
417 * defines the length of the array pointed to by @cmdbufs.
418 */
419 __u32 num_cmdbufs;
420
421 /**
422 * @num_relocs:
423 *
424 * The number of relocations to perform before executing this job.
425 * This defines the length of the array pointed to by @relocs.
426 */
427 __u32 num_relocs;
428
429 /**
430 * @num_waitchks:
431 *
432 * The number of wait checks to perform as part of this job. This
433 * defines the length of the array pointed to by @waitchks.
434 */
435 __u32 num_waitchks;
436
437 /**
438 * @waitchk_mask:
439 *
440 * Bitmask of valid wait checks.
441 */
442 __u32 waitchk_mask;
443
444 /**
445 * @timeout:
446 *
447 * Timeout, in milliseconds, before this job is cancelled.
448 */
449 __u32 timeout;
450
451 /**
452 * @syncpts:
453 *
454 * A pointer to an array of &struct drm_tegra_syncpt structures that
455 * specify the syncpoint operations performed as part of this job.
456 * The number of elements in the array must be equal to the value
457 * given by @num_syncpts.
458 */
459 __u64 syncpts;
460
461 /**
462 * @cmdbufs:
463 *
464 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
465 * define the command buffers to execute as part of this job. The
466 * number of elements in the array must be equal to the value given
467 * by @num_syncpts.
468 */
469 __u64 cmdbufs;
470
471 /**
472 * @relocs:
473 *
474 * A pointer to an array of &struct drm_tegra_reloc structures that
475 * specify the relocations that need to be performed before executing
476 * this job. The number of elements in the array must be equal to the
477 * value given by @num_relocs.
478 */
479 __u64 relocs;
480
481 /**
482 * @waitchks:
483 *
484 * A pointer to an array of &struct drm_tegra_waitchk structures that
485 * specify the wait checks to be performed while executing this job.
486 * The number of elements in the array must be equal to the value
487 * given by @num_waitchks.
488 */
489 __u64 waitchks;
490
491 /**
492 * @fence:
493 *
494 * The threshold of the syncpoint associated with this job after it
495 * has been completed. Set by the kernel upon successful completion of
496 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
497 * wait for this job to be finished.
498 */
499 __u32 fence;
500
501 /**
502 * @reserved:
503 *
504 * This field is reserved for future use. Must be 0.
505 */
506 __u32 reserved[5];
507};
508
509#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
510#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
511#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
512
513/**
514 * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
515 */
516struct drm_tegra_gem_set_tiling {
517 /**
518 * @handle:
519 *
520 * Handle to the GEM object for which to set the tiling parameters.
521 */
522 __u32 handle;
523
524 /**
525 * @mode:
526 *
527 * The tiling mode to set. Must be one of:
528 *
529 * DRM_TEGRA_GEM_TILING_MODE_PITCH
530 * pitch linear format
531 *
532 * DRM_TEGRA_GEM_TILING_MODE_TILED
533 * 16x16 tiling format
534 *
535 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
536 * 16Bx2 tiling format
537 */
538 __u32 mode;
539
540 /**
541 * @value:
542 *
543 * The value to set for the tiling mode parameter.
544 */
545 __u32 value;
546
547 /**
548 * @pad:
549 *
550 * Structure padding that may be used in the future. Must be 0.
551 */
552 __u32 pad;
553};
554
555/**
556 * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
557 */
558struct drm_tegra_gem_get_tiling {
559 /**
560 * @handle:
561 *
562 * Handle to the GEM object for which to query the tiling parameters.
563 */
564 __u32 handle;
565
566 /**
567 * @mode:
568 *
569 * The tiling mode currently associated with the GEM object. Set by
570 * the kernel upon successful completion of the IOCTL.
571 */
572 __u32 mode;
573
574 /**
575 * @value:
576 *
577 * The tiling mode parameter currently associated with the GEM object.
578 * Set by the kernel upon successful completion of the IOCTL.
579 */
580 __u32 value;
581
582 /**
583 * @pad:
584 *
585 * Structure padding that may be used in the future. Must be 0.
586 */
587 __u32 pad;
588};
589
590#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
591#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
592
593/**
594 * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
595 */
596struct drm_tegra_gem_set_flags {
597 /**
598 * @handle:
599 *
600 * Handle to the GEM object for which to set the flags.
601 */
602 __u32 handle;
603
604 /**
605 * @flags:
606 *
607 * The flags to set for the GEM object.
608 */
609 __u32 flags;
610};
611
612/**
613 * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
614 */
615struct drm_tegra_gem_get_flags {
616 /**
617 * @handle:
618 *
619 * Handle to the GEM object for which to query the flags.
620 */
621 __u32 handle;
622
623 /**
624 * @flags:
625 *
626 * The flags currently associated with the GEM object. Set by the
627 * kernel upon successful completion of the IOCTL.
628 */
629 __u32 flags;
630};
631
632#define DRM_TEGRA_GEM_CREATE 0x00
633#define DRM_TEGRA_GEM_MMAP 0x01
634#define DRM_TEGRA_SYNCPT_READ 0x02
635#define DRM_TEGRA_SYNCPT_INCR 0x03
636#define DRM_TEGRA_SYNCPT_WAIT 0x04
637#define DRM_TEGRA_OPEN_CHANNEL 0x05
638#define DRM_TEGRA_CLOSE_CHANNEL 0x06
639#define DRM_TEGRA_GET_SYNCPT 0x07
640#define DRM_TEGRA_SUBMIT 0x08
641#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
642#define DRM_TEGRA_GEM_SET_TILING 0x0a
643#define DRM_TEGRA_GEM_GET_TILING 0x0b
644#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
645#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
646
647#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
648#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
649#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
650#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
651#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
652#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
653#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
654#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
655#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
656#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
657#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
658#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
659#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
660#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
661
662/* New Tegra DRM UAPI */
663
664/*
665 * Reported by the driver in the `capabilities` field.
666 *
667 * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
668 * with regard to the system memory.
669 */
670#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
671
672struct drm_tegra_channel_open {
673 /**
674 * @host1x_class: [in]
675 *
676 * Host1x class of the engine that will be programmed using this
677 * channel.
678 */
679 __u32 host1x_class;
680
681 /**
682 * @flags: [in]
683 *
684 * Flags.
685 */
686 __u32 flags;
687
688 /**
689 * @context: [out]
690 *
691 * Opaque identifier corresponding to the opened channel.
692 */
693 __u32 context;
694
695 /**
696 * @version: [out]
697 *
698 * Version of the engine hardware. This can be used by userspace
699 * to determine how the engine needs to be programmed.
700 */
701 __u32 version;
702
703 /**
704 * @capabilities: [out]
705 *
706 * Flags describing the hardware capabilities.
707 */
708 __u32 capabilities;
709 __u32 padding;
710};
711
712struct drm_tegra_channel_close {
713 /**
714 * @context: [in]
715 *
716 * Identifier of the channel to close.
717 */
718 __u32 context;
719 __u32 padding;
720};
721
722/*
723 * Mapping flags that can be used to influence how the mapping is created.
724 *
725 * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
726 * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
727 */
728#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0)
729#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
730#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
731 DRM_TEGRA_CHANNEL_MAP_WRITE)
732
733struct drm_tegra_channel_map {
734 /**
735 * @context: [in]
736 *
737 * Identifier of the channel to which make memory available for.
738 */
739 __u32 context;
740
741 /**
742 * @handle: [in]
743 *
744 * GEM handle of the memory to map.
745 */
746 __u32 handle;
747
748 /**
749 * @flags: [in]
750 *
751 * Flags.
752 */
753 __u32 flags;
754
755 /**
756 * @mapping: [out]
757 *
758 * Identifier corresponding to the mapping, to be used for
759 * relocations or unmapping later.
760 */
761 __u32 mapping;
762};
763
764struct drm_tegra_channel_unmap {
765 /**
766 * @context: [in]
767 *
768 * Channel identifier of the channel to unmap memory from.
769 */
770 __u32 context;
771
772 /**
773 * @mapping: [in]
774 *
775 * Mapping identifier of the memory mapping to unmap.
776 */
777 __u32 mapping;
778};
779
780/* Submission */
781
782/**
783 * define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT - \
784 * Select sector layout swizzling for in-memory buffers.
785 *
786 * Specify that bit 39 of the patched-in address should be set to switch
787 * swizzling between Tegra and non-Tegra sector layout on systems that store
788 * surfaces in system memory in non-Tegra sector layout.
789 */
790#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
791
792struct drm_tegra_submit_buf {
793 /**
794 * @mapping: [in]
795 *
796 * Identifier of the mapping to use in the submission.
797 */
798 __u32 mapping;
799
800 /**
801 * @flags: [in]
802 *
803 * Flags.
804 */
805 __u32 flags;
806
807 /**
808 * Information for relocation patching.
809 */
810 struct {
811 /**
812 * @target_offset: [in]
813 *
814 * Offset from the start of the mapping of the data whose
815 * address is to be patched into the gather.
816 */
817 __u64 target_offset;
818
819 /**
820 * @gather_offset_words: [in]
821 *
822 * Offset in words from the start of the gather data to
823 * where the address should be patched into.
824 */
825 __u32 gather_offset_words;
826
827 /**
828 * @shift: [in]
829 *
830 * Number of bits the address should be shifted right before
831 * patching in.
832 */
833 __u32 shift;
834 } reloc;
835};
836
837/**
838 * define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR - \
839 * Execute Host1x opcodes from user pointer.
840 *
841 * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
842 * buffer. Each GATHER_UPTR command uses successive words from the buffer.
843 */
844#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0
845
846/**
847 * define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT - \
848 * Wait for syncpoint (absolute).
849 *
850 * Wait for a syncpoint to reach a value before continuing with further
851 * commands.
852 */
853#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1
854
855/**
856 * define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE - \
857 * Wait for syncpoint (relative).
858 *
859 * Wait for a syncpoint to reach a value before continuing with further
860 * commands. The threshold is calculated relative to the start of the job.
861 */
862#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2
863
864struct drm_tegra_submit_cmd_gather_uptr {
865 __u32 words;
866 __u32 reserved[3];
867};
868
869struct drm_tegra_submit_cmd_wait_syncpt {
870 __u32 id;
871 __u32 value;
872 __u32 reserved[2];
873};
874
875struct drm_tegra_submit_cmd {
876 /**
877 * @type: [in]
878 *
879 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
880 * defines.
881 */
882 __u32 type;
883
884 /**
885 * @flags: [in]
886 *
887 * Flags.
888 */
889 __u32 flags;
890
891 union {
892 struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
893 struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
894 __u32 reserved[4];
895 };
896};
897
898struct drm_tegra_submit_syncpt {
899 /**
900 * @id: [in]
901 *
902 * ID of the syncpoint that the job will increment.
903 */
904 __u32 id;
905
906 /**
907 * @flags: [in]
908 *
909 * Flags.
910 */
911 __u32 flags;
912
913 /**
914 * @increments: [in]
915 *
916 * Number of times the job will increment this syncpoint.
917 */
918 __u32 increments;
919
920 /**
921 * @value: [out]
922 *
923 * Value the syncpoint will have once the job has completed all
924 * its specified syncpoint increments.
925 *
926 * Note that the kernel may increment the syncpoint before or after
927 * the job. These increments are not reflected in this field.
928 *
929 * If the job hangs or times out, not all of the increments may
930 * get executed.
931 */
932 __u32 value;
933};
934
935struct drm_tegra_channel_submit {
936 /**
937 * @context: [in]
938 *
939 * Identifier of the channel to submit this job to.
940 */
941 __u32 context;
942
943 /**
944 * @num_bufs: [in]
945 *
946 * Number of elements in the `bufs_ptr` array.
947 */
948 __u32 num_bufs;
949
950 /**
951 * @num_cmds: [in]
952 *
953 * Number of elements in the `cmds_ptr` array.
954 */
955 __u32 num_cmds;
956
957 /**
958 * @gather_data_words: [in]
959 *
960 * Number of 32-bit words in the `gather_data_ptr` array.
961 */
962 __u32 gather_data_words;
963
964 /**
965 * @bufs_ptr: [in]
966 *
967 * Pointer to an array of drm_tegra_submit_buf structures.
968 */
969 __u64 bufs_ptr;
970
971 /**
972 * @cmds_ptr: [in]
973 *
974 * Pointer to an array of drm_tegra_submit_cmd structures.
975 */
976 __u64 cmds_ptr;
977
978 /**
979 * @gather_data_ptr: [in]
980 *
981 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
982 * commands.
983 */
984 __u64 gather_data_ptr;
985
986 /**
987 * @syncobj_in: [in]
988 *
989 * Handle for DRM syncobj that will be waited before submission.
990 * Ignored if zero.
991 */
992 __u32 syncobj_in;
993
994 /**
995 * @syncobj_out: [in]
996 *
997 * Handle for DRM syncobj that will have its fence replaced with
998 * the job's completion fence. Ignored if zero.
999 */
1000 __u32 syncobj_out;
1001
1002 /**
1003 * @syncpt_incr: [in,out]
1004 *
1005 * Information about the syncpoint the job will increment.
1006 */
1007 struct drm_tegra_submit_syncpt syncpt;
1008};
1009
1010struct drm_tegra_syncpoint_allocate {
1011 /**
1012 * @id: [out]
1013 *
1014 * ID of allocated syncpoint.
1015 */
1016 __u32 id;
1017 __u32 padding;
1018};
1019
1020struct drm_tegra_syncpoint_free {
1021 /**
1022 * @id: [in]
1023 *
1024 * ID of syncpoint to free.
1025 */
1026 __u32 id;
1027 __u32 padding;
1028};
1029
1030struct drm_tegra_syncpoint_wait {
1031 /**
1032 * @timeout: [in]
1033 *
1034 * Absolute timestamp at which the wait will time out.
1035 */
1036 __s64 timeout_ns;
1037
1038 /**
1039 * @id: [in]
1040 *
1041 * ID of syncpoint to wait on.
1042 */
1043 __u32 id;
1044
1045 /**
1046 * @threshold: [in]
1047 *
1048 * Threshold to wait for.
1049 */
1050 __u32 threshold;
1051
1052 /**
1053 * @value: [out]
1054 *
1055 * Value of the syncpoint upon wait completion.
1056 */
1057 __u32 value;
1058
1059 __u32 padding;
1060};
1061
1062#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
1063#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
1064#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
1065#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
1066#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
1067
1068#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
1069#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
1070#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
1071
1072#if defined(__cplusplus)
1073}
1074#endif
1075
1076#endif