1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2005, Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/* Machine dependent interfaces */
30
31#ifndef _DEV_HWPMC_AMD_H_
32#define _DEV_HWPMC_AMD_H_ 1
33
34/* AMD K8 PMCs */
35
36#define AMD_PMC_EVSEL_0 0xC0010000
37#define AMD_PMC_EVSEL_1 0xC0010001
38#define AMD_PMC_EVSEL_2 0xC0010002
39#define AMD_PMC_EVSEL_3 0xC0010003
40
41#define AMD_PMC_PERFCTR_0 0xC0010004
42#define AMD_PMC_PERFCTR_1 0xC0010005
43#define AMD_PMC_PERFCTR_2 0xC0010006
44#define AMD_PMC_PERFCTR_3 0xC0010007
45/* CORE */
46#define AMD_PMC_EVSEL_4 0xC0010208
47#define AMD_PMC_EVSEL_5 0xC001020A
48
49#define AMD_PMC_PERFCTR_4 0xC0010209
50#define AMD_PMC_PERFCTR_5 0xC001020B
51/* L3 */
52#define AMD_PMC_EVSEL_EP_L3_0 0xC0010230
53#define AMD_PMC_EVSEL_EP_L3_1 0xC0010232
54#define AMD_PMC_EVSEL_EP_L3_2 0xC0010234
55#define AMD_PMC_EVSEL_EP_L3_3 0xC0010236
56#define AMD_PMC_EVSEL_EP_L3_4 0xC0010238
57#define AMD_PMC_EVSEL_EP_L3_5 0xC001023A
58
59#define AMD_PMC_PERFCTR_EP_L3_0 0xC0010231
60#define AMD_PMC_PERFCTR_EP_L3_1 0xC0010233
61#define AMD_PMC_PERFCTR_EP_L3_2 0xC0010235
62#define AMD_PMC_PERFCTR_EP_L3_3 0xC0010237
63#define AMD_PMC_PERFCTR_EP_L3_4 0xC0010239
64#define AMD_PMC_PERFCTR_EP_L3_5 0xC001023B
65/* DF */
66#define AMD_PMC_EVSEL_EP_DF_0 0xC0010240
67#define AMD_PMC_EVSEL_EP_DF_1 0xC0010242
68#define AMD_PMC_EVSEL_EP_DF_2 0xC0010244
69#define AMD_PMC_EVSEL_EP_DF_3 0xC0010246
70
71#define AMD_PMC_PERFCTR_EP_DF_0 0xC0010241
72#define AMD_PMC_PERFCTR_EP_DF_1 0xC0010243
73#define AMD_PMC_PERFCTR_EP_DF_2 0xC0010245
74#define AMD_PMC_PERFCTR_EP_DF_3 0xC0010247
75
76#define AMD_NPMCS 16
77#define AMD_CORE_NPMCS 6
78
79
80#define AMD_PMC_COUNTERMASK 0xFF000000
81#define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK)
82#define AMD_PMC_INVERT (1 << 23)
83#define AMD_PMC_ENABLE (1 << 22)
84#define AMD_PMC_INT (1 << 20)
85#define AMD_PMC_PC (1 << 19)
86#define AMD_PMC_EDGE (1 << 18)
87#define AMD_PMC_OS (1 << 17)
88#define AMD_PMC_USR (1 << 16)
89#define AMD_PMC_L3SLICEMASK (0x000F000000000000)
90#define AMD_PMC_L3COREMASK (0xFF00000000000000)
91#define AMD_PMC_TO_L3SLICE(x) (((x) << 48) & AMD_PMC_L3SLICEMASK)
92#define AMD_PMC_TO_L3CORE(x) (((x) << 56) & AMD_PMC_L3COREMASK)
93
94#define AMD_PMC_UNITMASK_M 0x10
95#define AMD_PMC_UNITMASK_O 0x08
96#define AMD_PMC_UNITMASK_E 0x04
97#define AMD_PMC_UNITMASK_S 0x02
98#define AMD_PMC_UNITMASK_I 0x01
99#define AMD_PMC_UNITMASK_MOESI 0x1F
100
101#define AMD_PMC_UNITMASK 0xFF00
102#define AMD_PMC_EVENTMASK 0xF000000FF
103
104#define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK)
105#define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24))
106#define AMD_PMC_TO_EVENTMASK_DF(x) (((x) & 0xFF) | (((uint64_t)(x) & 0x0F00) << 24)) | (((uint64_t)(x) & 0x3000) << 47)
107#define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \
108 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \
109 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)
110
111#define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
112 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \
113 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
114
115#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
116#define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)
117
118#define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V))
119#define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
120
121enum sub_class{
122 PMC_AMD_SUB_CLASS_CORE,
123 PMC_AMD_SUB_CLASS_L3_CACHE,
124 PMC_AMD_SUB_CLASS_DATA_FABRIC
125};
126
127struct pmc_md_amd_op_pmcallocate {
128 uint64_t pm_amd_config;
129 uint32_t pm_amd_sub_class;
130};
131
132#ifdef _KERNEL
133
134/* MD extension for 'struct pmc' */
135struct pmc_md_amd_pmc {
136 uint64_t pm_amd_evsel;
137};
138
139#endif /* _KERNEL */
140#endif /* _DEV_HWPMC_AMD_H_ */