1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef __NVME_H__
30#define __NVME_H__
31
32#ifdef _KERNEL
33#include <sys/types.h>
34#endif
35
36#include <sys/param.h>
37#include <sys/endian.h>
38#ifndef _KERNEL
39#include <stdbool.h>
40#endif
41
42struct sbuf;
43
44#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
45#define NVME_RESET_CONTROLLER _IO('n', 1)
46#define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
47#define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
48#define NVME_GET_CONTROLLER_DATA _IOR('n', 4, struct nvme_controller_data)
49
50#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
51#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
52
53/* NB: Fabrics-specific ioctls defined in nvmf.h start at 200. */
54
55/*
56 * Macros to deal with NVME revisions, as defined VS register
57 */
58#define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
59#define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
60#define NVME_MINOR(r) (((r) >> 8) & 0xff)
61
62/*
63 * Use to mark a command to apply to all namespaces, or to retrieve global
64 * log pages.
65 */
66#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
67
68/* Host memory buffer sizes are always in 4096 byte chunks */
69#define NVME_HMB_UNITS 4096
70
71/* Many items are expressed in terms of power of two times MPS */
72#define NVME_MPS_SHIFT 12
73
74/* Limits on queue sizes: See 4.1.3 Queue Size in NVMe 1.4b. */
75#define NVME_MIN_ADMIN_ENTRIES 2
76#define NVME_MAX_ADMIN_ENTRIES 4096
77
78#define NVME_MIN_IO_ENTRIES 2
79#define NVME_MAX_IO_ENTRIES 65536
80
81/* Register field definitions */
82#define NVME_CAP_LO_REG_MQES_SHIFT (0)
83#define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
84#define NVME_CAP_LO_REG_CQR_SHIFT (16)
85#define NVME_CAP_LO_REG_CQR_MASK (0x1)
86#define NVME_CAP_LO_REG_AMS_SHIFT (17)
87#define NVME_CAP_LO_REG_AMS_MASK (0x3)
88#define NVME_CAP_LO_REG_TO_SHIFT (24)
89#define NVME_CAP_LO_REG_TO_MASK (0xFF)
90#define NVME_CAP_LO_MQES(x) \
91 NVMEV(NVME_CAP_LO_REG_MQES, x)
92#define NVME_CAP_LO_CQR(x) \
93 NVMEV(NVME_CAP_LO_REG_CQR, x)
94#define NVME_CAP_LO_AMS(x) \
95 NVMEV(NVME_CAP_LO_REG_AMS, x)
96#define NVME_CAP_LO_TO(x) \
97 NVMEV(NVME_CAP_LO_REG_TO, x)
98
99#define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
100#define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
101#define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
102#define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
103#define NVME_CAP_HI_REG_CSS_SHIFT (5)
104#define NVME_CAP_HI_REG_CSS_MASK (0xff)
105#define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
106#define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
107#define NVME_CAP_HI_REG_BPS_SHIFT (13)
108#define NVME_CAP_HI_REG_BPS_MASK (0x1)
109#define NVME_CAP_HI_REG_CPS_SHIFT (14)
110#define NVME_CAP_HI_REG_CPS_MASK (0x3)
111#define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
112#define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
113#define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
114#define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
115#define NVME_CAP_HI_REG_PMRS_SHIFT (24)
116#define NVME_CAP_HI_REG_PMRS_MASK (0x1)
117#define NVME_CAP_HI_REG_CMBS_SHIFT (25)
118#define NVME_CAP_HI_REG_CMBS_MASK (0x1)
119#define NVME_CAP_HI_REG_NSSS_SHIFT (26)
120#define NVME_CAP_HI_REG_NSSS_MASK (0x1)
121#define NVME_CAP_HI_REG_CRWMS_SHIFT (27)
122#define NVME_CAP_HI_REG_CRWMS_MASK (0x1)
123#define NVME_CAP_HI_REG_CRIMS_SHIFT (28)
124#define NVME_CAP_HI_REG_CRIMS_MASK (0x1)
125#define NVME_CAP_HI_DSTRD(x) \
126 NVMEV(NVME_CAP_HI_REG_DSTRD, x)
127#define NVME_CAP_HI_NSSRS(x) \
128 NVMEV(NVME_CAP_HI_REG_NSSRS, x)
129#define NVME_CAP_HI_CSS(x) \
130 NVMEV(NVME_CAP_HI_REG_CSS, x)
131#define NVME_CAP_HI_CSS_NVM(x) \
132 NVMEV(NVME_CAP_HI_REG_CSS_NVM, x)
133#define NVME_CAP_HI_BPS(x) \
134 NVMEV(NVME_CAP_HI_REG_BPS, x)
135#define NVME_CAP_HI_CPS(x) \
136 NVMEV(NVME_CAP_HI_REG_CPS, x)
137#define NVME_CAP_HI_MPSMIN(x) \
138 NVMEV(NVME_CAP_HI_REG_MPSMIN, x)
139#define NVME_CAP_HI_MPSMAX(x) \
140 NVMEV(NVME_CAP_HI_REG_MPSMAX, x)
141#define NVME_CAP_HI_PMRS(x) \
142 NVMEV(NVME_CAP_HI_REG_PMRS, x)
143#define NVME_CAP_HI_CMBS(x) \
144 NVMEV(NVME_CAP_HI_REG_CMBS, x)
145#define NVME_CAP_HI_NSSS(x) \
146 NVMEV(NVME_CAP_HI_REG_NSSS, x)
147#define NVME_CAP_HI_CRWMS(x) \
148 NVMEV(NVME_CAP_HI_REG_CRWMS, x)
149#define NVME_CAP_HI_CRIMS(x) \
150 NVMEV(NVME_CAP_HI_REG_CRIMS, x)
151
152#define NVME_CC_REG_EN_SHIFT (0)
153#define NVME_CC_REG_EN_MASK (0x1)
154#define NVME_CC_REG_CSS_SHIFT (4)
155#define NVME_CC_REG_CSS_MASK (0x7)
156#define NVME_CC_REG_MPS_SHIFT (7)
157#define NVME_CC_REG_MPS_MASK (0xF)
158#define NVME_CC_REG_AMS_SHIFT (11)
159#define NVME_CC_REG_AMS_MASK (0x7)
160#define NVME_CC_REG_SHN_SHIFT (14)
161#define NVME_CC_REG_SHN_MASK (0x3)
162#define NVME_CC_REG_IOSQES_SHIFT (16)
163#define NVME_CC_REG_IOSQES_MASK (0xF)
164#define NVME_CC_REG_IOCQES_SHIFT (20)
165#define NVME_CC_REG_IOCQES_MASK (0xF)
166#define NVME_CC_REG_CRIME_SHIFT (24)
167#define NVME_CC_REG_CRIME_MASK (0x1)
168
169#define NVME_CSTS_REG_RDY_SHIFT (0)
170#define NVME_CSTS_REG_RDY_MASK (0x1)
171#define NVME_CSTS_REG_CFS_SHIFT (1)
172#define NVME_CSTS_REG_CFS_MASK (0x1)
173#define NVME_CSTS_REG_SHST_SHIFT (2)
174#define NVME_CSTS_REG_SHST_MASK (0x3)
175#define NVME_CSTS_REG_NVSRO_SHIFT (4)
176#define NVME_CSTS_REG_NVSRO_MASK (0x1)
177#define NVME_CSTS_REG_PP_SHIFT (5)
178#define NVME_CSTS_REG_PP_MASK (0x1)
179#define NVME_CSTS_REG_ST_SHIFT (6)
180#define NVME_CSTS_REG_ST_MASK (0x1)
181
182#define NVME_CSTS_GET_SHST(csts) \
183 NVMEV(NVME_CSTS_REG_SHST, csts)
184
185#define NVME_AQA_REG_ASQS_SHIFT (0)
186#define NVME_AQA_REG_ASQS_MASK (0xFFF)
187#define NVME_AQA_REG_ACQS_SHIFT (16)
188#define NVME_AQA_REG_ACQS_MASK (0xFFF)
189
190#define NVME_PMRCAP_REG_RDS_SHIFT (3)
191#define NVME_PMRCAP_REG_RDS_MASK (0x1)
192#define NVME_PMRCAP_REG_WDS_SHIFT (4)
193#define NVME_PMRCAP_REG_WDS_MASK (0x1)
194#define NVME_PMRCAP_REG_BIR_SHIFT (5)
195#define NVME_PMRCAP_REG_BIR_MASK (0x7)
196#define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
197#define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
198#define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
199#define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
200#define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
201#define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
202#define NVME_PMRCAP_REG_CMSS_SHIFT (24)
203#define NVME_PMRCAP_REG_CMSS_MASK (0x1)
204
205#define NVME_PMRCAP_RDS(x) \
206 NVMEV(NVME_PMRCAP_REG_RDS, x)
207#define NVME_PMRCAP_WDS(x) \
208 NVMEV(NVME_PMRCAP_REG_WDS, x)
209#define NVME_PMRCAP_BIR(x) \
210 NVMEV(NVME_PMRCAP_REG_BIR, x)
211#define NVME_PMRCAP_PMRTU(x) \
212 NVMEV(NVME_PMRCAP_REG_PMRTU, x)
213#define NVME_PMRCAP_PMRWBM(x) \
214 NVMEV(NVME_PMRCAP_REG_PMRWBM, x)
215#define NVME_PMRCAP_PMRTO(x) \
216 NVMEV(NVME_PMRCAP_REG_PMRTO, x)
217#define NVME_PMRCAP_CMSS(x) \
218 NVMEV(NVME_PMRCAP_REG_CMSS, x)
219
220/* Command field definitions */
221
222enum nvme_fuse {
223 NVME_FUSE_NORMAL = 0x0,
224 NVME_FUSE_FIRST = 0x1,
225 NVME_FUSE_SECOND = 0x2
226};
227#define NVME_CMD_FUSE_SHIFT (0)
228#define NVME_CMD_FUSE_MASK (0x3)
229
230enum nvme_psdt {
231 NVME_PSDT_PRP = 0x0,
232 NVME_PSDT_SGL = 0x1,
233 NVME_PSDT_SGL_MPTR = 0x2
234};
235#define NVME_CMD_PSDT_SHIFT (6)
236#define NVME_CMD_PSDT_MASK (0x3)
237
238
239#define NVME_STATUS_P_SHIFT (0)
240#define NVME_STATUS_P_MASK (0x1)
241#define NVME_STATUS_SC_SHIFT (1)
242#define NVME_STATUS_SC_MASK (0xFF)
243#define NVME_STATUS_SCT_SHIFT (9)
244#define NVME_STATUS_SCT_MASK (0x7)
245#define NVME_STATUS_CRD_SHIFT (12)
246#define NVME_STATUS_CRD_MASK (0x3)
247#define NVME_STATUS_M_SHIFT (14)
248#define NVME_STATUS_M_MASK (0x1)
249#define NVME_STATUS_DNR_SHIFT (15)
250#define NVME_STATUS_DNR_MASK (0x1)
251
252#define NVME_STATUS_GET_P(st) \
253 NVMEV(NVME_STATUS_P, st)
254#define NVME_STATUS_GET_SC(st) \
255 NVMEV(NVME_STATUS_SC, st)
256#define NVME_STATUS_GET_SCT(st) \
257 NVMEV(NVME_STATUS_SCT, st)
258#define NVME_STATUS_GET_CRD(st) \
259 NVMEV(NVME_STATUS_CRD, st)
260#define NVME_STATUS_GET_M(st) \
261 NVMEV(NVME_STATUS_M, st)
262#define NVME_STATUS_GET_DNR(st) \
263 NVMEV(NVME_STATUS_DNR, st)
264
265#define NVME_PWR_ST_MPS_SHIFT (0)
266#define NVME_PWR_ST_MPS_MASK (0x1)
267#define NVME_PWR_ST_NOPS_SHIFT (1)
268#define NVME_PWR_ST_NOPS_MASK (0x1)
269#define NVME_PWR_ST_RRT_SHIFT (0)
270#define NVME_PWR_ST_RRT_MASK (0x1F)
271#define NVME_PWR_ST_RRL_SHIFT (0)
272#define NVME_PWR_ST_RRL_MASK (0x1F)
273#define NVME_PWR_ST_RWT_SHIFT (0)
274#define NVME_PWR_ST_RWT_MASK (0x1F)
275#define NVME_PWR_ST_RWL_SHIFT (0)
276#define NVME_PWR_ST_RWL_MASK (0x1F)
277#define NVME_PWR_ST_IPS_SHIFT (6)
278#define NVME_PWR_ST_IPS_MASK (0x3)
279#define NVME_PWR_ST_APW_SHIFT (0)
280#define NVME_PWR_ST_APW_MASK (0x7)
281#define NVME_PWR_ST_APS_SHIFT (6)
282#define NVME_PWR_ST_APS_MASK (0x3)
283
284/** Controller Multi-path I/O and Namespace Sharing Capabilities */
285/* More then one port */
286#define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
287#define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
288/* More then one controller */
289#define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
290#define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
291/* SR-IOV Virtual Function */
292#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
293#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
294/* Asymmetric Namespace Access Reporting */
295#define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
296#define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
297
298/** OAES - Optional Asynchronous Events Supported */
299/* supports Namespace Attribute Notices event */
300#define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
301#define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
302/* supports Firmware Activation Notices event */
303#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
304#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
305/* supports Asymmetric Namespace Access Change Notices event */
306#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
307#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
308/* supports Predictable Latency Event Aggregate Log Change Notices event */
309#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
310#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
311/* supports LBA Status Information Notices event */
312#define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
313#define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
314/* supports Endurance Group Event Aggregate Log Page Changes Notices event */
315#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
316#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
317/* supports Normal NVM Subsystem Shutdown event */
318#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
319#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
320/* supports Zone Descriptor Changed Notices event */
321#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
322#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
323/* supports Discovery Log Page Change Notification event */
324#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
325#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
326
327/** CTRATT - Controller Attributes */
328/* supports 128-bit Host Identifier */
329#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_SHIFT (0)
330#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_MASK (0x1)
331/* supports Non-Operational Power State Permissive Mode */
332#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_SHIFT (1)
333#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_MASK (0x1)
334/* supports NVM Sets */
335#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_SHIFT (2)
336#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_MASK (0x1)
337/* supports Read Recovery Levels */
338#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_SHIFT (3)
339#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_MASK (0x1)
340/* supports Endurance Groups */
341#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_SHIFT (4)
342#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_MASK (0x1)
343/* supports Predictable Latency Mode */
344#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_SHIFT (5)
345#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_MASK (0x1)
346/* supports Traffic Based Keep Alive Support */
347#define NVME_CTRLR_DATA_CTRATT_TBKAS_SHIFT (6)
348#define NVME_CTRLR_DATA_CTRATT_TBKAS_MASK (0x1)
349/* supports Namespace Granularity */
350#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_SHIFT (7)
351#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_MASK (0x1)
352/* supports SQ Associations */
353#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_SHIFT (8)
354#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_MASK (0x1)
355/* supports UUID List */
356#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_SHIFT (9)
357#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_MASK (0x1)
358
359/** OACS - optional admin command support */
360/* supports security send/receive commands */
361#define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
362#define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
363/* supports format nvm command */
364#define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
365#define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
366/* supports firmware activate/download commands */
367#define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
368#define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
369/* supports namespace management commands */
370#define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
371#define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
372/* supports Device Self-test command */
373#define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
374#define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
375/* supports Directives */
376#define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
377#define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
378/* supports NVMe-MI Send/Receive */
379#define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
380#define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
381/* supports Virtualization Management */
382#define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
383#define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
384/* supports Doorbell Buffer Config */
385#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
386#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
387/* supports Get LBA Status */
388#define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
389#define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
390
391/** firmware updates */
392/* first slot is read-only */
393#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
394#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
395/* number of firmware slots */
396#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
397#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
398/* firmware activation without reset */
399#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
400#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
401
402/** log page attributes */
403/* per namespace smart/health log page */
404#define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
405#define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
406/* Commands Supported and Effects log page */
407#define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_SHIFT (1)
408#define NVME_CTRLR_DATA_LPA_CMD_EFFECTS_MASK (0x1)
409/* extended data for Get Log Page command */
410#define NVME_CTRLR_DATA_LPA_EXT_DATA_SHIFT (2)
411#define NVME_CTRLR_DATA_LPA_EXT_DATA_MASK (0x1)
412/* telemetry */
413#define NVME_CTRLR_DATA_LPA_TELEMETRY_SHIFT (3)
414#define NVME_CTRLR_DATA_LPA_TELEMETRY_MASK (0x1)
415/* persistent event */
416#define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_SHIFT (4)
417#define NVME_CTRLR_DATA_LPA_PERSISTENT_EVENT_MASK (0x1)
418/* Supported log pages, etc */
419#define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_SHIFT (5)
420#define NVME_CTRLR_DATA_LPA_LOG_PAGES_PAGE_MASK (0x1)
421/* Data Area 4 for Telemetry */
422#define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_SHIFT (6)
423#define NVME_CTRLR_DATA_LPA_DA4_TELEMETRY_MASK (0x1)
424
425/** AVSCC - admin vendor specific command configuration */
426/* admin vendor specific commands use spec format */
427#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
428#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
429
430/** Autonomous Power State Transition Attributes */
431/* Autonomous Power State Transitions supported */
432#define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
433#define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
434
435/** Sanitize Capabilities */
436/* Crypto Erase Support */
437#define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
438#define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
439/* Block Erase Support */
440#define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
441#define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
442/* Overwrite Support */
443#define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
444#define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
445/* No-Deallocate Inhibited */
446#define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
447#define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
448/* No-Deallocate Modifies Media After Sanitize */
449#define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
450#define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
451#define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
452#define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
453#define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
454
455/** submission queue entry size */
456#define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
457#define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
458#define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
459#define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
460
461/** completion queue entry size */
462#define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
463#define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
464#define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
465#define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
466
467/** optional nvm command support */
468#define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
469#define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
470#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
471#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
472#define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
473#define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
474#define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
475#define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
476#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
477#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
478#define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
479#define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
480#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
481#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
482#define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
483#define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
484
485/** Fused Operation Support */
486#define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
487#define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
488
489/** Format NVM Attributes */
490#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
491#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
492#define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
493#define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
494#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
495#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
496
497/** volatile write cache */
498/* volatile write cache present */
499#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
500#define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
501/* flush all namespaces supported */
502#define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
503#define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
504#define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
505#define NVME_CTRLR_DATA_VWC_ALL_NO (2)
506#define NVME_CTRLR_DATA_VWC_ALL_YES (3)
507
508/** SGL Support */
509/* NVM command set SGL support */
510#define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_SHIFT (0)
511#define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_MASK (0x3)
512#define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_SHIFT (2)
513#define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_MASK (0x1)
514#define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_SHIFT (16)
515#define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_MASK (0x1)
516#define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_SHIFT (17)
517#define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_MASK (0x1)
518#define NVME_CTRLR_DATA_SGLS_OVERSIZED_SHIFT (18)
519#define NVME_CTRLR_DATA_SGLS_OVERSIZED_MASK (0x1)
520#define NVME_CTRLR_DATA_SGLS_MPTR_SGL_SHIFT (19)
521#define NVME_CTRLR_DATA_SGLS_MPTR_SGL_MASK (0x1)
522#define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_SHIFT (20)
523#define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_MASK (0x1)
524#define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_SHIFT (21)
525#define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_MASK (0x1)
526
527/** namespace features */
528/* thin provisioning */
529#define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
530#define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
531/* NAWUN, NAWUPF, and NACWU fields are valid */
532#define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
533#define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
534/* Deallocated or Unwritten Logical Block errors supported */
535#define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
536#define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
537/* NGUID and EUI64 fields are not reusable */
538#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
539#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
540/* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
541#define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
542#define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
543
544/** formatted lba size */
545#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
546#define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
547#define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
548#define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
549
550/** metadata capabilities */
551/* metadata can be transferred as part of data prp list */
552#define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
553#define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
554/* metadata can be transferred with separate metadata pointer */
555#define NVME_NS_DATA_MC_POINTER_SHIFT (1)
556#define NVME_NS_DATA_MC_POINTER_MASK (0x1)
557
558/** end-to-end data protection capabilities */
559/* protection information type 1 */
560#define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
561#define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
562/* protection information type 2 */
563#define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
564#define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
565/* protection information type 3 */
566#define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
567#define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
568/* first eight bytes of metadata */
569#define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
570#define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
571/* last eight bytes of metadata */
572#define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
573#define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
574
575/** end-to-end data protection type settings */
576/* protection information type */
577#define NVME_NS_DATA_DPS_PIT_SHIFT (0)
578#define NVME_NS_DATA_DPS_PIT_MASK (0x7)
579/* 1 == protection info transferred at start of metadata */
580/* 0 == protection info transferred at end of metadata */
581#define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
582#define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
583
584/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
585/* the namespace may be attached to two or more controllers */
586#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
587#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
588
589/** Reservation Capabilities */
590/* Persist Through Power Loss */
591#define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
592#define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
593/* supports the Write Exclusive */
594#define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
595#define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
596/* supports the Exclusive Access */
597#define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
598#define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
599/* supports the Write Exclusive – Registrants Only */
600#define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
601#define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
602/* supports the Exclusive Access - Registrants Only */
603#define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
604#define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
605/* supports the Write Exclusive – All Registrants */
606#define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
607#define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
608/* supports the Exclusive Access - All Registrants */
609#define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
610#define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
611/* Ignore Existing Key is used as defined in revision 1.3 or later */
612#define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
613#define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
614
615/** Format Progress Indicator */
616/* percentage of the Format NVM command that remains to be completed */
617#define NVME_NS_DATA_FPI_PERC_SHIFT (0)
618#define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
619/* namespace supports the Format Progress Indicator */
620#define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
621#define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
622
623/** Deallocate Logical Block Features */
624/* deallocated logical block read behavior */
625#define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
626#define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
627#define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
628#define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
629#define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
630/* supports the Deallocate bit in the Write Zeroes */
631#define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
632#define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
633/* Guard field for deallocated logical blocks is set to the CRC */
634#define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
635#define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
636
637/** lba format support */
638/* metadata size */
639#define NVME_NS_DATA_LBAF_MS_SHIFT (0)
640#define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
641/* lba data size */
642#define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
643#define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
644/* relative performance */
645#define NVME_NS_DATA_LBAF_RP_SHIFT (24)
646#define NVME_NS_DATA_LBAF_RP_MASK (0x3)
647
648enum nvme_critical_warning_state {
649 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
650 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
651 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
652 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
653 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
654 NVME_CRIT_WARN_ST_PERSISTENT_MEMORY_REGION = 0x20,
655};
656#define NVME_CRIT_WARN_ST_RESERVED_MASK (0xC0)
657#define NVME_ASYNC_EVENT_NS_ATTRIBUTE (1U << 8)
658#define NVME_ASYNC_EVENT_FW_ACTIVATE (1U << 9)
659#define NVME_ASYNC_EVENT_TELEMETRY_LOG (1U << 10)
660#define NVME_ASYNC_EVENT_ASYM_NS_ACC (1U << 11)
661#define NVME_ASYNC_EVENT_PRED_LAT_DELTA (1U << 12)
662#define NVME_ASYNC_EVENT_LBA_STATUS (1U << 13)
663#define NVME_ASYNC_EVENT_ENDURANCE_DELTA (1U << 14)
664#define NVME_ASYNC_EVENT_NVM_SHUTDOWN (1U << 15)
665#define NVME_ASYNC_EVENT_ZONE_DELTA (1U << 27)
666#define NVME_ASYNC_EVENT_DISCOVERY_DELTA (1U << 31)
667
668/* slot for current FW */
669#define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
670#define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
671
672/* Commands Supported and Effects */
673#define NVME_CE_PAGE_CSUP_SHIFT (0)
674#define NVME_CE_PAGE_CSUP_MASK (0x1)
675#define NVME_CE_PAGE_LBCC_SHIFT (1)
676#define NVME_CE_PAGE_LBCC_MASK (0x1)
677#define NVME_CE_PAGE_NCC_SHIFT (2)
678#define NVME_CE_PAGE_NCC_MASK (0x1)
679#define NVME_CE_PAGE_NIC_SHIFT (3)
680#define NVME_CE_PAGE_NIC_MASK (0x1)
681#define NVME_CE_PAGE_CCC_SHIFT (4)
682#define NVME_CE_PAGE_CCC_MASK (0x1)
683#define NVME_CE_PAGE_CSE_SHIFT (16)
684#define NVME_CE_PAGE_CSE_MASK (0x7)
685#define NVME_CE_PAGE_UUID_SHIFT (19)
686#define NVME_CE_PAGE_UUID_MASK (0x1)
687
688/* Sanitize Status */
689#define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
690#define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
691#define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
692#define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
693#define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
694#define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
695#define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
696#define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
697#define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
698#define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
699#define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
700
701/* Features */
702/* Get Features */
703#define NVME_FEAT_GET_SEL_SHIFT (8)
704#define NVME_FEAT_GET_SEL_MASK (0x7)
705#define NVME_FEAT_GET_FID_SHIFT (0)
706#define NVME_FEAT_GET_FID_MASK (0xff)
707
708/* Set Features */
709#define NVME_FEAT_SET_SV_SHIFT (31)
710#define NVME_FEAT_SET_SV_MASK (0x1)
711#define NVME_FEAT_SET_FID_SHIFT (0)
712#define NVME_FEAT_SET_FID_MASK (0xff)
713
714/* Async Events */
715#define NVME_ASYNC_EVENT_TYPE_SHIFT (0)
716#define NVME_ASYNC_EVENT_TYPE_MASK (0x7)
717#define NVME_ASYNC_EVENT_INFO_SHIFT (8)
718#define NVME_ASYNC_EVENT_INFO_MASK (0xff)
719#define NVME_ASYNC_EVENT_LOG_PAGE_ID_SHIFT (16)
720#define NVME_ASYNC_EVENT_LOG_PAGE_ID_MASK (0xff)
721
722/* Helper macro to combine *_MASK and *_SHIFT defines */
723#define NVMEM(name) (name##_MASK << name##_SHIFT)
724
725/* Helper macro to extract value from x */
726#define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
727
728/* Helper macro to construct a field value */
729#define NVMEF(name, x) (((x) & name##_MASK) << name##_SHIFT)
730
731/* CC register SHN field values */
732enum shn_value {
733 NVME_SHN_NORMAL = 0x1,
734 NVME_SHN_ABRUPT = 0x2,
735};
736
737/* CSTS register SHST field values */
738enum shst_value {
739 NVME_SHST_NORMAL = 0x0,
740 NVME_SHST_OCCURRING = 0x1,
741 NVME_SHST_COMPLETE = 0x2,
742};
743
744struct nvme_registers {
745 uint32_t cap_lo; /* controller capabilities */
746 uint32_t cap_hi;
747 uint32_t vs; /* version */
748 uint32_t intms; /* interrupt mask set */
749 uint32_t intmc; /* interrupt mask clear */
750 uint32_t cc; /* controller configuration */
751 uint32_t reserved1;
752 uint32_t csts; /* controller status */
753 uint32_t nssr; /* NVM Subsystem Reset */
754 uint32_t aqa; /* admin queue attributes */
755 uint64_t asq; /* admin submission queue base addr */
756 uint64_t acq; /* admin completion queue base addr */
757 uint32_t cmbloc; /* Controller Memory Buffer Location */
758 uint32_t cmbsz; /* Controller Memory Buffer Size */
759 uint32_t bpinfo; /* Boot Partition Information */
760 uint32_t bprsel; /* Boot Partition Read Select */
761 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
762 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
763 uint32_t cmbsts; /* Controller Memory Buffer Status */
764 uint32_t cmbebs; /* Controller Memory Buffer Elasticity Buffer Size */
765 uint32_t cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */
766 uint32_t nssd; /* NVM Subsystem Shutdown */
767 uint32_t crto; /* Controller Ready Timeouts */
768 uint8_t reserved3[3476]; /* 6Ch - DFFh */
769 uint32_t pmrcap; /* Persistent Memory Capabilities */
770 uint32_t pmrctl; /* Persistent Memory Region Control */
771 uint32_t pmrsts; /* Persistent Memory Region Status */
772 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
773 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
774 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
775 uint32_t pmrmsc_hi;
776 uint8_t reserved4[484]; /* E1Ch - FFFh */
777 struct {
778 uint32_t sq_tdbl; /* submission queue tail doorbell */
779 uint32_t cq_hdbl; /* completion queue head doorbell */
780 } doorbell[1];
781};
782
783_Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
784
785#define NVME_SGL_SUBTYPE_SHIFT (0)
786#define NVME_SGL_SUBTYPE_MASK (0xF)
787#define NVME_SGL_TYPE_SHIFT (4)
788#define NVME_SGL_TYPE_MASK (0xF)
789
790#define NVME_SGL_TYPE(type, subtype) \
791 ((subtype) << NVME_SGL_SUBTYPE_SHIFT | (type) << NVME_SGL_TYPE_SHIFT)
792
793enum nvme_sgl_type {
794 NVME_SGL_TYPE_DATA_BLOCK = 0x0,
795 NVME_SGL_TYPE_BIT_BUCKET = 0x1,
796 NVME_SGL_TYPE_SEGMENT = 0x2,
797 NVME_SGL_TYPE_LAST_SEGMENT = 0x3,
798 NVME_SGL_TYPE_KEYED_DATA_BLOCK = 0x4,
799 NVME_SGL_TYPE_TRANSPORT_DATA_BLOCK = 0x5,
800};
801
802enum nvme_sgl_subtype {
803 NVME_SGL_SUBTYPE_ADDRESS = 0x0,
804 NVME_SGL_SUBTYPE_OFFSET = 0x1,
805 NVME_SGL_SUBTYPE_TRANSPORT = 0xa,
806};
807
808struct nvme_sgl_descriptor {
809 uint64_t address;
810 uint32_t length;
811 uint8_t reserved[3];
812 uint8_t type;
813};
814
815_Static_assert(sizeof(struct nvme_sgl_descriptor) == 16, "bad size for nvme_sgl_descriptor");
816
817struct nvme_command {
818 /* dword 0 */
819 uint8_t opc; /* opcode */
820 uint8_t fuse; /* fused operation */
821 uint16_t cid; /* command identifier */
822
823 /* dword 1 */
824 uint32_t nsid; /* namespace identifier */
825
826 /* dword 2-3 */
827 uint32_t rsvd2;
828 uint32_t rsvd3;
829
830 /* dword 4-5 */
831 uint64_t mptr; /* metadata pointer */
832
833 /* dword 6-9 */
834 union {
835 struct {
836 uint64_t prp1; /* prp entry 1 */
837 uint64_t prp2; /* prp entry 2 */
838 };
839 struct nvme_sgl_descriptor sgl;
840 };
841
842 /* dword 10-15 */
843 uint32_t cdw10; /* command-specific */
844 uint32_t cdw11; /* command-specific */
845 uint32_t cdw12; /* command-specific */
846 uint32_t cdw13; /* command-specific */
847 uint32_t cdw14; /* command-specific */
848 uint32_t cdw15; /* command-specific */
849} __aligned(8);
850
851_Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
852
853struct nvme_completion {
854 /* dword 0 */
855 uint32_t cdw0; /* command-specific */
856
857 /* dword 1 */
858 uint32_t rsvd1;
859
860 /* dword 2 */
861 uint16_t sqhd; /* submission queue head pointer */
862 uint16_t sqid; /* submission queue identifier */
863
864 /* dword 3 */
865 uint16_t cid; /* command identifier */
866 uint16_t status;
867} __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
868
869_Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
870
871struct nvme_dsm_range {
872 uint32_t attributes;
873 uint32_t length;
874 uint64_t starting_lba;
875};
876
877/* Largest DSM Trim that can be done */
878#define NVME_MAX_DSM_TRIM 4096
879
880_Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
881
882/* status code types */
883enum nvme_status_code_type {
884 NVME_SCT_GENERIC = 0x0,
885 NVME_SCT_COMMAND_SPECIFIC = 0x1,
886 NVME_SCT_MEDIA_ERROR = 0x2,
887 NVME_SCT_PATH_RELATED = 0x3,
888 /* 0x3-0x6 - reserved */
889 NVME_SCT_VENDOR_SPECIFIC = 0x7,
890};
891
892/* generic command status codes */
893enum nvme_generic_command_status_code {
894 NVME_SC_SUCCESS = 0x00,
895 NVME_SC_INVALID_OPCODE = 0x01,
896 NVME_SC_INVALID_FIELD = 0x02,
897 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
898 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
899 NVME_SC_ABORTED_POWER_LOSS = 0x05,
900 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
901 NVME_SC_ABORTED_BY_REQUEST = 0x07,
902 NVME_SC_ABORTED_SQ_DELETION = 0x08,
903 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
904 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
905 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
906 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
907 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
908 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
909 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
910 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
911 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
912 NVME_SC_INVALID_USE_OF_CMB = 0x12,
913 NVME_SC_PRP_OFFET_INVALID = 0x13,
914 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
915 NVME_SC_OPERATION_DENIED = 0x15,
916 NVME_SC_SGL_OFFSET_INVALID = 0x16,
917 /* 0x17 - reserved */
918 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
919 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
920 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
921 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
922 NVME_SC_SANITIZE_FAILED = 0x1c,
923 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
924 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
925 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
926 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
927 NVME_SC_COMMAND_INTERRUPTED = 0x21,
928 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
929
930 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
931 NVME_SC_CAPACITY_EXCEEDED = 0x81,
932 NVME_SC_NAMESPACE_NOT_READY = 0x82,
933 NVME_SC_RESERVATION_CONFLICT = 0x83,
934 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
935};
936
937/* command specific status codes */
938enum nvme_command_specific_status_code {
939 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
940 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
941 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
942 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
943 /* 0x04 - reserved */
944 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
945 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
946 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
947 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
948 NVME_SC_INVALID_LOG_PAGE = 0x09,
949 NVME_SC_INVALID_FORMAT = 0x0a,
950 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
951 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
952 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
953 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
954 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
955 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
956 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
957 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
958 NVME_SC_FW_ACT_PROHIBITED = 0x13,
959 NVME_SC_OVERLAPPING_RANGE = 0x14,
960 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
961 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
962 /* 0x17 - reserved */
963 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
964 NVME_SC_NS_IS_PRIVATE = 0x19,
965 NVME_SC_NS_NOT_ATTACHED = 0x1a,
966 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
967 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
968 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
969 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
970 NVME_SC_INVALID_CTRLR_ID = 0x1f,
971 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
972 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
973 NVME_SC_INVALID_RESOURCE_ID = 0x22,
974 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
975 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
976 NVME_SC_ANA_ATTACH_FAILED = 0x25,
977
978 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
979 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
980 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
981};
982
983/* media error status codes */
984enum nvme_media_error_status_code {
985 NVME_SC_WRITE_FAULTS = 0x80,
986 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
987 NVME_SC_GUARD_CHECK_ERROR = 0x82,
988 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
989 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
990 NVME_SC_COMPARE_FAILURE = 0x85,
991 NVME_SC_ACCESS_DENIED = 0x86,
992 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
993};
994
995/* path related status codes */
996enum nvme_path_related_status_code {
997 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
998 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
999 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
1000 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
1001 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
1002 NVME_SC_HOST_PATHING_ERROR = 0x70,
1003 NVME_SC_COMMAND_ABORTED_BY_HOST = 0x71,
1004};
1005
1006/* admin opcodes */
1007enum nvme_admin_opcode {
1008 NVME_OPC_DELETE_IO_SQ = 0x00,
1009 NVME_OPC_CREATE_IO_SQ = 0x01,
1010 NVME_OPC_GET_LOG_PAGE = 0x02,
1011 /* 0x03 - reserved */
1012 NVME_OPC_DELETE_IO_CQ = 0x04,
1013 NVME_OPC_CREATE_IO_CQ = 0x05,
1014 NVME_OPC_IDENTIFY = 0x06,
1015 /* 0x07 - reserved */
1016 NVME_OPC_ABORT = 0x08,
1017 NVME_OPC_SET_FEATURES = 0x09,
1018 NVME_OPC_GET_FEATURES = 0x0a,
1019 /* 0x0b - reserved */
1020 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
1021 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
1022 /* 0x0e-0x0f - reserved */
1023 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
1024 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
1025 /* 0x12-0x13 - reserved */
1026 NVME_OPC_DEVICE_SELF_TEST = 0x14,
1027 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
1028 /* 0x16-0x17 - reserved */
1029 NVME_OPC_KEEP_ALIVE = 0x18,
1030 NVME_OPC_DIRECTIVE_SEND = 0x19,
1031 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
1032 /* 0x1b - reserved */
1033 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
1034 NVME_OPC_NVME_MI_SEND = 0x1d,
1035 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
1036 /* 0x1f - reserved */
1037 NVME_OPC_CAPACITY_MANAGEMENT = 0x20,
1038 /* 0x21-0x23 - reserved */
1039 NVME_OPC_LOCKDOWN = 0x24,
1040 /* 0x25-0x7b - reserved */
1041 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
1042 /* 0x7d-0x7e - reserved */
1043 NVME_OPC_FABRICS_COMMANDS = 0x7f,
1044
1045 NVME_OPC_FORMAT_NVM = 0x80,
1046 NVME_OPC_SECURITY_SEND = 0x81,
1047 NVME_OPC_SECURITY_RECEIVE = 0x82,
1048 /* 0x83 - reserved */
1049 NVME_OPC_SANITIZE = 0x84,
1050 /* 0x85 - reserved */
1051 NVME_OPC_GET_LBA_STATUS = 0x86,
1052};
1053
1054/* nvme nvm opcodes */
1055enum nvme_nvm_opcode {
1056 NVME_OPC_FLUSH = 0x00,
1057 NVME_OPC_WRITE = 0x01,
1058 NVME_OPC_READ = 0x02,
1059 /* 0x03 - reserved */
1060 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
1061 NVME_OPC_COMPARE = 0x05,
1062 /* 0x06-0x07 - reserved */
1063 NVME_OPC_WRITE_ZEROES = 0x08,
1064 NVME_OPC_DATASET_MANAGEMENT = 0x09,
1065 /* 0x0a-0x0b - reserved */
1066 NVME_OPC_VERIFY = 0x0c,
1067 NVME_OPC_RESERVATION_REGISTER = 0x0d,
1068 NVME_OPC_RESERVATION_REPORT = 0x0e,
1069 /* 0x0f-0x10 - reserved */
1070 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
1071 /* 0x12-0x14 - reserved */
1072 NVME_OPC_RESERVATION_RELEASE = 0x15,
1073 /* 0x16-0x18 - reserved */
1074 NVME_OPC_COPY = 0x19,
1075};
1076
1077enum nvme_feature {
1078 /* 0x00 - reserved */
1079 NVME_FEAT_ARBITRATION = 0x01,
1080 NVME_FEAT_POWER_MANAGEMENT = 0x02,
1081 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
1082 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
1083 NVME_FEAT_ERROR_RECOVERY = 0x05,
1084 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
1085 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
1086 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
1087 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
1088 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
1089 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
1090 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
1091 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
1092 NVME_FEAT_TIMESTAMP = 0x0E,
1093 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
1094 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
1095 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
1096 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
1097 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
1098 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
1099 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
1100 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
1101 NVME_FEAT_SANITIZE_CONFIG = 0x17,
1102 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
1103 /* 0x19-0x77 - reserved */
1104 /* 0x78-0x7f - NVMe Management Interface */
1105 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
1106 NVME_FEAT_HOST_IDENTIFIER = 0x81,
1107 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
1108 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
1109 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
1110 /* 0x85-0xBF - command set specific (reserved) */
1111 /* 0xC0-0xFF - vendor specific */
1112};
1113
1114enum nvme_dsm_attribute {
1115 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
1116 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
1117 NVME_DSM_ATTR_DEALLOCATE = 0x4,
1118};
1119
1120enum nvme_activate_action {
1121 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
1122 NVME_AA_REPLACE_ACTIVATE = 0x1,
1123 NVME_AA_ACTIVATE = 0x2,
1124};
1125
1126struct nvme_power_state {
1127 /** Maximum Power */
1128 uint16_t mp; /* Maximum Power */
1129 uint8_t ps_rsvd1;
1130 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
1131
1132 uint32_t enlat; /* Entry Latency */
1133 uint32_t exlat; /* Exit Latency */
1134
1135 uint8_t rrt; /* Relative Read Throughput */
1136 uint8_t rrl; /* Relative Read Latency */
1137 uint8_t rwt; /* Relative Write Throughput */
1138 uint8_t rwl; /* Relative Write Latency */
1139
1140 uint16_t idlp; /* Idle Power */
1141 uint8_t ips; /* Idle Power Scale */
1142 uint8_t ps_rsvd8;
1143
1144 uint16_t actp; /* Active Power */
1145 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
1146 uint8_t ps_rsvd10[9];
1147} __packed;
1148
1149_Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
1150
1151#define NVME_SERIAL_NUMBER_LENGTH 20
1152#define NVME_MODEL_NUMBER_LENGTH 40
1153#define NVME_FIRMWARE_REVISION_LENGTH 8
1154
1155struct nvme_controller_data {
1156 /* bytes 0-255: controller capabilities and features */
1157
1158 /** pci vendor id */
1159 uint16_t vid;
1160
1161 /** pci subsystem vendor id */
1162 uint16_t ssvid;
1163
1164 /** serial number */
1165 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
1166
1167 /** model number */
1168 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
1169
1170 /** firmware revision */
1171 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
1172
1173 /** recommended arbitration burst */
1174 uint8_t rab;
1175
1176 /** ieee oui identifier */
1177 uint8_t ieee[3];
1178
1179 /** multi-interface capabilities */
1180 uint8_t mic;
1181
1182 /** maximum data transfer size */
1183 uint8_t mdts;
1184
1185 /** Controller ID */
1186 uint16_t ctrlr_id;
1187
1188 /** Version */
1189 uint32_t ver;
1190
1191 /** RTD3 Resume Latency */
1192 uint32_t rtd3r;
1193
1194 /** RTD3 Enter Latency */
1195 uint32_t rtd3e;
1196
1197 /** Optional Asynchronous Events Supported */
1198 uint32_t oaes; /* bitfield really */
1199
1200 /** Controller Attributes */
1201 uint32_t ctratt; /* bitfield really */
1202
1203 /** Read Recovery Levels Supported */
1204 uint16_t rrls;
1205
1206 uint8_t reserved1[9];
1207
1208 /** Controller Type */
1209 uint8_t cntrltype;
1210
1211 /** FRU Globally Unique Identifier */
1212 uint8_t fguid[16];
1213
1214 /** Command Retry Delay Time 1 */
1215 uint16_t crdt1;
1216
1217 /** Command Retry Delay Time 2 */
1218 uint16_t crdt2;
1219
1220 /** Command Retry Delay Time 3 */
1221 uint16_t crdt3;
1222
1223 uint8_t reserved2[122];
1224
1225 /* bytes 256-511: admin command set attributes */
1226
1227 /** optional admin command support */
1228 uint16_t oacs;
1229
1230 /** abort command limit */
1231 uint8_t acl;
1232
1233 /** asynchronous event request limit */
1234 uint8_t aerl;
1235
1236 /** firmware updates */
1237 uint8_t frmw;
1238
1239 /** log page attributes */
1240 uint8_t lpa;
1241
1242 /** error log page entries */
1243 uint8_t elpe;
1244
1245 /** number of power states supported */
1246 uint8_t npss;
1247
1248 /** admin vendor specific command configuration */
1249 uint8_t avscc;
1250
1251 /** Autonomous Power State Transition Attributes */
1252 uint8_t apsta;
1253
1254 /** Warning Composite Temperature Threshold */
1255 uint16_t wctemp;
1256
1257 /** Critical Composite Temperature Threshold */
1258 uint16_t cctemp;
1259
1260 /** Maximum Time for Firmware Activation */
1261 uint16_t mtfa;
1262
1263 /** Host Memory Buffer Preferred Size */
1264 uint32_t hmpre;
1265
1266 /** Host Memory Buffer Minimum Size */
1267 uint32_t hmmin;
1268
1269 /** Name space capabilities */
1270 struct {
1271 /* if nsmgmt, report tnvmcap and unvmcap */
1272 uint8_t tnvmcap[16];
1273 uint8_t unvmcap[16];
1274 } __packed untncap;
1275
1276 /** Replay Protected Memory Block Support */
1277 uint32_t rpmbs; /* Really a bitfield */
1278
1279 /** Extended Device Self-test Time */
1280 uint16_t edstt;
1281
1282 /** Device Self-test Options */
1283 uint8_t dsto; /* Really a bitfield */
1284
1285 /** Firmware Update Granularity */
1286 uint8_t fwug;
1287
1288 /** Keep Alive Support */
1289 uint16_t kas;
1290
1291 /** Host Controlled Thermal Management Attributes */
1292 uint16_t hctma; /* Really a bitfield */
1293
1294 /** Minimum Thermal Management Temperature */
1295 uint16_t mntmt;
1296
1297 /** Maximum Thermal Management Temperature */
1298 uint16_t mxtmt;
1299
1300 /** Sanitize Capabilities */
1301 uint32_t sanicap; /* Really a bitfield */
1302
1303 /** Host Memory Buffer Minimum Descriptor Entry Size */
1304 uint32_t hmminds;
1305
1306 /** Host Memory Maximum Descriptors Entries */
1307 uint16_t hmmaxd;
1308
1309 /** NVM Set Identifier Maximum */
1310 uint16_t nsetidmax;
1311
1312 /** Endurance Group Identifier Maximum */
1313 uint16_t endgidmax;
1314
1315 /** ANA Transition Time */
1316 uint8_t anatt;
1317
1318 /** Asymmetric Namespace Access Capabilities */
1319 uint8_t anacap;
1320
1321 /** ANA Group Identifier Maximum */
1322 uint32_t anagrpmax;
1323
1324 /** Number of ANA Group Identifiers */
1325 uint32_t nanagrpid;
1326
1327 /** Persistent Event Log Size */
1328 uint32_t pels;
1329
1330 uint8_t reserved3[156];
1331 /* bytes 512-703: nvm command set attributes */
1332
1333 /** submission queue entry size */
1334 uint8_t sqes;
1335
1336 /** completion queue entry size */
1337 uint8_t cqes;
1338
1339 /** Maximum Outstanding Commands */
1340 uint16_t maxcmd;
1341
1342 /** number of namespaces */
1343 uint32_t nn;
1344
1345 /** optional nvm command support */
1346 uint16_t oncs;
1347
1348 /** fused operation support */
1349 uint16_t fuses;
1350
1351 /** format nvm attributes */
1352 uint8_t fna;
1353
1354 /** volatile write cache */
1355 uint8_t vwc;
1356
1357 /** Atomic Write Unit Normal */
1358 uint16_t awun;
1359
1360 /** Atomic Write Unit Power Fail */
1361 uint16_t awupf;
1362
1363 /** NVM Vendor Specific Command Configuration */
1364 uint8_t nvscc;
1365
1366 /** Namespace Write Protection Capabilities */
1367 uint8_t nwpc;
1368
1369 /** Atomic Compare & Write Unit */
1370 uint16_t acwu;
1371 uint16_t reserved6;
1372
1373 /** SGL Support */
1374 uint32_t sgls;
1375
1376 /** Maximum Number of Allowed Namespaces */
1377 uint32_t mnan;
1378
1379 /* bytes 540-767: Reserved */
1380 uint8_t reserved7[224];
1381
1382 /** NVM Subsystem NVMe Qualified Name */
1383 uint8_t subnqn[256];
1384
1385 /* bytes 1024-1791: Reserved */
1386 uint8_t reserved8[768];
1387
1388 /* bytes 1792-2047: NVMe over Fabrics specification */
1389 uint32_t ioccsz;
1390 uint32_t iorcsz;
1391 uint16_t icdoff;
1392 uint8_t fcatt;
1393 uint8_t msdbd;
1394 uint16_t ofcs;
1395 uint8_t reserved9[242];
1396
1397 /* bytes 2048-3071: power state descriptors */
1398 struct nvme_power_state power_state[32];
1399
1400 /* bytes 3072-4095: vendor specific */
1401 uint8_t vs[1024];
1402} __packed __aligned(4);
1403
1404_Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1405
1406struct nvme_namespace_data {
1407 /** namespace size */
1408 uint64_t nsze;
1409
1410 /** namespace capacity */
1411 uint64_t ncap;
1412
1413 /** namespace utilization */
1414 uint64_t nuse;
1415
1416 /** namespace features */
1417 uint8_t nsfeat;
1418
1419 /** number of lba formats */
1420 uint8_t nlbaf;
1421
1422 /** formatted lba size */
1423 uint8_t flbas;
1424
1425 /** metadata capabilities */
1426 uint8_t mc;
1427
1428 /** end-to-end data protection capabilities */
1429 uint8_t dpc;
1430
1431 /** end-to-end data protection type settings */
1432 uint8_t dps;
1433
1434 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1435 uint8_t nmic;
1436
1437 /** Reservation Capabilities */
1438 uint8_t rescap;
1439
1440 /** Format Progress Indicator */
1441 uint8_t fpi;
1442
1443 /** Deallocate Logical Block Features */
1444 uint8_t dlfeat;
1445
1446 /** Namespace Atomic Write Unit Normal */
1447 uint16_t nawun;
1448
1449 /** Namespace Atomic Write Unit Power Fail */
1450 uint16_t nawupf;
1451
1452 /** Namespace Atomic Compare & Write Unit */
1453 uint16_t nacwu;
1454
1455 /** Namespace Atomic Boundary Size Normal */
1456 uint16_t nabsn;
1457
1458 /** Namespace Atomic Boundary Offset */
1459 uint16_t nabo;
1460
1461 /** Namespace Atomic Boundary Size Power Fail */
1462 uint16_t nabspf;
1463
1464 /** Namespace Optimal IO Boundary */
1465 uint16_t noiob;
1466
1467 /** NVM Capacity */
1468 uint8_t nvmcap[16];
1469
1470 /** Namespace Preferred Write Granularity */
1471 uint16_t npwg;
1472
1473 /** Namespace Preferred Write Alignment */
1474 uint16_t npwa;
1475
1476 /** Namespace Preferred Deallocate Granularity */
1477 uint16_t npdg;
1478
1479 /** Namespace Preferred Deallocate Alignment */
1480 uint16_t npda;
1481
1482 /** Namespace Optimal Write Size */
1483 uint16_t nows;
1484
1485 /* bytes 74-91: Reserved */
1486 uint8_t reserved5[18];
1487
1488 /** ANA Group Identifier */
1489 uint32_t anagrpid;
1490
1491 /* bytes 96-98: Reserved */
1492 uint8_t reserved6[3];
1493
1494 /** Namespace Attributes */
1495 uint8_t nsattr;
1496
1497 /** NVM Set Identifier */
1498 uint16_t nvmsetid;
1499
1500 /** Endurance Group Identifier */
1501 uint16_t endgid;
1502
1503 /** Namespace Globally Unique Identifier */
1504 uint8_t nguid[16];
1505
1506 /** IEEE Extended Unique Identifier */
1507 uint8_t eui64[8];
1508
1509 /** lba format support */
1510 uint32_t lbaf[16];
1511
1512 uint8_t reserved7[192];
1513
1514 uint8_t vendor_specific[3712];
1515} __packed __aligned(4);
1516
1517_Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1518
1519enum nvme_log_page {
1520 /* 0x00 - reserved */
1521 NVME_LOG_ERROR = 0x01,
1522 NVME_LOG_HEALTH_INFORMATION = 0x02,
1523 NVME_LOG_FIRMWARE_SLOT = 0x03,
1524 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1525 NVME_LOG_COMMAND_EFFECT = 0x05,
1526 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1527 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1528 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1529 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1530 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1531 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1532 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1533 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1534 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1535 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1536 NVME_LOG_DISCOVERY = 0x70,
1537 /* 0x06-0x7F - reserved */
1538 /* 0x80-0xBF - I/O command set specific */
1539 NVME_LOG_RES_NOTIFICATION = 0x80,
1540 NVME_LOG_SANITIZE_STATUS = 0x81,
1541 /* 0x82-0xBF - reserved */
1542 /* 0xC0-0xFF - vendor specific */
1543
1544 /*
1545 * The following are Intel Specific log pages, but they seem
1546 * to be widely implemented.
1547 */
1548 INTEL_LOG_READ_LAT_LOG = 0xc1,
1549 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1550 INTEL_LOG_TEMP_STATS = 0xc5,
1551 INTEL_LOG_ADD_SMART = 0xca,
1552 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1553
1554 /*
1555 * HGST log page, with lots ofs sub pages.
1556 */
1557 HGST_INFO_LOG = 0xc1,
1558};
1559
1560struct nvme_error_information_entry {
1561 uint64_t error_count;
1562 uint16_t sqid;
1563 uint16_t cid;
1564 uint16_t status;
1565 uint16_t error_location;
1566 uint64_t lba;
1567 uint32_t nsid;
1568 uint8_t vendor_specific;
1569 uint8_t trtype;
1570 uint16_t reserved30;
1571 uint64_t csi;
1572 uint16_t ttsi;
1573 uint8_t reserved[22];
1574} __packed __aligned(4);
1575
1576_Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1577
1578struct nvme_health_information_page {
1579 uint8_t critical_warning;
1580 uint16_t temperature;
1581 uint8_t available_spare;
1582 uint8_t available_spare_threshold;
1583 uint8_t percentage_used;
1584
1585 uint8_t reserved[26];
1586
1587 /*
1588 * Note that the following are 128-bit values, but are
1589 * defined as an array of 2 64-bit values.
1590 */
1591 /* Data Units Read is always in 512-byte units. */
1592 uint64_t data_units_read[2];
1593 /* Data Units Written is always in 512-byte units. */
1594 uint64_t data_units_written[2];
1595 /* For NVM command set, this includes Compare commands. */
1596 uint64_t host_read_commands[2];
1597 uint64_t host_write_commands[2];
1598 /* Controller Busy Time is reported in minutes. */
1599 uint64_t controller_busy_time[2];
1600 uint64_t power_cycles[2];
1601 uint64_t power_on_hours[2];
1602 uint64_t unsafe_shutdowns[2];
1603 uint64_t media_errors[2];
1604 uint64_t num_error_info_log_entries[2];
1605 uint32_t warning_temp_time;
1606 uint32_t error_temp_time;
1607 uint16_t temp_sensor[8];
1608 /* Thermal Management Temperature 1 Transition Count */
1609 uint32_t tmt1tc;
1610 /* Thermal Management Temperature 2 Transition Count */
1611 uint32_t tmt2tc;
1612 /* Total Time For Thermal Management Temperature 1 */
1613 uint32_t ttftmt1;
1614 /* Total Time For Thermal Management Temperature 2 */
1615 uint32_t ttftmt2;
1616
1617 uint8_t reserved2[280];
1618} __packed __aligned(8);
1619
1620_Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1621
1622struct nvme_firmware_page {
1623 uint8_t afi;
1624 uint8_t reserved[7];
1625 /* revisions for 7 slots */
1626 uint8_t revision[7][NVME_FIRMWARE_REVISION_LENGTH];
1627 uint8_t reserved2[448];
1628} __packed __aligned(4);
1629
1630_Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1631
1632struct nvme_ns_list {
1633 uint32_t ns[1024];
1634} __packed __aligned(4);
1635
1636_Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1637
1638struct nvme_command_effects_page {
1639 uint32_t acs[256];
1640 uint32_t iocs[256];
1641 uint8_t reserved[2048];
1642} __packed __aligned(4);
1643
1644_Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1645 "bad size for nvme_command_effects_page");
1646
1647struct nvme_device_self_test_page {
1648 uint8_t curr_operation;
1649 uint8_t curr_compl;
1650 uint8_t rsvd2[2];
1651 struct {
1652 uint8_t status;
1653 uint8_t segment_num;
1654 uint8_t valid_diag_info;
1655 uint8_t rsvd3;
1656 uint64_t poh;
1657 uint32_t nsid;
1658 /* Define as an array to simplify alignment issues */
1659 uint8_t failing_lba[8];
1660 uint8_t status_code_type;
1661 uint8_t status_code;
1662 uint8_t vendor_specific[2];
1663 } __packed result[20];
1664} __packed __aligned(4);
1665
1666_Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1667 "bad size for nvme_device_self_test_page");
1668
1669/*
1670 * Header structure for both host initiated telemetry (page 7) and controller
1671 * initiated telemetry (page 8).
1672 */
1673struct nvme_telemetry_log_page {
1674 uint8_t identifier;
1675 uint8_t rsvd[4];
1676 uint8_t oui[3];
1677 uint16_t da1_last;
1678 uint16_t da2_last;
1679 uint16_t da3_last;
1680 uint8_t rsvd2[2];
1681 uint32_t da4_last;
1682 uint8_t rsvd3[361];
1683 uint8_t hi_gen;
1684 uint8_t ci_avail;
1685 uint8_t ci_gen;
1686 uint8_t reason[128];
1687 /* Blocks of telemetry data follow */
1688} __packed __aligned(4);
1689
1690_Static_assert(sizeof(struct nvme_telemetry_log_page) == 512,
1691 "bad size for nvme_telemetry_log");
1692
1693struct nvme_discovery_log_entry {
1694 uint8_t trtype;
1695 uint8_t adrfam;
1696 uint8_t subtype;
1697 uint8_t treq;
1698 uint16_t portid;
1699 uint16_t cntlid;
1700 uint16_t aqsz;
1701 uint8_t reserved1[22];
1702 uint8_t trsvcid[32];
1703 uint8_t reserved2[192];
1704 uint8_t subnqn[256];
1705 uint8_t traddr[256];
1706 union {
1707 struct {
1708 uint8_t rdma_qptype;
1709 uint8_t rdma_prtype;
1710 uint8_t rdma_cms;
1711 uint8_t reserved[5];
1712 uint16_t rdma_pkey;
1713 } rdma;
1714 struct {
1715 uint8_t sectype;
1716 } tcp;
1717 uint8_t reserved[256];
1718 } tsas;
1719} __packed __aligned(4);
1720
1721_Static_assert(sizeof(struct nvme_discovery_log_entry) == 1024,
1722 "bad size for nvme_discovery_log_entry");
1723
1724struct nvme_discovery_log {
1725 uint64_t genctr;
1726 uint64_t numrec;
1727 uint16_t recfmt;
1728 uint8_t reserved[1006];
1729 struct nvme_discovery_log_entry entries[];
1730} __packed __aligned(4);
1731
1732_Static_assert(sizeof(struct nvme_discovery_log) == 1024,
1733 "bad size for nvme_discovery_log");
1734
1735struct nvme_res_notification_page {
1736 uint64_t log_page_count;
1737 uint8_t log_page_type;
1738 uint8_t available_log_pages;
1739 uint8_t reserved2;
1740 uint32_t nsid;
1741 uint8_t reserved[48];
1742} __packed __aligned(4);
1743
1744_Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1745 "bad size for nvme_res_notification_page");
1746
1747struct nvme_sanitize_status_page {
1748 uint16_t sprog;
1749 uint16_t sstat;
1750 uint32_t scdw10;
1751 uint32_t etfo;
1752 uint32_t etfbe;
1753 uint32_t etfce;
1754 uint32_t etfownd;
1755 uint32_t etfbewnd;
1756 uint32_t etfcewnd;
1757 uint8_t reserved[480];
1758} __packed __aligned(4);
1759
1760_Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1761 "bad size for nvme_sanitize_status_page");
1762
1763struct intel_log_temp_stats {
1764 uint64_t current;
1765 uint64_t overtemp_flag_last;
1766 uint64_t overtemp_flag_life;
1767 uint64_t max_temp;
1768 uint64_t min_temp;
1769 uint64_t _rsvd[5];
1770 uint64_t max_oper_temp;
1771 uint64_t min_oper_temp;
1772 uint64_t est_offset;
1773} __packed __aligned(4);
1774
1775_Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1776
1777struct nvme_resv_reg_ctrlr {
1778 uint16_t ctrlr_id; /* Controller ID */
1779 uint8_t rcsts; /* Reservation Status */
1780 uint8_t reserved3[5];
1781 uint64_t hostid; /* Host Identifier */
1782 uint64_t rkey; /* Reservation Key */
1783} __packed __aligned(4);
1784
1785_Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1786
1787struct nvme_resv_reg_ctrlr_ext {
1788 uint16_t ctrlr_id; /* Controller ID */
1789 uint8_t rcsts; /* Reservation Status */
1790 uint8_t reserved3[5];
1791 uint64_t rkey; /* Reservation Key */
1792 uint64_t hostid[2]; /* Host Identifier */
1793 uint8_t reserved32[32];
1794} __packed __aligned(4);
1795
1796_Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1797
1798struct nvme_resv_status {
1799 uint32_t gen; /* Generation */
1800 uint8_t rtype; /* Reservation Type */
1801 uint8_t regctl[2]; /* Number of Registered Controllers */
1802 uint8_t reserved7[2];
1803 uint8_t ptpls; /* Persist Through Power Loss State */
1804 uint8_t reserved10[14];
1805 struct nvme_resv_reg_ctrlr ctrlr[0];
1806} __packed __aligned(4);
1807
1808_Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1809
1810struct nvme_resv_status_ext {
1811 uint32_t gen; /* Generation */
1812 uint8_t rtype; /* Reservation Type */
1813 uint8_t regctl[2]; /* Number of Registered Controllers */
1814 uint8_t reserved7[2];
1815 uint8_t ptpls; /* Persist Through Power Loss State */
1816 uint8_t reserved10[14];
1817 uint8_t reserved24[40];
1818 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1819} __packed __aligned(4);
1820
1821_Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1822
1823#define NVME_TEST_MAX_THREADS 128
1824
1825struct nvme_io_test {
1826 enum nvme_nvm_opcode opc;
1827 uint32_t size;
1828 uint32_t time; /* in seconds */
1829 uint32_t num_threads;
1830 uint32_t flags;
1831 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1832};
1833
1834enum nvme_io_test_flags {
1835 /*
1836 * Specifies whether dev_refthread/dev_relthread should be
1837 * called during NVME_BIO_TEST. Ignored for other test
1838 * types.
1839 */
1840 NVME_TEST_FLAG_REFTHREAD = 0x1,
1841};
1842
1843struct nvme_pt_command {
1844 /*
1845 * cmd is used to specify a passthrough command to a controller or
1846 * namespace.
1847 *
1848 * The following fields from cmd may be specified by the caller:
1849 * * opc (opcode)
1850 * * nsid (namespace id) - for admin commands only
1851 * * cdw10-cdw15
1852 *
1853 * Remaining fields must be set to 0 by the caller.
1854 */
1855 struct nvme_command cmd;
1856
1857 /*
1858 * cpl returns completion status for the passthrough command
1859 * specified by cmd.
1860 *
1861 * The following fields will be filled out by the driver, for
1862 * consumption by the caller:
1863 * * cdw0
1864 * * status (except for phase)
1865 *
1866 * Remaining fields will be set to 0 by the driver.
1867 */
1868 struct nvme_completion cpl;
1869
1870 /* buf is the data buffer associated with this passthrough command. */
1871 void * buf;
1872
1873 /*
1874 * len is the length of the data buffer associated with this
1875 * passthrough command.
1876 */
1877 uint32_t len;
1878
1879 /*
1880 * is_read = 1 if the passthrough command will read data into the
1881 * supplied buffer from the controller.
1882 *
1883 * is_read = 0 if the passthrough command will write data from the
1884 * supplied buffer to the controller.
1885 */
1886 uint32_t is_read;
1887
1888 /*
1889 * driver_lock is used by the driver only. It must be set to 0
1890 * by the caller.
1891 */
1892 struct mtx * driver_lock;
1893};
1894
1895struct nvme_get_nsid {
1896 char cdev[SPECNAMELEN + 1];
1897 uint32_t nsid;
1898};
1899
1900struct nvme_hmb_desc {
1901 uint64_t addr;
1902 uint32_t size;
1903 uint32_t reserved;
1904};
1905
1906#define nvme_completion_is_error(cpl) \
1907 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1908
1909void nvme_cpl_sbuf(const struct nvme_completion *cpl, struct sbuf *sbuf);
1910void nvme_opcode_sbuf(bool admin, uint8_t opc, struct sbuf *sb);
1911void nvme_sc_sbuf(const struct nvme_completion *cpl, struct sbuf *sbuf);
1912void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1913
1914#ifdef _KERNEL
1915
1916struct bio;
1917struct thread;
1918
1919struct nvme_namespace;
1920struct nvme_controller;
1921struct nvme_consumer;
1922struct nvme_passthru_cmd;
1923
1924typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1925
1926typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1927typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1928typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1929 uint32_t, void *, uint32_t);
1930typedef void (*nvme_cons_fail_fn_t)(void *);
1931
1932enum nvme_namespace_flags {
1933 NVME_NS_DEALLOCATE_SUPPORTED = 0x01,
1934 NVME_NS_FLUSH_SUPPORTED = 0x02,
1935 NVME_NS_ADDED = 0x04,
1936 NVME_NS_CHANGED = 0x08,
1937 NVME_NS_GONE = 0x10,
1938};
1939
1940int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1941 struct nvme_pt_command *pt,
1942 uint32_t nsid, int is_user_buffer,
1943 int is_admin_cmd);
1944
1945int nvme_ctrlr_linux_passthru_cmd(struct nvme_controller *ctrlr,
1946 struct nvme_passthru_cmd *npc,
1947 uint32_t nsid, bool is_user,
1948 bool is_admin);
1949
1950/* Admin functions */
1951void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1952 uint8_t feature, uint32_t cdw11,
1953 uint32_t cdw12, uint32_t cdw13,
1954 uint32_t cdw14, uint32_t cdw15,
1955 void *payload, uint32_t payload_size,
1956 nvme_cb_fn_t cb_fn, void *cb_arg);
1957void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1958 uint8_t feature, uint32_t cdw11,
1959 void *payload, uint32_t payload_size,
1960 nvme_cb_fn_t cb_fn, void *cb_arg);
1961void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1962 uint8_t log_page, uint32_t nsid,
1963 void *payload, uint32_t payload_size,
1964 nvme_cb_fn_t cb_fn, void *cb_arg);
1965
1966/* NVM I/O functions */
1967int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1968 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1969 void *cb_arg);
1970int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1971 nvme_cb_fn_t cb_fn, void *cb_arg);
1972int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1973 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1974 void *cb_arg);
1975int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1976 nvme_cb_fn_t cb_fn, void *cb_arg);
1977int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1978 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1979 void *cb_arg);
1980int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1981 void *cb_arg);
1982int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1983 size_t len);
1984
1985/* Registration functions */
1986struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1987 nvme_cons_ctrlr_fn_t ctrlr_fn,
1988 nvme_cons_async_fn_t async_fn,
1989 nvme_cons_fail_fn_t fail_fn);
1990void nvme_unregister_consumer(struct nvme_consumer *consumer);
1991
1992/* Controller helper functions */
1993device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1994const struct nvme_controller_data *
1995 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1996static inline bool
1997nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1998{
1999 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
2000 return (NVMEV(NVME_CTRLR_DATA_ONCS_DSM, cd->oncs) != 0);
2001}
2002
2003/* Namespace helper functions */
2004uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
2005uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
2006uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
2007uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
2008uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
2009const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
2010const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
2011const struct nvme_namespace_data *
2012 nvme_ns_get_data(struct nvme_namespace *ns);
2013uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
2014
2015int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
2016 nvme_cb_fn_t cb_fn);
2017int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
2018 caddr_t arg, int flag, struct thread *td);
2019
2020/*
2021 * Command building helper functions -- shared with CAM
2022 * These functions assume allocator zeros out cmd structure
2023 * CAM's xpt_get_ccb and the request allocator for nvme both
2024 * do zero'd allocations.
2025 */
2026static inline
2027void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
2028{
2029
2030 cmd->opc = NVME_OPC_FLUSH;
2031 cmd->nsid = htole32(nsid);
2032}
2033
2034static inline
2035void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
2036 uint64_t lba, uint32_t count)
2037{
2038 cmd->opc = rwcmd;
2039 cmd->nsid = htole32(nsid);
2040 cmd->cdw10 = htole32(lba & 0xffffffffu);
2041 cmd->cdw11 = htole32(lba >> 32);
2042 cmd->cdw12 = htole32(count-1);
2043}
2044
2045static inline
2046void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
2047 uint64_t lba, uint32_t count)
2048{
2049 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
2050}
2051
2052static inline
2053void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
2054 uint64_t lba, uint32_t count)
2055{
2056 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
2057}
2058
2059static inline
2060void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
2061 uint32_t num_ranges)
2062{
2063 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
2064 cmd->nsid = htole32(nsid);
2065 cmd->cdw10 = htole32(num_ranges - 1);
2066 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
2067}
2068
2069extern int nvme_use_nvd;
2070
2071#endif /* _KERNEL */
2072
2073/* Endianess conversion functions for NVMe structs */
2074static inline
2075void nvme_completion_swapbytes(struct nvme_completion *s __unused)
2076{
2077#if _BYTE_ORDER != _LITTLE_ENDIAN
2078
2079 s->cdw0 = le32toh(s->cdw0);
2080 /* omit rsvd1 */
2081 s->sqhd = le16toh(s->sqhd);
2082 s->sqid = le16toh(s->sqid);
2083 /* omit cid */
2084 s->status = le16toh(s->status);
2085#endif
2086}
2087
2088static inline
2089void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
2090{
2091#if _BYTE_ORDER != _LITTLE_ENDIAN
2092
2093 s->mp = le16toh(s->mp);
2094 s->enlat = le32toh(s->enlat);
2095 s->exlat = le32toh(s->exlat);
2096 s->idlp = le16toh(s->idlp);
2097 s->actp = le16toh(s->actp);
2098#endif
2099}
2100
2101static inline
2102void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
2103{
2104#if _BYTE_ORDER != _LITTLE_ENDIAN
2105 int i;
2106
2107 s->vid = le16toh(s->vid);
2108 s->ssvid = le16toh(s->ssvid);
2109 s->ctrlr_id = le16toh(s->ctrlr_id);
2110 s->ver = le32toh(s->ver);
2111 s->rtd3r = le32toh(s->rtd3r);
2112 s->rtd3e = le32toh(s->rtd3e);
2113 s->oaes = le32toh(s->oaes);
2114 s->ctratt = le32toh(s->ctratt);
2115 s->rrls = le16toh(s->rrls);
2116 s->crdt1 = le16toh(s->crdt1);
2117 s->crdt2 = le16toh(s->crdt2);
2118 s->crdt3 = le16toh(s->crdt3);
2119 s->oacs = le16toh(s->oacs);
2120 s->wctemp = le16toh(s->wctemp);
2121 s->cctemp = le16toh(s->cctemp);
2122 s->mtfa = le16toh(s->mtfa);
2123 s->hmpre = le32toh(s->hmpre);
2124 s->hmmin = le32toh(s->hmmin);
2125 s->rpmbs = le32toh(s->rpmbs);
2126 s->edstt = le16toh(s->edstt);
2127 s->kas = le16toh(s->kas);
2128 s->hctma = le16toh(s->hctma);
2129 s->mntmt = le16toh(s->mntmt);
2130 s->mxtmt = le16toh(s->mxtmt);
2131 s->sanicap = le32toh(s->sanicap);
2132 s->hmminds = le32toh(s->hmminds);
2133 s->hmmaxd = le16toh(s->hmmaxd);
2134 s->nsetidmax = le16toh(s->nsetidmax);
2135 s->endgidmax = le16toh(s->endgidmax);
2136 s->anagrpmax = le32toh(s->anagrpmax);
2137 s->nanagrpid = le32toh(s->nanagrpid);
2138 s->pels = le32toh(s->pels);
2139 s->maxcmd = le16toh(s->maxcmd);
2140 s->nn = le32toh(s->nn);
2141 s->oncs = le16toh(s->oncs);
2142 s->fuses = le16toh(s->fuses);
2143 s->awun = le16toh(s->awun);
2144 s->awupf = le16toh(s->awupf);
2145 s->acwu = le16toh(s->acwu);
2146 s->sgls = le32toh(s->sgls);
2147 s->mnan = le32toh(s->mnan);
2148 s->ioccsz = le32toh(s->ioccsz);
2149 s->iorcsz = le32toh(s->iorcsz);
2150 s->icdoff = le16toh(s->icdoff);
2151 s->ofcs = le16toh(s->ofcs);
2152 for (i = 0; i < 32; i++)
2153 nvme_power_state_swapbytes(&s->power_state[i]);
2154#endif
2155}
2156
2157static inline
2158void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
2159{
2160#if _BYTE_ORDER != _LITTLE_ENDIAN
2161 int i;
2162
2163 s->nsze = le64toh(s->nsze);
2164 s->ncap = le64toh(s->ncap);
2165 s->nuse = le64toh(s->nuse);
2166 s->nawun = le16toh(s->nawun);
2167 s->nawupf = le16toh(s->nawupf);
2168 s->nacwu = le16toh(s->nacwu);
2169 s->nabsn = le16toh(s->nabsn);
2170 s->nabo = le16toh(s->nabo);
2171 s->nabspf = le16toh(s->nabspf);
2172 s->noiob = le16toh(s->noiob);
2173 s->npwg = le16toh(s->npwg);
2174 s->npwa = le16toh(s->npwa);
2175 s->npdg = le16toh(s->npdg);
2176 s->npda = le16toh(s->npda);
2177 s->nows = le16toh(s->nows);
2178 s->anagrpid = le32toh(s->anagrpid);
2179 s->nvmsetid = le16toh(s->nvmsetid);
2180 s->endgid = le16toh(s->endgid);
2181 for (i = 0; i < 16; i++)
2182 s->lbaf[i] = le32toh(s->lbaf[i]);
2183#endif
2184}
2185
2186static inline
2187void nvme_error_information_entry_swapbytes(
2188 struct nvme_error_information_entry *s __unused)
2189{
2190#if _BYTE_ORDER != _LITTLE_ENDIAN
2191
2192 s->error_count = le64toh(s->error_count);
2193 s->sqid = le16toh(s->sqid);
2194 s->cid = le16toh(s->cid);
2195 s->status = le16toh(s->status);
2196 s->error_location = le16toh(s->error_location);
2197 s->lba = le64toh(s->lba);
2198 s->nsid = le32toh(s->nsid);
2199 s->csi = le64toh(s->csi);
2200 s->ttsi = le16toh(s->ttsi);
2201#endif
2202}
2203
2204static inline
2205void nvme_le128toh(void *p __unused)
2206{
2207#if _BYTE_ORDER != _LITTLE_ENDIAN
2208 /* Swap 16 bytes in place */
2209 char *tmp = (char*)p;
2210 char b;
2211 int i;
2212 for (i = 0; i < 8; i++) {
2213 b = tmp[i];
2214 tmp[i] = tmp[15-i];
2215 tmp[15-i] = b;
2216 }
2217#endif
2218}
2219
2220static inline
2221void nvme_health_information_page_swapbytes(
2222 struct nvme_health_information_page *s __unused)
2223{
2224#if _BYTE_ORDER != _LITTLE_ENDIAN
2225 int i;
2226
2227 s->temperature = le16toh(s->temperature);
2228 nvme_le128toh((void *)s->data_units_read);
2229 nvme_le128toh((void *)s->data_units_written);
2230 nvme_le128toh((void *)s->host_read_commands);
2231 nvme_le128toh((void *)s->host_write_commands);
2232 nvme_le128toh((void *)s->controller_busy_time);
2233 nvme_le128toh((void *)s->power_cycles);
2234 nvme_le128toh((void *)s->power_on_hours);
2235 nvme_le128toh((void *)s->unsafe_shutdowns);
2236 nvme_le128toh((void *)s->media_errors);
2237 nvme_le128toh((void *)s->num_error_info_log_entries);
2238 s->warning_temp_time = le32toh(s->warning_temp_time);
2239 s->error_temp_time = le32toh(s->error_temp_time);
2240 for (i = 0; i < 8; i++)
2241 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
2242 s->tmt1tc = le32toh(s->tmt1tc);
2243 s->tmt2tc = le32toh(s->tmt2tc);
2244 s->ttftmt1 = le32toh(s->ttftmt1);
2245 s->ttftmt2 = le32toh(s->ttftmt2);
2246#endif
2247}
2248
2249static inline
2250void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2251{
2252#if _BYTE_ORDER != _LITTLE_ENDIAN
2253 int i;
2254
2255 for (i = 0; i < 1024; i++)
2256 s->ns[i] = le32toh(s->ns[i]);
2257#endif
2258}
2259
2260static inline
2261void nvme_command_effects_page_swapbytes(
2262 struct nvme_command_effects_page *s __unused)
2263{
2264#if _BYTE_ORDER != _LITTLE_ENDIAN
2265 int i;
2266
2267 for (i = 0; i < 256; i++)
2268 s->acs[i] = le32toh(s->acs[i]);
2269 for (i = 0; i < 256; i++)
2270 s->iocs[i] = le32toh(s->iocs[i]);
2271#endif
2272}
2273
2274static inline
2275void nvme_res_notification_page_swapbytes(
2276 struct nvme_res_notification_page *s __unused)
2277{
2278#if _BYTE_ORDER != _LITTLE_ENDIAN
2279 s->log_page_count = le64toh(s->log_page_count);
2280 s->nsid = le32toh(s->nsid);
2281#endif
2282}
2283
2284static inline
2285void nvme_sanitize_status_page_swapbytes(
2286 struct nvme_sanitize_status_page *s __unused)
2287{
2288#if _BYTE_ORDER != _LITTLE_ENDIAN
2289 s->sprog = le16toh(s->sprog);
2290 s->sstat = le16toh(s->sstat);
2291 s->scdw10 = le32toh(s->scdw10);
2292 s->etfo = le32toh(s->etfo);
2293 s->etfbe = le32toh(s->etfbe);
2294 s->etfce = le32toh(s->etfce);
2295 s->etfownd = le32toh(s->etfownd);
2296 s->etfbewnd = le32toh(s->etfbewnd);
2297 s->etfcewnd = le32toh(s->etfcewnd);
2298#endif
2299}
2300
2301static inline
2302void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2303 size_t size __unused)
2304{
2305#if _BYTE_ORDER != _LITTLE_ENDIAN
2306 size_t i, n;
2307
2308 s->gen = le32toh(s->gen);
2309 n = (s->regctl[1] << 8) | s->regctl[0];
2310 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2311 for (i = 0; i < n; i++) {
2312 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2313 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2314 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2315 }
2316#endif
2317}
2318
2319static inline
2320void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2321 size_t size __unused)
2322{
2323#if _BYTE_ORDER != _LITTLE_ENDIAN
2324 size_t i, n;
2325
2326 s->gen = le32toh(s->gen);
2327 n = (s->regctl[1] << 8) | s->regctl[0];
2328 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2329 for (i = 0; i < n; i++) {
2330 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2331 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2332 nvme_le128toh((void *)s->ctrlr[i].hostid);
2333 }
2334#endif
2335}
2336
2337static inline void
2338nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2339{
2340#if _BYTE_ORDER != _LITTLE_ENDIAN
2341 uint8_t *tmp;
2342 uint32_t r, i;
2343 uint8_t b;
2344
2345 for (r = 0; r < 20; r++) {
2346 s->result[r].poh = le64toh(s->result[r].poh);
2347 s->result[r].nsid = le32toh(s->result[r].nsid);
2348 /* Unaligned 64-bit loads fail on some architectures */
2349 tmp = s->result[r].failing_lba;
2350 for (i = 0; i < 4; i++) {
2351 b = tmp[i];
2352 tmp[i] = tmp[7-i];
2353 tmp[7-i] = b;
2354 }
2355 }
2356#endif
2357}
2358
2359static inline void
2360nvme_discovery_log_entry_swapbytes(struct nvme_discovery_log_entry *s __unused)
2361{
2362#if _BYTE_ORDER != _LITTLE_ENDIAN
2363 s->portid = le16toh(s->portid);
2364 s->cntlid = le16toh(s->cntlid);
2365 s->aqsz = le16toh(s->aqsz);
2366 if (s->trtype == 0x01 /* RDMA */) {
2367 s->tsas.rdma.rdma_pkey = le16toh(s->tsas.rdma.rdma_pkey);
2368 }
2369#endif
2370}
2371
2372static inline void
2373nvme_discovery_log_swapbytes(struct nvme_discovery_log *s __unused)
2374{
2375#if _BYTE_ORDER != _LITTLE_ENDIAN
2376 s->genctr = le64toh(s->genctr);
2377 s->numrec = le64toh(s->numrec);
2378 s->recfmt = le16toh(s->recfmt);
2379#endif
2380}
2381#endif /* __NVME_H__ */